openocd-commit — OpenOCD commit maling list - read only

[openocd-svn] Main OpenOCD repository annotated tag, v0.4.0, created. v0.4.0

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The annotated tag, v0.4.0 has been created
        at  ed703c7f7189338cb60beef75d83fe85ccd8296c (tag)
   tagging  56e74908d17d740db0a376f354c21e6608e8af8d (commit)
  replaces  v0.4.0-rc2
 tagged by  David Brownell
        on  Sun Feb 21 12:22:31 2010 -0800

- Log -----------------------------------------------------------------
The OpenOCD 0.4.0 release

David Brownell (9):
      Restore "-dev" version suffix (0.4.0-rc2-dev)
      NEWS: mention removal of obsolete commands
      LPC1768.cfg -- partial fixes for bogus reset-init handler
      ARM920T scanchain 15 comments/cleanup
      FreeBSD buildfix
      CSB337 board cleanup (quasi-regression)
      arm920t line length cleanup
      User's Guide mentions OS-specific installation
      Label builds as OpenOCD v0.4.0

Marc Pignat (1):
      atm920t : fix breakpoints and data cache handling

Mathias Kuester (1):
      fix crash with DSP563XX

Øyvind Harboe (1):
      gpl: fix GPL startup message

-----------------------------------------------------------------------


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc2-12-g56e7490

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  56e74908d17d740db0a376f354c21e6608e8af8d (commit)
      from  4aa0a4d8111772c526ba84e3502b2f73ca06d603 (commit)

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- Log -----------------------------------------------------------------
commit 56e74908d17d740db0a376f354c21e6608e8af8d
Author: David Brownell <dbr...@us...>
Date:   Sun Feb 21 12:20:13 2010 -0800

    Label builds as OpenOCD v0.4.0
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/configure.in b/configure.in
index 65d7369..4681aeb 100644
--- a/configure.in
+++ b/configure.in
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.4.0-rc2-dev],
+AC_INIT([openocd], [0.4.0],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

-----------------------------------------------------------------------

Summary of changes:
 configure.in |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc2-11-g4aa0a4d

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  4aa0a4d8111772c526ba84e3502b2f73ca06d603 (commit)
      from  bb4cb7935e8c4eb41e1d68ac2c43f6a1caec1ae5 (commit)

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- Log -----------------------------------------------------------------
commit 4aa0a4d8111772c526ba84e3502b2f73ca06d603
Author: David Brownell <dbr...@us...>
Date:   Sun Feb 21 09:29:24 2010 -0800

    User's Guide mentions OS-specific installation
    
    Specifically the Linux issue of needing "udev" rules, and MS-Windows
    needing driver configuration.
    
    Also, update the existing udev note to use the correct name of that
    rules file in the source tree.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/README b/README
index 35118da..b69a69a 100644
--- a/README
+++ b/README
@@ -64,8 +64,8 @@ you can build the in-tree documentation.
 Installing OpenOCD
 ==================
 
-On Linux, you may have permissions problems to address.  The best
-way to do this is to use the contrib/udev.rules file.  It probably
+On Linux, you may have permissions problems to address.  The best way
+to do this is to use the contrib/openocd.udev rules file.  It probably
 belongs somewhere in /etc/udev/rules.d, but consult your operating
 system documentation to be sure.  In particular, make sure that it
 matches the syntax used by your operating system's version of udev.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 63b6ab0..61e39b2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -506,6 +506,14 @@ as Tcl scripts, from a @file{startup.tcl} file internal to the server.
 @cindex logfile
 @cindex directory search
 
+Properly installing OpenOCD sets up your operating system to grant it access
+to the JTAG adapters.  On Linux, this usually involves installing a file
+in @file{/etc/udev/rules.d,} so OpenOCD has permissions.  MS-Windows needs
+complex and confusing driver configuration for every peripheral.  Such issues
+are unique to each operating system, and are not detailed in this User's Guide.
+
+Then later you will invoke the OpenOCD server, with various options to
+tell it how each debug session should work.
 The @option{--help} option shows:
 @verbatim
 bash$ openocd --help
@@ -1984,6 +1992,10 @@ MMU: disabled, D-Cache: disabled, I-Cache: enabled
 @cindex config file, interface
 @cindex interface config file
 
+Correctly installing OpenOCD includes making your operating system give
+OpenOCD access to JTAG adapters.  Once that has been done, Tcl commands
+are used to select which one is used, and to configure how it is used.
+
 JTAG Adapters/Interfaces/Dongles are normally configured
 through commands in an interface configuration
 file which is sourced by your @file{openocd.cfg} file, or

-----------------------------------------------------------------------

Summary of changes:
 README           |    4 ++--
 doc/openocd.texi |   12 ++++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc2-10-gbb4cb79

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  bb4cb7935e8c4eb41e1d68ac2c43f6a1caec1ae5 (commit)
       via  57d5673dea2111d68a5266f23f6b6bacec38014e (commit)
      from  d2a2c14d202da736e2c820c26d6deceee4e1e530 (commit)

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- Log -----------------------------------------------------------------
commit bb4cb7935e8c4eb41e1d68ac2c43f6a1caec1ae5
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 20 20:47:38 2010 -0800

    arm920t line length cleanup
    
    The recent patch to fixbreakpoints and dcache handling added
    a bunch of overlong lines (80+ chars) ... shrink them, and do
    the same to a few lines which were already overlong.
    
    Also add a few FIXME comments to nudge (a) replacement of some
    magic numbers with opcode macros, which will be much better at
    showing what's actually going on, and (b) correct return codes.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 7cc228d..3e61545 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -276,7 +276,8 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 	jtag_execute_queue();
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-	LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
+	LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x",
+			cp15_opcode, address, *value);
 #endif
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -317,7 +318,8 @@ int arm920t_write_cp15_interpreted(struct target *target,
 	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-	LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
+	LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x",
+			cp15_opcode, value, address);
 #endif
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -335,14 +337,17 @@ uint32_t arm920t_get_ttb(struct target *target)
 	int retval;
 	uint32_t ttb = 0x0;
 
-	if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
+	if ((retval = arm920t_read_cp15_interpreted(target,
+			/* FIXME use opcode macro */
+			0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 		return retval;
 
 	return ttb;
 }
 
 // EXPORTED to FA256
-void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
+void arm920t_disable_mmu_caches(struct target *target, int mmu,
+		int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
 
@@ -363,7 +368,8 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, i
 }
 
 // EXPORTED to FA256
-void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
+void arm920t_enable_mmu_caches(struct target *target, int mmu,
+		int d_u_cache, int i_cache)
 {
 	uint32_t cp15_control;
 
@@ -393,7 +399,7 @@ void arm920t_post_debug_entry(struct target *target)
 	arm920t_read_cp15_physical(target,
 			CP15PHYS_CTRL, &arm920t->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm920t->cp15_control_reg);
 
 	if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
@@ -402,20 +408,26 @@ void arm920t_post_debug_entry(struct target *target)
 		arm920t_read_cp15_physical(target,
 				CP15PHYS_CACHETYPE, &cache_type_reg);
 		jtag_execute_queue();
-		armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
+		armv4_5_identify_cache(cache_type_reg,
+				&arm920t->armv4_5_mmu.armv4_5_cache);
 	}
 
-	arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
-	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
-	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
+	arm920t->armv4_5_mmu.mmu_enabled =
+			(arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+			(arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
+	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
+			(arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 
 	/* save i/d fault status and address register */
+			/* FIXME use opcode macros */
 	arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 	arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 	arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 	arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 
-	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
+	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32
+		", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32,
 		arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 
 	if (arm920t->preserve_cache)
@@ -490,9 +502,9 @@ int arm920t_arch_state(struct target *target)
 
 	arm_arch_state(target);
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
-			 state[arm920t->armv4_5_mmu.mmu_enabled],
-			 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
-			 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
+		 state[arm920t->armv4_5_mmu.mmu_enabled],
+		 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
+		 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 
 	return ERROR_OK;
 }
@@ -517,7 +529,8 @@ static int arm920_virt2phys(struct target *target,
 	uint32_t ap;
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
-	uint32_t ret = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
+	uint32_t ret = armv4_5_mmu_translate_va(target,
+			&arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
 	if (type == -1)
 	{
 		return ret;
@@ -527,7 +540,8 @@ static int arm920_virt2phys(struct target *target,
 }
 
 /** Reads a buffer, in the specified word size, with current MMU settings. */
-int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm920t_read_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
 
@@ -569,11 +583,14 @@ int arm920t_write_memory(struct target *target, uint32_t address,
 	/* FIX!!!! this should be cleaned up and made much more general. The
 	 * plan is to write up and test on arm920t specifically and
 	 * then generalize and clean up afterwards. */
-	if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
+	if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) &&
+			((size==2) || (size==4)))
 	{
-		/* special case the handling of single word writes to bypass MMU
-		 * to allow implementation of breakpoints in memory marked read only
-		 * by MMU */
+		/* special case the handling of single word writes to
+		 * bypass MMU, to allow implementation of breakpoints
+		 * in memory marked read only
+		 * by MMU
+		 */
 		int type;
 		uint32_t cb;
 		int domain;
@@ -583,23 +600,25 @@ int arm920t_write_memory(struct target *target, uint32_t address,
 		/*
 		 * We need physical address and cb
 		 */
-		pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
+		pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu,
+				address, &type, &cb, &domain, &ap);
 		if (type == -1)
-		{
 			return pa;
-		}
 
 		if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 		{
 			if (cb & 0x1)
 			{
-				LOG_DEBUG("D-Cache buffered, drain write buffer");
+				LOG_DEBUG("D-Cache buffered, "
+						"drain write buffer");
 				/*
 				 * Buffered ?
 				 * Drain write buffer - MCR p15,0,Rd,c7,c10,4
 				 */
 
-				retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 10, 4), 0x0, 0);
+				retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 10, 4),
+					0x0, 0);
 				if (retval != ERROR_OK)
 					return retval;
 			}
@@ -609,19 +628,25 @@ int arm920t_write_memory(struct target *target, uint32_t address,
 				/*
 				 * Write back memory ? -> clean cache
 				 *
-				 * There is no way for cleaning a data cache line using
-				 * cp15 scan chain, so copy the full cache line from
-				 * cache to physical memory.
+				 * There is no way to clean cache lines using
+				 * cp15 scan chain, so copy the full cache
+				 * line from cache to physical memory.
 				 */
 				uint8_t data[32];
 
-				LOG_DEBUG("D-Cache in 'write back' mode, flush cache line");
+				LOG_DEBUG("D-Cache in 'write back' mode, "
+						"flush cache line");
 
-				retval = target_read_memory(target, address & cache_mask, 1, sizeof(data), &data[0]);
+				retval = target_read_memory(target,
+						address & cache_mask, 1,
+						sizeof(data), &data[0]);
 				if (retval != ERROR_OK)
 					return retval;
 
-				retval = armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa & cache_mask, 1, sizeof(data), &data[0]);
+				retval = armv4_5_mmu_write_physical(target,
+						&arm920t->armv4_5_mmu,
+						pa & cache_mask, 1,
+						sizeof(data), &data[0]);
 				if (retval != ERROR_OK)
 					return retval;
 			}
@@ -634,45 +659,59 @@ int arm920t_write_memory(struct target *target, uint32_t address,
 				 *
 				 * MCR p15,0,Rd,c7,c6,1
 				 */
-				LOG_DEBUG("D-Cache enabled, invalidate cache line");
+				LOG_DEBUG("D-Cache enabled, "
+					"invalidate cache line");
 
-				retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0, address & cache_mask);
+				retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0,
+					address & cache_mask);
 				if (retval != ERROR_OK)
 					return retval;
 			}
 		}
 
-		/* write directly to physical memory bypassing any read only MMU bits, etc. */
-		retval = armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
+		/* write directly to physical memory,
+		 * bypassing any read only MMU bits, etc.
+		 */
+		retval = armv4_5_mmu_write_physical(target,
+				&arm920t->armv4_5_mmu, pa, size,
+				count, buffer);
 		if (retval != ERROR_OK)
 			return retval;
 	} else
 	{
-		if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
+		if ((retval = arm7_9_write_memory(target, address,
+					size, count, buffer)) != ERROR_OK)
 			return retval;
 	}
 
 	/* If ICache is enabled, we have to invalidate affected ICache lines
-	 * the DCache is forced to write-through, so we don't have to clean it here
+	 * the DCache is forced to write-through,
+	 * so we don't have to clean it here
 	 */
 	if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 	{
 		if (count <= 1)
 		{
 			/* invalidate ICache single entry with MVA
-			 * 	ee070f35 	mcr	15, 0, r0, cr7, cr5, {1}
+			 *   mcr	15, 0, r0, cr7, cr5, {1}
 			 */
-			LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
-			retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 1), 0x0, address & cache_mask);
+			LOG_DEBUG("I-Cache enabled, "
+				"invalidating affected I-Cache line");
+			retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
+					0x0, address & cache_mask);
 			if (retval != ERROR_OK)
 				return retval;
 		}
 		else
 		{
 			/* invalidate ICache
-			 *   8:	ee070f15 	mcr	15, 0, r0, cr7, cr5, {0}
-			 * */
-			retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0x0, 0x0);
+			 *  mcr	15, 0, r0, cr7, cr5, {0}
+			 */
+			retval = arm920t_write_cp15_interpreted(target,
+					ARMV4_5_MCR(15, 0, 0, 7, 5, 0),
+					0x0, 0x0);
 			if (retval != ERROR_OK)
 				return retval;
 		}
@@ -699,7 +738,8 @@ int arm920t_soft_reset_halt(struct target *target)
 	int timeout;
 	while (!(timeout = ((timeval_ms()-then) > 1000)))
 	{
-		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
+		if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)
+				== 0)
 		{
 			embeddedice_read_reg(dbg_stat);
 			if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -746,12 +786,7 @@ int arm920t_soft_reset_halt(struct target *target)
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-	if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-	{
-		return retval;
-	}
-
-	return ERROR_OK;
+	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
 
 /* FIXME remove forward decls */
@@ -764,7 +799,8 @@ static int arm920t_mcr(struct target *target, int cpnum,
 		uint32_t CRn, uint32_t CRm,
 		uint32_t value);
 
-int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
+int arm920t_init_arch_info(struct target *target,
+		struct arm920t_common *arm920t, struct jtag_tap *tap)
 {
 	struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
 
@@ -802,8 +838,9 @@ int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t
 
 static int arm920t_target_create(struct target *target, Jim_Interp *interp)
 {
-	struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
+	struct arm920t_common *arm920t;
 
+	arm920t = calloc(1,sizeof(struct arm920t_common));
 	return arm920t_init_arch_info(target, arm920t, target->tap);
 }
 
@@ -851,7 +888,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 		return retval;
 	}
 	cp15_ctrl_saved = cp15_ctrl;
-	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
+	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED
+		| ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl);
 
 	/* read CP15 test state register */
@@ -862,7 +900,9 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 	fprintf(output, "DCache:\n");
 
 	/* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
-	for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
+	for (segment = 0;
+		segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets;
+		segment++)
 	{
 		fprintf(output, "\nsegment: %i\n----------", segment);
 
@@ -876,7 +916,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* D CAM Read, loads current victim into C15.C.D.Ind */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 
 		/* read current victim */
 		arm920t_read_cp15_physical(target,
@@ -889,7 +930,9 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		for (index = 0; index < 64; index++)
 		{
-			/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
+			/* Ra:
+			 * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
+			 */
 			regs[0] = 0x0 | (segment << 5) | (index << 26);
 			arm9tdmi_write_core_regs(target, 0x1, regs);
 
@@ -899,13 +942,18 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* Write DCache victim */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 
 			/* Read D RAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,10,2),
+				ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 
 			/* Read D CAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,6,2),
+				ARMV4_5_LDR(9, 0));
 
 			/* clear interpret mode */
 			cp15c15 &= ~0x1;
@@ -923,12 +971,16 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* mask LFSR[6] */
 			regs[9] &= 0xfffffffe;
-			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8"
+				PRIx32 ", content (%s):\n",
+				segment, index, regs[9],
+				(regs[9] & 0x10) ? "valid" : "invalid");
 
 			for (i = 1; i < 9; i++)
 			{
 				 d_cache[segment][index].data[i] = regs[i];
-				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
+				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
+						i-1, regs[i]);
 			}
 
 		}
@@ -943,7 +995,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write DCache victim */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
@@ -955,7 +1008,9 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 	fprintf(output, "ICache:\n");
 
 	/* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
-	for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
+	for (segment = 0;
+		segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets;
+		segment++)
 	{
 		fprintf(output, "segment: %i\n----------", segment);
 
@@ -969,7 +1024,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* I CAM Read, loads current victim into C15.C.I.Ind */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 
 		/* read current victim */
 		arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX,
@@ -982,7 +1038,9 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		for (index = 0; index < 64; index++)
 		{
-			/* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
+			/* Ra:
+			 * r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0)
+			 */
 			regs[0] = 0x0 | (segment << 5) | (index << 26);
 			arm9tdmi_write_core_regs(target, 0x1, regs);
 
@@ -992,13 +1050,18 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* Write ICache victim */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 
 			/* Read I RAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,9,2),
+				ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 
 			/* Read I CAM */
-			arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
+			arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,2,0,15,5,2),
+				ARMV4_5_LDR(9, 0));
 
 			/* clear interpret mode */
 			cp15c15 &= ~0x1;
@@ -1016,12 +1079,16 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* mask LFSR[6] */
 			regs[9] &= 0xfffffffe;
-			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+			fprintf(output, "\nsegment: %i, index: %i, "
+				"CAM: 0x%8.8" PRIx32 ", content (%s):\n",
+				segment, index, regs[9],
+				(regs[9] & 0x10) ? "valid" : "invalid");
 
 			for (i = 1; i < 9; i++)
 			{
 				 i_cache[segment][index].data[i] = regs[i];
-				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
+				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n",
+						i-1, regs[i]);
 			}
 		}
 
@@ -1035,7 +1102,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write ICache victim */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
@@ -1046,7 +1114,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 	/* restore CP15 MMU and Cache settings */
 	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
 
-	command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
+	command_print(CMD_CTX, "cache content successfully output to %s",
+			CMD_ARGV[0]);
 
 	fclose(output);
 
@@ -1117,7 +1186,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 		return retval;
 	}
 	cp15_ctrl_saved = cp15_ctrl;
-	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
+	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED
+			| ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl);
 
 	/* read CP15 test state register */
@@ -1135,7 +1205,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* Read D TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
 
 	/* clear interpret mode */
 	cp15c15 &= ~0x1;
@@ -1152,7 +1223,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim += 8)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
@@ -1162,10 +1234,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write D TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,0,0,10,0,0),
+			ARMV4_5_STR(1, 0));
 
 		/* Read D TLB CAM */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
+		arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,4,0,15,6,4),
+			ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
@@ -1186,7 +1262,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim++)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
@@ -1196,13 +1273,16 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write D TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
 
 		/* Read D TLB RAM1 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
 
 		/* Read D TLB RAM2 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
@@ -1225,7 +1305,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm9tdmi_write_core_regs(target, 0x2, regs);
 
 	/* Write D TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
 
 	/* prepare reading I TLB content
 	 * */
@@ -1235,7 +1316,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* Read I TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
 
 	/* clear interpret mode */
 	cp15c15 &= ~0x1;
@@ -1252,7 +1334,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim += 8)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
@@ -1262,10 +1345,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write I TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,10,0,1),
+				ARMV4_5_STR(1, 0));
 
 		/* Read I TLB CAM */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,5,4),
+				ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
@@ -1286,7 +1373,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	for (victim = 0; victim < 64; victim++)
 	{
 		/* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
-		 * base remains unchanged, victim goes through entries 0 to 63 */
+		 * base remains unchanged, victim goes through entries 0 to 63
+		 */
 		regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
 		arm9tdmi_write_core_regs(target, 0x2, regs);
 
@@ -1296,13 +1384,16 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write I TLB lockdown */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
 
 		/* Read I TLB RAM1 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
 
 		/* Read I TLB RAM2 */
-		arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
+		arm920t_execute_cp15(target,
+				ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
@@ -1325,7 +1416,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm9tdmi_write_core_regs(target, 0x2, regs);
 
 	/* Write I TLB lockdown */
-	arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
+	arm920t_execute_cp15(target,
+			ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
 
 	/* restore CP15 MMU and Cache settings */
 	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
@@ -1334,16 +1426,23 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	fprintf(output, "D TLB content:\n");
 	for (i = 0; i < 64; i++)
 	{
-		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32
+			" 0x%8.8" PRIx32 " %s\n",
+			i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2,
+			(d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
 	fprintf(output, "\n\nI TLB content:\n");
 	for (i = 0; i < 64; i++)
 	{
-		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32
+			" 0x%8.8" PRIx32 " %s\n",
+			i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2,
+			(i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
-	command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
+	command_print(CMD_CTX, "mmu content successfully output to %s",
+			CMD_ARGV[0]);
 
 	fclose(output);
 
@@ -1382,11 +1481,14 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for "
+			"\"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	/* one or more argument, access a single register (write if second argument is given */
+	/* one argument, read a register.
+	 * two arguments, write it.
+	 */
 	if (CMD_ARGC >= 1)
 	{
 		int address;
@@ -1395,9 +1497,11 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 		if (CMD_ARGC == 1)
 		{
 			uint32_t value;
-			if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
+			if ((retval = arm920t_read_cp15_physical(target,
+					address, &value)) != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't access reg %i", address);
+				command_print(CMD_CTX,
+					"couldn't access reg %i", address);
 				return ERROR_OK;
 			}
 			if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -1405,18 +1509,24 @@ COMMAND_HANDLER(arm920t_handle_cp15_command)
 				return retval;
 			}
 
-			command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
+			command_print(CMD_CTX, "%i: %8.8" PRIx32,
+					address, value);
 		}
 		else if (CMD_ARGC == 2)
 		{
 			uint32_t value;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
-			if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
+			retval = arm920t_write_cp15_physical(target,
+					address, value);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't access reg %i", address);
+				command_print(CMD_CTX,
+					"couldn't access reg %i", address);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
+			command_print(CMD_CTX, "%i: %8.8" PRIx32,
+					address, value);
 		}
 	}
 
@@ -1436,11 +1546,14 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 
 	if (target->state != TARGET_HALTED)
 	{
-		command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
+		command_print(CMD_CTX, "target must be stopped for "
+				"\"%s\" command", CMD_NAME);
 		return ERROR_OK;
 	}
 
-	/* one or more argument, access a single register (write if second argument is given */
+	/* one argument, read a register.
+	 * two arguments, write it.
+	 */
 	if (CMD_ARGC >= 1)
 	{
 		uint32_t opcode;
@@ -1449,24 +1562,36 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 		if (CMD_ARGC == 1)
 		{
 			uint32_t value;
-			if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
+			retval = arm920t_read_cp15_interpreted(target,
+					opcode, 0x0, &value);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
+				command_print(CMD_CTX,
+					"couldn't execute %8.8" PRIx32,
+					opcode);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
 
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
+			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
+					opcode, value);
 		}
 		else if (CMD_ARGC == 2)
 		{
 			uint32_t value;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
-			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
+			retval = arm920t_write_cp15_interpreted(target,
+					opcode, value, 0);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
+				command_print(CMD_CTX,
+					"couldn't execute %8.8" PRIx32,
+					opcode);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
+			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32,
+					opcode, value);
 		}
 		else if (CMD_ARGC == 3)
 		{
@@ -1474,17 +1599,23 @@ COMMAND_HANDLER(arm920t_handle_cp15i_command)
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 			uint32_t address;
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
-			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
+			retval = arm920t_write_cp15_interpreted(target,
+					opcode, value, address);
+			if (retval != ERROR_OK)
 			{
-				command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
+				command_print(CMD_CTX,
+					"couldn't execute %8.8" PRIx32, opcode);
+				/* REVISIT why lie? "return retval"? */
 				return ERROR_OK;
 			}
-			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
+			command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32
+					" %8.8" PRIx32, opcode, value, address);
 		}
 	}
 	else
 	{
-		command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
+		command_print(CMD_CTX,
+			"usage: arm920t cp15i <opcode> [value] [address]");
 	}
 
 	return ERROR_OK;
@@ -1500,7 +1631,8 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD_CTX,
+			&arm920t->armv4_5_mmu.armv4_5_cache);
 }
 
 

commit 57d5673dea2111d68a5266f23f6b6bacec38014e
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 20 20:47:38 2010 -0800

    CSB337 board cleanup (quasi-regression)
    
    Get rid of new nasty warning:
    
    NOTE! Severe performance degradation without fast memory access enabled...
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/board/csb337.cfg b/tcl/board/csb337.cfg
index de19660..b7bce48 100644
--- a/tcl/board/csb337.cfg
+++ b/tcl/board/csb337.cfg
@@ -113,3 +113,5 @@ proc csb337_reset_init { } {
 }
 
 $_TARGETNAME configure -event reset-init {csb337_reset_init}
+
+arm7_9 fast_memory_access enable

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm920t.c |  362 ++++++++++++++++++++++++++++++++++----------------
 tcl/board/csb337.cfg |    2 +
 2 files changed, 249 insertions(+), 115 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc2-8-gd2a2c14

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit d2a2c14d202da736e2c820c26d6deceee4e1e530
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 20 11:11:43 2010 -0800

    FreeBSD buildfix
    
    Fix an unused variable warning seen when building the parport driver
    under FreeBSD.
    
    Using information from Xiaofan Chen <xia...@gm...>
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index a38ccfd..fa3373b 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -265,7 +265,6 @@ static int parport_init(void)
 	struct cable *cur_cable;
 #if PARPORT_USE_PPDEV == 1
 	char buffer[256];
-	int i = 0;
 #endif
 
 	cur_cable = cables;
@@ -323,7 +322,8 @@ static int parport_init(void)
 	LOG_DEBUG("...open");
 
 #if !defined(__FreeBSD__) && !defined(__FreeBSD_kernel__)
-	i = ioctl(device_handle, PPCLAIM);
+	int i = ioctl(device_handle, PPCLAIM);
+
 	if (i < 0)
 	{
 		LOG_ERROR("cannot claim device");

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/parport.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 3f30563c88fcf02a8a8e671d817299adfda628ec
Author: Marc Pignat <mar...@he...>
Date:   Tue Feb 16 10:08:18 2010 +0100

    atm920t : fix breakpoints and data cache handling
    
    Breakpoints did not work because the data cache was not flushed
    properly.
    
    As a bonus add capability to write to memory marked as read only
    by the MMU, which allows software breakpoints in such memory
    regions.

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 3b75ca9..7cc228d 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -559,34 +559,120 @@ static int arm920t_write_phys_memory(struct target *target,
 
 
 /** Writes a buffer, in the specified word size, with current MMU settings. */
-int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm920t_write_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	int retval;
+	const uint32_t cache_mask = ~0x1f; /* cache line size : 32 byte */
+	struct arm920t_common *arm920t = target_to_arm920(target);
 
-	if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
-		return retval;
-
-	/* This fn is used to write breakpoints, so we need to make sure
-	 * that the data cache is flushed and the instruction cache is
-	 * invalidated
-	 */
-	if (((size == 4) || (size == 2)) && (count == 1))
+	/* FIX!!!! this should be cleaned up and made much more general. The
+	 * plan is to write up and test on arm920t specifically and
+	 * then generalize and clean up afterwards. */
+	if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
 	{
-		struct arm920t_common *arm920t = target_to_arm920(target);
+		/* special case the handling of single word writes to bypass MMU
+		 * to allow implementation of breakpoints in memory marked read only
+		 * by MMU */
+		int type;
+		uint32_t cb;
+		int domain;
+		uint32_t ap;
+		uint32_t pa;
+
+		/*
+		 * We need physical address and cb
+		 */
+		pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
+		if (type == -1)
+		{
+			return pa;
+		}
 
 		if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 		{
-			LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
-			/* MCR p15,0,Rd,c7,c10,2 */
-			retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
-			if (retval != ERROR_OK)
-				return retval;
+			if (cb & 0x1)
+			{
+				LOG_DEBUG("D-Cache buffered, drain write buffer");
+				/*
+				 * Buffered ?
+				 * Drain write buffer - MCR p15,0,Rd,c7,c10,4
+				 */
+
+				retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 10, 4), 0x0, 0);
+				if (retval != ERROR_OK)
+					return retval;
+			}
+
+			if (cb == 0x3)
+			{
+				/*
+				 * Write back memory ? -> clean cache
+				 *
+				 * There is no way for cleaning a data cache line using
+				 * cp15 scan chain, so copy the full cache line from
+				 * cache to physical memory.
+				 */
+				uint8_t data[32];
+
+				LOG_DEBUG("D-Cache in 'write back' mode, flush cache line");
+
+				retval = target_read_memory(target, address & cache_mask, 1, sizeof(data), &data[0]);
+				if (retval != ERROR_OK)
+					return retval;
+
+				retval = armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa & cache_mask, 1, sizeof(data), &data[0]);
+				if (retval != ERROR_OK)
+					return retval;
+			}
+
+			/* Cached ? */
+			if (cb & 0x2)
+			{
+				/*
+				 * Cached ? -> Invalidate data cache using MVA
+				 *
+				 * MCR p15,0,Rd,c7,c6,1
+				 */
+				LOG_DEBUG("D-Cache enabled, invalidate cache line");
+
+				retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0, address & cache_mask);
+				if (retval != ERROR_OK)
+					return retval;
+			}
 		}
 
-		if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+		/* write directly to physical memory bypassing any read only MMU bits, etc. */
+		retval = armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
+		if (retval != ERROR_OK)
+			return retval;
+	} else
+	{
+		if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
+			return retval;
+	}
+
+	/* If ICache is enabled, we have to invalidate affected ICache lines
+	 * the DCache is forced to write-through, so we don't have to clean it here
+	 */
+	if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+	{
+		if (count <= 1)
 		{
+			/* invalidate ICache single entry with MVA
+			 * 	ee070f35 	mcr	15, 0, r0, cr7, cr5, {1}
+			 */
 			LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
-			retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
+			retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 1), 0x0, address & cache_mask);
+			if (retval != ERROR_OK)
+				return retval;
+		}
+		else
+		{
+			/* invalidate ICache
+			 *   8:	ee070f15 	mcr	15, 0, r0, cr7, cr5, {0}
+			 * */
+			retval = arm920t_write_cp15_interpreted(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 0), 0x0, 0x0);
 			if (retval != ERROR_OK)
 				return retval;
 		}

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm920t.c |  120 +++++++++++++++++++++++++++++++++++++++++++-------
 1 files changed, 103 insertions(+), 17 deletions(-)


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- Log -----------------------------------------------------------------
commit aa8db989b90766f4aefe72f96c1c0a37d27d1369
Author: David Brownell <dbr...@us...>
Date:   Tue Feb 16 18:50:16 2010 -0800

    ARM920T scanchain 15 comments/cleanup
    
    For folk who don't know the ARM920 JTAG interface very well, the
    two modes of scan chain 15 access to CP15 are confusing.
    
    Make those parts of the ARM920 code less opaque, by:
    
     - Adding comments referencing the relevant parts of the TRM,
       catching up to similar updates in the User's Guide.
    
     - Replacing magic numbers in physical access clients with
       symbolic equivalents.
    
    No functional change.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e04d9fc..3b75ca9 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -42,7 +42,8 @@
  *   6 ... ETM9
  *   15 ... access coprocessor 15, "physical" or "interpreted" modes
  *	"interpreted" works with a few actual MRC/MCR instructions
- *	"physical" provides register-like behaviors.
+ *	"physical" provides register-like behaviors.  Section 9.6.7
+ *	covers these details.
  *
  * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
  */
@@ -51,8 +52,33 @@
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
+/* Table 9-8 shows scan chain 15 format during physical access mode, using a
+ * dedicated 6-bit address space (encoded in bits 33:38).  Writes use one
+ * JTAG scan, while reads use two.
+ *
+ * Table 9-9 lists the thirteen registers which support physical access.
+ * ARM920T_CP15_PHYS_ADDR() constructs the 6-bit reg_addr parameter passed
+ * to arm920t_read_cp15_physical() and arm920t_write_cp15_physical().
+ *
+ *  x == bit[38]
+ *  y == bits[37:34]
+ *  z == bit[33]
+ */
 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
 
+/* Registers supporting physical Read access (from table 9-9) */
+#define CP15PHYS_CACHETYPE	ARM920T_CP15_PHYS_ADDR(0, 0x0, 1)
+#define CP15PHYS_ICACHE_IDX	ARM920T_CP15_PHYS_ADDR(1, 0xd, 1)
+#define CP15PHYS_DCACHE_IDX	ARM920T_CP15_PHYS_ADDR(1, 0xe, 1)
+/* NOTE: several more registers support only physical read access */
+
+/* Registers supporting physical Read/Write access (from table 9-9) */
+#define CP15PHYS_CTRL		ARM920T_CP15_PHYS_ADDR(0, 0x1, 0)
+#define CP15PHYS_PID		ARM920T_CP15_PHYS_ADDR(0, 0xd, 0)
+#define CP15PHYS_TESTSTATE	ARM920T_CP15_PHYS_ADDR(0, 0xf, 0)
+#define CP15PHYS_ICACHE		ARM920T_CP15_PHYS_ADDR(1, 0x1, 1)
+#define CP15PHYS_DCACHE		ARM920T_CP15_PHYS_ADDR(1, 0x2, 1)
+
 static int arm920t_read_cp15_physical(struct target *target,
 		int reg_addr, uint32_t *value)
 {
@@ -153,6 +179,13 @@ static int arm920t_write_cp15_physical(struct target *target,
 	return ERROR_OK;
 }
 
+/* See table 9-10 for scan chain 15 format during interpreted access mode.
+ * If the TESTSTATE register is set for interpreted access, certain CP15
+ * MRC and MCR instructions may be executed through scan chain 15.
+ *
+ * Tables 9-11, 9-12, and 9-13 show which MRC and MCR instructions can be
+ * executed using scan chain 15 interpreted mode.
+ */
 static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 		uint32_t arm_opcode)
 {
@@ -225,17 +258,17 @@ static int arm920t_read_cp15_interpreted(struct target *target,
 
 	/* read-modify-write CP15 test state register
 	* to enable interpreted access mode */
-	arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	jtag_execute_queue();
 	cp15c15 |= 1;	/* set interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* execute CP15 instruction and ARM load (reading from coprocessor) */
 	arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 
 	/* disable interpreted access mode */
 	cp15c15 &= ~1U;	/* clear interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* retrieve value from R0 */
 	regs_p[0] = value;
@@ -271,17 +304,17 @@ int arm920t_write_cp15_interpreted(struct target *target,
 
 	/* read-modify-write CP15 test state register
 	* to enable interpreted access mode */
-	arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	jtag_execute_queue();
 	cp15c15 |= 1;	/* set interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* execute CP15 instruction and ARM store (writing to coprocessor) */
 	arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 
 	/* disable interpreted access mode */
 	cp15c15 &= ~1U;	/* set interpret mode */
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
@@ -314,7 +347,7 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, i
 	uint32_t cp15_control;
 
 	/* read cp15 control register */
-	arm920t_read_cp15_physical(target, 0x2, &cp15_control);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
 	jtag_execute_queue();
 
 	if (mmu)
@@ -326,7 +359,7 @@ void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, i
 	if (i_cache)
 		cp15_control &= ~0x1000U;
 
-	arm920t_write_cp15_physical(target, 0x2, cp15_control);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
 }
 
 // EXPORTED to FA256
@@ -335,7 +368,7 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, in
 	uint32_t cp15_control;
 
 	/* read cp15 control register */
-	arm920t_read_cp15_physical(target, 0x2, &cp15_control);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_control);
 	jtag_execute_queue();
 
 	if (mmu)
@@ -347,7 +380,7 @@ void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, in
 	if (i_cache)
 		cp15_control |= 0x1000U;
 
-	arm920t_write_cp15_physical(target, 0x2, cp15_control);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_control);
 }
 
 // EXPORTED to FA256
@@ -357,7 +390,8 @@ void arm920t_post_debug_entry(struct target *target)
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
 	/* examine cp15 control reg */
-	arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
+	arm920t_read_cp15_physical(target,
+			CP15PHYS_CTRL, &arm920t->cp15_control_reg);
 	jtag_execute_queue();
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
 
@@ -365,7 +399,8 @@ void arm920t_post_debug_entry(struct target *target)
 	{
 		uint32_t cache_type_reg;
 		/* identify caches */
-		arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_CACHETYPE, &cache_type_reg);
 		jtag_execute_queue();
 		armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 	}
@@ -387,10 +422,12 @@ void arm920t_post_debug_entry(struct target *target)
 	{
 		/* read-modify-write CP15 test state register
 		 * to disable I/D-cache linefills */
-		arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_TESTSTATE, &cp15c15);
 		jtag_execute_queue();
 		cp15c15 |= 0x600;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 }
 
@@ -410,10 +447,12 @@ void arm920t_pre_restore_context(struct target *target)
 	* to reenable I/D-cache linefills */
 	if (arm920t->preserve_cache)
 	{
-		arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_TESTSTATE, &cp15c15);
 		jtag_execute_queue();
 		cp15c15 &= ~0x600U;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 }
 
@@ -720,17 +759,17 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 		regs_p[i] = &regs[i];
 
 	/* disable MMU and Caches */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
 	cp15_ctrl_saved = cp15_ctrl;
 	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl);
 
 	/* read CP15 test state register */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	jtag_execute_queue();
 
 	/* read DCache content */
@@ -747,17 +786,20 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* D CAM Read, loads current victim into C15.C.D.Ind */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 
 		/* read current victim */
-		arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
+		arm920t_read_cp15_physical(target,
+				CP15PHYS_DCACHE_IDX, &C15_C_D_Ind);
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		for (index = 0; index < 64; index++)
 		{
@@ -767,7 +809,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* set interpret mode */
 			cp15c15 |= 0x1;
-			arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* Write DCache victim */
 			arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
@@ -780,7 +823,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* clear interpret mode */
 			cp15c15 &= ~0x1;
-			arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* read D RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
@@ -809,14 +853,16 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write DCache victim */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 
 	/* read ICache content */
@@ -833,17 +879,20 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* I CAM Read, loads current victim into C15.C.I.Ind */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 
 		/* read current victim */
-		arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
+		arm920t_read_cp15_physical(target, CP15PHYS_ICACHE_IDX,
+				&C15_C_I_Ind);
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		for (index = 0; index < 64; index++)
 		{
@@ -853,7 +902,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* set interpret mode */
 			cp15c15 |= 0x1;
-			arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* Write ICache victim */
 			arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
@@ -866,7 +916,8 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 			/* clear interpret mode */
 			cp15c15 &= ~0x1;
-			arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+			arm920t_write_cp15_physical(target,
+					CP15PHYS_TESTSTATE, cp15c15);
 
 			/* read I RAM and CAM content */
 			arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
@@ -894,18 +945,20 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write ICache victim */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 	}
 
 	/* restore CP15 MMU and Cache settings */
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
 
 	command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
 
@@ -972,17 +1025,17 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 		regs_p[i] = &regs[i];
 
 	/* disable MMU and Caches */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
+	arm920t_read_cp15_physical(target, CP15PHYS_CTRL, &cp15_ctrl);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
 	}
 	cp15_ctrl_saved = cp15_ctrl;
 	cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl);
 
 	/* read CP15 test state register */
-	arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
+	arm920t_read_cp15_physical(target, CP15PHYS_TESTSTATE, &cp15c15);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
 		return retval;
@@ -993,14 +1046,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 	/* set interpret mode */
 	cp15c15 |= 0x1;
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* Read D TLB lockdown */
 	arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
 
 	/* clear interpret mode */
 	cp15c15 &= ~0x1;
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* read D TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
@@ -1019,7 +1072,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write D TLB lockdown */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
@@ -1029,7 +1083,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read D TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
@@ -1051,7 +1106,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write D TLB lockdown */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
@@ -1064,7 +1120,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read D TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
@@ -1089,14 +1146,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 	/* set interpret mode */
 	cp15c15 |= 0x1;
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* Read I TLB lockdown */
 	arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
 
 	/* clear interpret mode */
 	cp15c15 &= ~0x1;
-	arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+	arm920t_write_cp15_physical(target, CP15PHYS_TESTSTATE, cp15c15);
 
 	/* read I TLB lockdown stored to r1 */
 	arm9tdmi_read_core_regs(target, 0x2, regs_p);
@@ -1115,7 +1172,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write I TLB lockdown */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
@@ -1125,7 +1183,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read I TLB CAM content stored to r2-r9 */
 		arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
@@ -1147,7 +1206,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* set interpret mode */
 		cp15c15 |= 0x1;
-		arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* Write I TLB lockdown */
 		arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
@@ -1160,7 +1220,8 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 
 		/* clear interpret mode */
 		cp15c15 &= ~0x1;
-		arm920t_write_cp15_physical(target, 0x1e, cp15c15);
+		arm920t_write_cp15_physical(target,
+				CP15PHYS_TESTSTATE, cp15c15);
 
 		/* read I TLB RAM content stored to r2 and r3 */
 		arm9tdmi_read_core_regs(target, 0xc, regs_p);
@@ -1181,7 +1242,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 	arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
 
 	/* restore CP15 MMU and Cache settings */
-	arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
+	arm920t_write_cp15_physical(target, CP15PHYS_CTRL, cp15_ctrl_saved);
 
 	/* output data to file */
 	fprintf(output, "D TLB content:\n");

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm920t.c |  163 ++++++++++++++++++++++++++++++++++----------------
 1 files changed, 112 insertions(+), 51 deletions(-)


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-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc2-5-gfa1cfc2

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  fa1cfc2d4da808f752518d3221619bc2e1ea628b (commit)
      from  58699923148fa1e0bc3eee4308e351cedecf296a (commit)

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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit fa1cfc2d4da808f752518d3221619bc2e1ea628b
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Feb 15 13:41:08 2010 +0100

    gpl: fix GPL startup message
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/helper/options.c b/src/helper/options.c
index 63c5b05..3a95df4 100644
--- a/src/helper/options.c
+++ b/src/helper/options.c
@@ -190,7 +190,7 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[])
 
 	if (help_flag)
 	{
-		LOG_OUTPUT("Open On-Chip Debugger\n(c) 2005-2008 by Dominic Rath\n\n");
+		LOG_OUTPUT("Open On-Chip Debugger\nLicensed under GNU GPL v2\n");
 		LOG_OUTPUT("--help       | -h\tdisplay this help\n");
 		LOG_OUTPUT("--version    | -v\tdisplay OpenOCD version\n");
 		LOG_OUTPUT("--file       | -f\tuse configuration file <name>\n");
diff --git a/src/openocd.c b/src/openocd.c
index 1105d2a..a689d59 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -228,7 +228,8 @@ struct command_context *setup_command_handler(Jim_Interp *interp)
 	}
 	LOG_DEBUG("command registration: complete");
 
-	LOG_OUTPUT(OPENOCD_VERSION "\n");
+	LOG_OUTPUT(OPENOCD_VERSION "\n"
+			"Licensed under GNU GPL v2\n");
 
 	global_cmd_ctx = cmd_ctx;
 

-----------------------------------------------------------------------

Summary of changes:
 src/helper/options.c |    2 +-
 src/openocd.c        |    3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc2-4-g5869992

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  58699923148fa1e0bc3eee4308e351cedecf296a (commit)
      from  52d4ba3467134a1489583dbb6d6de3002f0f76fa (commit)

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- Log -----------------------------------------------------------------
commit 58699923148fa1e0bc3eee4308e351cedecf296a
Author: David Brownell <dbr...@us...>
Date:   Mon Feb 15 13:39:16 2010 -0800

    LPC1768.cfg -- partial fixes for bogus reset-init handler
    
    Cortex-M targets don't support ARM instructions.
    
    Leave the NVIC.VTOR setup alone, but comment how the whole
    routine looks like one big bug...
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/target/lpc1768.cfg b/tcl/target/lpc1768.cfg
index 9a813f5..f0093ad 100644
--- a/tcl/target/lpc1768.cfg
+++ b/tcl/target/lpc1768.cfg
@@ -33,11 +33,11 @@ target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNA
 # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
 
+# REVISIT is there any good reason to have this reset-init event handler??
+# Normally they should set up (board-specific) clocking then probe the flash...
 $_TARGETNAME configure -event reset-init {
-	# Force target into ARM state
-	arm core_state arm
-	#do not remap 0x0000-0x0020 to anything but the flash
-#	mwb 0xE01FC040 0x01
+	# Force NVIC.VTOR to point to flash at 0 ...
+	# WHY?  This is it's reset value; we run right after reset!!
 	mwb 0xE000ED08 0x00
 }
 

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/lpc1768.cfg |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


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The branch, master has been updated
       via  52d4ba3467134a1489583dbb6d6de3002f0f76fa (commit)
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- Log -----------------------------------------------------------------
commit 52d4ba3467134a1489583dbb6d6de3002f0f76fa
Author: Mathias Kuester <mk...@us...>
Date:   Sun Feb 14 12:59:10 2010 -0800

    fix crash with DSP563XX
    
    When a DSP563xx-aware GDB asks OpenOCD for target registers,
    the result should be a GDB with register data ... not an
    OpenOCD crash.
    
    (Note that mainline GDB doesn't currently support this core,
    so for now, this requires a GDB with FreeScale patches.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 9e2f609..049ee1a 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -246,6 +246,29 @@ static const struct
 	/* *INDENT-ON* */
 };
 
+static int dsp563xx_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
+			      int *reg_list_size)
+{
+	struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
+	int i;
+
+	if (target->state != TARGET_HALTED)
+	{
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	*reg_list_size = DSP563XX_NUMCOREREGS;
+	*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+
+	for (i = 0; i < DSP563XX_NUMCOREREGS; i++)
+	{
+		(*reg_list)[i] = &dsp563xx->core_cache->reg_list[i];
+	}
+
+	return ERROR_OK;
+
+}
+
 int dsp563xx_read_core_reg(struct target *target, int num)
 {
 	uint32_t reg_value;
@@ -974,6 +997,8 @@ struct target_type dsp563xx_target = {
 
 	.target_request_data = NULL,
 
+	.get_gdb_reg_list = dsp563xx_get_gdb_reg_list,
+
 	.halt = dsp563xx_halt,
 	.resume = dsp563xx_resume,
 	.step = dsp563xx_step,

-----------------------------------------------------------------------

Summary of changes:
 src/target/dsp563xx.c |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)


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commit a2ce3a51dfbc9760e7a4e3f5d5806a1de019721d
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 13 20:14:49 2010 -0800

    NEWS: mention removal of obsolete commands
    
    Removed remaining support for various commands, like advice for
    migrating old-style TAP declarations.
    
    The documentation no longer describes them either ... so if users have
    been delaying config updates, they may need to consult older releases.
    
    ALL this stuff has been clearly marked as "do not use" for at least a
    year now, so anyone still using it hasn't been holding up their end.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWS b/NEWS
index f7bf1d3..cbd5526 100644
--- a/NEWS
+++ b/NEWS
@@ -11,6 +11,8 @@ Boundary Scan:
 
 Target Layer:
 	General
+		- Removed commands which have been obsolete for at least
+		  a year (from both documentation and, sometimes, code).
 		- new "reset-assert" event, for systems without SRST
 	ARM
 		- supports "reset-assert" event (except on Cortex-M3)

-----------------------------------------------------------------------

Summary of changes:
 NEWS |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)


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commit 4c4ec09110db0cb89a6692093aa6579a85fc3552
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 13 15:28:05 2010 -0800

    Restore "-dev" version suffix (0.4.0-rc2-dev)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/configure.in b/configure.in
index a08085b..65d7369 100644
--- a/configure.in
+++ b/configure.in
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.4.0-rc2],
+AC_INIT([openocd], [0.4.0-rc2-dev],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

commit a0a1be5cd69a412c55af14be6c6250cb85b652cd
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 13 14:47:17 2010 -0800

    v4.0-rc2 milestone
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/configure.in b/configure.in
index ecc9c6d..a08085b 100644
--- a/configure.in
+++ b/configure.in
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.4.0-rc1-dev],
+AC_INIT([openocd], [0.4.0-rc2],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

-----------------------------------------------------------------------

Summary of changes:
 configure.in |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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[openocd-svn] Main OpenOCD repository annotated tag, v0.4.0-rc2, created. v0.4.0-rc2

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   tagging  a0a1be5cd69a412c55af14be6c6250cb85b652cd (commit)
  replaces  v0.4.0-rc1
 tagged by  David Brownell
        on  Sat Feb 13 14:48:37 2010 -0800

- Log -----------------------------------------------------------------
RC2 -- hope this is a brief cycle

Alex Austin (1):
      Clang buildfixes

Andreas Fritiofson (1):
      update win32 script search path

Antonio Borneo (6):
      PARPORT code cleanup:
      Fix parport_dcl5 config file.
      ARM9TDMI: Fix segfault.
      whitespace cleanup, mostly for docs
      ARM7_9: Fix segfaults
      Added ST FlashLINK interface config file.

Catalin Patulea (1):
      Driver for USB-JTAG, Altera USB-Blaster and compatibles

David Brownell (104):
      Restore "-dev" version suffix
      cygwin 1.7 build fixes
      NOR: Allocate the right amount of memory
      NOR: messaging fix
      User's Guide: update GDB info
      ARM: add comment re register exports
      NOR: make flash_write_unlock() pad to sector end
      create tcl/board/dm365evm.cfg
      Fix Luminary FT2232 layout docs/configs
      User's Guide: warn about the forum
      streamline and document helptext mode displays
      Cortex-M3: minor breakpoint cleanup
      ARM: ADIv5 symbol and comment cleanup
      ARM: ADIv5 export cleanup
      ARM: dap info fix + tweaks
      ARM: ADIv5 JTAG symbol cleanup
      JTAG/drivers: amt_jtagaccel fixes + cleanup
      JTAG/drivers: cleanup jtag_interface structs
      JTAG: Amontec JTAG accelerater "rtck" is back
      JTAG/Drivers: Amontec JTAG accelerator fixes
      JTAG/drivers: ft2232 docs
      FT2232: fix doc typo
      ARMv7-M:  use AP_REG_* symbol
      ARM: add comments re DAP assumptions
      ARM: add #defines for JTAG ack codes
      don't require 'openocd.cfg' to start
      buildfix with -DNDEBUG
      XScale: help/usage updates
      target misc: help/usage updates
      ARM ETM/ETB/trace: help/usage updates
      ARMv7: help/usage updates
      ARM7/ARM9: help/usage updates
      ARM11: help/usage updates
      ARM720: help/usage updates
      ARM720: help/usage updates
      Xscale: User's Guide updates
      ARM966: help/usage updates
      misc ARM help/usage updates
      NOR: add FIXMEs for writing ones
      Coexist with quilt: rename PATCHES --> PATCHES.txt
      MFLASH: help/usage updates
      *SVF: help/usage updates
      Doc/examples: clarify usage messages
      NAND: help/usage/doc updates
      PLD: usage/help updates
      src/server: usage/help/doc updates
      src/flash/nor: usage/help/doc updates
      src/helper: usage/help updates
      parport (mostly) doc fixes
      jtag/gw16012 usage/help updates
      jtag: presto, parport help/usage updates
      ZY1000 help/usage fixups
      jtag/tcl help/usage fixups
      Presto: doxygen fix
      FreeBSD build fixes
      Doxygen file comments
      ARM: bugfix for "movt" disassembly
      Cortex-M3: improved core exception handling
      NOR: add optional "flash erase_address" sector padding
      User's Guide updates
      ARM7/9 minor cleanups
      ARM7/ARM9: improved reset support
      ARM ADIv5: add comments
      jtag.h whitespace/comment cleanup
      NEWS: include s3c64xx NAND driver
      ARM DPM: disable some nyet-ready breakpoint code
      ADIv5 improved diagnostic
      vsllink -- add comment
      NOR: fix diagnostic
      gdb_server -- symbol cleanup
      gdb_server -- subroutinize memory map logic
      User's guide: mention lpc2000 checksum issue
      gdb_server: correctly report flash sector sizes
      board configs -- unique names for flash chips
      Cortex-M3 vector_catch testing support
      ADIv5 header cleanup (+ #defines)
      User's Guide secton on target hardware setup
      Various doc/comment updates
      ARM11: fix breakpoints with GDB
      NEWS updates
      EmbeddedICE - fix Feroceon/Dragonite message
      cygwin buildfix
      various: don't mention wiki
      Cortex-A8: debug messaging tweaks
      ARM ADIv5: messaging tweaks
      Cortex-M3: report lockup, and recover
      ARM: reference DPM defn from v6/v7 arch spec
      doc clarifications for server flags
      NOR: cleanup driver decls
      ARMv7-M: use command handler for "dap baseaddr".
      ADIv5: cleanup, rename swjdp_transaction_endcheck()
      ARM ADIv5: fix diagnostics for block writes
      ADIv5 error checking for Tcl commands
      Subject: ADIv5: fix more diagnostics
      ADIv5: more messaging cleanup, docs
      NOR: User's Guide updates
      JLink: reference protocol documentation
      Documentation: mention bug database
      ARMv7-M: make DAP commands verify target is an ARMv7-M
      ADIv5: doxygen
      Re-title Developer's Guide
      User's Guide: clarify jtag_rclk advice
      User's Guide: "#" in filesystems names is bad
      v4.0-rc2 milestone

David Claffey (1):
      MIPS: merge mips fast_data patch from David N. Claffey

Dean Glazeski (4):
      Olimex SAM9-L9260 board configuration update.
      Remove some more Eclipse stuff from Git's eyes.
      Add the current command to the command information
      Fix usage/help search for subcommands.

Edgar Grimberg (6):
      target: Fixed format problem for mdh
      interface: Changed parport address to LPT1
      core arm11: Silence logs at level 3 if there is no activity
      Test cases ran on v0.4.0-rc1
      flash/str7x: After reset init the flash is unlocked
      tcl/str7x: Reset init unlocks the flash

Ethan Eade (1):
      scripts: Phytec/LPC2350 config scripts

Freddie Chopin (2):
      stm32x commands get "usage"
      MinGW build fixes

Harald Kipp (1):
      AT91R40008/Ethernut 3 configuration

Johannes Stezenbach (1):
      update udev rules for new udev version

Laurentiu Cocanu (1):
      str9x.c: remove optimization when erasing the whole bank

Marc Pignat (1):
      arm920: add virt2phys fn

Masaki Muranaka (1):
      buildfix on MacOS

Michael Grzeschik (1):
      tcl/target/at91sam3u4e.cfg: changed case in dependent file

Nicolas Pitre (1):
      ARM semihosting: fix EOF handling with SYS_READ

Peter Korsgaard (1):
      nand flash support for s3c64xx

Piotr Esden-Tempski (3):
      NOR: last_addr also needs correction when checking alignment
      Added floss-jtag interface config file.
      Added Open-BLDC board config file.

Spencer Oliver (19):
      parport: output port as hex rather than dec
      MIPS: optimize pracc access
      PIC32: enable ram execution
      MIPS: pracc access tweaks
      MIPS: fastdata bulk write fallback
      MIPS: whitespace cleanup
      MIPS: change bulk_write_memory fallback msg to LOG_DEBUG
      MIPS: update arch_info access to match other targets
      build: doxygen build
      GDB: change gdb_breakpoint_override to COMMAND_ANY
      ARMV7M: handle bkpt instruction on resume/step
      BUILD: remove cygwin gcc 3.4.4 build warnings
      ARM semihosting: fix writing to stdout
      ARM semihosting: win32 and cygwin fixes
      JTAG: fix bug when no interface connected
      CMD: duplicate cmd error msg
      str730.cfg: fix incorrect mem regions
      STM32x: issue warning when unlocking device (bug #16)
      STR9xpec: issue warning when unlocking device

Viktar Palstsiuk (1):
      target library: configuration files for openocd tested with Atmel SAM-ICE V6 JTAG.

Vladimir Zapolskiy (1):
      Added Openmoko USB JTAG interface config file.

richard vegh (1):
      NAND: lpc3180 crashes on LPC3250

simon qian (3):
      read target voltage first in vsllink
      SVF: insert space before '(' and after ')'
      SVF: all content between parentheses is one parameter

Øyvind Harboe (32):
      zy1000: less warnings
      zy1000: firmware upgrade fixes for revc
      zy1000: reconfigure FPGA upon reset instead of just the CPU
      zy1000: unlock flash upon startup for revc
      zy1000: add zy1000_ prefix to uart command
      gdb: fix regression in gdb_port command
      shutdown: more graceful shutdown
      zy1000: reset bugfix
      commands: make error messages a bit more terse
      reset: better error messages
      target: return JIM_OK instead of ERROR_OK
      debug: make logging of commands terser
      gdbserver: fix typo that broke read/write watchpoint
      target: add check_reset hook
      arm7/9: add fn to check if dcc downloads have been enabled
      arm7/9: enable check that DCC downloads have been enabled
      commands: allow scan_chain command to be executed during config
      flash: add error messages upon incorrect arguments to flash iteration
      zy1000: print out PCB revision upon boot
      zy1000: flush jtag buffer before changing speed
      arm7/9: add nags upon reset about options to improve performance
      testing: fix str710 test case now builds
      ecos: add missing PRId8 definition
      gdb_server: handle stepi/continue packet while target is running with more grace
      target: print reason why GDB halts
      telnet: fix strage blank spaces at beginning of telnet lines
      build: fix problems with "struct stat" not being defined under eCos
      gdb: restore behavior from 0.3.1 for srst_asserted and power_restore
      zy1000: complete zy1000_uart to jim command switch
      target: add todo in target_write_memory() about alignment
      arm11: fix another infinite loop bug
      arm720t: virt2phys callback added

-----------------------------------------------------------------------


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- Log -----------------------------------------------------------------
commit f7a6e6277681f6e2702bb9d3e0176000bd09a402
Author: Spencer Oliver <nt...@us...>
Date:   Thu Feb 11 20:56:32 2010 +0000

    STR9xpec: issue warning when unlocking device
    
    Issue warning to user when unlocking or writing the option bytes.
    The new settings will not take effect until a target reset.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index f0e11a5..243336a 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -915,6 +915,10 @@ COMMAND_HANDLER(str9xpec_handle_flash_options_write_command)
 	if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
 		return ERROR_FLASH_OPERATION_FAILED;
 
+	command_print(CMD_CTX, "str9xpec write options complete.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
+
 	return ERROR_OK;
 }
 
@@ -1077,6 +1081,10 @@ COMMAND_HANDLER(str9xpec_handle_flash_unlock_command)
 	if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS)
 		return ERROR_FLASH_OPERATION_FAILED;
 
+	command_print(CMD_CTX, "str9xpec unlocked.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
+
 	return ERROR_OK;
 }
 

commit 747a607aef6572dad8740b76596f2b72036b8685
Author: Spencer Oliver <nt...@us...>
Date:   Thu Feb 11 20:55:31 2010 +0000

    STM32x: issue warning when unlocking device (bug #16)
    
    Issue warning to user when unlocking or writing the option bytes.
    The new settings will not take effect until a target reset.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index eaa3a0e..bfdd3cd 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -978,7 +978,9 @@ COMMAND_HANDLER(stm32x_handle_unlock_command)
 		return ERROR_OK;
 	}
 
-	command_print(CMD_CTX, "stm32x unlocked");
+	command_print(CMD_CTX, "stm32x unlocked.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
 
 	return ERROR_OK;
 }
@@ -1114,7 +1116,9 @@ COMMAND_HANDLER(stm32x_handle_options_write_command)
 		return ERROR_OK;
 	}
 
-	command_print(CMD_CTX, "stm32x write options complete");
+	command_print(CMD_CTX, "stm32x write options complete.\n"
+				"INFO: a reset or power cycle is required "
+				"for the new settings to take effect.");
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32x.c   |    8 ++++++--
 src/flash/nor/str9xpec.c |    8 ++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)


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      from  ff404da1558f0dcc5d92b18caa1706b9edf067d1 (commit)

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- Log -----------------------------------------------------------------
commit d4d4b11a778c169a23a99f03e9d61f6bf21002c2
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Feb 12 08:39:56 2010 +0100

    arm720t: virt2phys callback added
    
    This is a copy and paste of arm926ejs. Not tested, but
    ready for testing at least. There is a good chance that
    it will work if the generic armv4_5 fn's are robust enough...
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index a5dde2c..efafa5e 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -255,11 +255,21 @@ static int arm720_mmu(struct target *target, int *enabled)
 }
 
 static int arm720_virt2phys(struct target *target,
-		uint32_t virt, uint32_t *phys)
+		uint32_t virtual, uint32_t *physical)
 {
-	/** @todo Implement this!  */
-	LOG_ERROR("%s: not implemented", __func__);
-	return ERROR_FAIL;
+	int type;
+	uint32_t cb;
+	int domain;
+	uint32_t ap;
+	struct arm720t_common *arm720t = target_to_arm720(target);
+
+	uint32_t ret = armv4_5_mmu_translate_va(target, &arm720t->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
+	if (type == -1)
+	{
+		return ret;
+	}
+	*physical = ret;
+	return ERROR_OK;
 }
 
 static int arm720t_read_memory(struct target *target,

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm720t.c |   18 ++++++++++++++----
 1 files changed, 14 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit ff404da1558f0dcc5d92b18caa1706b9edf067d1
Author: Marc Pignat <mar...@he...>
Date:   Fri Feb 12 08:23:44 2010 +0100

    arm920: add virt2phys fn
    
    Copy of the 926ejs function. I have tested it only using
    my rtems application (where virtual address mapping == physical).
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e0b1c70..e04d9fc 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -472,9 +472,19 @@ static int arm920_mmu(struct target *target, int *enabled)
 static int arm920_virt2phys(struct target *target,
 		uint32_t virt, uint32_t *phys)
 {
-	/** @todo Implement this!  */
-	LOG_ERROR("%s: not implemented", __func__);
-	return ERROR_FAIL;
+	int type;
+	uint32_t cb;
+	int domain;
+	uint32_t ap;
+	struct arm920t_common *arm920t = target_to_arm920(target);
+
+	uint32_t ret = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, virt, &type, &cb, &domain, &ap);
+	if (type == -1)
+	{
+		return ret;
+	}
+	*phys = ret;
+	return ERROR_OK;
 }
 
 /** Reads a buffer, in the specified word size, with current MMU settings. */

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm920t.c |   16 +++++++++++++---
 1 files changed, 13 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit 32188c500468c117d2a79106ba9ae41d61ce1897
Author: Viktar Palstsiuk <vik...@pr...>
Date:   Thu Feb 11 21:09:21 2010 +0100

    target library: configuration files for openocd tested with Atmel SAM-ICE V6 JTAG.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/tcl/board/atmel_at91sam9rl-ek.cfg b/tcl/board/atmel_at91sam9rl-ek.cfg
new file mode 100644
index 0000000..3b932bf
--- /dev/null
+++ b/tcl/board/atmel_at91sam9rl-ek.cfg
@@ -0,0 +1,75 @@
+################################################################################
+#
+# Generated for Atmel AT91SAM9RL-EK evaluation board using Atmel SAM-ICE (J-Link) V6
+#
+# Atmel AT91SAM9RL : PLL = 200 MHz, MCK = 100 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9rl.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        mww phys 0xfffffd08 0xa5000501
+}
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x2031bf03         # CKGR_PLLR: Set PLL Register for 200 MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLL is selected (100 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xfffff670 0xffff0000         # PIO_ASR  : Select peripheral function for D16..D31 (PIOB)
+        mww 0xfffff604 0xffff0000         # PIO_PDR  : Disable PIO function for D16..D31 (PIOB)
+
+        mww 0xffffef20 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
+}
diff --git a/tcl/target/at91sam9rl.cfg b/tcl/target/at91sam9rl.cfg
new file mode 100644
index 0000000..6db1826
--- /dev/null
+++ b/tcl/target/at91sam9rl.cfg
@@ -0,0 +1,44 @@
+######################################
+# Target:    Atmel AT91SAM9RL
+######################################
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME at91sam9rl
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 300
+jtag_ntrst_delay 200
+
+jtag_rclk 3
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x10000 -work-area-backup 1
+
+

-----------------------------------------------------------------------

Summary of changes:
 ..._at91sam9260-ek.cfg => atmel_at91sam9rl-ek.cfg} |   22 +++++++------------
 tcl/target/{at91sam9260.cfg => at91sam9rl.cfg}     |    6 ++--
 2 files changed, 11 insertions(+), 17 deletions(-)
 copy tcl/board/{atmel_at91sam9260-ek.cfg => atmel_at91sam9rl-ek.cfg} (76%)
 copy tcl/target/{at91sam9260.cfg => at91sam9rl.cfg} (90%)


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- Log -----------------------------------------------------------------
commit 527e073bba3145235534a9273e85a714bf87f330
Author: David Brownell <dbr...@us...>
Date:   Wed Feb 10 16:42:37 2010 -0800

    User's Guide: "#" in filesystems names is bad
    
    Sometimes MS-Windows users try to use filesystem names which include
    the "#" character.  That's generally unwise, since it begins Tcl
    comments.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index c1c49a8..63b6ab0 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -539,6 +539,11 @@ Configuration files and scripts are searched for in
 @end enumerate
 The first found file with a matching file name will be used.
 
+@quotation Note
+Don't try to use configuration script names or paths which
+include the "#" character.  That character begins Tcl comments.  
+@end quotation
+
 @section Simple setup, no customization
 
 In the best case, you can use two scripts from one of the script
@@ -7633,12 +7638,15 @@ in the same basic way.
 @* Example: @b{ source [find FILENAME] }
 @*Remember the parsing rules
 @enumerate
-@item The FIND command is in square brackets.
-@* The FIND command is executed with the parameter FILENAME. It should
-find the full path to the named file. The RESULT is a string, which is
-substituted on the orginal command line.
-@item The command source is executed with the resulting filename.
-@* SOURCE reads a file and executes as a script.
+@item The @command{find} command is in square brackets,
+and is executed with the parameter FILENAME. It should find and return
+the full path to a file with that name; it uses an internal search path.
+The RESULT is a string, which is substituted into the command line in
+place of the bracketed @command{find} command.
+(Don't try to use a FILENAME which includes the "#" character.
+That character begins Tcl comments.)
+@item The @command{source} command is executed with the resulting filename;
+it reads a file and executes as a script.
 @end enumerate
 @subsection format command
 @b{Where:} Generally occurs in numerous places.

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)


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commit 65cc81ddb609456707c2ba47cfe8540192c6dce7
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Feb 10 20:04:00 2010 +0100

    arm11: fix another infinite loop bug
    
    reset init would get stuck in an infinite loop when
    e.g. khz was too high. Added timeout. This is a copy
    of paste of a number of such bugfixes in the arm11
    code.
    
    Arm11 code reviewed for further such infinite loop bugs
    and I couldn't find any more. Xing fingers it's the last
    one...
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 088981f..6d132a7 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -854,7 +854,9 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
 			AddressOut	= 0;
 		}
 
-		do
+		/* Timeout here so we don't get stuck. */
+		int i = 0;
+		while (1)
 		{
 			JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
 					(unsigned) AddressOut,
@@ -866,10 +868,27 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
 
 			CHECK_RETVAL(jtag_execute_queue());
 
-			if (!Ready)
-				JTAG_DEBUG("SC7 => !ready");
+			/* 'nRW' is 'Ready' on read out */
+			if (Ready)
+				break;
+
+			long long then = 0;
+
+			if (i == 1000)
+			{
+				then = timeval_ms();
+			}
+			if (i >= 1000)
+			{
+				if ((timeval_ms()-then) > 1000)
+				{
+					LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+					return ERROR_FAIL;
+				}
+			}
+
+			i++;
 		}
-		while (!Ready); /* 'nRW' is 'Ready' on read out */
 
 		if (!nRW)
 			JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn);

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11_dbgtap.c |   27 +++++++++++++++++++++++----
 1 files changed, 23 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit 84ac6bb0d99275ccf7ff15691ffa1b22127d7339
Author: David Brownell <dbr...@us...>
Date:   Wed Feb 10 11:27:48 2010 -0800

    User's Guide: clarify jtag_rclk advice
    
    Not all cores and boards support adaptive clocking, so qualify
    all advice to use it to depend on core and board support.
    
    It's primarily ARM cores which support this; and many of the
    newer ones (like Cortex-M series) don't.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index d4e60a8..c1c49a8 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1447,7 +1447,8 @@ Adaptive clocking provides a partial workaround, but a more complete
 solution just avoids using that instruction with JTAG debuggers.
 @end quotation
 
-If the board supports adaptive clocking, use the @command{jtag_rclk}
+If both the chip and the board support adaptive clocking,
+use the @command{jtag_rclk}
 command, in case your board is used with JTAG adapter which
 also supports it.  Otherwise use @command{jtag_khz}.
 Set the slow rate at the beginning of the reset sequence,
@@ -2387,7 +2388,8 @@ However, it introduces delays to synchronize clocks; so it
 may not be the fastest solution.
 
 @b{NOTE:} Script writers should consider using @command{jtag_rclk}
-instead of @command{jtag_khz}.
+instead of @command{jtag_khz}, but only for (ARM) cores and boards
+which support adaptive clocking.
 
 @deffn {Command} jtag_khz max_speed_kHz
 A non-zero speed is in KHZ. Hence: 3000 is 3mhz.

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


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commit c646b767971f5750b32f0bc8290a2eea351cb514
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Feb 9 21:54:55 2010 +0100

    target: add todo in target_write_memory() about alignment
    
    target_write_buffer() does not align "buffer" in host
    memory passed to target_write_memory().
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/target.h b/src/target/target.h
index da91d46..7400b7e 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007-9 Øyvind Harboe                                    *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -371,7 +371,18 @@ int target_read_memory(struct target *target,
 		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 /**
  * Write @a count items of @a size bytes to the memory of @a target at
- * the @a address given.
+ * the @a address given. @a address must be aligned to @a size
+ * in target memory.
+ *
+ * The endianness is the same in the host and target memory for this
+ * function.
+ *
+ * \todo TODO:
+ * Really @a buffer should have been defined as "const void *" and
+ * @a buffer should have been aligned to @a size in the host memory.
+ *
+ * This is not enforced via e.g. assert's today and e.g. the
+ * target_write_buffer fn breaks this assumption.
  *
  * This routine is wrapper for target->type->write_memory.
  */

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.h |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)


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commit f899c2aa9767ba7bf731e6c6c1af2c437af97dac
Author: Spencer Oliver <nt...@us...>
Date:   Tue Feb 9 14:49:47 2010 +0000

    str730.cfg: fix incorrect mem regions
    
     - update str73x mem regions to correct values.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index cab2338..0917953 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -46,9 +46,9 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
 	flash protect 0 0 7 off
 }
 
-$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+$_TARGETNAME configure -work-area-phys 0xA0000000 -work-area-size 0x4000 -work-area-backup 0
 
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR3x
+flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR3x
 

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/str730.cfg |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


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commit 885a2f5b96697e3aca9a5b9deb855d6d025c5021
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 6 19:19:25 2010 -0800

    Re-title Developer's Guide
    
    The Doxygen output was previously titled "OpenOCD Reference Manual",
    which was quite misleading ... the User's Guide is the reference
    manual which folk should consult about how to use the software.
    
    Just rename it to match how it's been discussed previously, and to
    bring out its intended audience:  developers of this software.  As a
    rule, Doxygen is only for folk who work with the code it documents.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/manual/main.txt b/doc/manual/main.txt
index 8e76464..2b6e7e1 100644
--- a/doc/manual/main.txt
+++ b/doc/manual/main.txt
@@ -1,6 +1,6 @@
-/** @mainpage OpenOCD Reference Manual
+/** @mainpage OpenOCD Developer's Guide
 
-Welcome to the OpenOCD Reference Manual -- the developer's resource for
+Welcome to the OpenOCD Developer's Guide -- the developer's resource for
 learning about the internal architecture of the OpenOCD project. @par
 
 In addition, this document contains the tactical and strategic plans

commit 6f262b69f407e5982be9858d66b5dda6835a2e28
Author: David Brownell <dbr...@us...>
Date:   Sat Feb 6 19:16:21 2010 -0800

    ADIv5: doxygen
    
    Provide doxygen for many of the public ADIv5 interfaces (i.e. the ones
    called from Cortex core support code).
    
    Add FIXMEs (and a TODO) to help resolve implementation issues which
    became more apparent when trying to document this code:
    
     - Error-prone context-sensitivity (queued/nonqueued) in many procedures.
    
     - Procedures that lie by ignoring errors and wrongly claiming success.
    
    Also, there was no point in a return from dap_ap_select(); it can't fail,
    and no caller checks its return status.  Clean that up, make it void.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 4089567..94c8ed8 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -42,6 +42,12 @@
  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
+ *
+ * @todo Remove modality (queued/nonqueued, via DAP trans_mode) from all
+ * procedure interfaces.  Modal programming interfaces are very error prone.
+ * Procedures should be either queued, or synchronous.  Otherwise input
+ * and output constraints are context-sensitive, and it's hard to know
+ * what a block of code will do just by reading it.
  */
 
 /*
@@ -402,7 +408,16 @@ static int dap_dp_read_reg(struct swjdp_common *swjdp,
 			reg_addr, DPAP_READ, 0, value);
 }
 
-int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
+/**
+ * Select one of the APs connected to the specified DAP.  The
+ * selection is implicitly used with future AP transactions.
+ * This is a NOP if the specified AP is already selected.
+ *
+ * @param swjdp The DAP
+ * @param apsel Number of the AP to (implicitly) use with further
+ *	transactions.  This normally identifies a MEM-AP.
+ */
+void dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 {
 	uint32_t select;
 	select = (apsel << 24) & 0xFF000000;
@@ -415,8 +430,6 @@ int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel)
 		swjdp->ap_csw_value = -1;
 		swjdp->ap_tar_value = -1;
 	}
-
-	return ERROR_OK;
 }
 
 static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
@@ -430,6 +443,7 @@ static int dap_dp_bankselect(struct swjdp_common *swjdp, uint32_t ap_reg)
 		swjdp->dp_select_value = select;
 	}
 
+	/* FIXME return any fault code from write() call */
 	return ERROR_OK;
 }
 
@@ -440,10 +454,25 @@ static int dap_ap_write_reg(struct swjdp_common *swjdp,
 	scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 			DPAP_WRITE, out_value_buf, NULL);
 
+	/* FIXME return fault code from above calls */
 	return ERROR_OK;
 }
 
-int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t value)
+/**
+ * Write an AP register value.
+ * This is synchronous iff the mode is set to ATOMIC, in which
+ * case any queued transactions are flushed.
+ *
+ * @param swjdp The DAP whose currently selected AP will be written.
+ * @param reg_addr Eight bit AP register address.
+ * @param value Word to be written at reg_addr
+ *
+ * @return In synchronous mode: ERROR_OK for success, and the register holds
+ * the specified value; else a fault code.  In asynchronous mode, a status
+ * code reflecting whether the transaction was properly queued.
+ */
+int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
+		uint32_t reg_addr, uint32_t value)
 {
 	uint8_t out_value_buf[4];
 
@@ -452,20 +481,39 @@ int dap_ap_write_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t
 	scan_inout_check(swjdp, JTAG_DP_APACC, reg_addr,
 			DPAP_WRITE, out_value_buf, NULL);
 
+	/* FIXME return any fault code from above calls */
 	return ERROR_OK;
 }
 
-int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t *value)
+/**
+ * Read an AP register value.
+ * This is synchronous iff the mode is set to ATOMIC, in which
+ * case any queued transactions are flushed.
+ *
+ * @param swjdp The DAP whose currently selected AP will be read.
+ * @param reg_addr Eight bit AP register address.
+ * @param value Points to where the 32-bit (little-endian) word will be stored.
+ *
+ * @return In synchronous mode: ERROR_OK for success, and *value holds
+ * the specified value; else a fault code.  In asynchronous mode, a status
+ * code reflecting whether the transaction was properly queued.
+ */
+int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
+		uint32_t reg_addr, uint32_t *value)
 {
 	dap_dp_bankselect(swjdp, reg_addr);
 	scan_inout_check_u32(swjdp, JTAG_DP_APACC, reg_addr,
 			DPAP_READ, 0, value);
 
+	/* FIXME return any fault code from above calls */
 	return ERROR_OK;
 }
 
 /**
  * Set up transfer parameters for the currently selected MEM-AP.
+ * This is synchronous iff the mode is set to ATOMIC, in which
+ * case any queued transactions are flushed.
+ *
  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
  * initiate data reads or writes using memory or peripheral addresses.
  * If the CSW is configured for it, the TAR may be automatically
@@ -478,6 +526,10 @@ int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t
  *	matches the cached value, the register is not changed.
  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
  *	matches the cached address, the register is not changed.
+ *
+ * @return In synchronous mode: ERROR_OK for success, and the AP is set
+ * up as requested else a fault code.  In asynchronous mode, a status
+ * code reflecting whether the transaction was properly queued.
  */
 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 {
@@ -485,12 +537,14 @@ int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 	if (csw != swjdp->ap_csw_value)
 	{
 		/* LOG_DEBUG("DAP: Set CSW %x",csw); */
+		/* FIXME if this call fails, fail this procedure! */
 		dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 		swjdp->ap_csw_value = csw;
 	}
 	if (tar != swjdp->ap_tar_value)
 	{
 		/* LOG_DEBUG("DAP: Set TAR %x",tar); */
+		/* FIXME if this call fails, fail this procedure! */
 		dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 		swjdp->ap_tar_value = tar;
 	}
@@ -500,51 +554,97 @@ int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 	return ERROR_OK;
 }
 
-/*****************************************************************************
-*                                                                            *
-* mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)      *
-*                                                                            *
-* Read a uint32_t value from memory or system register                            *
-* Functionally equivalent to target_read_u32(target, address, uint32_t *value),   *
-* but with less overhead                                                     *
-*****************************************************************************/
-int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
+/**
+ * Asynchronous (queued) read of a word from memory or a system register.
+ *
+ * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param address Address of the 32-bit word to read; it must be
+ *	readable by the currently selected MEM-AP.
+ * @param value points to where the word will be stored when the
+ *	transaction queue is flushed (assuming no errors).
+ *
+ * @return ERROR_OK for success.  Otherwise a fault code.
+ */
+int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address,
+		uint32_t *value)
 {
 	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
-	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+	/* Use banked addressing (REG_BDx) to avoid some link traffic
+	 * (updating TAR) when reading several consecutive addresses.
+	 */
+	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+			address & 0xFFFFFFF0);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 
+	/* FIXME return any fault code from above calls */
 	return ERROR_OK;
 }
 
-int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value)
+/**
+ * Synchronous read of a word from memory or a system register.
+ * As a side effect, this flushes any queued transactions.
+ *
+ * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param address Address of the 32-bit word to read; it must be
+ *	readable by the currently selected MEM-AP.
+ * @param value points to where the result will be stored.
+ *
+ * @return ERROR_OK for success; *value holds the result.
+ * Otherwise a fault code.
+ */
+int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
+		uint32_t *value)
 {
 	mem_ap_read_u32(swjdp, address, value);
+	/* FIXME return any fault code from above call */
 
 	return jtagdp_transaction_endcheck(swjdp);
 }
 
-/*****************************************************************************
-*                                                                            *
-* mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)      *
-*                                                                            *
-* Write a uint32_t value to memory or memory mapped register                              *
-*                                                                            *
-*****************************************************************************/
-int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
+/**
+ * Asynchronous (queued) write of a word to memory or a system register.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param address Address to be written; it must be writable by
+ *	the currently selected MEM-AP.
+ * @param value Word that will be written to the address when transaction
+ *	queue is flushed (assuming no errors).
+ *
+ * @return ERROR_OK for success.  Otherwise a fault code.
+ */
+int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address,
+		uint32_t value)
 {
 	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
 
-	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+	/* Use banked addressing (REG_BDx) to avoid some link traffic
+	 * (updating TAR) when writing several consecutive addresses.
+	 */
+	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+			address & 0xFFFFFFF0);
 	dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
 
+	/* FIXME return any fault code from above calls */
 	return ERROR_OK;
 }
 
-int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value)
+/**
+ * Synchronous write of a word to memory or a system register.
+ * As a side effect, this flushes any queued transactions.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param address Address to be written; it must be writable by
+ *	the currently selected MEM-AP.
+ * @param value Word that will be written.
+ *
+ * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
+ */
+int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address,
+		uint32_t value)
 {
 	mem_ap_write_u32(swjdp, address, value);
+	/* FIXME return any fault code from above call */
 
 	return jtagdp_transaction_endcheck(swjdp);
 }
@@ -1083,7 +1183,11 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u
 }
 
 /**
- * Initialize a DAP.
+ * Initialize a DAP.  This sets up the power domains, prepares the DP
+ * for further use, and arranges to use AP #0 for all AP operations
+ * until dap_ap-select() changes that policy.
+ *
+ * @param swjdp The DAP being initialized.
  *
  * @todo Rename this.  We also need an initialization scheme which account
  * for SWD transports not just JTAG; that will need to address differences
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index a807027..759f233 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -155,16 +155,18 @@ struct swjdp_common
 
 };
 
-/* Accessor function for currently selected DAP-AP number */
+/** Accessor for currently selected DAP-AP number (0..255) */
 static inline uint8_t dap_ap_get_select(struct swjdp_common *swjdp)
 {
 	return (uint8_t)(swjdp ->apsel >> 24);
 }
 
-/* Queued transactions -- use with care */
+/* AP selection applies to future AP transactions */
+void dap_ap_select(struct swjdp_common *dap,uint8_t apsel);
+
+/* AP transactions ... synchronous given TRANS_MODE_ATOMIC */
 int dap_setup_accessport(struct swjdp_common *swjdp,
 		uint32_t csw, uint32_t tar);
-int dap_ap_select(struct swjdp_common *swjdp,uint8_t apsel);
 int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 		uint32_t addr, uint32_t value);
 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
@@ -173,11 +175,11 @@ int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 /* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
 int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
 
-/* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
+/* Queued MEM-AP memory mapped single word transfers */
 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
 int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
 
-/* MEM-AP memory mapped bus transfers, single registers, complete transactions */
+/* Synchronous MEM-AP memory mapped single word transfers */
 int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
 		uint32_t address, uint32_t *value);
 int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,

-----------------------------------------------------------------------

Summary of changes:
 doc/manual/main.txt     |    4 +-
 src/target/arm_adi_v5.c |  158 +++++++++++++++++++++++++++++++++++++++--------
 src/target/arm_adi_v5.h |   12 ++--
 3 files changed, 140 insertions(+), 34 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-182-g41d0901

[Øyvind H. <go...@us...>]

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the project "Main OpenOCD repository".

The branch, master has been updated
       via  41d0901115903cb02b42249690b33cf616e133b5 (commit)
      from  ff5deeeeaa4f394931e3c5ccfb4cfd33beda0743 (commit)

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- Log -----------------------------------------------------------------
commit 41d0901115903cb02b42249690b33cf616e133b5
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Feb 5 14:38:26 2010 +0100

    zy1000: complete zy1000_uart to jim command switch
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/ecosboard.c b/src/ecosboard.c
index 2e73585..f752354 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -847,7 +847,7 @@ static int zylinjtag_Jim_Command_uart(Jim_Interp *interp, int argc,
 	static int current_baud = 38400;
 	if (argc == 1)
 	{
-		command_print(cmd_ctx, "%d", current_baud);
+		Jim_SetResult(interp, Jim_NewIntObj(interp, current_baud));
 		return JIM_OK;
 	}
 	else if (argc != 2)
@@ -883,8 +883,8 @@ static int zylinjtag_Jim_Command_uart(Jim_Interp *interp, int argc,
 		baud = CYGNUM_SERIAL_BAUD_230400;
 		break;
 	default:
-		command_print(cmd_ctx, "unsupported baudrate");
-		return ERROR_INVALID_ARGUMENTS;
+		Jim_SetResult(interp, Jim_NewStringObj(interp, "unsupported baudrate", -1));
+		return JIM_ERR;
 	}
 
 	cyg_serial_info_t buf;
@@ -897,7 +897,7 @@ static int zylinjtag_Jim_Command_uart(Jim_Interp *interp, int argc,
 	err = cyg_io_lookup(ZY1000_SER_DEV, &serial_handle);
 	if (err != ENOERR)
 	{
-		LOG_ERROR("Could not open serial port\n");
+		Jim_SetResult(interp, Jim_NewStringObj(interp, "Could not open serial port", -1));
 		return JIM_ERR;
 	}
 
@@ -907,7 +907,7 @@ static int zylinjtag_Jim_Command_uart(Jim_Interp *interp, int argc,
 			&len);
 	if (err != ENOERR)
 	{
-		LOG_ERROR("Failed to get serial port settings %d", err);
+		Jim_SetResult(interp, Jim_NewStringObj(interp, "Failed to get serial port settings", -1));
 		return JIM_ERR;
 	}
 	buf.baud = baud;
@@ -916,7 +916,7 @@ static int zylinjtag_Jim_Command_uart(Jim_Interp *interp, int argc,
 			&len);
 	if (err != ENOERR)
 	{
-		LOG_ERROR("Failed to set serial port settings %d", err);
+		Jim_SetResult(interp, Jim_NewStringObj(interp, "Failed to set serial port settings", -1));
 		return JIM_ERR;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/ecosboard.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-181-gff5deee

[David B. <dbr...@us...>]

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      from  3ea9e62189205cfa84a04ec6955aaf1f5184a937 (commit)

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- Log -----------------------------------------------------------------
commit ff5deeeeaa4f394931e3c5ccfb4cfd33beda0743
Author: David Brownell <dbr...@us...>
Date:   Thu Feb 4 14:39:51 2010 -0800

    ARMv7-M: make DAP commands verify target is an ARMv7-M
    
    Init the ARMv7-M magic number.  Define predicate verifying it.
    Use it to resolve a lurking bug/FIXME:  make sure the ARMv7-M
    specific DAP ops reject non-ARMv7-M targets.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index edfcdf9..9fe705a 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -538,7 +538,7 @@ struct reg_cache *armv7m_build_reg_cache(struct target *target)
 /** Sets up target as a generic ARMv7-M core */
 int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
 {
-	/* register arch-specific functions */
+	armv7m->common_magic = ARMV7M_COMMON_MAGIC;
 
 	target->arch_info = armv7m;
 	armv7m->read_core_reg = armv7m_read_core_reg;
@@ -737,8 +737,6 @@ int armv7m_maybe_skip_bkpt_inst(struct target *target, bool *inst_found)
 /*
  * Only stuff below this line should need to verify that its target
  * is an ARMv7-M node.
- *
- * FIXME yet none of it _does_ verify target types yet!
  */
 
 
@@ -752,6 +750,11 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
+	if (!is_armv7m(armv7m)) {
+		command_print(CMD_CTX, "current target isn't an ARM7-M");
+		return ERROR_TARGET_INVALID;
+	}
+
 	return CALL_COMMAND_HANDLER(dap_baseaddr_command, swjdp);
 }
 
@@ -765,6 +768,11 @@ COMMAND_HANDLER(handle_dap_apid_command)
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
+	if (!is_armv7m(armv7m)) {
+		command_print(CMD_CTX, "current target isn't an ARM7-M");
+		return ERROR_TARGET_INVALID;
+	}
+
 	return CALL_COMMAND_HANDLER(dap_apid_command, swjdp);
 }
 
@@ -774,6 +782,11 @@ COMMAND_HANDLER(handle_dap_apsel_command)
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
+	if (!is_armv7m(armv7m)) {
+		command_print(CMD_CTX, "current target isn't an ARM7-M");
+		return ERROR_TARGET_INVALID;
+	}
+
 	return CALL_COMMAND_HANDLER(dap_apsel_command, swjdp);
 }
 
@@ -783,6 +796,11 @@ COMMAND_HANDLER(handle_dap_memaccess_command)
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 
+	if (!is_armv7m(armv7m)) {
+		command_print(CMD_CTX, "current target isn't an ARM7-M");
+		return ERROR_TARGET_INVALID;
+	}
+
 	return CALL_COMMAND_HANDLER(dap_memaccess_command, swjdp);
 }
 
@@ -794,6 +812,11 @@ COMMAND_HANDLER(handle_dap_info_command)
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
 	uint32_t apsel;
 
+	if (!is_armv7m(armv7m)) {
+		command_print(CMD_CTX, "current target isn't an ARM7-M");
+		return ERROR_TARGET_INVALID;
+	}
+
 	switch (CMD_ARGC) {
 	case 0:
 		apsel = swjdp->apsel;
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 9787e30..b6be1d2 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -131,6 +131,11 @@ target_to_armv7m(struct target *target)
 	return target->arch_info;
 }
 
+static inline bool is_armv7m(struct armv7m_common *armv7m)
+{
+	return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
+}
+
 struct armv7m_algorithm
 {
 	int common_magic;

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7m.c |   29 ++++++++++++++++++++++++++---
 src/target/armv7m.h |    5 +++++
 2 files changed, 31 insertions(+), 3 deletions(-)


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