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From: David B. <dbr...@us...> - 2009-12-16 23:17:54
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via d265c219b90bfe9454991bed6b41f790f085d230 (commit) via 1cd7b3b49b33860a5652b9dd2829e9ed71ac6289 (commit) via 6f2b9ea9e158aa116937b234a9c069bfef1f4238 (commit) via f85dc92d2a2b336f9844c0eddcdf4df4c0dc9fbf (commit) via 47998a55e0f66d513b52f7851901bc79bc1f7213 (commit) from fcd3c52611009559b1954a43463e7015870d36c2 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit d265c219b90bfe9454991bed6b41f790f085d230 Author: David Brownell <dbr...@us...> Date: Wed Dec 16 14:17:31 2009 -0800 stellaris: comments Someday revisit various issues: Tempest parts support writing more than one word at a time; for some target firmware it might be necessary to save and restore flash IRQ configuration. (The safest policy is likely to always reset after flash updates.) Plus swap some undesirable TAB characters with SPACE. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 34649fc..4183cba 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -553,6 +553,11 @@ static int stellaris_read_part_info(struct flash_bank *bank) stellaris_info->pagesize = 1024; stellaris_info->pages_in_lockregion = 2; + /* REVISIT for at least Tempest parts, read NVMSTAT.FWB too. + * That exposes a 32-word Flash Write Buffer ... enabling + * writes of more than one word at a time. + */ + return ERROR_OK; } @@ -640,6 +645,10 @@ static int stellaris_erase(struct flash_bank *bank, int first, int last) target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_MISC, PMISC | AMISC); + /* REVISIT this clobbers state set by any halted firmware ... + * it might want to process those IRQs. + */ + for (banknr = first; banknr <= last; banknr++) { /* Address is first word in page */ @@ -726,6 +735,10 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_MISC, PMISC | AMISC); + /* REVISIT this clobbers state set by any halted firmware ... + * it might want to process those IRQs. + */ + LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe); target_write_u32(target, SCB_BASE | FMPPE, fmppe); @@ -921,6 +934,10 @@ static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t of target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_MISC, PMISC | AMISC); + /* REVISIT this clobbers state set by any halted firmware ... + * it might want to process those IRQs. + */ + /* multiple words to be programmed? */ if (words_remaining > 0) { @@ -1068,6 +1085,10 @@ static int stellaris_mass_erase(struct flash_bank *bank) target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_MISC, PMISC | AMISC); + /* REVISIT this clobbers state set by any halted firmware ... + * it might want to process those IRQs. + */ + target_write_u32(target, FLASH_FMA, 0); target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_MERASE); /* Wait until erase complete */ diff --git a/src/flash/nor/stellaris.h b/src/flash/nor/stellaris.h index 4de4f00..a469323 100644 --- a/src/flash/nor/stellaris.h +++ b/src/flash/nor/stellaris.h @@ -53,18 +53,19 @@ struct stellaris_flash_bank /* STELLARIS control registers */ #define SCB_BASE 0x400FE000 -#define DID0 0x000 -#define DID1 0x004 -#define DC0 0x008 -#define DC1 0x010 -#define DC2 0x014 -#define DC3 0x018 -#define DC4 0x01C - -#define RIS 0x050 -#define RCC 0x060 -#define PLLCFG 0x064 -#define RCC2 0x070 +#define DID0 0x000 +#define DID1 0x004 +#define DC0 0x008 +#define DC1 0x010 +#define DC2 0x014 +#define DC3 0x018 +#define DC4 0x01C + +#define RIS 0x050 +#define RCC 0x060 +#define PLLCFG 0x064 +#define RCC2 0x070 +#define NVMSTAT 0x1a0 /* "legacy" flash memory protection registers (64KB max) */ #define FMPRE 0x130 commit 1cd7b3b49b33860a5652b9dd2829e9ed71ac6289 Author: David Brownell <dbr...@us...> Date: Wed Dec 16 14:17:31 2009 -0800 stellaris: probe() cleanups Fix potential memory leak: make sure the per-bank data structures are only allocated in probe(), and that calling probe() multiple times is a NOP. Use it for auto_probe(). Require probe() to have done its thing: don't make access routines cope with it not having been called. Shrink a bunch of failure paths; and in some cases, correct them. Don't needlessly insist on a halted target for probe(). Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 0ae65dc..34649fc 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -36,8 +36,7 @@ #define DID0_VER(did0) ((did0 >> 28)&0x07) -static int stellaris_read_part_info(struct flash_bank *bank); - +static void stellaris_read_clock_info(struct flash_bank *bank); static int stellaris_mass_erase(struct flash_bank *bank); static struct { @@ -261,15 +260,11 @@ static int stellaris_info(struct flash_bank *bank, char *buf, int buf_size) int printed, device_class; struct stellaris_flash_bank *stellaris_info = bank->driver_priv; - stellaris_read_part_info(bank); - if (stellaris_info->did1 == 0) - { - printed = snprintf(buf, buf_size, "Cannot identify target as a Stellaris\n"); - buf += printed; - buf_size -= printed; - return ERROR_FLASH_OPERATION_FAILED; - } + return ERROR_FLASH_BANK_NOT_PROBED; + + /* Read main and master clock freqency register */ + stellaris_read_clock_info(bank); if (DID0_VER(stellaris_info->did0) > 0) { @@ -495,7 +490,8 @@ static int stellaris_read_part_info(struct flash_bank *bank) fam = (did1 >> 24) & 0xF; if (((ver != 0) && (ver != 1)) || (fam != 0)) { - LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris"); + LOG_WARNING("Unknown did1 version/family."); + return ERROR_FLASH_OPERATION_FAILED; } /* For Sandstorm, Fury, DustDevil: current data sheets say IOSC @@ -535,9 +531,10 @@ static int stellaris_read_part_info(struct flash_bank *bank) default: LOG_WARNING("Unknown did0 class"); } - default: break; + default: LOG_WARNING("Unknown did0 version"); + break; } for (i = 0; StellarisParts[i].partno; i++) @@ -554,23 +551,8 @@ static int stellaris_read_part_info(struct flash_bank *bank) stellaris_info->num_lockbits = 1 + (stellaris_info->dc0 & 0xFFFF); stellaris_info->num_pages = 2 *(1 + (stellaris_info->dc0 & 0xFFFF)); stellaris_info->pagesize = 1024; - bank->size = 1024 * stellaris_info->num_pages; stellaris_info->pages_in_lockregion = 2; - /* provide this for the benefit of the higher flash driver layers */ - bank->num_sectors = stellaris_info->num_pages; - bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); - for (i = 0; i < bank->num_sectors; i++) - { - bank->sectors[i].offset = i * stellaris_info->pagesize; - bank->sectors[i].size = stellaris_info->pagesize; - bank->sectors[i].is_erased = -1; - bank->sectors[i].is_protected = -1; - } - - /* Read main and master clock freqency register */ - stellaris_read_clock_info(bank); - return ERROR_OK; } @@ -586,11 +568,7 @@ static int stellaris_protect_check(struct flash_bank *bank) unsigned page; if (stellaris->did1 == 0) - { - status = stellaris_read_part_info(bank); - if (status < 0) - return status; - } + return ERROR_FLASH_BANK_NOT_PROBED; for (i = 0; i < (unsigned) bank->num_sectors; i++) bank->sectors[i].is_protected = -1; @@ -642,15 +620,7 @@ static int stellaris_erase(struct flash_bank *bank, int first, int last) } if (stellaris_info->did1 == 0) - { - stellaris_read_part_info(bank); - } - - if (stellaris_info->did1 == 0) - { - LOG_WARNING("Cannot identify target as Stellaris"); - return ERROR_FLASH_OPERATION_FAILED; - } + return ERROR_FLASH_BANK_NOT_PROBED; if ((first < 0) || (last < first) || (last >= (int)stellaris_info->num_pages)) { @@ -719,6 +689,9 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la return ERROR_INVALID_ARGUMENTS; } + if (stellaris_info->did1 == 0) + return ERROR_FLASH_BANK_NOT_PROBED; + /* lockregions are 2 pages ... must protect [even..odd] */ if ((first < 0) || (first & 1) || (last < first) || !(last & 1) @@ -728,17 +701,6 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la return ERROR_FLASH_SECTOR_INVALID; } - if (stellaris_info->did1 == 0) - { - stellaris_read_part_info(bank); - } - - if (stellaris_info->did1 == 0) - { - LOG_WARNING("Cannot identify target as an Stellaris MCU"); - return ERROR_FLASH_OPERATION_FAILED; - } - /* Refresh flash controller timing */ stellaris_read_clock_info(bank); stellaris_set_flash_timing(bank); @@ -940,15 +902,7 @@ static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t of bank, buffer, offset, count); if (stellaris_info->did1 == 0) - { - stellaris_read_part_info(bank); - } - - if (stellaris_info->did1 == 0) - { - LOG_WARNING("Cannot identify target as a Stellaris processor"); - return ERROR_FLASH_OPERATION_FAILED; - } + return ERROR_FLASH_BANK_NOT_PROBED; if (offset & 0x3) { @@ -1056,26 +1010,36 @@ static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t of static int stellaris_probe(struct flash_bank *bank) { - /* we can't probe on an stellaris - * if this is an stellaris, it has the configured flash + struct stellaris_flash_bank *stellaris_info = bank->driver_priv; + int retval; + + /* If this is a stellaris chip, it has flash; probe() is just + * to figure out how much is present. Only do it once. + */ + if (stellaris_info->did1 != 0) + return ERROR_OK; + + /* stellaris_read_part_info() already handled error checking and + * reporting. Note that it doesn't write, so we don't care about + * whether the target is halted or not. */ + retval = stellaris_read_part_info(bank); + if (retval != ERROR_OK) + return retval; - if (bank->target->state != TARGET_HALTED) + /* provide this for the benefit of the NOR flash framework */ + bank->size = 1024 * stellaris_info->num_pages; + bank->num_sectors = stellaris_info->num_pages; + bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector)); + for (int i = 0; i < bank->num_sectors; i++) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; + bank->sectors[i].offset = i * stellaris_info->pagesize; + bank->sectors[i].size = stellaris_info->pagesize; + bank->sectors[i].is_erased = -1; + bank->sectors[i].is_protected = -1; } - /* stellaris_read_part_info() already takes care about error checking and reporting */ - return stellaris_read_part_info(bank); -} - -static int stellaris_auto_probe(struct flash_bank *bank) -{ - struct stellaris_flash_bank *stellaris_info = bank->driver_priv; - if (stellaris_info->did1) - return ERROR_OK; - return stellaris_probe(bank); + return retval; } static int stellaris_mass_erase(struct flash_bank *bank) @@ -1094,15 +1058,7 @@ static int stellaris_mass_erase(struct flash_bank *bank) } if (stellaris_info->did1 == 0) - { - stellaris_read_part_info(bank); - } - - if (stellaris_info->did1 == 0) - { - LOG_WARNING("Cannot identify target as Stellaris"); - return ERROR_FLASH_OPERATION_FAILED; - } + return ERROR_FLASH_BANK_NOT_PROBED; /* Refresh flash controller timing */ stellaris_read_clock_info(bank); @@ -1198,7 +1154,7 @@ struct flash_driver stellaris_flash = { .protect = stellaris_protect, .write = stellaris_write, .probe = stellaris_probe, - .auto_probe = stellaris_auto_probe, + .auto_probe = stellaris_probe, .erase_check = default_flash_mem_blank_check, .protect_check = stellaris_protect_check, .info = stellaris_info, commit 6f2b9ea9e158aa116937b234a9c069bfef1f4238 Author: David Brownell <dbr...@us...> Date: Wed Dec 16 14:17:31 2009 -0800 stellaris: remove needless code No point in reading and discarding a status value when fetching part description data. Or having that needless "#if 0" code. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 8b0d9d3..0ae65dc 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -37,7 +37,6 @@ #define DID0_VER(did0) ((did0 >> 28)&0x07) static int stellaris_read_part_info(struct flash_bank *bank); -static uint32_t stellaris_get_flash_status(struct flash_bank *bank); static int stellaris_mass_erase(struct flash_bank *bank); @@ -335,16 +334,6 @@ static int stellaris_info(struct flash_bank *bank, char *buf, int buf_size) * chip identification and status * ***************************************************************************/ -static uint32_t stellaris_get_flash_status(struct flash_bank *bank) -{ - struct target *target = bank->target; - uint32_t fmc; - - target_read_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, &fmc); - - return fmc; -} - /* Set the flash timimg register to match current clocking */ static void stellaris_set_flash_timing(struct flash_bank *bank) { @@ -473,48 +462,12 @@ static void stellaris_read_clock_info(struct flash_bank *bank) stellaris_info->mck_freq = mainfreq; } -#if 0 -static uint32_t stellaris_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout) -{ - uint32_t status; - - /* Stellaris waits for cmdbit to clear */ - while (((status = stellaris_get_flash_status(bank)) & waitbits) && (timeout-- > 0)) - { - LOG_DEBUG("status: 0x%x", status); - alive_sleep(1); - } - - /* Flash errors are reflected in the FLASH_CRIS register */ - - return status; -} - -/* Send one command to the flash controller */ -static int stellaris_flash_command(struct flash_bank *bank,uint8_t cmd,uint16_t pagen) -{ - uint32_t fmc; - struct target *target = bank->target; - - fmc = FMC_WRKEY | cmd; - target_write_u32(target, FLASH_CONTROL_BASE | FLASH_FMC, fmc); - LOG_DEBUG("Flash command: 0x%x", fmc); - - if (stellaris_wait_status_busy(bank, cmd, 100)) - { - return ERROR_FLASH_OPERATION_FAILED; - } - - return ERROR_OK; -} -#endif - /* Read device id register, main clock frequency register and fill in driver info structure */ static int stellaris_read_part_info(struct flash_bank *bank) { struct stellaris_flash_bank *stellaris_info = bank->driver_priv; struct target *target = bank->target; - uint32_t did0, did1, ver, fam, status; + uint32_t did0, did1, ver, fam; int i; /* Read and parse chip identification register */ @@ -618,8 +571,6 @@ static int stellaris_read_part_info(struct flash_bank *bank) /* Read main and master clock freqency register */ stellaris_read_clock_info(bank); - status = stellaris_get_flash_status(bank); - return ERROR_OK; } commit f85dc92d2a2b336f9844c0eddcdf4df4c0dc9fbf Author: David Brownell <dbr...@us...> Date: Wed Dec 16 14:17:31 2009 -0800 stellaris: avoid chip writes Previously "reading" clock info (and part info) also, as a side effect, wrote the flash timing register. Instead, be more safe: "reading" should only read. Write paths still refresh timing, coping with changes the application code may have made. Also rename the routine which sets flash timing, indicating what it's really doing; it's got nothing to do with a "mode". Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 103202d..8b0d9d3 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -345,8 +345,8 @@ static uint32_t stellaris_get_flash_status(struct flash_bank *bank) return fmc; } -/* Setup the timimg registers */ -static void stellaris_set_flash_mode(struct flash_bank *bank,int mode) +/* Set the flash timimg register to match current clocking */ +static void stellaris_set_flash_timing(struct flash_bank *bank) { struct stellaris_flash_bank *stellaris_info = bank->driver_priv; struct target *target = bank->target; @@ -471,9 +471,6 @@ static void stellaris_read_clock_info(struct flash_bank *bank) stellaris_info->mck_freq = mainfreq/(1 + sysdiv); else stellaris_info->mck_freq = mainfreq; - - /* Forget old flash timing */ - stellaris_set_flash_mode(bank, 0); } #if 0 @@ -714,9 +711,9 @@ static int stellaris_erase(struct flash_bank *bank, int first, int last) return stellaris_mass_erase(bank); } - /* Configure the flash controller timing */ + /* Refresh flash controller timing */ stellaris_read_clock_info(bank); - stellaris_set_flash_mode(bank,0); + stellaris_set_flash_timing(bank); /* Clear and disable flash programming interrupts */ target_write_u32(target, FLASH_CIM, 0); @@ -791,9 +788,9 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la return ERROR_FLASH_OPERATION_FAILED; } - /* Configure the flash controller timing */ + /* Refresh flash controller timing */ stellaris_read_clock_info(bank); - stellaris_set_flash_mode(bank, 0); + stellaris_set_flash_timing(bank); /* convert from pages to lockregions */ first /= 2; @@ -1011,9 +1008,9 @@ static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t of if (offset + count > bank->size) return ERROR_FLASH_DST_OUT_OF_BANK; - /* Configure the flash controller timing */ + /* Refresh flash controller timing */ stellaris_read_clock_info(bank); - stellaris_set_flash_mode(bank, 0); + stellaris_set_flash_timing(bank); /* Clear and disable flash programming interrupts */ target_write_u32(target, FLASH_CIM, 0); @@ -1156,9 +1153,9 @@ static int stellaris_mass_erase(struct flash_bank *bank) return ERROR_FLASH_OPERATION_FAILED; } - /* Configure the flash controller timing */ + /* Refresh flash controller timing */ stellaris_read_clock_info(bank); - stellaris_set_flash_mode(bank, 0); + stellaris_set_flash_timing(bank); /* Clear and disable flash programming interrupts */ target_write_u32(target, FLASH_CIM, 0); commit 47998a55e0f66d513b52f7851901bc79bc1f7213 Author: David Brownell <dbr...@us...> Date: Wed Dec 16 11:57:59 2009 -0800 NOR: bugfix "flash fill[bwh] ..." helptext These commands don't have a "bank" parameter. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c index 6ab710b..1e933b2 100644 --- a/src/flash/nor/tcl.c +++ b/src/flash/nor/tcl.c @@ -697,21 +697,21 @@ static const struct command_registration flash_exec_command_handlers[] = { .name = "fillw", .handler = &handle_flash_fill_command, .mode = COMMAND_EXEC, - .usage = "<bank> <address> <word_pattern> <count>", + .usage = "<address> <word_pattern> <count>", .help = "fill with pattern (no autoerase)", }, { .name = "fillh", .handler = &handle_flash_fill_command, .mode = COMMAND_EXEC, - .usage = "<bank> <address> <halfword_pattern> <count>", + .usage = "<address> <halfword_pattern> <count>", .help = "fill with pattern", }, { .name = "fillb", .handler = &handle_flash_fill_command, .mode = COMMAND_EXEC, - .usage = "<bank> <address> <byte_pattern> <count>", + .usage = "<address> <byte_pattern> <count>", .help = "fill with pattern", }, ----------------------------------------------------------------------- Summary of changes: src/flash/nor/stellaris.c | 221 +++++++++++++++------------------------------ src/flash/nor/stellaris.h | 23 +++--- src/flash/nor/tcl.c | 6 +- 3 files changed, 88 insertions(+), 162 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-16 14:55:53
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via fcd3c52611009559b1954a43463e7015870d36c2 (commit) from c8b8a34bb5e98660c4ce3683fb64af31b494d55c (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit fcd3c52611009559b1954a43463e7015870d36c2 Author: Ãyvind Harboe <oyv...@zy...> Date: Wed Dec 16 14:44:58 2009 +0100 zy1000: removed some redundant include spotted by lint. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/ecosboard.c b/src/ecosboard.c index 2a9950d..32eb085 100644 --- a/src/ecosboard.c +++ b/src/ecosboard.c @@ -32,6 +32,7 @@ #include <openocd.h> #include <helper/time_support.h> + #include <sys/time.h> #include <stdio.h> #include <stdlib.h> @@ -53,31 +54,12 @@ #include <cyg/athttpd/cgi.h> #include <cyg/athttpd/forms.h> #include <cyg/discover/discover.h> -#include <cyg/hal/hal_diag.h> -#include <cyg/kernel/kapi.h> -#include <cyg/io/serialio.h> #include <cyg/io/io.h> +#include <cyg/io/serialio.h> #include <netinet/tcp.h> -#include "rom.h" -#include <sys/ioctl.h> -#include <sys/socket.h> -#include <netinet/in.h> -#include <net/if.h> -#include <arpa/inet.h> -#include <sys/types.h> -#include <sys/socket.h> -#include <netdb.h> -#include <netinet/in.h> -#include <unistd.h> -#include <arpa/inet.h> -#include <stdio.h> -#include <ifaddrs.h> -#include <string.h> - -#include <unistd.h> -#include <stdio.h> +#include <cyg/hal/hal_diag.h> -#include <openocd.h> +#include "rom.h" #ifdef CYGPKG_HAL_NIOS2 #define ZY1000_SER_DEV "/dev/uart_0" ----------------------------------------------------------------------- Summary of changes: src/ecosboard.c | 26 ++++---------------------- 1 files changed, 4 insertions(+), 22 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-16 11:26:32
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via c8b8a34bb5e98660c4ce3683fb64af31b494d55c (commit) from 74ce435d97ca4f6f81645d755d04123f075aa42b (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit c8b8a34bb5e98660c4ce3683fb64af31b494d55c Author: Ãyvind Harboe <oyv...@zy...> Date: Tue Dec 15 14:57:38 2009 +0100 ecos: crisper implementation of timeval_ms() A crisper/faster implementation under eCos that makes profiling a tad easier. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am index 244ada7..3ec4f31 100644 --- a/src/helper/Makefile.am +++ b/src/helper/Makefile.am @@ -7,9 +7,9 @@ METASOURCES = AUTO noinst_LTLIBRARIES = libhelper.la if ECOSBOARD -CONFIGFILES = +CONFIGFILES = time_support_ecos.c else -CONFIGFILES = options.c jim.c jim-eventloop.c +CONFIGFILES = options.c jim.c jim-eventloop.c time_support_common.c endif diff --git a/src/helper/time_support.c b/src/helper/time_support.c index 693528f..1934315 100644 --- a/src/helper/time_support.c +++ b/src/helper/time_support.c @@ -29,7 +29,6 @@ #include "time_support.h" - /* calculate difference between two struct timeval values */ int timeval_subtract(struct timeval *result, struct timeval *x, struct timeval *y) { @@ -73,16 +72,6 @@ int timeval_add_time(struct timeval *result, long sec, long usec) return 0; } -int64_t timeval_ms() -{ - struct timeval now; - int retval = gettimeofday(&now, NULL); - if (retval < 0) - return retval; - return (int64_t)now.tv_sec * 1000 + now.tv_usec / 1000; -} - - int duration_start(struct duration *duration) { return gettimeofday(&duration->start, NULL); diff --git a/src/helper/time_support_common.c b/src/helper/time_support_common.c new file mode 100644 index 0000000..1ad3676 --- /dev/null +++ b/src/helper/time_support_common.c @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (C) 2006 by Dominic Rath * + * Dom...@gm... * + * * + * Copyright (C) 2007,2008 Ãyvind Harboe * + * oyv...@zy... * + * * + * Copyright (C) 2008 by Spencer Oliver * + * sp...@sp... * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "time_support.h" + +/* simple and low overhead fetching of ms counter. Use only + * the difference between ms counters returned from this fn. + */ +int64_t timeval_ms() +{ + struct timeval now; + int retval = gettimeofday(&now, NULL); + if (retval < 0) + return retval; + return (int64_t)now.tv_sec * 1000 + now.tv_usec / 1000; +} diff --git a/src/helper/time_support_ecos.c b/src/helper/time_support_ecos.c new file mode 100644 index 0000000..b0911fc --- /dev/null +++ b/src/helper/time_support_ecos.c @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (C) 2006 by Dominic Rath * + * Dom...@gm... * + * * + * Copyright (C) 2007,2008 Ãyvind Harboe * + * oyv...@zy... * + * * + * Copyright (C) 2008 by Spencer Oliver * + * sp...@sp... * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include "time_support.h" + +#include <cyg/kernel/kapi.h> + +int64_t timeval_ms() +{ + /* Faster/less noisy implementation of getting ms when + * profiling + */ + static const int ms_per_tick = + (CYGNUM_HAL_RTC_NUMERATOR / CYGNUM_HAL_RTC_DENOMINATOR) / 1000000; + cyg_tick_count_t cur_time = cyg_current_time(); + return ((int)cur_time) * ms_per_tick; +} ----------------------------------------------------------------------- Summary of changes: src/helper/Makefile.am | 4 +- src/helper/time_support.c | 11 ------ .../gdb_server.h => helper/time_support_common.c} | 36 +++++++++----------- .../gdb_server.h => helper/time_support_ecos.c} | 35 +++++++++---------- 4 files changed, 34 insertions(+), 52 deletions(-) copy src/{server/gdb_server.h => helper/time_support_common.c} (76%) copy src/{server/gdb_server.h => helper/time_support_ecos.c} (76%) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-16 08:12:20
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 74ce435d97ca4f6f81645d755d04123f075aa42b (commit) from 4a2f4e34336dbb662a308e5a881edbba9f3657ec (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 74ce435d97ca4f6f81645d755d04123f075aa42b Author: Ãyvind Harboe <oyv...@zy...> Date: Tue Dec 15 15:43:38 2009 +0100 server: server loop will exhaust data inputs before sleeping By exhausting data on input, the performance will be more consistent + the code more clearly distinguishes between polling and processing. A test showed gdb packet load performance go from ~1550kByte/s to 1650kBytes/s + being more stable. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/server/server.c b/src/server/server.c index 75a6bed..f762704 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -292,9 +292,10 @@ int server_loop(struct command_context *command_context) { struct service *service; + bool poll = true; + /* used in select() */ fd_set read_fds; - struct timeval tv; int fd_max; /* used in accept() */ @@ -305,10 +306,6 @@ int server_loop(struct command_context *command_context) LOG_ERROR("couldn't set SIGPIPE to SIG_IGN"); #endif - /* do regular tasks after at most 10ms */ - tv.tv_sec = 0; - tv.tv_usec = 10000; - while (!shutdown_openocd) { /* monitor sockets for activity */ @@ -351,12 +348,24 @@ int server_loop(struct command_context *command_context) #endif #endif - openocd_sleep_prelude(); - kept_alive(); - - /* Only while we're sleeping we'll let others run */ - retval = socket_select(fd_max + 1, &read_fds, NULL, NULL, &tv); - openocd_sleep_postlude(); + struct timeval tv; + tv.tv_sec = 0; + if (poll) + { + /* we're just polling this iteration, this is faster on embedded + * hosts */ + tv.tv_usec = 0; + retval = socket_select(fd_max + 1, &read_fds, NULL, NULL, &tv); + } else + { + /* Every 100ms */ + tv.tv_usec = 100000; + /* Only while we're sleeping we'll let others run */ + openocd_sleep_prelude(); + kept_alive(); + retval = socket_select(fd_max + 1, &read_fds, NULL, NULL, &tv); + openocd_sleep_postlude(); + } if (retval == -1) { @@ -385,15 +394,20 @@ int server_loop(struct command_context *command_context) #endif } - target_call_timer_callbacks(); - process_jim_events(command_context); - if (retval == 0) { - /* do regular tasks after at most 100ms */ - tv.tv_sec = 0; - tv.tv_usec = 10000; + /* We only execute these callbacks when there was nothing to do or we timed out */ + target_call_timer_callbacks(); + process_jim_events(command_context); + FD_ZERO(&read_fds); /* eCos leaves read_fds unchanged in this case! */ + + /* We timed out/there was nothing to do, timeout rather than poll next time */ + poll = false; + } else + { + /* There was something to do, next time we'll just poll */ + poll = true; } for (service = services; service; service = service->next) ----------------------------------------------------------------------- Summary of changes: src/server/server.c | 48 +++++++++++++++++++++++++++++++----------------- 1 files changed, 31 insertions(+), 17 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-15 23:46:22
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 4a2f4e34336dbb662a308e5a881edbba9f3657ec (commit) via 80a757d82eafb36ffd54414f33ce91302f4522da (commit) via fc99287b097e719a6dbe8d139e71c5ed136e48e8 (commit) from 646ce814b4fb678b7d8d341afe0694c266112426 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 4a2f4e34336dbb662a308e5a881edbba9f3657ec Author: David Brownell <dbr...@us...> Date: Tue Dec 15 14:39:25 2009 -0800 more tcl/{board,target} cleanup Remove more remnants of the old "jtag_device" syntax. Don't [format "%s.cpu" $_CHIPNAME] ... it's needless complexity. Remove various non-supported "-variant" target options; they're not needed often at all. Flag some of the board files as needing to have and use target files for the TAP and target declarations. Signed-off-by: David Brownell <dbr...@us...> diff --git a/tcl/board/at91eb40a.cfg b/tcl/board/at91eb40a.cfg index 62d3c9c..40f2e12 100644 --- a/tcl/board/at91eb40a.cfg +++ b/tcl/board/at91eb40a.cfg @@ -1,5 +1,9 @@ #Script for AT91EB40a +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -30,12 +34,11 @@ if { [info exists CPUTAPID ] } { reset_config srst_only srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID #target configuration set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME # speed up memory downloads arm7_9 fast_memory_access enable diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index 6e8a193..b0fe546 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -5,6 +5,10 @@ # # ################################################################################################# +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + # Define basic characteristics for the CPU. The AT91SAM9G20 processor is a subtle variant of # the AT91SAM9260 and shares the same tap ID as it. @@ -34,8 +38,8 @@ jtag_ntrst_delay 200 jtag_rclk 5 -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME # Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc. The # AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000. diff --git a/tcl/board/digi_connectcore_wi-9c.cfg b/tcl/board/digi_connectcore_wi-9c.cfg index 3bc26ad..2d82376 100644 --- a/tcl/board/digi_connectcore_wi-9c.cfg +++ b/tcl/board/digi_connectcore_wi-9c.cfg @@ -4,6 +4,10 @@ reset_config trst_and_srst +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -29,7 +33,7 @@ if { [info exists CPUTAPID ] } { set _CPUTAPID 0x07926031 } -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +set _TARGETNAME $_CHIPNAME.cpu jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID jtag_nsrst_delay 200 @@ -40,7 +44,7 @@ jtag_ntrst_delay 0 # Target configuration ###################### -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -event reset-init { mww 0x90600104 0x33313333 diff --git a/tcl/board/hitex_str9-comstick.cfg b/tcl/board/hitex_str9-comstick.cfg index 968d80e..af7527a 100644 --- a/tcl/board/hitex_str9-comstick.cfg +++ b/tcl/board/hitex_str9-comstick.cfg @@ -11,8 +11,13 @@ jtag_nsrst_delay 100 jtag_ntrst_delay 100 #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) + +# +# FIXME use the standard str912 target config; that script might need +# updating to "-ignore-version" for the boundary scan TAP +# +# source [find target/str912.cfg] +# if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -50,8 +55,8 @@ if { [info exists BSTAPID ] } { } jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg index 0f7ebf8..47bebc4 100644 --- a/tcl/board/mini2440.cfg +++ b/tcl/board/mini2440.cfg @@ -71,6 +71,11 @@ # # # + +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + #------------------------------------------------------------------------- # Target configuration for the Samsung 2440 system on chip # Tested on a S3C2440 Evaluation board by keesj @@ -102,8 +107,8 @@ if { [info exists CPUTAPID ] } { #jtag scan chain jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 1 #reset configuration diff --git a/tcl/board/str910-eval.cfg b/tcl/board/str910-eval.cfg index 0cf794a..a2772a8 100644 --- a/tcl/board/str910-eval.cfg +++ b/tcl/board/str910-eval.cfg @@ -3,6 +3,10 @@ # Need reset scripts reset_config trst_and_srst +# FIXME use some standard target config, maybe create one from this +# +# source [find target/...cfg] + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { @@ -37,8 +41,8 @@ if { [info exists BSTAPID ] } { } jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 1 $_TARGETNAME configure -event reset-init { diff --git a/tcl/board/zy1000.cfg b/tcl/board/zy1000.cfg index 3f526d0..8278fa4 100644 --- a/tcl/board/zy1000.cfg +++ b/tcl/board/zy1000.cfg @@ -31,8 +31,8 @@ if { [info exists CPUTAPID ] } { } jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME # at CPU CLK <32kHz this must be disabled arm7_9 fast_memory_access enable diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 47bab1e..2038331 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -10,7 +10,7 @@ set CHIPNAME ar71xx jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1 -set TARGETNAME [format "%s.cpu" $CHIPNAME] +set TARGETNAME $CHIPNAME.cpu target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME $TARGETNAME configure -event reset-halt-post { diff --git a/tcl/target/c100.cfg b/tcl/target/c100.cfg index a0a28d8..b175f23 100644 --- a/tcl/target/c100.cfg +++ b/tcl/target/c100.cfg @@ -35,7 +35,7 @@ jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_D # Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME # C100's ARAM 64k SRAM diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg index 2371dd7..769d39d 100644 --- a/tcl/target/lpc2900.cfg +++ b/tcl/target/lpc2900.cfg @@ -29,7 +29,7 @@ if { [info exists ETBTAPID ] } { reset_config trst_and_srst separate # Define the _TARGETNAME -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +set _TARGETNAME $_CHIPNAME.cpu # Include the ETB tap controller if asked for. # Has to be done manually for newer devices (not an "old" LPC2917/2919). diff --git a/tcl/target/tmpa900.cfg b/tcl/target/tmpa900.cfg index 80adc65..329e03c 100644 --- a/tcl/target/tmpa900.cfg +++ b/tcl/target/tmpa900.cfg @@ -39,8 +39,8 @@ jtag_ntrst_delay 20 # Target configuration ###################### -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME # built-in RAM0 #working_area 0 0xf8004000 0x4000 nobackup diff --git a/tcl/target/tmpa910.cfg b/tcl/target/tmpa910.cfg index 4af5e4e..29d2d6e 100644 --- a/tcl/target/tmpa910.cfg +++ b/tcl/target/tmpa910.cfg @@ -39,8 +39,8 @@ jtag_ntrst_delay 20 # Target configuration ###################### -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME # built-in RAM0 #working_area 0 0xf8004000 0x4000 nobackup commit 80a757d82eafb36ffd54414f33ce91302f4522da Author: David Brownell <dbr...@us...> Date: Tue Dec 15 09:15:54 2009 -0800 testing/examples/.../*cfg: rm jtag_device calls That syntax has been obsolete forever and is now gone; remove a few remaining references. Shows how seldom this stuff gets used. Signed-off-by: David Brownell <dbr...@us...> diff --git a/tcl/target/is5114.cfg b/tcl/target/is5114.cfg index 091bfc2..64c0c8e 100644 --- a/tcl/target/is5114.cfg +++ b/tcl/target/is5114.cfg @@ -28,12 +28,9 @@ jtag_rclk 16 reset_config trst_and_srst # Do not specify a tap id here... -#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 -#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe # This is the "arm946" chip. jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf -#OLD SYNTAX: jtag_device 5 0x1 0x1 0x1e jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1 diff --git a/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg b/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg index 95f7918..bf760b2 100644 --- a/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg +++ b/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg @@ -20,8 +20,7 @@ jtag_ntrst_delay 200 reset_config srst_only srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap at91 cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi diff --git a/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg b/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg index 8d9492b..d491d7d 100644 --- a/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg +++ b/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg @@ -18,8 +18,7 @@ jtag_speed 3 reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap lpc cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 diff --git a/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg b/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg index 526cce1..e8d3051 100644 --- a/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg +++ b/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg @@ -18,8 +18,7 @@ jtag_speed 3 reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap lpc cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg b/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg index e08b84b..4fd729e 100644 --- a/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg +++ b/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg @@ -21,8 +21,7 @@ jtag_ntrst_delay 200 reset_config srst_only srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap sam7 cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi diff --git a/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg b/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg index 17e2716..930a1b6 100644 --- a/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg +++ b/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg @@ -21,8 +21,7 @@ jtag_ntrst_delay 200 reset_config srst_only srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap sam7 cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi - endian little -chain-position 0 -variant arm7tdmi diff --git a/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg b/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg index 2bef163..0e0cff5 100644 --- a/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg +++ b/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg @@ -18,8 +18,7 @@ jtag_speed 0 reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap str7 cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi diff --git a/testing/examples/STR710Test/prj/str710_jtagkey.cfg b/testing/examples/STR710Test/prj/str710_jtagkey.cfg index da4c243..31240cc 100644 --- a/testing/examples/STR710Test/prj/str710_jtagkey.cfg +++ b/testing/examples/STR710Test/prj/str710_jtagkey.cfg @@ -18,8 +18,7 @@ jtag_speed 0 reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap str7 cpu -irlen 4 -irmask 0xf #target configuration target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi diff --git a/testing/examples/STR912Test/prj/str912_jtagkey.cfg b/testing/examples/STR912Test/prj/str912_jtagkey.cfg index 487ec04..d4577f3 100644 --- a/testing/examples/STR912Test/prj/str912_jtagkey.cfg +++ b/testing/examples/STR912Test/prj/str912_jtagkey.cfg @@ -21,10 +21,9 @@ jtag_ntrst_delay 100 reset_config trst_and_srst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 8 0x1 0x1 0xfe -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e +jtag newtap str9 flash -irlen 8 +jtag newtap str9 cpu -irlen 4 -irmask 0xf +jtag newtap str9 bs -irlen 5 #target configuration target create target0 arm966e -endian little -chain-position 1 -variant arm966e commit fc99287b097e719a6dbe8d139e71c5ed136e48e8 Author: David Brownell <dbr...@us...> Date: Mon Dec 14 20:06:21 2009 -0800 XScale: use all-ones for BYPASS, not five-ones PXA3xx has more than five bits in IR. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/xscale.c b/src/target/xscale.c index 9ed9eea..4cf5aeb 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -1496,7 +1496,7 @@ static int xscale_assert_reset(struct target *target) xscale_write_dcsr(target, 1, 0); /* select BYPASS, because having DCSR selected caused problems on the PXA27x */ - xscale_jtag_set_instr(target->tap, 0x7f); + xscale_jtag_set_instr(target->tap, ~0); jtag_execute_queue(); /* assert reset */ ----------------------------------------------------------------------- Summary of changes: src/target/xscale.c | 2 +- tcl/board/at91eb40a.cfg | 7 +++++-- tcl/board/at91sam9g20-ek.cfg | 8 ++++++-- tcl/board/digi_connectcore_wi-9c.cfg | 8 ++++++-- tcl/board/hitex_str9-comstick.cfg | 13 +++++++++---- tcl/board/mini2440.cfg | 9 +++++++-- tcl/board/str910-eval.cfg | 8 ++++++-- tcl/board/zy1000.cfg | 4 ++-- tcl/target/ar71xx.cfg | 2 +- tcl/target/c100.cfg | 2 +- tcl/target/is5114.cfg | 3 --- tcl/target/lpc2900.cfg | 2 +- tcl/target/tmpa900.cfg | 4 ++-- tcl/target/tmpa910.cfg | 4 ++-- .../AT91R40008Test/prj/at91r40008_turtle.cfg | 3 +-- .../examples/LPC2148Test/prj/lpc2148_jtagkey.cfg | 3 +-- .../examples/LPC2294Test/prj/lpc2294_jtagkey.cfg | 3 +-- .../examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg | 3 +-- .../examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg | 3 +-- .../STR710JtagSpeed/prj/str710_jtagkey.cfg | 3 +-- testing/examples/STR710Test/prj/str710_jtagkey.cfg | 3 +-- testing/examples/STR912Test/prj/str912_jtagkey.cfg | 7 +++---- 22 files changed, 59 insertions(+), 45 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-15 18:41:22
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 646ce814b4fb678b7d8d341afe0694c266112426 (commit) from 4639366947427da6face9cb6954b6603eb2e2fd3 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 646ce814b4fb678b7d8d341afe0694c266112426 Author: mk...@us... <mk...@us...> Date: Tue Dec 15 18:30:59 2009 +0100 target: add basic dsp563xx support diff --git a/doc/openocd.texi b/doc/openocd.texi index 01dfa76..9d56523 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -3157,6 +3157,8 @@ This is fixed in Fury Rev B, DustDevil Rev B, Tempest; these revisions will be detected and the normal reset behaviour used. @end itemize @item @code{dragonite} -- resembles arm966e +@item @code{dsp563xx} -- implements Freescale's 24-bit DSP. +(Support for this is still incomplete.) @item @code{fa526} -- resembles arm920 (w/o Thumb) @item @code{feroceon} -- resembles arm926 @item @code{mips_m4k} -- a MIPS core. This supports one variant: diff --git a/src/target/Makefile.am b/src/target/Makefile.am index f1d4caa..df54a03 100644 --- a/src/target/Makefile.am +++ b/src/target/Makefile.am @@ -33,7 +33,9 @@ libtarget_la_SOURCES = \ $(ARMV7_SRC) \ $(ARM_MISC_SRC) \ $(MIPS32_SRC) \ - avrt.c + avrt.c \ + dsp563xx.c \ + dsp563xx_once.c TARGET_CORE_SRC = \ algorithm.c \ @@ -120,6 +122,8 @@ noinst_HEADERS = \ armv7a.h \ armv7m.h \ avrt.h \ + dsp563xx.h \ + dsp563xx_once.h \ breakpoints.h \ cortex_m3.h \ cortex_a8.h \ diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c new file mode 100644 index 0000000..d3fa4c3 --- /dev/null +++ b/src/target/dsp563xx.c @@ -0,0 +1,990 @@ +/*************************************************************************** + * Copyright (C) 2009 by Mathias Kuester * + * mk...@us... * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/jim.h> + +#include "target.h" +#include "target_type.h" +#include "register.h" +#include "dsp563xx.h" +#include "dsp563xx_once.h" + +#define DSP563XX_JTAG_INS_LEN 4 + +#define JTAG_STATUS_NORMAL 0x01 +#define JTAG_STATUS_STOPWAIT 0x05 +#define JTAG_STATUS_BUSY 0x09 +#define JTAG_STATUS_DEBUG 0x0d + +#define JTAG_INSTR_EXTEST 0x00 +#define JTAG_INSTR_SAMPLE_PRELOAD 0x01 +#define JTAG_INSTR_IDCODE 0x02 +#define JTAG_INSTR_CLAMP 0x03 +#define JTAG_INSTR_HIZ 0x04 +#define JTAG_INSTR_ENABLE_ONCE 0x06 +#define JTAG_INSTR_DEBUG_REQUEST 0x07 +#define JTAG_INSTR_BYPASS 0x0F + +/* forward declarations */ +int dsp563xx_target_create(struct target *target, Jim_Interp * interp); +int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target); + +int dsp563xx_arch_state(struct target *target); +int dsp563xx_poll(struct target *target); +int dsp563xx_halt(struct target *target); +int dsp563xx_resume(struct target *target, int current, uint32_t address, + int handle_breakpoints, int debug_execution); +int dsp563xx_step(struct target *target, int current, uint32_t address, + int handle_breakpoints); + +int dsp563xx_assert_reset(struct target *target); +int dsp563xx_deassert_reset(struct target *target); +int dsp563xx_soft_reset_halt(struct target *target); + +/* IR and DR functions */ +int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out); +int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out, + int len); + +int dsp563xx_read_memory_p(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t * buffer); +int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t * buffer); + +#define ASM_REG_R_R0 0x607000 +#define ASM_REG_R_R1 0x617000 +#define ASM_REG_R_R2 0x627000 +#define ASM_REG_R_R3 0x637000 +#define ASM_REG_R_R4 0x647000 +#define ASM_REG_R_R5 0x657000 +#define ASM_REG_R_R6 0x667000 +#define ASM_REG_R_R7 0x677000 + +#define ASM_REG_W_R0 0x60F400 +#define ASM_REG_W_R1 0x61F400 +#define ASM_REG_W_R2 0x62F400 +#define ASM_REG_W_R3 0x63F400 +#define ASM_REG_W_R4 0x64F400 +#define ASM_REG_W_R5 0x65F400 +#define ASM_REG_W_R6 0x66F400 +#define ASM_REG_W_R7 0x67F400 + +#define ASM_REG_R_N0 0x707000 +#define ASM_REG_R_N1 0x717000 +#define ASM_REG_R_N2 0x727000 +#define ASM_REG_R_N3 0x737000 +#define ASM_REG_R_N4 0x747000 +#define ASM_REG_R_N5 0x757000 +#define ASM_REG_R_N6 0x767000 +#define ASM_REG_R_N7 0x777000 + +#define ASM_REG_W_N0 0x70F400 +#define ASM_REG_W_N1 0x71F400 +#define ASM_REG_W_N2 0x72F400 +#define ASM_REG_W_N3 0x73F400 +#define ASM_REG_W_N4 0x74F400 +#define ASM_REG_W_N5 0x75F400 +#define ASM_REG_W_N6 0x76F400 +#define ASM_REG_W_N7 0x77F400 + +#define ASM_REG_R_M0 0x057020 /* control register m[0..7] */ +#define ASM_REG_R_M1 0x057021 +#define ASM_REG_R_M2 0x057022 +#define ASM_REG_R_M3 0x057023 +#define ASM_REG_R_M4 0x057024 +#define ASM_REG_R_M5 0x057025 +#define ASM_REG_R_M6 0x057026 +#define ASM_REG_R_M7 0x057027 + +#define ASM_REG_W_M0 0x05F420 +#define ASM_REG_W_M1 0x05F421 +#define ASM_REG_W_M2 0x05F422 +#define ASM_REG_W_M3 0x05F423 +#define ASM_REG_W_M4 0x05F424 +#define ASM_REG_W_M5 0x05F425 +#define ASM_REG_W_M6 0x05F426 +#define ASM_REG_W_M7 0x05F427 + +#define ASM_REG_R_X0 0x447000 +#define ASM_REG_R_X1 0x457000 + +#define ASM_REG_W_X0 0x44F400 +#define ASM_REG_W_X1 0x45F400 + +#define ASM_REG_R_Y0 0x467000 +#define ASM_REG_R_Y1 0x477000 + +#define ASM_REG_W_Y0 0x46F400 +#define ASM_REG_W_Y1 0x47F400 + +#define ASM_REG_R_A0 0x507000 +#define ASM_REG_R_A1 0x547000 +#define ASM_REG_R_A2 0x527000 + +#define ASM_REG_W_A0 0x50F400 +#define ASM_REG_W_A1 0x54F400 +#define ASM_REG_W_A2 0x52F400 + +#define ASM_REG_R_B0 0x517000 +#define ASM_REG_R_B1 0x557000 +#define ASM_REG_R_B2 0x537000 + +#define ASM_REG_W_B0 0x51F400 +#define ASM_REG_W_B1 0x55F400 +#define ASM_REG_W_B2 0x53F400 + +#define ASM_REG_R_VBA 0x057030 /* control register */ +#define ASM_REG_W_VBA 0x05F430 + +#define ASM_REG_R_OMR 0x05703A /* control register */ +#define ASM_REG_W_OMR 0x05F43A + +#define ASM_REG_R_EP 0x05702A +#define ASM_REG_W_EP 0x05F42A + +#define ASM_REG_R_SC 0x057031 /* stack counter */ +#define ASM_REG_W_SC 0x05F431 + +#define ASM_REG_R_SZ 0x057038 /* stack size */ +#define ASM_REG_W_SZ 0x05F438 + +#define ASM_REG_R_SR 0x057039 /* control register, status register */ +#define ASM_REG_W_SR 0x05F439 + +#define ASM_REG_R_SP 0x05703B /* control register, stack pointer */ +#define ASM_REG_W_SP 0x05F43B + +#define ASM_REG_R_SSH 0x05703C /* control register, system stack high */ +#define ASM_REG_W_SSH 0x05743C + +#define ASM_REG_R_SSL 0x05703D /* control register, system stack low */ +#define ASM_REG_W_SSL 0x05F43D + +#define ASM_REG_R_LA 0x05703E /* control register, loop address */ +#define ASM_REG_W_LA 0x05F43E + +#define ASM_REG_R_LC 0x05703F /* control register, loop count */ +#define ASM_REG_W_LC 0x05F43F + +#define ASM_REG_R_PC 0x000000 +#define ASM_REG_W_PC 0x000000 + +static const struct +{ + unsigned id; + char *name; + unsigned bits; + uint32_t r_cmd; + uint32_t w_cmd; +} dsp563xx_regs[] = +{ + /* *INDENT-OFF* */ + {0, "r0", 24, ASM_REG_R_R0, ASM_REG_W_R0}, + {1, "r1", 24, ASM_REG_R_R1, ASM_REG_W_R1}, + {2, "r2", 24, ASM_REG_R_R2, ASM_REG_W_R2}, + {3, "r3", 24, ASM_REG_R_R3, ASM_REG_W_R3}, + {4, "r4", 24, ASM_REG_R_R4, ASM_REG_W_R4}, + {5, "r5", 24, ASM_REG_R_R5, ASM_REG_W_R5}, + {6, "r6", 24, ASM_REG_R_R6, ASM_REG_W_R6}, + {7, "r7", 24, ASM_REG_R_R7, ASM_REG_W_R7}, + {8, "n0", 24, ASM_REG_R_N0, ASM_REG_W_N0}, + {9, "n1", 24, ASM_REG_R_N1, ASM_REG_W_N1}, + {10, "n2", 24, ASM_REG_R_N2, ASM_REG_W_N2}, + {11, "n3", 24, ASM_REG_R_N3, ASM_REG_W_N3}, + {12, "n4", 24, ASM_REG_R_N4, ASM_REG_W_N4}, + {13, "n5", 24, ASM_REG_R_N5, ASM_REG_W_N5}, + {14, "n6", 24, ASM_REG_R_N6, ASM_REG_W_N6}, + {15, "n7", 24, ASM_REG_R_N7, ASM_REG_W_N7}, + {16, "m0", 24, ASM_REG_R_M0, ASM_REG_W_M0}, + {17, "m1", 24, ASM_REG_R_M1, ASM_REG_W_M1}, + {18, "m2", 24, ASM_REG_R_M2, ASM_REG_W_M2}, + {19, "m3", 24, ASM_REG_R_M3, ASM_REG_W_M3}, + {20, "m4", 24, ASM_REG_R_M4, ASM_REG_W_M4}, + {21, "m5", 24, ASM_REG_R_M5, ASM_REG_W_M5}, + {22, "m6", 24, ASM_REG_R_M6, ASM_REG_W_M6}, + {23, "m7", 24, ASM_REG_R_M7, ASM_REG_W_M7}, + {24, "x0", 24, ASM_REG_R_X0, ASM_REG_W_X0}, + {25, "x1", 24, ASM_REG_R_X1, ASM_REG_W_X1}, + {26, "y0", 24, ASM_REG_R_Y0, ASM_REG_W_Y0}, + {27, "y1", 24, ASM_REG_R_Y1, ASM_REG_W_Y1}, + {28, "a0", 24, ASM_REG_R_A0, ASM_REG_W_A0}, + {29, "a1", 24, ASM_REG_R_A1, ASM_REG_W_A1}, + {30, "a2", 8, ASM_REG_R_A2, ASM_REG_W_A2}, + {31, "b0", 24, ASM_REG_R_B0, ASM_REG_W_B0}, + {32, "b1", 24, ASM_REG_R_B1, ASM_REG_W_B1}, + {33, "b2", 8, ASM_REG_R_B2, ASM_REG_W_B2}, + {34, "omr", 24, ASM_REG_R_OMR, ASM_REG_W_OMR}, + {35, "vba", 24, ASM_REG_R_VBA, ASM_REG_W_VBA}, + {36, "ep", 24, ASM_REG_R_EP, ASM_REG_W_EP}, + {37, "sc", 24, ASM_REG_R_SC, ASM_REG_W_SC}, + {38, "sz", 24, ASM_REG_R_SZ, ASM_REG_W_SZ}, + {39, "sr", 24, ASM_REG_R_SR, ASM_REG_W_SR}, + {40, "sp", 24, ASM_REG_R_SP, ASM_REG_W_SP}, + {41, "la", 24, ASM_REG_R_LA, ASM_REG_W_LA}, + {42, "lc", 24, ASM_REG_R_LC, ASM_REG_W_LC}, + {43, "pc", 24, ASM_REG_R_PC, ASM_REG_W_PC} + /* *INDENT-ON* */ +}; + +int dsp563xx_read_core_reg(struct target *target, int num) +{ + uint32_t reg_value; + struct dsp563xx_core_reg *dsp563xx_core_reg; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if ((num < 0) || (num >= DSP563XX_NUMCOREREGS)) + return ERROR_INVALID_ARGUMENTS; + + dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info; + reg_value = dsp563xx->core_regs[num]; + buf_set_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32, reg_value); + dsp563xx->core_cache->reg_list[num].valid = 1; + dsp563xx->core_cache->reg_list[num].dirty = 0; + + return ERROR_OK; +} + +int dsp563xx_write_core_reg(struct target *target, int num) +{ + uint32_t reg_value; + struct dsp563xx_core_reg *dsp563xx_core_reg; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if ((num < 0) || (num >= DSP563XX_NUMCOREREGS)) + return ERROR_INVALID_ARGUMENTS; + + reg_value = buf_get_u32(dsp563xx->core_cache->reg_list[num].value, 0, 32); + dsp563xx_core_reg = dsp563xx->core_cache->reg_list[num].arch_info; + dsp563xx->core_regs[num] = reg_value; + dsp563xx->core_cache->reg_list[num].valid = 1; + dsp563xx->core_cache->reg_list[num].dirty = 0; + + return ERROR_OK; +} + +int dsp563xx_target_create(struct target *target, Jim_Interp * interp) +{ + struct dsp563xx_common *dsp563xx = calloc(1, sizeof(struct dsp563xx_common)); + + dsp563xx->jtag_info.tap = target->tap; + target->arch_info = dsp563xx; + dsp563xx->read_core_reg = dsp563xx_read_core_reg; + dsp563xx->write_core_reg = dsp563xx_write_core_reg; + + return ERROR_OK; +} + +int dsp563xx_get_core_reg(struct reg *reg) +{ + int retval = 0; + + LOG_DEBUG("%s", __FUNCTION__); + + struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info; + struct target *target = dsp563xx_reg->target; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if (target->state != TARGET_HALTED) + { + return ERROR_TARGET_NOT_HALTED; + } + + retval = dsp563xx->read_core_reg(target, dsp563xx_reg->num); + + return retval; +} + +int dsp563xx_set_core_reg(struct reg *reg, uint8_t * buf) +{ + LOG_DEBUG("%s", __FUNCTION__); + + struct dsp563xx_core_reg *dsp563xx_reg = reg->arch_info; + struct target *target = dsp563xx_reg->target; + uint32_t value = buf_get_u32(buf, 0, 32); + + if (target->state != TARGET_HALTED) + { + return ERROR_TARGET_NOT_HALTED; + } + + buf_set_u32(reg->value, 0, reg->size, value); + reg->dirty = 1; + reg->valid = 1; + + return ERROR_OK; +} + +int dsp563xx_save_context(struct target *target) +{ + int i; + uint32_t data = 0; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + struct dsp563xx_core_reg *arch_info; + + for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++) + { + +// if (!dsp563xx->core_cache->reg_list[i].valid) + { + arch_info = dsp563xx->core_cache->reg_list[i].arch_info; + dsp563xx_once_execute_dw_ir(target->tap, arch_info->r_cmd, + 0xfffffc); + dsp563xx_once_execute_sw_ir(target->tap, 0x000000); + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, + &data); + dsp563xx->core_regs[i] = data; + dsp563xx->read_core_reg(target, i); + } + } + + /* read pc */ + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, &data); + dsp563xx->core_regs[i] = data; + dsp563xx->read_core_reg(target, i); + + return ERROR_OK; +} + +int dsp563xx_restore_context(struct target *target) +{ + int i; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + struct dsp563xx_core_reg *arch_info; + + for (i = 0; i < DSP563XX_NUMCOREREGS - 1; i++) + { + if (dsp563xx->core_cache->reg_list[i].dirty) + { + arch_info = dsp563xx->core_cache->reg_list[i].arch_info; + + dsp563xx->write_core_reg(target, i); + + dsp563xx_once_execute_dw_ir(target->tap, arch_info->w_cmd, + dsp563xx->core_regs[i]); + dsp563xx_once_execute_sw_ir(target->tap, 0x000000); + } + } + + return ERROR_OK; +} + +static const struct reg_arch_type dsp563xx_reg_type = { + .get = dsp563xx_get_core_reg, + .set = dsp563xx_set_core_reg, +}; + +int dsp563xx_init_target(struct command_context *cmd_ctx, struct target *target) +{ + /* get pointers to arch-specific information */ + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); + struct reg_cache *cache = malloc(sizeof(struct reg_cache)); + struct reg *reg_list = malloc(sizeof(struct reg) * DSP563XX_NUMCOREREGS); + struct dsp563xx_core_reg *arch_info = + malloc(sizeof(struct dsp563xx_core_reg) * DSP563XX_NUMCOREREGS); + int i; + + LOG_DEBUG("%s", __FUNCTION__); + + /* Build the process context cache */ + cache->name = "dsp563xx registers"; + cache->next = NULL; + cache->reg_list = reg_list; + cache->num_regs = DSP563XX_NUMCOREREGS; + (*cache_p) = cache; + dsp563xx->core_cache = cache; + + for (i = 0; i < DSP563XX_NUMCOREREGS; i++) + { + arch_info[i].num = dsp563xx_regs[i].id; + arch_info[i].name = dsp563xx_regs[i].name; + arch_info[i].size = dsp563xx_regs[i].bits; + arch_info[i].r_cmd = dsp563xx_regs[i].r_cmd; + arch_info[i].w_cmd = dsp563xx_regs[i].w_cmd; + arch_info[i].target = target; + arch_info[i].dsp563xx_common = dsp563xx; + reg_list[i].name = dsp563xx_regs[i].name; + reg_list[i].size = dsp563xx_regs[i].bits; + reg_list[i].value = calloc(1, 4); + reg_list[i].dirty = 0; + reg_list[i].valid = 0; + reg_list[i].type = &dsp563xx_reg_type; + reg_list[i].arch_info = &arch_info[i]; + } + + return ERROR_OK; +} + +int dsp563xx_arch_state(struct target *target) +{ + LOG_DEBUG("%s", __FUNCTION__); + return ERROR_OK; +} + +int dsp563xx_jtag_status(struct target *target, uint8_t * status) +{ + uint8_t ir_in; + + ir_in = 0; + + dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE); + dsp563xx_execute_queue(); + + *status = ir_in; + + return ERROR_OK; +} + +int dsp563xx_jtag_debug_request(struct target *target) +{ + uint8_t ir_in = 0; + uint32_t retry = 0; + + while (ir_in != JTAG_STATUS_DEBUG) + { + dsp563xx_jtag_sendinstr(target->tap, &ir_in, + JTAG_INSTR_DEBUG_REQUEST); + dsp563xx_execute_queue(); + LOG_DEBUG("JTAG CMD 7 res: %02X", ir_in); + dsp563xx_jtag_sendinstr(target->tap, &ir_in, JTAG_INSTR_ENABLE_ONCE); + dsp563xx_execute_queue(); + LOG_DEBUG("JTAG CMD 6 res: %02X", ir_in); + + if (retry++ == 100) + return ERROR_TARGET_FAILURE; + } + + if (ir_in != JTAG_STATUS_DEBUG) + { + return ERROR_TARGET_FAILURE; + } + + return ERROR_OK; +} + +int dsp563xx_poll(struct target *target) +{ + uint8_t jtag_status; + uint32_t once_status; + + dsp563xx_jtag_status(target, &jtag_status); + + if ((jtag_status & 1) != 1) + { + target->state = TARGET_UNKNOWN; + LOG_ERROR + ("jtag status contains invalid mode value - communication failure"); + return ERROR_TARGET_FAILURE; + } + + if (jtag_status != JTAG_STATUS_DEBUG) + { + target->state = TARGET_RUNNING; + } + + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, &once_status); + + if ((once_status & DSP563XX_ONCE_OSCR_DEBUG_M) == DSP563XX_ONCE_OSCR_DEBUG_M) + { + target->state = TARGET_HALTED; + + } + + return ERROR_OK; +} + +int dsp563xx_halt(struct target *target) +{ + uint8_t jtag_status; + uint32_t once_status; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if (target->state == TARGET_HALTED) + { + LOG_DEBUG("target was already halted"); + return ERROR_OK; + } + + if (target->state == TARGET_UNKNOWN) + { + LOG_WARNING("target was in unknown state when halt was requested"); + } + +// if ( jtag_status != 0x0d ) + { + dsp563xx_jtag_debug_request(target); + + /* store pipeline register */ + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR, + &dsp563xx->pipeline_context.once_opilr); + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR, + &dsp563xx->pipeline_context.once_opdbr); + + dsp563xx_save_context(target); + + dsp563xx_jtag_status(target, &jtag_status); + LOG_DEBUG("%02X", jtag_status); + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, + &once_status); + LOG_DEBUG("%02X", once_status); + } + + LOG_DEBUG("target->state: %s", target_state_name(target)); + + LOG_DEBUG("%s", __FUNCTION__); + + return ERROR_OK; +} + +#define DSP563XX_ASM_CMD_JUMP 0x0AF080 + +int dsp563xx_resume(struct target *target, int current, uint32_t address, + int handle_breakpoints, int debug_execution) +{ + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + LOG_DEBUG("%s", __FUNCTION__); + + dsp563xx_restore_context(target); + + if (current) + { + /* restore pipeline registers and go */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR, + dsp563xx->pipeline_context.once_opilr); + dsp563xx_once_reg_write(target->tap, + DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | + DSP563XX_ONCE_OCR_GO, + dsp563xx->pipeline_context.once_opdbr); + } + else + { + /* set to go register and jump */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR, + DSP563XX_ASM_CMD_JUMP); + dsp563xx_once_reg_write(target->tap, + DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX + | DSP563XX_ONCE_OCR_GO, address); + } + + target->state = TARGET_RUNNING; + + return ERROR_OK; +} + +int dsp563xx_step(struct target *target, int current, uint32_t address, + int handle_breakpoints) +{ + uint32_t once_status; + uint32_t dr_in, cnt; + struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target); + + if (target->state != TARGET_HALTED) + { + LOG_DEBUG("target was not halted"); + return ERROR_OK; + } + + LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, address); + + dsp563xx_jtag_debug_request(target); + + dsp563xx_restore_context(target); + + /* reset trace mode */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, 0x000000); + /* enable trace mode */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, + DSP563XX_ONCE_OSCR_TME); + + cnt = 0; + + /* on JUMP we need one extra cycle */ + if (!current) + cnt++; + + /* load step counter with N-1 */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OTC, cnt); + + if (current) + { + /* restore pipeline registers and go */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPILR, + dsp563xx->pipeline_context.once_opilr); + dsp563xx_once_reg_write(target->tap, + DSP563XX_ONCE_OPDBR | DSP563XX_ONCE_OCR_EX | + DSP563XX_ONCE_OCR_GO, + dsp563xx->pipeline_context.once_opdbr); + } + else + { + /* set to go register and jump */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OPDBR, + DSP563XX_ASM_CMD_JUMP); + dsp563xx_once_reg_write(target->tap, + DSP563XX_ONCE_PDBGOTO | DSP563XX_ONCE_OCR_EX + | DSP563XX_ONCE_OCR_GO, address); + } + + while (1) + { + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR, + &once_status); + + if (once_status & DSP563XX_ONCE_OSCR_TO) + { + /* store pipeline register */ + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPILR, + &dsp563xx->pipeline_context. + once_opilr); + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPDBR, + &dsp563xx->pipeline_context. + once_opdbr); + + dsp563xx_save_context(target); + + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABFR, + &dr_in); + LOG_DEBUG("%08X", dr_in); + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR, + &dr_in); + LOG_DEBUG("%08X", dr_in); + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX, + &dr_in); + LOG_DEBUG("%08X", dr_in); + + /* reset trace mode */ + dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR, + 0x000000); + + break; + } + } + + return ERROR_OK; +} + +int dsp563xx_assert_reset(struct target *target) +{ + target->state = TARGET_RESET; + + LOG_DEBUG("%s", __FUNCTION__); + return ERROR_OK; +} + +int dsp563xx_deassert_reset(struct target *target) +{ + target->state = TARGET_RUNNING; + + LOG_DEBUG("%s", __FUNCTION__); + return ERROR_OK; +} + +int dsp563xx_soft_reset_halt(struct target *target) +{ + LOG_DEBUG("%s", __FUNCTION__); + return ERROR_OK; +} + +/* +* 000000 nop +* 46F400 AABBCC move #$aabbcc,y0 +* 60F400 AABBCC move #$aabbcc,r0 +* 467000 AABBCC move y0,x:AABBCC +* 607000 AABBCC move r0,x:AABBCC + +* 46E000 move x:(r0),y0 +* 4EE000 move y:(r0),y0 +* 07E086 move p:(r0),y0 + +* 0450B9 move sr,r0 +* 0446BA move omr,y0 +* 0446BC move ssh,y0 +* 0446BD move ssl,y0 +* 0446BE move la,y0 +* 0446BF move lc,y0 +* +* 61F000 AABBCC move x:AABBCC,r1 +* 076190 movem r0,p:(r1) +* +*/ +int dsp563xx_read_memory_p(struct target *target, uint32_t address, + uint32_t size, uint32_t count, uint8_t * buffer) +{ + uint32_t i, x; + uint32_t data; + uint8_t *b; + + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" + PRIx32, address, size, count); + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + x = count; + + for (i = 0; i < x; i++) + { + dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, address + i); + dsp563xx_once_execute_sw_ir_nq(target->tap, 0x07E086); + dsp563xx_once_execute_dw_ir_nq(target->tap, 0x467000, 0xfffffc); + dsp563xx_execute_queue(); + + dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OGDBR, &data); + + b = buffer + 4 * i; + if (size > 0) + *b++ = data >> 0; + if (size > 1) + *b++ = data >> 8; + if (size > 2) + *b++ = data >> 16; + if (size > 3) + *b++ = 0x00; + } + + return ERROR_OK; +} + +int dsp563xx_write_memory_p(struct target *target, uint32_t address, uint32_t size, + uint32_t count, uint8_t * buffer) +{ + uint32_t i, x; + uint32_t data; + uint8_t *b; + + LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" + PRIx32 "", address, size, count); + + if (target->state != TARGET_HALTED) + { + LOG_WARNING("target not halted"); + return ERROR_TARGET_NOT_HALTED; + } + + x = count; + + for (i = 0; i < x; i++) + { + b = buffer + 4 * i; + + data = 0; + if (size > 0) + data = *buffer++; + if (size > 1) + data |= (*buffer++) << 8; + if (size > 2) + data |= (*buffer++) << 16; + if (size > 3) + data |= (*buffer++) << 24; + +// LOG_DEBUG("%08X", data); + + dsp563xx_once_execute_dw_ir_nq(target->tap, 0x61F400, address + i); + dsp563xx_once_execute_dw_ir_nq(target->tap, 0x60F400, data); + dsp563xx_once_execute_sw_ir_nq(target->tap, 0x076190); + dsp563xx_execute_queue(); + } + + return ERROR_OK; +} + +int dsp563xx_jtag_senddat(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out, + int len) +{ + return dsp563xx_write_dr_u32(tap, dr_in, dr_out, len, 1); +} + +int dsp563xx_jtag_sendinstr(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out) +{ + return dsp563xx_write_ir_u8(tap, ir_in, ir_out, DSP563XX_JTAG_INS_LEN, 1); +} + +/* IR and DR functions */ +int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out, + int ir_len, int rti) +{ + if (NULL == tap) + { + LOG_ERROR("invalid tap"); + return ERROR_FAIL; + } + if (ir_len != tap->ir_length) + { + LOG_ERROR("invalid ir_len"); + return ERROR_FAIL; + } + + { + struct scan_field field[1]; + + field[0].tap = tap; + field[0].num_bits = tap->ir_length; + field[0].out_value = ir_out; + field[0].in_value = ir_in; + jtag_add_plain_ir_scan(ARRAY_SIZE(field), field, + jtag_set_end_state(TAP_IDLE)); + } + + return ERROR_OK; +} + +int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out, + int dr_len, int rti) +{ + if (NULL == tap) + { + LOG_ERROR("invalid tap"); + return ERROR_FAIL; + } + + { + struct scan_field field[1]; + + field[0].tap = tap; + field[0].num_bits = dr_len; + field[0].out_value = dr_out; + field[0].in_value = dr_in; + jtag_add_plain_dr_scan(ARRAY_SIZE(field), field, + jtag_set_end_state(TAP_IDLE)); + } + + return ERROR_OK; +} + +int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out, + int ir_len, int rti) +{ + if (ir_len > 8) + { + LOG_ERROR("ir_len overflow, maxium is 8"); + return ERROR_FAIL; + } + + dsp563xx_write_ir(tap, ir_in, &ir_out, ir_len, rti); + + return ERROR_OK; +} + +int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * dr_in, uint8_t dr_out, + int dr_len, int rti) +{ + if (dr_len > 8) + { + LOG_ERROR("dr_len overflow, maxium is 8"); + return ERROR_FAIL; + } + + dsp563xx_write_dr(tap, dr_in, &dr_out, dr_len, rti); + + return ERROR_OK; +} + +int dsp563xx_write_ir_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out, + int ir_len, int rti) +{ + if (ir_len > 16) + { + LOG_ERROR("ir_len overflow, maxium is 16"); + return ERROR_FAIL; + } + + dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti); + + return ERROR_OK; +} + +int dsp563xx_write_dr_u16(struct jtag_tap *tap, uint16_t * dr_in, uint16_t dr_out, + int dr_len, int rti) +{ + if (dr_len > 16) + { + LOG_ERROR("dr_len overflow, maxium is 16"); + return ERROR_FAIL; + } + + dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti); + + return ERROR_OK; +} + +int dsp563xx_write_ir_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out, + int ir_len, int rti) +{ + if (ir_len > 32) + { + LOG_ERROR("ir_len overflow, maxium is 32"); + return ERROR_FAIL; + } + + dsp563xx_write_ir(tap, (uint8_t *) ir_in, (uint8_t *) & ir_out, ir_len, rti); + + return ERROR_OK; +} + +int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * dr_in, uint32_t dr_out, + int dr_len, int rti) +{ + if (dr_len > 32) + { + LOG_ERROR("dr_len overflow, maxium is 32"); + return ERROR_FAIL; + } + + dsp563xx_write_dr(tap, (uint8_t *) dr_in, (uint8_t *) & dr_out, dr_len, rti); + + return ERROR_OK; +} + +int dsp563xx_execute_queue(void) +{ + return jtag_execute_queue(); +} + +/** Holds methods for DSP563XX targets. */ +struct target_type dsp563xx_target = { + .name = "dsp563xx", + + .poll = dsp563xx_poll, + .arch_state = dsp563xx_arch_state, + + .target_request_data = NULL, + + .halt = dsp563xx_halt, + .resume = dsp563xx_resume, + .step = dsp563xx_step, + + .assert_reset = dsp563xx_assert_reset, + .deassert_reset = dsp563xx_deassert_reset, + .soft_reset_halt = dsp563xx_soft_reset_halt, + + .read_memory = dsp563xx_read_memory_p, + .write_memory = dsp563xx_write_memory_p, + + .target_create = dsp563xx_target_create, + .init_target = dsp563xx_init_target, +}; diff --git a/src/target/dsp563xx.h b/src/target/dsp563xx.h new file mode 100644 index 0000000..73050b6 --- /dev/null +++ b/src/target/dsp563xx.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2009 by Mathias Kuester * + * mk...@us... * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef DSP563XX_H +#define DSP563XX_H + +#include <jtag/jtag.h> + +#define DSP563XX_NUMCOREREGS 44 + +struct mcu_jtag +{ + struct jtag_tap *tap; +}; + +struct dsp563xx_pipeline_context +{ + /* PIL Register */ + uint32_t once_opilr; + /* PDB Register */ + uint32_t once_opdbr; +}; + +struct dsp563xx_common +{ + struct mcu_jtag jtag_info; + struct reg_cache *core_cache; + uint32_t core_regs[DSP563XX_NUMCOREREGS]; + + struct dsp563xx_pipeline_context pipeline_context; + + /* register cache to processor synchronization */ + int (*read_core_reg) (struct target * target, int num); + int (*write_core_reg) (struct target * target, int num); +}; + +struct dsp563xx_core_reg +{ + uint32_t num; + char *name; + uint32_t size; + uint32_t r_cmd; + uint32_t w_cmd; + struct target *target; + struct dsp563xx_common *dsp563xx_common; +}; + +static inline struct dsp563xx_common *target_to_dsp563xx(struct target *target) +{ + return target->arch_info; +} + +int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out, + int ir_len, int rti); +int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out, + int dr_len, int rti); +int dsp563xx_write_ir_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out, + int ir_len, int rti); +int dsp563xx_write_dr_u8(struct jtag_tap *tap, uint8_t * ir_in, uint8_t ir_out, + int dr_len, int rti); +int dsp563xx_write_ir_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out, + int ir_len, int rti); +int dsp563xx_write_dr_u16(struct jtag_tap *tap, uint16_t * ir_in, uint16_t ir_out, + int dr_len, int rti); +int dsp563xx_write_ir_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out, + int ir_len, int rti); +int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t * ir_in, uint32_t ir_out, + int dr_len, int rti); + +int dsp563xx_execute_queue(void); + +#endif /* DSP563XX_H */ diff --git a/src/target/dsp563xx_once.c b/src/target/dsp563xx_once.c new file mode 100644 index 0000000..0186751 --- /dev/null +++ b/src/target/dsp563xx_once.c @@ -0,0 +1,124 @@ +/*************************************************************************** + * Copyright (C) 2009 by Mathias Kuester * + * mk...@us... * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <helper/jim.h> + +#include "target.h" +#include "target_type.h" +#include "register.h" +#include "dsp563xx.h" +#include "dsp563xx_once.h" + +/** single word instruction */ +int dsp563xx_once_ir_exec(struct jtag_tap *tap, uint8_t instr, uint8_t rw, + uint8_t go, uint8_t ex) +{ + dsp563xx_write_dr_u8(tap, 0, + instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0); + dsp563xx_execute_queue(); + + return ERROR_OK; +} + +/** single word instruction */ +int dsp563xx_once_ir_exec_nq(struct jtag_tap *tap, uint8_t instr, uint8_t rw, + uint8_t go, uint8_t ex) +{ + dsp563xx_write_dr_u8(tap, 0, + instr | (ex << 5) | (go << 6) | (rw << 7), 8, 0); + + return ERROR_OK; +} + +/** once read register */ +int dsp563xx_once_reg_read(struct jtag_tap *tap, uint8_t reg, uint32_t * data) +{ + uint32_t dr_in; + + dr_in = 0; + + dsp563xx_once_ir_exec(tap, reg, 1, 0, 0); + dsp563xx_write_dr_u32(tap, &dr_in, 0x00, 24, 0); + dsp563xx_execute_queue(); + + *data = dr_in; + + return ERROR_OK; +} + +/** once write register */ +int dsp563xx_once_reg_write(struct jtag_tap *tap, uint8_t reg, uint32_t data) +{ + dsp563xx_once_ir_exec(tap, reg, 0, 0, 0); + dsp563xx_write_dr_u32(tap, 0x00, data, 24, 0); + dsp563xx_execute_queue(); + + return ERROR_OK; +} + +/** single word instruction */ +int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, uint32_t opcode) +{ + dsp563xx_once_ir_exec(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0); + dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + dsp563xx_execute_queue(); + + return ERROR_OK; +} + +/** double word instruction */ +int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, uint32_t opcode, + uint32_t operand) +{ + dsp563xx_once_ir_exec(tap, DSP563XX_ONCE_OPDBR, 0, 0, 0); + dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + dsp563xx_execute_queue(); + + dsp563xx_once_ir_exec(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0); + dsp563xx_write_dr_u32(tap, 0, operand, 24, 0); + dsp563xx_execute_queue(); + + return ERROR_OK; +} + +/** single word instruction */ +int dsp563xx_once_execute_sw_ir_nq(struct jtag_tap *tap, uint32_t opcode) +{ + dsp563xx_once_ir_exec_nq(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0); + dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + + return ERROR_OK; +} + +/** double word instruction */ +int dsp563xx_once_execute_dw_ir_nq(struct jtag_tap *tap, uint32_t opcode, + uint32_t operand) +{ + dsp563xx_once_ir_exec_nq(tap, DSP563XX_ONCE_OPDBR, 0, 0, 0); + dsp563xx_write_dr_u32(tap, 0, opcode, 24, 0); + + dsp563xx_once_ir_exec_nq(tap, DSP563XX_ONCE_OPDBR, 0, 1, 0); + dsp563xx_write_dr_u32(tap, 0, operand, 24, 0); + + return ERROR_OK; +} diff --git a/src/target/dsp563xx_once.h b/src/target/dsp563xx_once.h new file mode 100644 index 0000000..871f622 --- /dev/null +++ b/src/target/dsp563xx_once.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2009 by Mathias Kuester * + * mk...@us... * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, write to the * + * Free Software Foundation, Inc., * + * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + ***************************************************************************/ +#ifndef DSP563XX_ONCE_H +#define DSP563XX_ONCE_H + +#include <jtag/jtag.h> + +#define DSP563XX_ONCE_OCR_EX (1<<5) +#define DSP563XX_ONCE_OCR_GO (1<<6) +#define DSP563XX_ONCE_OCR_RW (1<<7) + +#define DSP563XX_ONCE_OSCR_OS1 (1<<7) +#define DSP563XX_ONCE_OSCR_OS0 (1<<6) +#define DSP563XX_ONCE_OSCR_HIT (1<<5) +#define DSP563XX_ONCE_OSCR_TO (1<<4) +#define DSP563XX_ONCE_OSCR_MBO (1<<3) +#define DSP563XX_ONCE_OSCR_SWO (1<<2) +#define DSP563XX_ONCE_OSCR_IME (1<<1) +#define DSP563XX_ONCE_OSCR_TME (1<<0) + +#define DSP563XX_ONCE_OSCR_NORMAL_M (0) +#define DSP563XX_ONCE_OSCR_STOPWAIT_M (DSP563XX_ONCE_OSCR_OS0) +#define DSP563XX_ONCE_OSCR_BUSY_M (DSP563XX_ONCE_OSCR_OS1) +#define DSP563XX_ONCE_OSCR_DEBUG_M (DSP563XX_ONCE_OSCR_OS0|DSP563XX_ONCE_OSCR_OS1) + +#define DSP563XX_ONCE_OSCR 0x000 /* status/ctrl reg. */ +#define DSP563XX_ONCE_OMBC 0x001 /* memory breakp. reg. */ +#define DSP563XX_ONCE_OBCR 0x002 /* breakp. ctrl reg */ +#define DSP563XX_ONCE_OMLR0 0x005 /* memory limit reg */ +#define DSP563XX_ONCE_OMLR1 0x006 /* memory limit reg */ +#define DSP563XX_ONCE_OGDBR 0x009 /* gdb reg */ +#define DSP563XX_ONCE_OPDBR 0x00A /* pdb reg */ +#define DSP563XX_ONCE_OPILR 0x00B /* pil reg */ +#define DSP563XX_ONCE_PDBGOTO 0x00C /* pdb to go reg */ +#define DSP563XX_ONCE_OTC 0x00D /* trace cnt */ +#define DSP563XX_ONCE_TAGB 0x00E /* tags buffer */ +#define DSP563XX_ONCE_OPABFR 0x00F /* pab fetch reg */ +#define DSP563XX_ONCE_OPABDR 0x010 /* pab decode reg */ +#define DSP563XX_ONCE_OPABEX 0x011 /* pab exec reg */ +#define DSP563XX_ONCE_OPABEX 0x011 /* trace buffer/inc ptr */ +#define DSP563XX_ONCE_NOREG 0x01F /* no register selected */ + +/** single word instruction */ +int dsp563xx_once_ir_exec(struct jtag_tap *tap, uint8_t instr, uint8_t rw, + uint8_t go, uint8_t ex); +/** single word instruction */ +int dsp563xx_once_ir_exec_nq(struct jtag_tap *tap, uint8_t instr, uint8_t rw, + uint8_t go, uint8_t ex); +/** once read register */ +int dsp563xx_once_reg_read(struct jtag_tap *tap, uint8_t reg, uint32_t * data); +/** once write register */ +int dsp563xx_once_reg_write(struct jtag_tap *tap, uint8_t reg, uint32_t data); +/** single word instruction */ +int dsp563xx_once_execute_sw_ir(struct jtag_tap *tap, uint32_t opcode); +/** double word instruction */ +int dsp563xx_once_execute_dw_ir(struct jtag_tap *tap, uint32_t opcode, + uint32_t operand); +/** single word instruction */ +int dsp563xx_once_execute_sw_ir_nq(struct jtag_tap *tap, uint32_t opcode); +/** double word instruction */ +int dsp563xx_once_execute_dw_ir_nq(struct jtag_tap *tap, uint32_t opcode, + uint32_t operand); + +#endif /* DSP563XX_ONCE_H */ diff --git a/src/target/target.c b/src/target/target.c index 740db0f..ebddbba 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -64,6 +64,7 @@ extern struct target_type cortexa8_target; extern struct target_type arm11_target; extern struct target_type mips_m4k_target; extern struct target_type avr_target; +extern struct target_type dsp563xx_target; extern struct target_type testee_target; struct target_type *target_types[] = @@ -83,6 +84,7 @@ struct target_type *target_types[] = &arm11_target, &mips_m4k_target, &avr_target, + &dsp563xx_target, &testee_target, NULL, }; diff --git a/tcl/interface/arm-usb-ocd-tiny.cfg b/tcl/interface/arm-usb-ocd-tiny.cfg new file mode 100644 index 0000000..34793f3 --- /dev/null +++ b/tcl/interface/arm-usb-ocd-tiny.cfg @@ -0,0 +1,10 @@ +# +# Olimex ARM-USB-OCD-TINY +# +# http://www.olimex.com/dev/arm-usb-tiny.html +# + +interface ft2232 +ft2232_device_desc "Olimex OpenOCD JTAG TINY" +ft2232_layout "olimex-jtag" +ft2232_vid_pid 0x15ba 0x0004 diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg new file mode 100644 index 0000000..4506837 --- /dev/null +++ b/tcl/target/dsp56321.cfg @@ -0,0 +1,38 @@ +# Script for freescale DSP56321 +# + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME dsp56321 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a big endian + set _ENDIAN big +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0x1181501d +} + +#jtag speed +jtag_khz 4500 + +#has only srst +reset_config srst_only + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0x1 -expected-id $_CPUTAPID + +#target configuration +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME dsp563xx -endian $_ENDIAN -chain-position $_TARGETNAME + +#working area at base of ram +$_TARGETNAME configure -work-area-virt 0 ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 2 + src/target/Makefile.am | 6 +- src/target/dsp563xx.c | 990 ++++++++++++++++++++ src/target/dsp563xx.h | 88 ++ src/target/dsp563xx_once.c | 124 +++ src/target/dsp563xx_once.h | 81 ++ src/target/target.c | 2 + .../{olimex-jtag-tiny.cfg => arm-usb-ocd-tiny.cfg} | 5 +- tcl/target/dsp56321.cfg | 38 + 9 files changed, 1332 insertions(+), 4 deletions(-) create mode 100644 src/target/dsp563xx.c create mode 100644 src/target/dsp563xx.h create mode 100644 src/target/dsp563xx_once.c create mode 100644 src/target/dsp563xx_once.h copy tcl/interface/{olimex-jtag-tiny.cfg => arm-usb-ocd-tiny.cfg} (72%) create mode 100644 tcl/target/dsp56321.cfg hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-15 13:29:44
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 4639366947427da6face9cb6954b6603eb2e2fd3 (commit) via dca173053b1ebf3e99145a3cf6ea14937bf2fa3d (commit) from d6aff79f1a5263e920d23b6b63331437fa0a6af8 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 4639366947427da6face9cb6954b6603eb2e2fd3 Author: Ãyvind Harboe <oyv...@zy...> Date: Tue Dec 15 13:24:28 2009 +0100 zy1000: keep up with command.h cleanup Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/ecosboard.c b/src/ecosboard.c index 2e491c2..2a9950d 100644 --- a/src/ecosboard.c +++ b/src/ecosboard.c @@ -249,11 +249,21 @@ int zy1000_configuration_output_handler_log(struct command_context *context, } #ifdef CYGPKG_PROFILE_GPROF +//extern int64_t totaltime; -int eCosBoard_handle_eCosBoard_profile_command(struct command_context *cmd_ctx, char *cmd, char **args, int argc) +static int zylinjtag_Jim_Command_profile(Jim_Interp *interp, int argc, + Jim_Obj * const *argv) { - command_print(cmd_ctx, "Profiling started"); - start_profile(); + if ((argc == 2) && (strcmp(Jim_GetString(argv[1], NULL), "stats")==0)) + { +// profile_off(); + //LOG_USER("Stats %dms sleeping in select()", (int)totaltime); + } else + { + LOG_USER("Profiling started"); + start_profile(); + //totaltime = 0; + } return ERROR_OK; } @@ -1079,8 +1089,8 @@ int main(int argc, char *argv[]) return EXIT_FAILURE; #ifdef CYGPKG_PROFILE_GPROF - COMMAND_REGISTER(cmd_ctx, NULL, "ecosboard_profile", eCosBoard_handle_eCosBoard_profile_command, - COMMAND_ANY, NULL); + Jim_CreateCommand(httpstate.jim_interp, "zy1000_profile", zylinjtag_Jim_Command_profile, + NULL, NULL); #endif Jim_CreateCommand(httpstate.jim_interp, "uart", zylinjtag_Jim_Command_uart, NULL, NULL); commit dca173053b1ebf3e99145a3cf6ea14937bf2fa3d Author: Ãyvind Harboe <oyv...@zy...> Date: Tue Dec 15 13:23:07 2009 +0100 command: retire obsolete macro COMMAND_REGISTER() was only used transiently during code conversion. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/helper/command.h b/src/helper/command.h index aaba9b0..8a418d3 100644 --- a/src/helper/command.h +++ b/src/helper/command.h @@ -253,17 +253,6 @@ struct command_registration { struct command* register_command(struct command_context *cmd_ctx, struct command *parent, const struct command_registration *rec); -#define COMMAND_REGISTER(_cmd_ctx, _parent, _name, _handler, _mode, _help) \ - ({ \ - struct command_registration cr = { \ - .name = _name, \ - .handler = _handler, \ - .mode = _mode, \ - .help = _help, \ - }; \ - register_command(_cmd_ctx, _parent, &cr); \ - }) - /** * Register one or more commands in the specified context, as children * of @c parent (or top-level commends, if NULL). In a registration's ----------------------------------------------------------------------- Summary of changes: src/ecosboard.c | 20 +++++++++++++++----- src/helper/command.h | 11 ----------- 2 files changed, 15 insertions(+), 16 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-15 07:58:05
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via d6aff79f1a5263e920d23b6b63331437fa0a6af8 (commit) from bb77e5d32f67870e304011fc6e9d47257569f323 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit d6aff79f1a5263e920d23b6b63331437fa0a6af8 Author: Ãyvind Harboe <oyv...@zy...> Date: Tue Dec 15 07:55:20 2009 +0100 imx31: move srst delay into config script reset init/run now works again. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg index b613ba6..46b4f94 100644 --- a/tcl/target/imx31.cfg +++ b/tcl/target/imx31.cfg @@ -3,6 +3,8 @@ reset_config trst_and_srst srst_gates_jtag +jtag_nsrst_delay 5 + if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME } else { ----------------------------------------------------------------------- Summary of changes: tcl/target/imx31.cfg | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-15 04:56:59
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via bb77e5d32f67870e304011fc6e9d47257569f323 (commit) via 27b13e3377f546e9441291d3f1c3b6cc1438430b (commit) from c86a64dff7e9ebe8ab87e353f5b4156f830a0de7 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit bb77e5d32f67870e304011fc6e9d47257569f323 Author: David Brownell <dbr...@us...> Date: Mon Dec 14 19:56:36 2009 -0800 ARM11: improved reset support Teach ARM11 how to use: - the new "reset-assert" event - vector catch to implement "reset halt" - use SRST more like other cores do - ... including leaving post-SRST delays up to config scripts This gives OMAP2420 the ability to reset, and doesn't seem to cause new iMX31 problems. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm11.c b/src/target/arm11.c index 7c747c0..970738c 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -352,7 +352,9 @@ static int arm11_poll(struct target *target) return retval; target_call_event_callbacks(target, - old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED); + (old_state == TARGET_DEBUG_RUNNING) + ? TARGET_EVENT_DEBUG_HALTED + : TARGET_EVENT_HALTED); } } else @@ -749,67 +751,72 @@ static int arm11_step(struct target *target, int current, static int arm11_assert_reset(struct target *target) { - int retval; struct arm11_common *arm11 = target_to_arm11(target); - retval = arm11_check_init(arm11); - if (retval != ERROR_OK) - return retval; - - target->state = TARGET_UNKNOWN; + /* optionally catch reset vector */ + if (target->reset_halt && !(arm11_vcr & 1)) + arm11_sc7_set_vcr(arm11, arm11_vcr | 1); - /* we would very much like to reset into the halted, state, - * but resetting and halting is second best... */ - if (target->reset_halt) - { - CHECK_RETVAL(target_halt(target)); + /* Issue some kind of warm reset. */ + if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { + target_handle_event(target, TARGET_EVENT_RESET_ASSERT); + } else if (jtag_get_reset_config() & RESET_HAS_SRST) { + /* REVISIT handle "pulls" cases, if there's + * hardware that needs them to work. + */ + jtag_add_reset(0, 1); + } else { + LOG_ERROR("%s: how to reset?", target_name(target)); + return ERROR_FAIL; } + /* registers are now invalid */ + register_cache_invalidate(arm11->arm.core_cache); - /* srst is funny. We can not do *anything* else while it's asserted - * and it has unkonwn side effects. Make sure no other code runs - * meanwhile. - * - * Code below assumes srst: - * - * - Causes power-on-reset (but of what parts of the system?). Bug - * in arm11? - * - * - Messes us TAP state without asserting trst. - * - * - There is another bug in the arm11 core. When you generate an access to - * external logic (for example ddr controller via AHB bus) and that block - * is not configured (perhaps it is still held in reset), that transaction - * will never complete. This will hang arm11 core but it will also hang - * JTAG controller. Nothing, short of srst assertion will bring it out of - * this. - * - * Mysteries: - * - * - What should the PC be after an srst reset when starting in the halted - * state? - */ + target->state = TARGET_RESET; - jtag_add_reset(0, 1); - jtag_add_reset(0, 0); + return ERROR_OK; +} - /* How long do we have to wait? */ - jtag_add_sleep(5000); +/* + * - There is another bug in the arm11 core. (iMX31 specific again?) + * When you generate an access to external logic (for example DDR + * controller via AHB bus) and that block is not configured (perhaps + * it is still held in reset), that transaction will never complete. + * This will hang arm11 core but it will also hang JTAG controller. + * Nothing short of srst assertion will bring it out of this. + */ + +static int arm11_deassert_reset(struct target *target) +{ + struct arm11_common *arm11 = target_to_arm11(target); + int retval; + + /* be certain SRST is off */ + jtag_add_reset(0, 0); - /* un-mess up TAP state */ + /* WORKAROUND i.MX31 problems: SRST goofs the TAP, and resets + * at least DSCR. OMAP24xx doesn't show that problem, though + * SRST-only reset seems to be problematic for other reasons. + * (Secure boot sequences being one likelihood!) + */ jtag_add_tlr(); - retval = jtag_execute_queue(); - if (retval != ERROR_OK) - { - return retval; + retval = arm11_poll(target); + + if (target->reset_halt) { + if (target->state != TARGET_HALTED) { + LOG_WARNING("%s: ran after reset and before halt ...", + target_name(target)); + if ((retval = target_halt(target)) != ERROR_OK) + return retval; + } } - return ERROR_OK; -} + /* maybe restore vector catch config */ + if (target->reset_halt && !(arm11_vcr & 1)) + arm11_sc7_set_vcr(arm11, arm11_vcr); -static int arm11_deassert_reset(struct target *target) -{ return ERROR_OK; } commit 27b13e3377f546e9441291d3f1c3b6cc1438430b Author: David Brownell <dbr...@us...> Date: Mon Dec 14 19:53:10 2009 -0800 ARM: disassemble STM correctly There is no "STMMIDA" instruction. There is however "STMDAMI". Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 770c5e9..912e37c 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -1097,8 +1097,11 @@ static int evaluate_ldm_stm(uint32_t opcode, } } - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s", - address, opcode, mnemonic, COND(opcode), addressing_mode, + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 + "\t%s%s%s r%i%s, {%s}%s", + address, opcode, + mnemonic, addressing_mode, COND(opcode), Rn, (W) ? "!" : "", reg_list, (S) ? "^" : ""); return ERROR_OK; ----------------------------------------------------------------------- Summary of changes: src/target/arm11.c | 103 ++++++++++++++++++++++------------------- src/target/arm_disassembler.c | 7 ++- 2 files changed, 60 insertions(+), 50 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-15 02:08:22
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via c86a64dff7e9ebe8ab87e353f5b4156f830a0de7 (commit) via a1009509fb0fc187243435a0f38ef327e2aac147 (commit) from 36dec1b319bec7723f8dc3f84732911ebeed250a (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit c86a64dff7e9ebe8ab87e353f5b4156f830a0de7 Author: David Brownell <dbr...@us...> Date: Mon Dec 14 16:29:53 2009 -0800 lm3748: use new Stellaris config file Use the new file, and remove the old target/lm3s3748.cfg one. Signed-off-by: David Brownell <dbr...@us...> diff --git a/tcl/board/ek-lm3s3748.cfg b/tcl/board/ek-lm3s3748.cfg index 1d56c7f..950e511 100644 --- a/tcl/board/ek-lm3s3748.cfg +++ b/tcl/board/ek-lm3s3748.cfg @@ -4,10 +4,7 @@ # NOTE: to use the on-board FT2232 JTAG interface: # source [find interface/luminary.cfg] -source [find target/lm3s3748.cfg] - -# LM3S parts don't support RTCK -jtag_khz 500 +source [find target/stellaris.cfg] # Board has only srst reset_config srst_only diff --git a/tcl/target/lm3s3748.cfg b/tcl/target/lm3s3748.cfg deleted file mode 100644 index 274377a..0000000 --- a/tcl/target/lm3s3748.cfg +++ /dev/null @@ -1,29 +0,0 @@ -# TI/Luminary Stellaris lm3s3748 - -if { [info exists CHIPNAME] } { - set _CHIPNAME $CHIPNAME -} else { - set _CHIPNAME lm3s3748 -} - -if { [info exists CPUTAPID ] } { - set _CPUTAPID $CPUTAPID -} else { - set _CPUTAPID 0x3ba00477 -} - -# JTAG scan chain -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID - -# The "lm3s" variant works around an erratum when using Rev A of "DustDevil" -# parts (third generation, includes LM3S3748). It keeps the debug registers -# from being cleared, by using software reset not SRST; NOP on newer revs. -set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s - -# 8k working area at base of ram, not backed up -$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000 - -# flash configuration -- one bank of 128K -set _FLASHNAME $_CHIPNAME.flash -flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME commit a1009509fb0fc187243435a0f38ef327e2aac147 Author: Yegor Yefremov <yeg...@go...> Date: Mon Dec 14 16:29:31 2009 -0800 Common target file for Stellaris chips Common target.cfg file for LM3S CPU family [dbr...@us...: rename, generalize more] Signed-off-by: Yegor Yefremov <yeg...@go...> Signed-off-by: David Brownell <dbr...@us...> diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg new file mode 100644 index 0000000..6fafac9 --- /dev/null +++ b/tcl/target/stellaris.cfg @@ -0,0 +1,49 @@ +# TI/Luminary Stellaris LM3S chip family + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s +} + +# CPU TAP ID 0x1ba00477 for early Sandstorm parts +# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2 +# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil) +# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest) +# ... we'll ignore the JTAG version field, rather than list every +# chip revision that turns up. +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x0ba00477 +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \ + -expected-id $_CPUTAPID -ignore-version + +# The "lm3s" variant uses a software reset rather than SRST. +# This stops the debug registers from being cleared; it works +# around an erratum which should be fixed in later silicon. +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \ + -variant lm3s + +# 8K working area at base of ram, not backed up +# +# NOTE: you may need or want to reconfigure the work area; +# some parts have just 6K, and you may want to use other +# addresses (at end of mem not beginning) or back it up. +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000 + +# JTAG speed ... slow enough to work with a 12 MHz RC oscillator; +# LM3S parts don't support RTCK +# +# NOTE: this may be increased by a reset-init handler, after it +# configures and enables the PLL. Or you might need to decrease +# this, if you're using a slower clock. +jtag_khz 500 +$_TARGETNAME configure -event reset-start {jtag_khz 500} + +# flash configuration ... autodetects sizes, autoprobed +flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME + ----------------------------------------------------------------------- Summary of changes: tcl/board/ek-lm3s3748.cfg | 5 +--- tcl/target/lm3s3748.cfg | 29 -------------------------- tcl/target/stellaris.cfg | 49 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+), 33 deletions(-) delete mode 100644 tcl/target/lm3s3748.cfg create mode 100644 tcl/target/stellaris.cfg hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-15 00:59:42
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 36dec1b319bec7723f8dc3f84732911ebeed250a (commit) via af79925eb1937044977f969a53ea3b7635f576b1 (commit) from 6f929dbd93e1b2c0373f389060bf64e60e8194ab (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 36dec1b319bec7723f8dc3f84732911ebeed250a Author: Eric Wetzel <the...@gm...> Date: Mon Dec 14 15:59:27 2009 -0500 stellaris: device IDs I added the remaining devices and device IDs to stellaris.c, and removed several devices that don't exist on the Stellaris web page. Additionally, I found a few devices with duplicate IDs ... the DID1 Version Number for LM3Sxxx parts have DID1 Version = 0x0, and for LM3Sxxxx have DID1 Version = 0x1. So I extended the comparison to use the VER and FAM fields from DID1 also. ID=0x33: LM3S812 (DID1v0) and LM3S2616 (DID1v1) ID=0x39: LM3S808 (DID1v0) and LM3S2276 (DID1v1) These are the parts I removed from the file for lack of documentation (no data sheet to confirm part ID): LM3S318, LM3S1101, LM3S1108, LM3S1615, LM3S1616, LM3S2016, LM3S2101, LM3S2108, LM3S3759, LM3S3768, LM3S5757, LM3S5767, LM3S5768, LM3S5769, LM3S6815, LM3S6816, LM3S6915, LM3S6916, LM3S6111, LM3S6118. Also, sort devices according to part number. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 8584843..103202d 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -46,155 +46,173 @@ static struct { char *partname; } StellarisParts[] = { - {0x01,"LM3S101"}, - {0x02,"LM3S102"}, - {0x03,"LM3S1625"}, - {0x04,"LM3S1626"}, - {0x05,"LM3S1627"}, - {0x06,"LM3S1607"}, - {0x10,"LM3S1776"}, - {0x19,"LM3S300"}, - {0x11,"LM3S301"}, - {0x12,"LM3S310"}, - {0x1A,"LM3S308"}, - {0x13,"LM3S315"}, - {0x14,"LM3S316"}, - {0x17,"LM3S317"}, - {0x18,"LM3S318"}, - {0x15,"LM3S328"}, - {0x2A,"LM3S600"}, - {0x21,"LM3S601"}, - {0x2B,"LM3S608"}, - {0x22,"LM3S610"}, - {0x23,"LM3S611"}, - {0x24,"LM3S612"}, - {0x25,"LM3S613"}, - {0x26,"LM3S615"}, - {0x28,"LM3S617"}, - {0x29,"LM3S618"}, - {0x27,"LM3S628"}, - {0x38,"LM3S800"}, - {0x31,"LM3S801"}, - {0x39,"LM3S808"}, - {0x32,"LM3S811"}, - {0x33,"LM3S812"}, - /*{0x33,"LM3S2616"},*/ - {0x34,"LM3S815"}, - {0x36,"LM3S817"}, - {0x37,"LM3S818"}, - {0x35,"LM3S828"}, - {0x39,"LM3S2276"}, - {0x3A,"LM3S2776"}, - {0x43,"LM3S3651"}, - {0x44,"LM3S3739"}, - {0x45,"LM3S3749"}, - {0x46,"LM3S3759"}, - {0x48,"LM3S3768"}, - {0x49,"LM3S3748"}, - {0x4B,"LM3S5R36"}, - {0x50,"LM3S2678"}, - {0x51,"LM3S2110"}, - {0x52,"LM3S2739"}, - {0x53,"LM3S2651"}, - {0x54,"LM3S2939"}, - {0x55,"LM3S2965"}, - {0x56,"LM3S2432"}, - {0x57,"LM3S2620"}, - {0x58,"LM3S2950"}, - {0x59,"LM3S2412"}, - {0x5A,"LM3S2533"}, - {0x61,"LM3S8630"}, - {0x62,"LM3S8970"}, - {0x63,"LM3S8730"}, - {0x64,"LM3S8530"}, - {0x65,"LM3S8930"}, - {0x71,"LM3S6610"}, - {0x72,"LM3S6950"}, - {0x73,"LM3S6965"}, - {0x74,"LM3S6110"}, - {0x75,"LM3S6432"}, - {0x76,"LM3S6537"}, - {0x77,"LM3S6753"}, - {0x78,"LM3S6952"}, - {0x80,"LM3S2671"}, - {0x81,"LM3S5632"}, - {0x82,"LM3S6422"}, - {0x83,"LM3S6633"}, - {0x84,"LM3S2139"}, - {0x85,"LM3S2637"}, - {0x86,"LM3S8738"}, - {0x88,"LM3S8938"}, - {0x89,"LM3S6938"}, - {0x8A,"LM3S5652"}, - {0x8B,"LM3S6637"}, - {0x8C,"LM3S8933"}, - {0x8D,"LM3S8733"}, - {0x8E,"LM3S8538"}, - {0x8F,"LM3S2948"}, - {0x91,"LM3S5662"}, - {0x96,"LM3S5732"}, - {0x97,"LM3S5737"}, - {0x99,"LM3S5747"}, - {0x9A,"LM3S5752"}, - {0x9B,"LM3S5757"}, - {0x9C,"LM3S5762"}, - {0x9D,"LM3S5767"}, - {0xA0,"LM3S5739"}, - {0xA1,"LM3S6100"}, - {0xA2,"LM3S2410"}, - {0xA3,"LM3S6730"}, - {0xA4,"LM3S2730"}, - {0xA5,"LM3S6420"}, - {0xA6,"LM3S8962"}, - {0xA7,"LM3S5749"}, - {0xA8,"LM3S5769"}, - {0xA9,"LM3S5768"}, - {0xB3,"LM3S1635"}, - {0xB4,"LM3S1850"}, - {0xB5,"LM3S1960"}, - {0xB7,"LM3S1937"}, - {0xB8,"LM3S1968"}, - {0xB9,"LM3S1751"}, - {0xBA,"LM3S1439"}, - {0xBB,"LM3S1512"}, - {0xBC,"LM3S1435"}, - {0xBD,"LM3S1637"}, - {0xBE,"LM3S1958"}, - {0xBF,"LM3S1110"}, - {0xC0,"LM3S1620"}, - {0xC1,"LM3S1150"}, - {0xC2,"LM3S1165"}, - {0xC3,"LM3S1133"}, - {0xC4,"LM3S1162"}, - {0xC5,"LM3S1138"}, - {0xC6,"LM3S1332"}, - {0xC7,"LM3S1538"}, - {0xD0,"LM3S6815"}, - {0xD1,"LM3S6816"}, - {0xD2,"LM3S6915"}, - {0xD3,"LM3S6916"}, - {0xD4,"LM3S2016"}, - {0xD5,"LM3S1615"}, - {0xD6,"LM3S1616"}, - {0xD7,"LM3S8971"}, - {0xD8,"LM3S1108"}, - {0xD9,"LM3S1101"}, - {0xDA,"LM3S1608"}, - {0xDB,"LM3S1601"}, - {0xDC,"LM3S1918"}, - {0xDD,"LM3S1911"}, - {0xDE,"LM3S2108"}, - {0xDF,"LM3S2101"}, - {0xE0,"LM3S2608"}, - {0xE1,"LM3S2601"}, - {0xE2,"LM3S2918"}, - {0xE3,"LM3S2911"}, - {0xE4,"LM3S6118"}, - {0xE5,"LM3S6111"}, - {0xE6,"LM3S6618"}, - {0xE7,"LM3S6611"}, - {0xE8,"LM3S6918"}, - {0xE9,"LM3S6911"}, + {0x0001,"LM3S101"}, + {0x0002,"LM3S102"}, + {0x0019,"LM3S300"}, + {0x0011,"LM3S301"}, + {0x001A,"LM3S308"}, + {0x0012,"LM3S310"}, + {0x0013,"LM3S315"}, + {0x0014,"LM3S316"}, + {0x0017,"LM3S317"}, + {0x0015,"LM3S328"}, + {0x002A,"LM3S600"}, + {0x0021,"LM3S601"}, + {0x002B,"LM3S608"}, + {0x0022,"LM3S610"}, + {0x0023,"LM3S611"}, + {0x0024,"LM3S612"}, + {0x0025,"LM3S613"}, + {0x0026,"LM3S615"}, + {0x0028,"LM3S617"}, + {0x0029,"LM3S618"}, + {0x0027,"LM3S628"}, + {0x0038,"LM3S800"}, + {0x0031,"LM3S801"}, + {0x0039,"LM3S808"}, + {0x0032,"LM3S811"}, + {0x0033,"LM3S812"}, + {0x0034,"LM3S815"}, + {0x0036,"LM3S817"}, + {0x0037,"LM3S818"}, + {0x0035,"LM3S828"}, + {0x10BF,"LM3S1110"}, + {0x10C3,"LM3S1133"}, + {0x10C5,"LM3S1138"}, + {0x10C1,"LM3S1150"}, + {0x10C4,"LM3S1162"}, + {0x10C2,"LM3S1165"}, + {0x10C6,"LM3S1332"}, + {0x10BC,"LM3S1435"}, + {0x10BA,"LM3S1439"}, + {0x10BB,"LM3S1512"}, + {0x10C7,"LM3S1538"}, + {0x10DB,"LM3S1601"}, + {0x1006,"LM3S1607"}, + {0x10DA,"LM3S1608"}, + {0x10C0,"LM3S1620"}, + {0x1003,"LM3S1625"}, + {0x1004,"LM3S1626"}, + {0x1005,"LM3S1627"}, + {0x10B3,"LM3S1635"}, + {0x10BD,"LM3S1637"}, + {0x10B9,"LM3S1751"}, + {0x1010,"LM3S1776"}, + {0x1016,"LM3S1811"}, + {0x103D,"LM3S1816"}, + {0x10B4,"LM3S1850"}, + {0x10DD,"LM3S1911"}, + {0x10DC,"LM3S1918"}, + {0x10B7,"LM3S1937"}, + {0x10BE,"LM3S1958"}, + {0x10B5,"LM3S1960"}, + {0x10B8,"LM3S1968"}, + {0x100F,"LM3S1J11"}, + {0x103C,"LM3S1J16"}, + {0x100E,"LM3S1N11"}, + {0x103B,"LM3S1N16"}, + {0x1030,"LM3S1W16"}, + {0x102F,"LM3S1Z16"}, + {0x1051,"LM3S2110"}, + {0x1084,"LM3S2139"}, + {0x1039,"LM3S2276"}, + {0x10A2,"LM3S2410"}, + {0x1059,"LM3S2412"}, + {0x1056,"LM3S2432"}, + {0x105A,"LM3S2533"}, + {0x10E1,"LM3S2601"}, + {0x10E0,"LM3S2608"}, + {0x1033,"LM3S2616"}, + {0x1057,"LM3S2620"}, + {0x1085,"LM3S2637"}, + {0x1053,"LM3S2651"}, + {0x1080,"LM3S2671"}, + {0x1050,"LM3S2678"}, + {0x10A4,"LM3S2730"}, + {0x1052,"LM3S2739"}, + {0x103A,"LM3S2776"}, + {0x106D,"LM3S2793"}, + {0x10E3,"LM3S2911"}, + {0x10E2,"LM3S2918"}, + {0x1054,"LM3S2939"}, + {0x108F,"LM3S2948"}, + {0x1058,"LM3S2950"}, + {0x1055,"LM3S2965"}, + {0x106C,"LM3S2B93"}, + {0x1043,"LM3S3651"}, + {0x1044,"LM3S3739"}, + {0x1049,"LM3S3748"}, + {0x1045,"LM3S3749"}, + {0x1042,"LM3S3826"}, + {0x1041,"LM3S3J26"}, + {0x1040,"LM3S3N26"}, + {0x103F,"LM3S3W26"}, + {0x103E,"LM3S3Z26"}, + {0x1081,"LM3S5632"}, + {0x100C,"LM3S5651"}, + {0x108A,"LM3S5652"}, + {0x104D,"LM3S5656"}, + {0x1091,"LM3S5662"}, + {0x1096,"LM3S5732"}, + {0x1097,"LM3S5737"}, + {0x10A0,"LM3S5739"}, + {0x1099,"LM3S5747"}, + {0x10A7,"LM3S5749"}, + {0x109A,"LM3S5752"}, + {0x109C,"LM3S5762"}, + {0x1069,"LM3S5791"}, + {0x100B,"LM3S5951"}, + {0x104E,"LM3S5956"}, + {0x1068,"LM3S5B91"}, + {0x1009,"LM3S5K31"}, + {0x104A,"LM3S5K36"}, + {0x100A,"LM3S5P31"}, + {0x1048,"LM3S5P36"}, + {0x100D,"LM3S5P51"}, + {0x104C,"LM3S5P56"}, + {0x1007,"LM3S5R31"}, + {0x104B,"LM3S5R36"}, + {0x1047,"LM3S5T36"}, + {0x1046,"LM3S5Y36"}, + {0x10A1,"LM3S6100"}, + {0x1074,"LM3S6110"}, + {0x10A5,"LM3S6420"}, + {0x1082,"LM3S6422"}, + {0x1075,"LM3S6432"}, + {0x1076,"LM3S6537"}, + {0x1071,"LM3S6610"}, + {0x10E7,"LM3S6611"}, + {0x10E6,"LM3S6618"}, + {0x1083,"LM3S6633"}, + {0x108B,"LM3S6637"}, + {0x10A3,"LM3S6730"}, + {0x1077,"LM3S6753"}, + {0x10E9,"LM3S6911"}, + {0x10E8,"LM3S6918"}, + {0x1089,"LM3S6938"}, + {0x1072,"LM3S6950"}, + {0x1078,"LM3S6952"}, + {0x1073,"LM3S6965"}, + {0x1064,"LM3S8530"}, + {0x108E,"LM3S8538"}, + {0x1061,"LM3S8630"}, + {0x1063,"LM3S8730"}, + {0x108D,"LM3S8733"}, + {0x1086,"LM3S8738"}, + {0x1065,"LM3S8930"}, + {0x108C,"LM3S8933"}, + {0x1088,"LM3S8938"}, + {0x10A6,"LM3S8962"}, + {0x1062,"LM3S8970"}, + {0x10D7,"LM3S8971"}, + {0x1067,"LM3S9790"}, + {0x106B,"LM3S9792"}, + {0x1020,"LM3S9997"}, + {0x1066,"LM3S9B90"}, + {0x106A,"LM3S9B92"}, + {0x106E,"LM3S9B95"}, + {0x106F,"LM3S9B96"}, + {0x1018,"LM3S9L97"}, {0,"Unknown part"} }; @@ -574,7 +592,7 @@ static int stellaris_read_part_info(struct flash_bank *bank) for (i = 0; StellarisParts[i].partno; i++) { - if (StellarisParts[i].partno == ((did1 >> 16) & 0xFF)) + if (StellarisParts[i].partno == ((did1 >> 16) & 0xFFFF)) break; } commit af79925eb1937044977f969a53ea3b7635f576b1 Author: David Brownell <dbr...@us...> Date: Mon Dec 14 15:55:51 2009 -0800 jtag: add '-ignore-version' option Add a "-ignore-version" to "jtag newtap" which makes the IDCODE comparison logic optionally ignore version differences. Update the "scan_chain" command to illustrate this by showing the "*" character instead of the (ignored) version nibble. Signed-off-by: David Brownell <dbr...@us...> diff --git a/doc/openocd.texi b/doc/openocd.texi index a83c966..01dfa76 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -2763,6 +2763,12 @@ are provided in vendors' chip documentation, usually a technical reference manual. Sometimes you may need to probe the JTAG hardware to find these values. @xref{Autoprobing}. +@item @code{-ignore-version} +@*Specify this to ignore the JTAG version field in the @code{-expected-id} +option. When vendors put out multiple versions of a chip, or use the same +JTAG-level ID for several largely-compatible chips, it may be more practical +to ignore the version field than to update config files to handle all of +the various chip IDs. @item @code{-ircapture} @var{NUMBER} @*The bit pattern loaded by the TAP into the JTAG shift register on entry to the @sc{ircapture} state, such as 0x01. diff --git a/src/jtag/core.c b/src/jtag/core.c index 77cf48a..e311bfb 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -958,16 +958,25 @@ static bool jtag_examine_chain_end(uint8_t *idcodes, unsigned count, unsigned ma static bool jtag_examine_chain_match_tap(const struct jtag_tap *tap) { + uint32_t idcode = tap->idcode; + /* ignore expected BYPASS codes; warn otherwise */ - if (0 == tap->expected_ids_cnt && !tap->idcode) + if (0 == tap->expected_ids_cnt && !idcode) return true; + /* optionally ignore the JTAG version field */ + uint32_t mask = tap->ignore_version ? ~(0xff << 24) : ~0; + + idcode &= mask; + /* Loop over the expected identification codes and test for a match */ unsigned ii, limit = tap->expected_ids_cnt; for (ii = 0; ii < limit; ii++) { - if (tap->idcode == tap->expected_ids[ii]) + uint32_t expected = tap->expected_ids[ii] & mask; + + if (idcode == expected) return true; /* treat "-expected-id 0" as a "don't-warn" wildcard */ diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h index fa2fcdc..f79ef93 100644 --- a/src/jtag/jtag.h +++ b/src/jtag/jtag.h @@ -156,6 +156,9 @@ struct jtag_tap { /// Number of expected identification codes uint8_t expected_ids_cnt; + /// Flag saying whether to ignore version field in expected_ids[] + bool ignore_version; + /// current instruction uint8_t* cur_instr; /// Bypass register selected diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c index 9704c30..f4815c8 100644 --- a/src/jtag/tcl.c +++ b/src/jtag/tcl.c @@ -454,6 +454,7 @@ static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi, #define NTAP_OPT_ENABLED 3 #define NTAP_OPT_DISABLED 4 #define NTAP_OPT_EXPECTED_ID 5 +#define NTAP_OPT_VERSION 6 static int jim_newtap_ir_param(Jim_Nvp *n, Jim_GetOptInfo *goi, struct jtag_tap *pTap) @@ -520,6 +521,7 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi) { .name = "-enable" , .value = NTAP_OPT_ENABLED }, { .name = "-disable" , .value = NTAP_OPT_DISABLED }, { .name = "-expected-id" , .value = NTAP_OPT_EXPECTED_ID }, + { .name = "-ignore-version" , .value = NTAP_OPT_VERSION }, { .name = NULL , .value = -1 }, }; @@ -595,6 +597,9 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi) return e; } break; + case NTAP_OPT_VERSION: + pTap->ignore_version = true; + break; } /* switch (n->value) */ } /* while (goi->argc) */ @@ -1013,6 +1018,7 @@ COMMAND_HANDLER(handle_interface_command) COMMAND_HANDLER(handle_scan_chain_command) { struct jtag_tap *tap; + char expected_id[12]; tap = jtag_all_taps(); command_print(CMD_CTX, " TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr "); @@ -1020,25 +1026,39 @@ COMMAND_HANDLER(handle_scan_chain_command) while (tap) { uint32_t expected, expected_mask, cur_instr, ii; + + snprintf(expected_id, sizeof expected_id, "0x%08x", + (unsigned)((tap->expected_ids_cnt > 0) + ? tap->expected_ids[0] + : 0)); + if (tap->ignore_version) + expected_id[2] = '*'; + expected = buf_get_u32(tap->expected, 0, tap->ir_length); expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length); cur_instr = buf_get_u32(tap->cur_instr, 0, tap->ir_length); command_print(CMD_CTX, - "%2d | %-18s | %c | 0x%08x | 0x%08x | 0x%02x | 0x%02x | 0x%02x | 0x%02x", + "%2d | %-18s | %c | 0x%08x | %s | 0x%02x | 0x%02x | 0x%02x | 0x%02x", tap->abs_chain_position, tap->dotted_name, tap->enabled ? 'Y' : 'n', (unsigned int)(tap->idcode), - (unsigned int)(tap->expected_ids_cnt > 0 ? tap->expected_ids[0] : 0), + expected_id, (unsigned int)(tap->ir_length), (unsigned int)(expected), (unsigned int)(expected_mask), (unsigned int)(cur_instr)); for (ii = 1; ii < tap->expected_ids_cnt; ii++) { - command_print(CMD_CTX, " | | | | 0x%08x | | | | ", - (unsigned int)(tap->expected_ids[ii])); + snprintf(expected_id, sizeof expected_id, "0x%08x", + (unsigned) tap->expected_ids[1]); + if (tap->ignore_version) + expected_id[2] = '*'; + + command_print(CMD_CTX, + " | | | | %s | | | | ", + expected_id); } tap = tap->next_tap; ----------------------------------------------------------------------- Summary of changes: doc/openocd.texi | 6 + src/flash/nor/stellaris.c | 318 ++++++++++++++++++++++++--------------------- src/jtag/core.c | 13 ++- src/jtag/jtag.h | 3 + src/jtag/tcl.c | 28 ++++- 5 files changed, 212 insertions(+), 156 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-13 21:54:42
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 6f929dbd93e1b2c0373f389060bf64e60e8194ab (commit) via 38e376d232ecb3d6a436a20c09019d1a13b0d42b (commit) from 0a9d7cab6d76d1203d46e51140ad97d0b5cace56 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 6f929dbd93e1b2c0373f389060bf64e60e8194ab Author: David Brownell <dbr...@us...> Date: Sun Dec 13 12:52:23 2009 -0800 target files shouldn't #include <target/...h> Make these ".h" files adopt the same policy the ".c" files already follow: don't use <subsystem/...h> syntax for private interfaces. If we ever get reviewed/supported "public" interfaces they should come exclusively from some include/... directory; that'll be the time to switch to <...> syntax for any subsystem's own interfaces. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm.h b/src/target/arm.h index 36763b4..988266e 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -26,8 +26,8 @@ #ifndef ARM_H #define ARM_H -#include <target/target.h> #include <helper/command.h> +#include "target.h" /** diff --git a/src/target/arm11.h b/src/target/arm11.h index bce5bd9..dd2f3a2 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -23,8 +23,8 @@ #ifndef ARM11_H #define ARM11_H -#include <target/arm.h> -#include <target/arm_dpm.h> +#include "arm.h" +#include "arm_dpm.h" #define ARM11_TAP_DEFAULT TAP_INVALID diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h index 7f87e3a..45052b9 100644 --- a/src/target/arm11_dbgtap.h +++ b/src/target/arm11_dbgtap.h @@ -1,7 +1,7 @@ #ifndef ARM11_DBGTAP_H #define ARM11_DBGTAP_H -#include <target/arm11.h> +#include "arm11.h" /* ARM11 internals */ diff --git a/src/target/arm720t.h b/src/target/arm720t.h index b13cff8..f0ab444 100644 --- a/src/target/arm720t.h +++ b/src/target/arm720t.h @@ -20,8 +20,8 @@ #ifndef ARM720T_H #define ARM720T_H -#include <target/arm7tdmi.h> -#include <target/armv4_5_mmu.h> +#include "arm7tdmi.h" +#include "armv4_5_mmu.h" #define ARM720T_COMMON_MAGIC 0xa720a720 diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index bce17ef..021238e 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -29,8 +29,8 @@ #ifndef ARM7_9_COMMON_H #define ARM7_9_COMMON_H -#include <target/arm.h> -#include <target/arm_jtag.h> +#include "arm.h" +#include "arm_jtag.h" #define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */ diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h index ce771e2..b6bbe59 100644 --- a/src/target/arm7tdmi.h +++ b/src/target/arm7tdmi.h @@ -23,7 +23,7 @@ #ifndef ARM7TDMI_H #define ARM7TDMI_H -#include <target/embeddedice.h> +#include "embeddedice.h" int arm7tdmi_init_arch_info(struct target *target, struct arm7_9_common *arm7_9, struct jtag_tap *tap); diff --git a/src/target/arm920t.h b/src/target/arm920t.h index 0eb14fc..a75f01a 100644 --- a/src/target/arm920t.h +++ b/src/target/arm920t.h @@ -20,8 +20,8 @@ #ifndef ARM920T_H #define ARM920T_H -#include <target/arm9tdmi.h> -#include <target/armv4_5_mmu.h> +#include "arm9tdmi.h" +#include "armv4_5_mmu.h" #define ARM920T_COMMON_MAGIC 0xa920a920 diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h index 604ab08..274733b 100644 --- a/src/target/arm926ejs.h +++ b/src/target/arm926ejs.h @@ -20,8 +20,8 @@ #ifndef ARM926EJS_H #define ARM926EJS_H -#include <target/arm9tdmi.h> -#include <target/armv4_5_mmu.h> +#include "arm9tdmi.h" +#include "armv4_5_mmu.h" #define ARM926EJS_COMMON_MAGIC 0xa926a926 diff --git a/src/target/arm966e.h b/src/target/arm966e.h index 6c16970..24dcec3 100644 --- a/src/target/arm966e.h +++ b/src/target/arm966e.h @@ -23,7 +23,7 @@ #ifndef ARM966E_H #define ARM966E_H -#include <target/arm9tdmi.h> +#include "arm9tdmi.h" #define ARM966E_COMMON_MAGIC 0x20f920f9 diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h index ea43690..aff9fc5 100644 --- a/src/target/arm9tdmi.h +++ b/src/target/arm9tdmi.h @@ -23,7 +23,7 @@ #ifndef ARM9TDMI_H #define ARM9TDMI_H -#include <target/embeddedice.h> +#include "embeddedice.h" int arm9tdmi_init_target(struct command_context *cmd_ctx, struct target *target); diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h index c268f96..a78193c 100644 --- a/src/target/arm_adi_v5.h +++ b/src/target/arm_adi_v5.h @@ -23,7 +23,7 @@ #ifndef ARM_ADI_V5_H #define ARM_ADI_V5_H -#include <target/arm_jtag.h> +#include "arm_jtag.h" #define DAP_IR_DPACC 0xA #define DAP_IR_APACC 0xB diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h index 428a373..6b9ed34 100644 --- a/src/target/armv4_5_mmu.h +++ b/src/target/armv4_5_mmu.h @@ -20,7 +20,7 @@ #ifndef ARMV4_5_MMU_H #define ARMV4_5_MMU_H -#include <target/armv4_5_cache.h> +#include "armv4_5_cache.h" struct target; diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 663e5d9..581813a 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -19,11 +19,11 @@ #ifndef ARMV7A_H #define ARMV7A_H -#include <target/arm_adi_v5.h> -#include <target/arm.h> -#include <target/armv4_5_mmu.h> -#include <target/armv4_5_cache.h> -#include <target/arm_dpm.h> +#include "arm_adi_v5.h" +#include "arm.h" +#include "armv4_5_mmu.h" +#include "armv4_5_cache.h" +#include "arm_dpm.h" enum { diff --git a/src/target/armv7m.h b/src/target/armv7m.h index 07090b4..ac559b9 100644 --- a/src/target/armv7m.h +++ b/src/target/armv7m.h @@ -26,8 +26,8 @@ #ifndef ARMV7M_COMMON_H #define ARMV7M_COMMON_H -#include <target/arm_adi_v5.h> -#include <target/arm.h> +#include "arm_adi_v5.h" +#include "arm.h" /* define for enabling armv7 gdb workarounds */ #if 1 diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h index 82a34a7..cc2e009 100644 --- a/src/target/cortex_a8.h +++ b/src/target/cortex_a8.h @@ -29,7 +29,7 @@ #ifndef CORTEX_A8_H #define CORTEX_A8_H -#include <target/armv7a.h> +#include "armv7a.h" #define CORTEX_A8_COMMON_MAGIC 0x411fc082 diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h index c31c3f5..7ce8901 100644 --- a/src/target/cortex_m3.h +++ b/src/target/cortex_m3.h @@ -26,7 +26,7 @@ #ifndef CORTEX_M3_H #define CORTEX_M3_H -#include <target/armv7m.h> +#include "armv7m.h" #define CORTEX_M3_COMMON_MAGIC 0x1A451A45 diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index 693391c..cd48ce6 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -26,7 +26,7 @@ #ifndef EMBEDDED_ICE_H #define EMBEDDED_ICE_H -#include <target/arm7_9_common.h> +#include "arm7_9_common.h" enum { diff --git a/src/target/etm.h b/src/target/etm.h index 5aea657..5b4d5e1 100644 --- a/src/target/etm.h +++ b/src/target/etm.h @@ -23,8 +23,8 @@ #ifndef ETM_H #define ETM_H -#include <target/trace.h> -#include <target/arm_jtag.h> +#include "trace.h" +#include "arm_jtag.h" struct image; diff --git a/src/target/etm_dummy.h b/src/target/etm_dummy.h index 95980f8..2673e4f 100644 --- a/src/target/etm_dummy.h +++ b/src/target/etm_dummy.h @@ -20,7 +20,7 @@ #ifndef ETM_DUMMY_H #define ETM_DUMMY_H -#include <target/etm.h> +#include "etm.h" extern struct etm_capture_driver etm_dummy_capture_driver; diff --git a/src/target/mips32.h b/src/target/mips32.h index 98186af..7d1928e 100644 --- a/src/target/mips32.h +++ b/src/target/mips32.h @@ -23,8 +23,8 @@ #ifndef MIPS32_H #define MIPS32_H -#include <target/target.h> -#include <target/mips32_pracc.h> +#include "target.h" +#include "mips32_pracc.h" #define MIPS32_COMMON_MAGIC 0xB320B320 diff --git a/src/target/mips32_dmaacc.h b/src/target/mips32_dmaacc.h index e614c12..c1aa07d 100644 --- a/src/target/mips32_dmaacc.h +++ b/src/target/mips32_dmaacc.h @@ -25,7 +25,7 @@ #ifndef MIPS32_DMAACC_H #define MIPS32_DMAACC_H -#include <target/mips_ejtag.h> +#include "mips_ejtag.h" #define EJTAG_CTRL_DMA_BYTE 0x00000000 #define EJTAG_CTRL_DMA_HALFWORD 0x00000080 diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h index eceea5d..5d1cf3d 100644 --- a/src/target/mips32_pracc.h +++ b/src/target/mips32_pracc.h @@ -22,7 +22,7 @@ #ifndef MIPS32_PRACC_H #define MIPS32_PRACC_H -#include <target/mips_ejtag.h> +#include "mips_ejtag.h" #define MIPS32_PRACC_TEXT 0xFF200200 //#define MIPS32_PRACC_STACK 0xFF2FFFFC diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c index ae3a5df..b9615bc 100644 --- a/src/target/oocd_trace.c +++ b/src/target/oocd_trace.c @@ -22,6 +22,7 @@ #endif #include "arm.h" +#include "etm.h" #include "oocd_trace.h" /* diff --git a/src/target/oocd_trace.h b/src/target/oocd_trace.h index 7c334f2..6646933 100644 --- a/src/target/oocd_trace.h +++ b/src/target/oocd_trace.h @@ -20,8 +20,6 @@ #ifndef OOCD_TRACE_H #define OOCD_TRACE_H -#include <target/etm.h> - #include <termios.h> /* registers */ diff --git a/src/target/xscale.h b/src/target/xscale.h index 97038d8..f20074f 100644 --- a/src/target/xscale.h +++ b/src/target/xscale.h @@ -23,9 +23,9 @@ #ifndef XSCALE_H #define XSCALE_H -#include <target/arm.h> -#include <target/armv4_5_mmu.h> -#include <target/trace.h> +#include "arm.h" +#include "armv4_5_mmu.h" +#include "trace.h" #define XSCALE_COMMON_MAGIC 0x58534341 commit 38e376d232ecb3d6a436a20c09019d1a13b0d42b Author: David Brownell <dbr...@us...> Date: Sun Dec 13 12:52:23 2009 -0800 target: further shrink Jim-awareness Don't include <helper/jim.h> from target.h ... not everything which touches targets needs to be able to talk to Jim. Plus, most files include this header by another path. Also, switch the affected files to use the classic sequence for #included files: all <framework/headers.h> first, then the "local_headers.h". This helps prevent growth of problematic layering, by minimizing entanglement. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/target.c b/src/target/target.c index 70130d9..740db0f 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -33,15 +33,16 @@ #include "config.h" #endif +#include <helper/time_support.h> +#include <jtag/jtag.h> + #include "target.h" #include "target_type.h" #include "target_request.h" #include "breakpoints.h" -#include <helper/time_support.h> #include "register.h" #include "trace.h" #include "image.h" -#include <jtag/jtag.h> static int target_array2mem(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv); diff --git a/src/target/target.h b/src/target/target.h index fededb9..4151c22 100644 --- a/src/target/target.h +++ b/src/target/target.h @@ -27,7 +27,6 @@ #define TARGET_H #include <helper/types.h> -#include <helper/jim.h> struct reg; struct trace; @@ -214,7 +213,7 @@ enum target_event struct target_event_action { enum target_event event; - Jim_Interp *interp; + struct Jim_Interp *interp; struct Jim_Obj *body; int has_percent; struct target_event_action *next; diff --git a/src/target/target_request.c b/src/target/target_request.c index fc0ba1a..d22b8a2 100644 --- a/src/target/target_request.c +++ b/src/target/target_request.c @@ -27,12 +27,13 @@ #include "config.h" #endif +#include <helper/log.h> +#include <helper/binarybuffer.h> + #include "target.h" #include "target_request.h" #include "target_type.h" -#include <helper/binarybuffer.h> #include "trace.h" -#include <helper/log.h> static int charmsg_mode = 0; diff --git a/src/target/testee.c b/src/target/testee.c index 991c64e..280111a 100644 --- a/src/target/testee.c +++ b/src/target/testee.c @@ -20,9 +20,11 @@ #ifdef HAVE_CONFIG_H #include "config.h" #endif + +#include <helper/log.h> + #include "target.h" #include "target_type.h" -#include <helper/log.h> #include "hello.h" static const struct command_registration testee_command_handlers[] = { ----------------------------------------------------------------------- Summary of changes: src/target/arm.h | 2 +- src/target/arm11.h | 4 ++-- src/target/arm11_dbgtap.h | 2 +- src/target/arm720t.h | 4 ++-- src/target/arm7_9_common.h | 4 ++-- src/target/arm7tdmi.h | 2 +- src/target/arm920t.h | 4 ++-- src/target/arm926ejs.h | 4 ++-- src/target/arm966e.h | 2 +- src/target/arm9tdmi.h | 2 +- src/target/arm_adi_v5.h | 2 +- src/target/armv4_5_mmu.h | 2 +- src/target/armv7a.h | 10 +++++----- src/target/armv7m.h | 4 ++-- src/target/cortex_a8.h | 2 +- src/target/cortex_m3.h | 2 +- src/target/embeddedice.h | 2 +- src/target/etm.h | 4 ++-- src/target/etm_dummy.h | 2 +- src/target/mips32.h | 4 ++-- src/target/mips32_dmaacc.h | 2 +- src/target/mips32_pracc.h | 2 +- src/target/oocd_trace.c | 1 + src/target/oocd_trace.h | 2 -- src/target/target.c | 5 +++-- src/target/target.h | 3 +-- src/target/target_request.c | 5 +++-- src/target/testee.c | 4 +++- src/target/xscale.h | 6 +++--- 29 files changed, 48 insertions(+), 46 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-13 00:44:14
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 0a9d7cab6d76d1203d46e51140ad97d0b5cace56 (commit) from b3e64566ab88dde3f664d7ae59116e7644533ea3 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 0a9d7cab6d76d1203d46e51140ad97d0b5cace56 Author: David Brownell <dbr...@us...> Date: Sat Dec 12 15:43:02 2009 -0800 LPC2000: rename "r13_svc" as "sp_svc" This driver didn't get updated when the name changed. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 18896f7..ae0a384 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -343,7 +343,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta case lpc2000_v1: case lpc2000_v2: /* IAP stack */ - init_reg_param(®_params[3], "r13_svc", 32, PARAM_OUT); + init_reg_param(®_params[3], "sp_svc", 32, PARAM_OUT); buf_set_u32(reg_params[3].value, 0, 32, lpc2000_info->iap_working_area->address + 0xb4); /* return address */ ----------------------------------------------------------------------- Summary of changes: src/flash/nor/lpc2000.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-12 10:35:41
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via b3e64566ab88dde3f664d7ae59116e7644533ea3 (commit) from 75892bfc6ecc41ae19d65c862f0db6f2c1023c2d (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit b3e64566ab88dde3f664d7ae59116e7644533ea3 Author: David Brownell <dbr...@us...> Date: Fri Dec 11 15:38:36 2009 -0800 ARM11: avoid pointless status returns For some routines that only returned ERROR_OK and where the caller never checked ... don't bother. Remove some noise, and bugfix some comments. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 554d6e2..088981f 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -48,14 +48,14 @@ static const tap_state_t arm11_move_pi_to_si_via_ci[] = }; -static int arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, +/* REVISIT no error handling here! */ +static void arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) { if (cmd_queue_cur_state == TAP_IRPAUSE) jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci); jtag_add_ir_scan(num_fields, fields, state); - return ERROR_OK; } static const tap_state_t arm11_move_pd_to_sd_via_cd[] = @@ -63,13 +63,14 @@ static const tap_state_t arm11_move_pd_to_sd_via_cd[] = TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT }; -int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state) +/* REVISIT no error handling here! */ +void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, + tap_state_t state) { if (cmd_queue_cur_state == TAP_DRPAUSE) jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd); jtag_add_dr_scan(num_fields, fields, state); - return ERROR_OK; } @@ -83,7 +84,8 @@ int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t * <em > (data is written when the JTAG queue is executed)</em> * \param field target data structure that will be initialized */ -void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_data, void * in_data, struct scan_field * field) +void arm11_setup_field(struct arm11_common *arm11, int num_bits, + void *out_data, void *in_data, struct scan_field *field) { field->tap = arm11->arm.target->tap; field->num_bits = num_bits; @@ -151,24 +153,17 @@ void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state) arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state); } -/** Verify shifted out data from Scan Chain Register (SCREG) - * Used as parameter to struct scan_field::in_handler in - * arm11_add_debug_SCAN_N(). - * - */ +/** Verify data shifted out from Scan Chain Register (SCREG). */ static void arm11_in_handler_SCAN_N(uint8_t *in_value) { - /** \todo TODO: clarify why this isnt properly masked in core.c jtag_read_buffer() */ + /* Don't expect JTAG layer to modify bits we didn't ask it to read */ uint8_t v = *in_value & 0x1F; if (v != 0x10) { - LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v); + LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v); jtag_set_error(ERROR_FAIL); } - - if (v != 0x10) - JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v); } /** Select and write to Scan Chain Register (SCREG) diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h index 3139a09..7f87e3a 100644 --- a/src/target/arm11_dbgtap.h +++ b/src/target/arm11_dbgtap.h @@ -30,7 +30,7 @@ int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11, int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data); -int arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, +void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields, tap_state_t state); /** ----------------------------------------------------------------------- Summary of changes: src/target/arm11_dbgtap.c | 25 ++++++++++--------------- src/target/arm11_dbgtap.h | 2 +- 2 files changed, 11 insertions(+), 16 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Zach W. <zw...@us...> - 2009-12-12 03:46:37
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 75892bfc6ecc41ae19d65c862f0db6f2c1023c2d (commit) via 8438dee786d857723e29eef23f897df6b194a793 (commit) from 75c706cc043183d98592dbe3c6f170d627849d0f (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 75892bfc6ecc41ae19d65c862f0db6f2c1023c2d Author: Zachary T Welch <zw...@su...> Date: Fri Dec 11 18:43:27 2009 -0800 add missing call to add new NAND devices I forgot to add a call to the newly factored nand_device_add(), along with its forward declaration. diff --git a/src/flash/nand/imp.h b/src/flash/nand/imp.h index e0d411f..e6c9c5f 100644 --- a/src/flash/nand/imp.h +++ b/src/flash/nand/imp.h @@ -22,6 +22,8 @@ #include "core.h" #include "driver.h" +void nand_device_add(struct nand_device *c); + int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size); diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c index e69882b..ad77d7c 100644 --- a/src/flash/nand/tcl.c +++ b/src/flash/nand/tcl.c @@ -580,6 +580,8 @@ static COMMAND_HELPER(create_nand_device, const char *bank_name, return ERROR_OK; } + nand_device_add(c); + return ERROR_OK; } commit 8438dee786d857723e29eef23f897df6b194a793 Author: Zachary T Welch <zw...@su...> Date: Fri Dec 11 18:38:44 2009 -0800 fix 'write_image' usage information The 'flash write_image' command erroneously listed the bank number, when it actually uses target addresses to do that lookup for the user. diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c index 5ba941b..6ab710b 100644 --- a/src/flash/nor/tcl.c +++ b/src/flash/nor/tcl.c @@ -726,7 +726,7 @@ static const struct command_registration flash_exec_command_handlers[] = { .name = "write_image", .handler = &handle_flash_write_image_command, .mode = COMMAND_EXEC, - .usage = "<bank> [erase] [unlock] <file> [offset] [type]", + .usage = "[erase] [unlock] <file> [offset] [type]", .help = "write an image to flash" }, { ----------------------------------------------------------------------- Summary of changes: src/flash/nand/imp.h | 2 ++ src/flash/nand/tcl.c | 2 ++ src/flash/nor/tcl.c | 2 +- 3 files changed, 5 insertions(+), 1 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-12 00:27:22
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 75c706cc043183d98592dbe3c6f170d627849d0f (commit) via 838d41af29c0b703fd55ebb5c3aebcb4e0bea460 (commit) via cfd79e96a6436cea427245a2c2f18fd52001898b (commit) from 08589462adf3f81b480faacecb8352428212a2f5 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 75c706cc043183d98592dbe3c6f170d627849d0f Author: David Brownell <dbr...@us...> Date: Fri Dec 11 15:26:10 2009 -0800 ARM DPM: support updating HW breakpoints Abstract the DPM breakpoint and watchpoint data structures to have a shared core for housekeeping. Abstract the code updating the watchpoint registers so that it can be used to update breakpoint registers. Then do so, when something has set up the breakpoint state used by this code. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index bd9c5d1..0908ca9 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -277,6 +277,51 @@ fail: return retval; } +/* Avoid needless I/O ... leave breakpoints and watchpoints alone + * unless they're removed, or need updating because of single-stepping + * or running debugger code. + */ +static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp, + struct dpm_bpwp *xp, int *set_p) +{ + int retval = ERROR_OK; + bool disable; + + if (!set_p) { + if (!xp->dirty) + goto done; + xp->dirty = false; + /* removed or startup; we must disable it */ + disable = true; + } else if (bpwp) { + if (!xp->dirty) + goto done; + /* disabled, but we must set it */ + xp->dirty = disable = false; + *set_p = true; + } else { + if (!*set_p) + goto done; + /* set, but we must temporarily disable it */ + xp->dirty = disable = true; + *set_p = false; + } + + if (disable) + retval = dpm->bpwp_disable(dpm, xp->number); + else + retval = dpm->bpwp_enable(dpm, xp->number, + xp->address, xp->control); + + if (retval != ERROR_OK) + LOG_ERROR("%s: can't %s HW bp/wp %d", + disable ? "disable" : "enable", + target_name(dpm->arm->target), + xp->number); +done: + return retval; +} + /** * Writes all modified core registers for all processor modes. In normal * operation this is called on exit from halting debug state. @@ -296,47 +341,22 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) if (retval != ERROR_OK) goto done; + /* enable/disable hardware breakpoints */ + for (unsigned i = 0; i < dpm->nbp; i++) { + struct dpm_bp *dbp = dpm->dbp + i; + struct breakpoint *bp = dbp->bp; + + retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp, + bp ? &bp->set : NULL); + } + /* enable/disable watchpoints */ for (unsigned i = 0; i < dpm->nwp; i++) { struct dpm_wp *dwp = dpm->dwp + i; struct watchpoint *wp = dwp->wp; - bool disable; - - /* Avoid needless I/O ... leave watchpoints alone - * unless they're removed, or need updating because - * of single-stepping or running debugger code. - */ - if (!wp) { - if (!dwp->dirty) - continue; - dwp->dirty = false; - /* removed or startup; we must disable it */ - disable = true; - } else if (bpwp) { - if (!dwp->dirty) - continue; - /* disabled, but we must set it */ - dwp->dirty = disable = false; - wp->set = true; - } else { - if (!wp->set) - continue; - /* set, but we must temporarily disable it */ - dwp->dirty = disable = true; - wp->set = false; - } - - if (disable) - retval = dpm->bpwp_disable(dpm, 16 + i); - else - retval = dpm->bpwp_enable(dpm, 16 + i, - wp->address & ~3, dwp->control); - if (retval != ERROR_OK) - LOG_ERROR("%s: can't %s HW watchpoint %d", - target_name(arm->target), - disable ? "disable" : "enable", - i); + retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp, + wp ? &wp->set : NULL); } /* NOTE: writes to breakpoint and watchpoint registers might @@ -696,8 +716,9 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index, */ dpm->dwp[index].wp = wp; - dpm->dwp[index].control = control; - dpm->dwp[index].dirty = true; + dpm->dwp[index].bpwp.address = addr & ~3; + dpm->dwp[index].bpwp.control = control; + dpm->dwp[index].bpwp.dirty = true; /* hardware is updated in write_dirty_registers() */ return ERROR_OK; @@ -731,7 +752,7 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp) for (unsigned i = 0; i < dpm->nwp; i++) { if (dpm->dwp[i].wp == wp) { dpm->dwp[i].wp = NULL; - dpm->dwp[i].dirty = true; + dpm->dwp[i].bpwp.dirty = true; /* hardware is updated in write_dirty_registers() */ retval = ERROR_OK; @@ -869,10 +890,14 @@ int arm_dpm_initialize(struct arm_dpm *dpm) if (dpm->bpwp_disable) { unsigned i; - for (i = 0; i < dpm->nbp; i++) + for (i = 0; i < dpm->nbp; i++) { + dpm->dbp[i].bpwp.number = i; (void) dpm->bpwp_disable(dpm, i); - for (i = 0; i < dpm->nwp; i++) + } + for (i = 0; i < dpm->nwp; i++) { + dpm->dwp[i].bpwp.number = 16 + i; (void) dpm->bpwp_disable(dpm, 16 + i); + } } else LOG_WARNING("%s: can't disable breakpoints and watchpoints", target_name(dpm->arm->target)); diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index 135e3db..5d75ed4 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -31,24 +31,22 @@ * registers are compatible. */ -struct dpm_bp { - struct breakpoint *bp; - /* bp->address == breakpoint value register - * control == breakpoint control register - */ +struct dpm_bpwp { + unsigned number; + uint32_t address; uint32_t control; /* true if hardware state needs flushing */ bool dirty; }; +struct dpm_bp { + struct breakpoint *bp; + struct dpm_bpwp bpwp; +}; + struct dpm_wp { struct watchpoint *wp; - /* wp->address == watchpoint value register - * control == watchpoint control register - */ - uint32_t control; - /* true if hardware state needs flushing */ - bool dirty; + struct dpm_bpwp bpwp; }; /** commit 838d41af29c0b703fd55ebb5c3aebcb4e0bea460 Author: David Brownell <dbr...@us...> Date: Fri Dec 11 15:24:08 2009 -0800 ARM: disassembly fixes for LDC/STC/MRRC/MCRR Properly detect all of these, including the "2" variants; and bugfix parameter display for LDC and STC. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 5c8ad6a..770c5e9 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -288,8 +288,13 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, mnemonic = "MRRC"; } - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, %x, r%i, r%i, c%i", - address, opcode, mnemonic, COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm); + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 + "\t%s%s%s p%i, %x, r%i, r%i, c%i", + address, opcode, mnemonic, + ((opcode & 0xf0000000) == 0xf0000000) + ? "2" : COND(opcode), + COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm); } else /* LDC or STC */ { @@ -300,7 +305,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, CRd = (opcode & 0xf000) >> 12; Rn = (opcode & 0xf0000) >> 16; - offset = (opcode & 0xff); + offset = (opcode & 0xff) << 2; /* load/store */ if (opcode & 0x00100000) @@ -318,19 +323,27 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, N = (opcode & 0x00400000) >> 22; /* addressing modes */ - if ((opcode & 0x01200000) == 0x01000000) /* immediate offset */ - snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]", Rn, (U) ? "" : "-", offset); - else if ((opcode & 0x01200000) == 0x01200000) /* immediate pre-indexed */ - snprintf(addressing_mode, 32, "[r%i, #%s0x%2.2x*4]!", Rn, (U) ? "" : "-", offset); - else if ((opcode & 0x01200000) == 0x00200000) /* immediate post-indexed */ - snprintf(addressing_mode, 32, "[r%i], #%s0x%2.2x*4", Rn, (U) ? "" : "-", offset); + if ((opcode & 0x01200000) == 0x01000000) /* offset */ + snprintf(addressing_mode, 32, "[r%i, #%s%d]", + Rn, U ? "" : "-", offset); + else if ((opcode & 0x01200000) == 0x01200000) /* pre-indexed */ + snprintf(addressing_mode, 32, "[r%i, #%s%d]!", + Rn, U ? "" : "-", offset); + else if ((opcode & 0x01200000) == 0x00200000) /* post-indexed */ + snprintf(addressing_mode, 32, "[r%i], #%s%d", + Rn, U ? "" : "-", offset); else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */ - snprintf(addressing_mode, 32, "[r%i], #0x%2.2x", Rn, offset); + snprintf(addressing_mode, 32, "[r%i], {%d}", + Rn, offset >> 2); - snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s p%i, c%i, %s", - address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) ? COND(opcode) : "2", - (N) ? "L" : "", - cp_num, CRd, addressing_mode); + snprintf(instruction->text, 128, "0x%8.8" PRIx32 + "\t0x%8.8" PRIx32 + "\t%s%s%s p%i, c%i, %s", + address, opcode, mnemonic, + ((opcode & 0xf0000000) == 0xf0000000) + ? "2" : COND(opcode), + (opcode & (1 << 22)) ? "L" : "", + cp_num, CRd, addressing_mode); } return ERROR_OK; @@ -1638,7 +1651,8 @@ static int evaluate_data_proc(uint32_t opcode, return ERROR_OK; } -int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instruction *instruction) +int arm_evaluate_opcode(uint32_t opcode, uint32_t address, + struct arm_instruction *instruction) { /* clear fields, to avoid confusion */ memset(instruction, 0, sizeof(struct arm_instruction)); @@ -1760,7 +1774,7 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instructio } /* catch opcodes with [27:25] = b110 */ - if ((opcode & 0x0e000000) == 0x0a000000) + if ((opcode & 0x0e000000) == 0x0c000000) { /* Coprocessor load/store and double register transfers */ return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction); @@ -1782,7 +1796,8 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, struct arm_instructio return evaluate_cdp_mcr_mrc(opcode, address, instruction); } - LOG_ERROR("should never reach this point"); + LOG_ERROR("ARM: should never reach this point (opcode=%08x)", + (unsigned) opcode); return -1; } @@ -2796,7 +2811,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct } } - LOG_ERROR("should never reach this point (opcode=%04x)",opcode); + LOG_ERROR("Thumb: should never reach this point (opcode=%04x)", opcode); return -1; } commit cfd79e96a6436cea427245a2c2f18fd52001898b Author: David Brownell <dbr...@us...> Date: Fri Dec 11 15:24:08 2009 -0800 ARM11: minor cleanup, mostly ITR comments ITR register handling seemed to be giving me problems, so I updated the comments to better say what the code is trying to do ... and to note the preconditions (one of which seems to be an issue) as listed in the ARM1136 TRM. Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code; all the callers already specify an exit path, since this register isn't usable with such vague semantics. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm11.c b/src/target/arm11.c index 7b29f53..7c747c0 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -1012,27 +1012,25 @@ static int arm11_write_memory_inner(struct target *target, } case 4: { + /* increment: STC p14,c5,[R0],#4 */ + /* no increment: STC p14,c5,[R0]*/ uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00; /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ uint32_t *words = (uint32_t*)buffer; + /* "burst" here just means trusting each instruction executes + * fully before we run the next one: per-word roundtrips, to + * check the Ready flag, are not used. + */ if (!burst) - { - /* STC p14,c5,[R0],#4 */ - /* STC p14,c5,[R0]*/ - retval = arm11_run_instr_data_to_core(arm11, instr, words, count); - if (retval != ERROR_OK) - return retval; - } + retval = arm11_run_instr_data_to_core(arm11, + instr, words, count); else - { - /* STC p14,c5,[R0],#4 */ - /* STC p14,c5,[R0]*/ - retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count); - if (retval != ERROR_OK) - return retval; - } + retval = arm11_run_instr_data_to_core_noack(arm11, + instr, words, count); + if (retval != ERROR_OK) + return retval; break; } @@ -1309,7 +1307,7 @@ static const struct command_registration arm11_mw_command_handlers[] = { .name = "burst", .handler = &arm11_handle_bool_memwrite_burst, .mode = COMMAND_ANY, - .help = "Enable/Disable non-standard but fast burst mode" + .help = "Enable/Disable potentially risky fast burst mode" " (default: enabled)", }, { diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 9ad5662..554d6e2 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -230,22 +230,23 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11, return jtag_execute_queue(); } -/** Write an instruction into the ITR register +/** + * Queue a DR scan of the ITR register. Caller must have selected + * scan chain 4 (ITR), possibly using ITRSEL. * * \param arm11 Target state variable. * \param inst An ARM11 processor instruction/opcode. - * \param flag Optional parameter to retrieve the InstCompl flag - * (this will be written when the JTAG chain is executed). - * \param state Pass the final TAP state or ARM11_TAP_DEFAULT for the default - * value (Run-Test/Idle). + * \param flag Optional parameter to retrieve the Ready flag; + * this address will be written when the JTAG chain is scanned. + * \param state The TAP state to enter after the DR scan. * - * \remarks By default this ends with Run-Test/Idle state - * and causes the instruction to be executed. If - * a subsequent write to DTR is needed before - * executing the instruction then TAP_DRPAUSE should be - * passed to \p state. + * Going through the TAP_DRUPDATE state writes ITR only if Ready was + * previously set. Only the Ready flag is readable by the scan. * - * \remarks This adds to the JTAG command queue but does \em not execute it. + * An instruction loaded into ITR is executed when going through the + * TAP_IDLE state only if Ready was previously set and the debug state + * is properly set up. Depending on the instruction, you may also need + * to ensure that the rDTR is ready before that Run-Test/Idle state. */ static void arm11_add_debug_INST(struct arm11_common * arm11, uint32_t inst, uint8_t * flag, tap_state_t state) @@ -257,7 +258,7 @@ static void arm11_add_debug_INST(struct arm11_common * arm11, arm11_setup_field(arm11, 32, &inst, NULL, itr + 0); arm11_setup_field(arm11, 1, NULL, flag, itr + 1); - arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state == ARM11_TAP_DEFAULT ? TAP_IDLE : state); + arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state); } /** @@ -374,7 +375,11 @@ int arm11_run_instr_data_finish(struct arm11_common * arm11) -/** Execute one or multiple instructions via ITR +/** + * Execute one or more instructions via ITR. + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block * @@ -444,6 +449,10 @@ int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode) /** Execute one instruction via ITR repeatedly while * passing data to the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * The executed instruction \em must read data from DTR. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block @@ -570,6 +579,10 @@ static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = /** Execute one instruction via ITR repeatedly while * passing data to the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * No Ready check during transmission. * * The executed instruction \em must read data from DTR. @@ -678,6 +691,10 @@ int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, /** Execute one instruction via ITR repeatedly while * reading data from the core via DTR on each execution. * + * Caller guarantees that processor is in debug state, that DSCR_ITR_EN + * is set, the ITR Ready flag is set (as seen on the previous entry to + * TAP_DRCAPTURE), and the DSCR sticky abort flag is clear. + * * The executed instruction \em must write data to DTR. * * \pre arm11_run_instr_data_prepare() / arm11_run_instr_data_finish() block ----------------------------------------------------------------------- Summary of changes: src/target/arm11.c | 28 +++++------ src/target/arm11_dbgtap.c | 43 +++++++++++----- src/target/arm_disassembler.c | 51 +++++++++++++------- src/target/arm_dpm.c | 107 +++++++++++++++++++++++++---------------- src/target/arm_dpm.h | 20 ++++---- 5 files changed, 151 insertions(+), 98 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Spencer O. <nt...@us...> - 2009-12-11 11:41:53
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 08589462adf3f81b480faacecb8352428212a2f5 (commit) via 6b9c14e9085b5620c20e9cadffe1f5e64f09a0c6 (commit) from 97996214f593d0d1969446484598c58077da3965 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 08589462adf3f81b480faacecb8352428212a2f5 Author: Spencer Oliver <nt...@us...> Date: Thu Dec 10 14:31:28 2009 +0000 server: add server_preinit which is called before config file is parsed. This fixes the issue under native win32 of the socket interface not being enabled (via WSAStartup) before init is called from a script. Signed-off-by: Spencer Oliver <nt...@us...> diff --git a/src/openocd.c b/src/openocd.c index 8cb8674..1105d2a 100644 --- a/src/openocd.c +++ b/src/openocd.c @@ -62,7 +62,6 @@ COMMAND_HANDLER(handle_version_command) return ERROR_OK; } - static int log_target_callback_event_handler(struct target *target, enum target_event event, void *priv) { switch (event) @@ -255,13 +254,15 @@ int openocd_main(int argc, char *argv[]) "http://openocd.berlios.de/doc/doxygen/bugs.html" "\n"); - command_context_mode(cmd_ctx, COMMAND_CONFIG); command_set_output_handler(cmd_ctx, configuration_output_handler, NULL); if (parse_cmdline_args(cmd_ctx, argc, argv) != ERROR_OK) return EXIT_FAILURE; + if (server_preinit() != ERROR_OK) + return EXIT_FAILURE; + ret = parse_config_file(cmd_ctx); if (ret != ERROR_OK) return EXIT_FAILURE; diff --git a/src/server/server.c b/src/server/server.c index 2f4bfb0..75a6bed 100644 --- a/src/server/server.c +++ b/src/server/server.c @@ -487,8 +487,12 @@ void sig_handler(int sig) { } #endif -int server_init(struct command_context *cmd_ctx) +int server_preinit(void) { + /* this currently only calls WSAStartup on native win32 systems + * before any socket operations are performed. + * This is an issue if you call init in your config script */ + #ifdef _WIN32 WORD wVersionRequested; WSADATA wsaData; @@ -518,6 +522,11 @@ int server_init(struct command_context *cmd_ctx) signal(SIGABRT, sig_handler); #endif + return ERROR_OK; +} + +int server_init(struct command_context *cmd_ctx) +{ int ret = tcl_init(cmd_ctx); if (ERROR_OK != ret) return ret; diff --git a/src/server/server.h b/src/server/server.h index be1afbe..a25920e 100644 --- a/src/server/server.h +++ b/src/server/server.h @@ -74,6 +74,7 @@ int add_service(char *name, enum connection_type type, unsigned short port, input_handler_t in_handler, connection_closed_handler_t close_handler, void *priv); +int server_preinit(void); int server_init(struct command_context *cmd_ctx); int server_quit(void); commit 6b9c14e9085b5620c20e9cadffe1f5e64f09a0c6 Author: Spencer Oliver <nt...@us...> Date: Thu Dec 10 11:28:38 2009 +0000 build: fix cygwin build warnings Signed-off-by: Spencer Oliver <nt...@us...> diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c index 54f7cb1..4ca4349 100644 --- a/src/jtag/drivers/jlink.c +++ b/src/jtag/drivers/jlink.c @@ -186,7 +186,7 @@ static void jlink_execute_reset(struct jtag_command *cmd) static void jlink_execute_sleep(struct jtag_command *cmd) { - DEBUG_JTAG_IO("sleep %i", cmd->cmd.sleep->us); + DEBUG_JTAG_IO("sleep %" PRIi32 "", cmd->cmd.sleep->us); jlink_tap_execute(); jtag_sleep(cmd->cmd.sleep->us); } ----------------------------------------------------------------------- Summary of changes: src/jtag/drivers/jlink.c | 2 +- src/openocd.c | 5 +++-- src/server/server.c | 11 ++++++++++- src/server/server.h | 1 + 4 files changed, 15 insertions(+), 4 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-11 09:19:54
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 97996214f593d0d1969446484598c58077da3965 (commit) via 1c42606aea99e870f0ffd435390e29a160d019ee (commit) via ac46e072dfa708ab83c5667f2dc8ee504504aa4b (commit) via 068626fde4590a3d3e5e7a80a3ac07adb53b9b48 (commit) from a34345451deaa952b8b868d2dd74954035f503c5 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 97996214f593d0d1969446484598c58077da3965 Author: Ãyvind Harboe <oyv...@zy...> Date: Thu Dec 10 19:14:45 2009 +0100 gdb_server: use more local variables in inner loop of fetching packetstiny refactoring to allow optimisation of inner loops Some profiling information for arm7 16MHz GDB load operation shows gdb_get_packet_inner() near the very top. Each sample counts as 0.01 seconds. % cumulative self self total time seconds seconds calls Ts/call Ts/call name 52.91 2.27 2.27 embeddedice_write_dcc 11.89 2.78 0.51 gdb_get_packet_inner 8.86 3.16 0.38 memcpy 3.26 3.30 0.14 idle_thread_main(unsigned int) 3.03 3.43 0.13 cyg_in_cksum Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index ea92d3b..8798ae0 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -149,30 +149,11 @@ int check_pending(struct connection *connection, int timeout_s, int *got_data) return ERROR_OK; } -int gdb_get_char(struct connection *connection, int* next_char) +static int gdb_get_char_inner(struct connection *connection, int* next_char) { struct gdb_connection *gdb_con = connection->priv; int retval = ERROR_OK; -#ifdef _DEBUG_GDB_IO_ - char *debug_buffer; -#endif - - if (gdb_con->buf_cnt-- > 0) - { - *next_char = *(gdb_con->buf_p++); - if (gdb_con->buf_cnt > 0) - connection->input_pending = 1; - else - connection->input_pending = 0; - -#ifdef _DEBUG_GDB_IO_ - LOG_DEBUG("returned char '%c' (0x%2.2x)", *next_char, *next_char); -#endif - - return ERROR_OK; - } - for (;;) { if (connection->service->type == CONNECTION_PIPE) @@ -257,6 +238,50 @@ int gdb_get_char(struct connection *connection, int* next_char) return retval; } +/** + * The cool thing about this fn is that it allows buf_p and buf_cnt to be + * held in registers in the inner loop. + * + * For small caches and embedded systems this is important! + */ +static inline int gdb_get_char_fast(struct connection *connection, int* next_char, char **buf_p, int *buf_cnt) +{ + int retval = ERROR_OK; + + if ((*buf_cnt)-- > 0) + { + *next_char = **buf_p; + (*buf_p)++; + if (*buf_cnt > 0) + connection->input_pending = 1; + else + connection->input_pending = 0; + +#ifdef _DEBUG_GDB_IO_ + LOG_DEBUG("returned char '%c' (0x%2.2x)", *next_char, *next_char); +#endif + + return ERROR_OK; + } + + struct gdb_connection *gdb_con = connection->priv; + gdb_con->buf_p = *buf_p; + gdb_con->buf_cnt = *buf_cnt; + retval = gdb_get_char_inner(connection, next_char); + *buf_p = gdb_con->buf_p; + *buf_cnt = gdb_con->buf_cnt; + + return retval; +} + + +int gdb_get_char(struct connection *connection, int* next_char) +{ + struct gdb_connection *gdb_con = connection->priv; + return gdb_get_char_fast(connection, next_char, &gdb_con->buf_p, &gdb_con->buf_cnt); +} + + int gdb_putback_char(struct connection *connection, int last_char) { struct gdb_connection *gdb_con = connection->priv; @@ -461,27 +486,33 @@ static __inline__ int fetch_packet(struct connection *connection, int *checksum_ unsigned char my_checksum = 0; char checksum[3]; int character; - int retval; + int retval = ERROR_OK; struct gdb_connection *gdb_con = connection->priv; my_checksum = 0; int count = 0; count = 0; + + /* move this over into local variables to use registers and give the + * more freedom to optimize */ + char *buf_p = gdb_con->buf_p; + int buf_cnt = gdb_con->buf_cnt; + for (;;) { /* The common case is that we have an entire packet with no escape chars. * We need to leave at least 2 bytes in the buffer to have * gdb_get_char() update various bits and bobs correctly. */ - if ((gdb_con->buf_cnt > 2) && ((gdb_con->buf_cnt + count) < *len)) + if ((buf_cnt > 2) && ((buf_cnt + count) < *len)) { /* The compiler will struggle a bit with constant propagation and * aliasing, so we help it by showing that these values do not * change inside the loop */ int i; - char *buf = gdb_con->buf_p; - int run = gdb_con->buf_cnt - 2; + char *buf = buf_p; + int run = buf_cnt - 2; i = 0; int done = 0; while (i < run) @@ -513,19 +544,21 @@ static __inline__ int fetch_packet(struct connection *connection, int *checksum_ buffer[count++] = character & 0xff; } } - gdb_con->buf_p += i; - gdb_con->buf_cnt -= i; + buf_p += i; + buf_cnt -= i; if (done) break; } if (count > *len) { LOG_ERROR("packet buffer too small"); - return ERROR_GDB_BUFFER_TOO_SMALL; + retval = ERROR_GDB_BUFFER_TOO_SMALL; + break; } - if ((retval = gdb_get_char(connection, &character)) != ERROR_OK) - return retval; + retval = gdb_get_char_fast(connection, &character, &buf_p, &buf_cnt); + if (retval != ERROR_OK) + break; if (character == '#') break; @@ -535,8 +568,11 @@ static __inline__ int fetch_packet(struct connection *connection, int *checksum_ /* data transmitted in binary mode (X packet) * uses 0x7d as escape character */ my_checksum += character & 0xff; - if ((retval = gdb_get_char(connection, &character)) != ERROR_OK) - return retval; + + retval = gdb_get_char_fast(connection, &character, &buf_p, &buf_cnt); + if (retval != ERROR_OK) + break; + my_checksum += character & 0xff; buffer[count++] = (character ^ 0x20) & 0xff; } @@ -547,6 +583,12 @@ static __inline__ int fetch_packet(struct connection *connection, int *checksum_ } } + gdb_con->buf_p = buf_p; + gdb_con->buf_cnt = buf_cnt; + + if (retval != ERROR_OK) + return retval; + *len = count; if ((retval = gdb_get_char(connection, &character)) != ERROR_OK) commit 1c42606aea99e870f0ffd435390e29a160d019ee Author: Ãyvind Harboe <oyv...@zy...> Date: Thu Dec 10 19:11:03 2009 +0100 gdb_server: make struct gdb_connection private it is only used inside gdb_server.c Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c index f9cca99..ea92d3b 100644 --- a/src/server/gdb_server.c +++ b/src/server/gdb_server.c @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 Ãyvind Harboe * + * Copyright (C) 2007-2009 Ãyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * @@ -37,6 +37,25 @@ #include <jtag/jtag.h> +/* private connection data for GDB */ +struct gdb_connection +{ + char buffer[GDB_BUFFER_SIZE]; + char *buf_p; + int buf_cnt; + int ctrl_c; + enum target_state frontend_state; + struct image *vflash_image; + int closed; + int busy; + int noack_mode; + bool sync; /* set flag to true if you want the next stepi to return immediately. + allowing GDB to pick up a fresh set of register values from the target + without modifying the target state. */ + +}; + + #if 0 #define _DEBUG_GDB_IO_ #endif diff --git a/src/server/gdb_server.h b/src/server/gdb_server.h index 05666a5..17e40fe 100644 --- a/src/server/gdb_server.h +++ b/src/server/gdb_server.h @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 Ãyvind Harboe * + * Copyright (C) 2007-2009 Ãyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * @@ -31,23 +31,6 @@ struct image; #define GDB_BUFFER_SIZE 16384 -struct gdb_connection -{ - char buffer[GDB_BUFFER_SIZE]; - char *buf_p; - int buf_cnt; - int ctrl_c; - enum target_state frontend_state; - struct image *vflash_image; - int closed; - int busy; - int noack_mode; - bool sync; /* set flag to true if you want the next stepi to return immediately. - allowing GDB to pick up a fresh set of register values from the target - without modifying the target state. */ - -}; - struct gdb_service { struct target *target; commit ac46e072dfa708ab83c5667f2dc8ee504504aa4b Author: Ãyvind Harboe <oyv...@zy...> Date: Thu Dec 10 15:09:20 2009 +0100 optimisation: tiny optimisation for embedded ice use two shift operations instead of three to set embedded ice register. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h index 1faa1ee..693391c 100644 --- a/src/target/embeddedice.h +++ b/src/target/embeddedice.h @@ -118,15 +118,14 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou */ static __inline__ void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg_addr, uint32_t value) { - static const int embeddedice_num_bits[]={32,5,1}; - uint32_t values[3]; + static const int embeddedice_num_bits[] = {32, 6}; + uint32_t values[2]; - values[0]=value; - values[1]=reg_addr; - values[2]=1; + values[0] = value; + values[1] = (1 << 5) | reg_addr; jtag_add_dr_out(tap, - 3, + 2, embeddedice_num_bits, values, jtag_get_end_state()); commit 068626fde4590a3d3e5e7a80a3ac07adb53b9b48 Author: Ãyvind Harboe <oyv...@zy...> Date: Thu Dec 10 15:00:19 2009 +0100 embedded hosts: optimize common code path for core arm operations avoid fn call for the if check on whether anything needs to be done. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c index af626ec..f7a540a 100644 --- a/src/target/arm_jtag.c +++ b/src/target/arm_jtag.c @@ -31,65 +31,54 @@ #define _ARM_JTAG_SCAN_N_CHECK_ #endif -int arm_jtag_set_instr(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture) +int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture) { struct jtag_tap *tap; tap = jtag_info->tap; - if (tap == NULL) - return ERROR_FAIL; + struct scan_field field; + uint8_t t[4]; - if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) + field.tap = tap; + field.num_bits = tap->ir_length; + field.out_value = t; + buf_set_u32(field.out_value, 0, field.num_bits, new_instr); + field.in_value = NULL; + + if (no_verify_capture == NULL) + { + jtag_add_ir_scan(1, &field, jtag_get_end_state()); + } else { - struct scan_field field; - uint8_t t[4]; - - field.tap = tap; - field.num_bits = tap->ir_length; - field.out_value = t; - buf_set_u32(field.out_value, 0, field.num_bits, new_instr); - field.in_value = NULL; - - - - if (no_verify_capture == NULL) - { - jtag_add_ir_scan(1, &field, jtag_get_end_state()); - } else - { - /* FIX!!!! this is a kludge!!! arm926ejs.c should reimplement this arm_jtag_set_instr to - * have special verification code. - */ - jtag_add_ir_scan_noverify(1, &field, jtag_get_end_state()); - } + /* FIX!!!! this is a kludge!!! arm926ejs.c should reimplement this arm_jtag_set_instr to + * have special verification code. + */ + jtag_add_ir_scan_noverify(1, &field, jtag_get_end_state()); } return ERROR_OK; } -int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain) +int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain) { int retval = ERROR_OK; - if (jtag_info->cur_scan_chain != new_scan_chain) - { - uint32_t values[1]; - int num_bits[1]; + uint32_t values[1]; + int num_bits[1]; - values[0]=new_scan_chain; - num_bits[0]=jtag_info->scann_size; + values[0]=new_scan_chain; + num_bits[0]=jtag_info->scann_size; - if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL)) != ERROR_OK) - { - return retval; - } + if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL)) != ERROR_OK) + { + return retval; + } - jtag_add_dr_out(jtag_info->tap, - 1, - num_bits, - values, - jtag_get_end_state()); + jtag_add_dr_out(jtag_info->tap, + 1, + num_bits, + values, + jtag_get_end_state()); - jtag_info->cur_scan_chain = new_scan_chain; - } + jtag_info->cur_scan_chain = new_scan_chain; return retval; } diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h index 6f03fc6..cf230b4 100644 --- a/src/target/arm_jtag.h +++ b/src/target/arm_jtag.h @@ -36,9 +36,40 @@ struct arm_jtag uint32_t intest_instr; }; -int arm_jtag_set_instr(struct arm_jtag *jtag_info, - uint32_t new_instr, void *verify_capture); -int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain); +int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, void *no_verify_capture); +static inline int arm_jtag_set_instr(struct arm_jtag *jtag_info, + uint32_t new_instr, void *no_verify_capture) +{ + /* inline most common code path */ + struct jtag_tap *tap; + tap = jtag_info->tap; + if (tap == NULL) + return ERROR_FAIL; + + if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) + { + return arm_jtag_set_instr_inner(jtag_info, new_instr, no_verify_capture); + } + + return ERROR_OK; + +} + + +int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain); +static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain) +{ + /* inline most common code path */ + int retval = ERROR_OK; + if (jtag_info->cur_scan_chain != new_scan_chain) + { + return arm_jtag_scann_inner(jtag_info, new_scan_chain); + } + + return retval; +} + + int arm_jtag_setup_connection(struct arm_jtag *jtag_info); /* use this as a static so we can inline it in -O3 and refer to it via a pointer */ ----------------------------------------------------------------------- Summary of changes: src/server/gdb_server.c | 125 ++++++++++++++++++++++++++++++++++------------ src/server/gdb_server.h | 19 +------- src/target/arm_jtag.c | 75 ++++++++++++---------------- src/target/arm_jtag.h | 37 ++++++++++++- src/target/embeddedice.h | 11 ++-- 5 files changed, 165 insertions(+), 102 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-11 02:42:58
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via a34345451deaa952b8b868d2dd74954035f503c5 (commit) from 134df4b701a343acc598d111986570bc90eb675d (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit a34345451deaa952b8b868d2dd74954035f503c5 Author: David Brownell <dbr...@us...> Date: Thu Dec 10 17:42:20 2009 -0800 anotyer cygwin compile fix Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index b5e1010..8584843 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -641,7 +641,8 @@ static int stellaris_protect_check(struct flash_bank *bank) status = target_read_u32(bank->target, SCB_BASE + (i ? (FMPPE0 + 4 * i) : FMPPE), &lockbits); - LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i, lockbits, status); + LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i, + (unsigned) lockbits, status); if (status != ERROR_OK) goto done; ----------------------------------------------------------------------- Summary of changes: src/flash/nor/stellaris.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-10 14:42:45
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 134df4b701a343acc598d111986570bc90eb675d (commit) from 29a8cdc3b066df0a6038775621154ba525389321 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 134df4b701a343acc598d111986570bc90eb675d Author: Ãyvind Harboe <oyv...@zy...> Date: Mon Dec 7 12:38:56 2009 +0100 zy1000: revc FPGA now works remove kludge code. Signed-off-by: Ãyvind Harboe <oyv...@zy...> diff --git a/src/jtag/zy1000/jtag_minidriver.h b/src/jtag/zy1000/jtag_minidriver.h index 536c677..a78a063 100644 --- a/src/jtag/zy1000/jtag_minidriver.h +++ b/src/jtag/zy1000/jtag_minidriver.h @@ -32,33 +32,9 @@ int diag_printf(const char *fmt, ...); #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b); diag_printf("peek 0x%08x = 0x%08x\n", a, b) #else #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b) - -#ifdef CYGPKG_HAL_NIOS2 -#define ZY1000_POKE(a, b) \ - {/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \ - flush every "often". No precise system has been found, but 4 seems solid. \ - This code goes away once the FPGA has been fixed. */ \ -\ -CYG_INTERRUPT_STATE _old_; \ -HAL_DISABLE_INTERRUPTS(_old_); \ -HAL_WRITE_UINT32(a, b);\ - static int overflow_counter = 0; \ - if (++overflow_counter >= 1) \ - { \ - /* clear FIFO */ \ - cyg_uint32 empty; ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); \ - overflow_counter = 0; \ - } \ - /* NB! interrupts must be restored *after* read */ \ - HAL_RESTORE_INTERRUPTS(_old_); \ -}\ - -#else #define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b) #endif -#endif - // FIFO empty? static __inline__ void waitIdle(void) { diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c index 5ddc7c5..30b9a4b 100644 --- a/src/jtag/zy1000/zy1000.c +++ b/src/jtag/zy1000/zy1000.c @@ -93,8 +93,8 @@ static bool readPowerDropout(void) { cyg_uint32 state; // sample and clear power dropout - HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x10, 0x80); - HAL_READ_UINT32(ZY1000_JTAG_BASE + 0x10, state); + ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x80); + ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state); bool powerDropout; powerDropout = (state & 0x80) != 0; return powerDropout; @@ -105,8 +105,8 @@ static bool readSRST(void) { cyg_uint32 state; // sample and clear SRST sensing - HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x10, 0x00000040); - HAL_READ_UINT32(ZY1000_JTAG_BASE + 0x10, state); + ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x00000040); + ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, state); bool srstAsserted; srstAsserted = (state & 0x40) != 0; return srstAsserted; @@ -218,10 +218,10 @@ static void setPower(bool power) savePower = power; if (power) { - HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x14, 0x8); + ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x8); } else { - HAL_WRITE_UINT32(ZY1000_JTAG_BASE + 0x10, 0x8); + ZY1000_POKE(ZY1000_JTAG_BASE + 0x10, 0x8); } } ----------------------------------------------------------------------- Summary of changes: src/jtag/zy1000/jtag_minidriver.h | 24 ------------------------ src/jtag/zy1000/zy1000.c | 12 ++++++------ 2 files changed, 6 insertions(+), 30 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-10 06:45:04
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 29a8cdc3b066df0a6038775621154ba525389321 (commit) from 3d9cb516c2cf4f5c5d77fb96899f1c44eb3f3450 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 29a8cdc3b066df0a6038775621154ba525389321 Author: David Brownell <dbr...@us...> Date: Wed Dec 9 21:43:23 2009 -0800 ARM: update arm_opcodes.h copyright I neglected to copy Magnus' copyright when I moved several declarations from the ARMv7-M header. Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index 58498ac..b77721e 100644 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -2,6 +2,9 @@ * Copyright (C) 2005 by Dominic Rath * Dom...@gm... * + * Copyright (C) 2006 by Magnus Lundin + * lu...@ml... + * * Copyright (C) 2008 by Spencer Oliver * sp...@sp... * ----------------------------------------------------------------------- Summary of changes: src/target/arm_opcodes.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-10 06:23:40
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 3d9cb516c2cf4f5c5d77fb96899f1c44eb3f3450 (commit) from 910dd664ceb6faef5e9029e9b0848d7ccc63bf4b (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 3d9cb516c2cf4f5c5d77fb96899f1c44eb3f3450 Author: David Brownell <dbr...@us...> Date: Wed Dec 9 21:16:09 2009 -0800 stellaris: flash protection updates, minor fixes Bugfix the read side of flash protection: - read the right register(s)! - handle more than 64K - record the results in the right places - don't display garbage. Partially bugfix the write side: - use 2KB lock regions instead of 1KB pages (!) - validate input range - don't try to _remove_ protection (it's write-once) - #define values we'll need to commit writes. - ... still doesn't handle pages over 64KB mark, or commit writes And minor cleanup and fixes: - get rid of some forward decls - properly locate a doxygen comment - fix some bad indentation - remove superfluous #include - add a new part ID (many are still missing) - make the downloaded algorithm code be read-only Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c index 3988542..b5e1010 100644 --- a/src/flash/nor/stellaris.c +++ b/src/flash/nor/stellaris.c @@ -30,7 +30,6 @@ #include "imp.h" #include "stellaris.h" -#include <helper/binarybuffer.h> #include <target/algorithm.h> #include <target/armv7m.h> @@ -39,8 +38,6 @@ static int stellaris_read_part_info(struct flash_bank *bank); static uint32_t stellaris_get_flash_status(struct flash_bank *bank); -static void stellaris_set_flash_mode(struct flash_bank *bank,int mode); -//static uint32_t stellaris_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout); static int stellaris_mass_erase(struct flash_bank *bank); @@ -94,6 +91,7 @@ static struct { {0x46,"LM3S3759"}, {0x48,"LM3S3768"}, {0x49,"LM3S3748"}, + {0x4B,"LM3S5R36"}, {0x50,"LM3S2678"}, {0x51,"LM3S2110"}, {0x52,"LM3S2739"}, @@ -302,12 +300,13 @@ static int stellaris_info(struct flash_bank *bank, char *buf, int buf_size) if (stellaris_info->num_lockbits > 0) { printed = snprintf(buf, - buf_size, - "pagesize: %" PRIi32 ", lockbits: %i 0x%4.4" PRIx32 ", pages in lock region: %i \n", - stellaris_info->pagesize, - stellaris_info->num_lockbits, - stellaris_info->lockbits, - (int)(stellaris_info->num_pages/stellaris_info->num_lockbits)); + buf_size, + "pagesize: %" PRIi32 ", pages: %d, " + "lockbits: %i, pages per lockbit: %i\n", + stellaris_info->pagesize, + (unsigned) stellaris_info->num_pages, + stellaris_info->num_lockbits, + (unsigned) stellaris_info->pages_in_lockregion); buf += printed; buf_size -= printed; } @@ -328,7 +327,16 @@ static uint32_t stellaris_get_flash_status(struct flash_bank *bank) return fmc; } -/** Read clock configuration and set stellaris_info->usec_clocks*/ +/* Setup the timimg registers */ +static void stellaris_set_flash_mode(struct flash_bank *bank,int mode) +{ + struct stellaris_flash_bank *stellaris_info = bank->driver_priv; + struct target *target = bank->target; + uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1); + + LOG_DEBUG("usecrl = %i",(int)(usecrl)); + target_write_u32(target, SCB_BASE | USECRL, usecrl); +} static const unsigned rcc_xtal[32] = { [0x00] = 1000000, /* no pll */ @@ -363,6 +371,7 @@ static const unsigned rcc_xtal[32] = { [0x16] = 16384000, }; +/** Read clock configuration and set stellaris_info->usec_clocks. */ static void stellaris_read_clock_info(struct flash_bank *bank) { struct stellaris_flash_bank *stellaris_info = bank->driver_priv; @@ -449,17 +458,6 @@ static void stellaris_read_clock_info(struct flash_bank *bank) stellaris_set_flash_mode(bank, 0); } -/* Setup the timimg registers */ -static void stellaris_set_flash_mode(struct flash_bank *bank,int mode) -{ - struct stellaris_flash_bank *stellaris_info = bank->driver_priv; - struct target *target = bank->target; - - uint32_t usecrl = (stellaris_info->mck_freq/1000000ul-1); - LOG_DEBUG("usecrl = %i",(int)(usecrl)); - target_write_u32(target, SCB_BASE | USECRL, usecrl); -} - #if 0 static uint32_t stellaris_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout) { @@ -590,7 +588,6 @@ static int stellaris_read_part_info(struct flash_bank *bank) stellaris_info->pagesize = 1024; bank->size = 1024 * stellaris_info->num_pages; stellaris_info->pages_in_lockregion = 2; - target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits); /* provide this for the benefit of the higher flash driver layers */ bank->num_sectors = stellaris_info->num_pages; @@ -617,31 +614,51 @@ static int stellaris_read_part_info(struct flash_bank *bank) static int stellaris_protect_check(struct flash_bank *bank) { - uint32_t status; - - struct stellaris_flash_bank *stellaris_info = bank->driver_priv; + struct stellaris_flash_bank *stellaris = bank->driver_priv; + int status = ERROR_OK; + unsigned i; + unsigned page; - if (bank->target->state != TARGET_HALTED) + if (stellaris->did1 == 0) { - LOG_ERROR("Target not halted"); - return ERROR_TARGET_NOT_HALTED; + status = stellaris_read_part_info(bank); + if (status < 0) + return status; } - if (stellaris_info->did1 == 0) - { - stellaris_read_part_info(bank); - } + for (i = 0; i < (unsigned) bank->num_sectors; i++) + bank->sectors[i].is_protected = -1; - if (stellaris_info->did1 == 0) - { - LOG_WARNING("Cannot identify target as Stellaris"); - return ERROR_FLASH_OPERATION_FAILED; + /* Read each Flash Memory Protection Program Enable (FMPPE) register + * to report any pages that we can't write. Ignore the Read Enable + * register (FMPRE). + */ + for (i = 0, page = 0; + i < DIV_ROUND_UP(stellaris->num_lockbits, 32u); + i++) { + uint32_t lockbits; + + status = target_read_u32(bank->target, + SCB_BASE + (i ? (FMPPE0 + 4 * i) : FMPPE), + &lockbits); + LOG_DEBUG("FMPPE%d = %#8.8x (status %d)", i, lockbits, status); + if (status != ERROR_OK) + goto done; + + for (unsigned j = 0; j < 32; j++) { + unsigned k; + + for (k = 0; k < stellaris->pages_in_lockregion; k++) { + if (page >= (unsigned) bank->num_sectors) + goto done; + bank->sectors[page++].is_protected = + !(lockbits & (1 << j)); + } + } } - status = stellaris_get_flash_status(bank); - stellaris_info->lockbits = status >> 16; - - return ERROR_OK; +done: + return status; } static int stellaris_erase(struct flash_bank *bank, int first, int last) @@ -728,8 +745,19 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la return ERROR_TARGET_NOT_HALTED; } - if ((first < 0) || (last < first) || (last >= stellaris_info->num_lockbits)) + if (!set) + { + LOG_ERROR("Can't unprotect write-protected pages."); + /* except by the "recover locked device" procedure ... */ + return ERROR_INVALID_ARGUMENTS; + } + + /* lockregions are 2 pages ... must protect [even..odd] */ + if ((first < 0) || (first & 1) + || (last < first) || !(last & 1) + || (last >= 2 * stellaris_info->num_lockbits)) { + LOG_ERROR("Can't protect unaligned or out-of-range sectors."); return ERROR_FLASH_SECTOR_INVALID; } @@ -748,27 +776,40 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la stellaris_read_clock_info(bank); stellaris_set_flash_mode(bank, 0); - fmppe = stellaris_info->lockbits; - for (lockregion = first; lockregion <= last; lockregion++) - { - if (set) - fmppe &= ~(1 << lockregion); - else - fmppe |= (1 << lockregion); + /* convert from pages to lockregions */ + first /= 2; + last /= 2; + + /* FIXME this assumes single FMPPE, for a max of 64K of flash!! + * Current parts can be much bigger. + */ + if (last >= 32) { + LOG_ERROR("No support yet for protection > 64K"); + return ERROR_FLASH_OPERATION_FAILED; } + target_read_u32(target, SCB_BASE | FMPPE, &fmppe); + + for (lockregion = first; lockregion <= last; lockregion++) + fmppe &= ~(1 << lockregion); + /* Clear and disable flash programming interrupts */ target_write_u32(target, FLASH_CIM, 0); target_write_u32(target, FLASH_MISC, PMISC | AMISC); LOG_DEBUG("fmppe 0x%" PRIx32 "",fmppe); target_write_u32(target, SCB_BASE | FMPPE, fmppe); + /* Commit FMPPE */ target_write_u32(target, FLASH_FMA, 1); + /* Write commit command */ - /* TODO safety check, sice this cannot be undone */ + /* REVISIT safety check, since this cannot be undone + * except by the "Recover a locked device" procedure. + */ LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !"); /* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */ + /* Wait until erase complete */ do { @@ -785,12 +826,10 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la return ERROR_FLASH_OPERATION_FAILED; } - target_read_u32(target, SCB_BASE | FMPPE, &stellaris_info->lockbits); - return ERROR_OK; } -static uint8_t stellaris_write_code[] = +static const uint8_t stellaris_write_code[] = { /* Call with : @@ -827,10 +866,11 @@ static uint8_t stellaris_write_code[] = /* pFLASH_CTRL_BASE: */ 0x00,0xD0,0x0F,0x40, /* .word 0x400FD000 */ /* FLASHWRITECMD: */ - 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */ + 0x01,0x00,0x42,0xA4 /* .word 0xA4420001 */ }; -static int stellaris_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t wcount) +static int stellaris_write_block(struct flash_bank *bank, + uint8_t *buffer, uint32_t offset, uint32_t wcount) { struct target *target = bank->target; uint32_t buffer_size = 8192; @@ -851,7 +891,9 @@ static int stellaris_write_block(struct flash_bank *bank, uint8_t *buffer, uint3 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; }; - target_write_buffer(target, write_algorithm->address, sizeof(stellaris_write_code), stellaris_write_code); + target_write_buffer(target, write_algorithm->address, + sizeof(stellaris_write_code), + (uint8_t *) stellaris_write_code); /* memory buffer */ while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) @@ -1182,15 +1224,15 @@ static const struct command_registration stellaris_command_handlers[] = { }; struct flash_driver stellaris_flash = { - .name = "stellaris", - .commands = stellaris_command_handlers, - .flash_bank_command = &stellaris_flash_bank_command, - .erase = &stellaris_erase, - .protect = &stellaris_protect, - .write = &stellaris_write, - .probe = &stellaris_probe, - .auto_probe = &stellaris_auto_probe, - .erase_check = &default_flash_mem_blank_check, - .protect_check = &stellaris_protect_check, - .info = &stellaris_info, - }; + .name = "stellaris", + .commands = stellaris_command_handlers, + .flash_bank_command = stellaris_flash_bank_command, + .erase = stellaris_erase, + .protect = stellaris_protect, + .write = stellaris_write, + .probe = stellaris_probe, + .auto_probe = stellaris_auto_probe, + .erase_check = default_flash_mem_blank_check, + .protect_check = stellaris_protect_check, + .info = stellaris_info, +}; diff --git a/src/flash/nor/stellaris.h b/src/flash/nor/stellaris.h index a5f04e4..4de4f00 100644 --- a/src/flash/nor/stellaris.h +++ b/src/flash/nor/stellaris.h @@ -39,7 +39,6 @@ struct stellaris_flash_bank /* nv memory bits */ uint16_t num_lockbits; - uint32_t lockbits; /* main clock status */ uint32_t rcc; @@ -67,8 +66,14 @@ struct stellaris_flash_bank #define PLLCFG 0x064 #define RCC2 0x070 +/* "legacy" flash memory protection registers (64KB max) */ #define FMPRE 0x130 #define FMPPE 0x134 + +/* new flash memory protection registers (for more than 64KB) */ +#define FMPRE0 0x200 /* PRE1 = PRE0 + 4, etc */ +#define FMPPE0 0x400 /* PPE1 = PPE0 + 4, etc */ + #define USECRL 0x140 #define FLASH_CONTROL_BASE 0x400FD000 @@ -94,4 +99,8 @@ struct stellaris_flash_bank /* STELLARIS constants */ +/* values to write in FMA to commit write-"once" values */ +#define FLASH_FMA_PRE(x) (2 * (x)) /* for FMPPREx */ +#define FLASH_FMA_PPE(x) (2 * (x) + 1) /* for FMPPPEx */ + #endif /* STELLARIS_H */ ----------------------------------------------------------------------- Summary of changes: src/flash/nor/stellaris.c | 176 ++++++++++++++++++++++++++++----------------- src/flash/nor/stellaris.h | 11 +++- 2 files changed, 119 insertions(+), 68 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: David B. <dbr...@us...> - 2009-12-09 19:26:15
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 910dd664ceb6faef5e9029e9b0848d7ccc63bf4b (commit) from 26d7ed08f9ff220be583179fdea76466739cf32d (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 910dd664ceb6faef5e9029e9b0848d7ccc63bf4b Author: David Brownell <dbr...@us...> Date: Wed Dec 9 10:25:08 2009 -0800 Comment and doxygen fixes Signed-off-by: David Brownell <dbr...@us...> diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h index 545a731..fe73e90 100644 --- a/src/flash/nand/driver.h +++ b/src/flash/nand/driver.h @@ -86,7 +86,7 @@ struct nand_flash_controller /** * Find a NAND flash controller by name. - * @param The name of the NAND controller to find. + * @param name Identifies the NAND controller to find. * @returns The nand_flash_controller named @c name, or NULL if not found. */ struct nand_flash_controller *nand_driver_find_by_name(const char *name); diff --git a/src/flash/nor/imp.h b/src/flash/nor/imp.h index 4c849fe..34ccbe4 100644 --- a/src/flash/nor/imp.h +++ b/src/flash/nor/imp.h @@ -22,14 +22,12 @@ // this is an internal header #include "core.h" #include "driver.h" -// common flash internals -#include <flash/common.h> // almost all drivers will need this file #include <target/target.h> /** * Adds a new NOR bank to the global list of banks. - * @params bank The bank that should be added. + * @param bank The bank that should be added. */ void flash_bank_add(struct flash_bank *bank); diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h index fece652..fa2fcdc 100644 --- a/src/jtag/jtag.h +++ b/src/jtag/jtag.h @@ -417,24 +417,9 @@ typedef void (*jtag_callback1_t)(jtag_callback_data_t data0); void jtag_add_callback(jtag_callback1_t, jtag_callback_data_t data0); - -/** - * Defines the interface of the JTAG callback mechanism. - * - * @param in the pointer to the data clocked in - * @param data1 An integer big enough to use as an @c int or a pointer. - * @param data2 An integer big enough to use as an @c int or a pointer. - * @param data3 An integer big enough to use as an @c int or a pointer. - * @returns an error code - */ -typedef int (*jtag_callback_t)(jtag_callback_data_t data0, - jtag_callback_data_t data1, - jtag_callback_data_t data2, - jtag_callback_data_t data3); - - /** - * This callback can be executed immediately the queue has been flushed. + * Defines the interface of the JTAG callback mechanism. Such + * callbacks can be executed once the queue has been flushed. * * The JTAG queue can be executed synchronously or asynchronously. * Typically for USB, the queue is executed asynchronously. For @@ -448,19 +433,21 @@ typedef int (*jtag_callback_t)(jtag_callback_data_t data0, * * If the execution of the queue fails before the callbacks, then -- * depending on driver implementation -- the callbacks may or may not be - * invoked. @todo Can we make this behavior consistent? + * invoked. * - * The strange name is due to C's lack of overloading using function - * arguments. + * @todo Make that behavior consistent. * - * @param f The callback function to add. * @param data0 Typically used to point to the data to operate on. * Frequently this will be the data clocked in during a shift operation. * @param data1 An integer big enough to use as an @c int or a pointer. * @param data2 An integer big enough to use as an @c int or a pointer. * @param data3 An integer big enough to use as an @c int or a pointer. - * + * @returns an error code */ +typedef int (*jtag_callback_t)(jtag_callback_data_t data0, + jtag_callback_data_t data1, + jtag_callback_data_t data2, + jtag_callback_data_t data3); /** * Run a TAP_RESET reset where the end state is TAP_RESET, diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index b3b5143..58498ac 100644 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -26,6 +26,11 @@ #ifndef __ARM_OPCODES_H #define __ARM_OPCODES_H +/** + * @file + * Macros used to generate various ARM or Thumb opcodes. + */ + /* ARM mode instructions */ /* Store multiple increment after @@ -145,9 +150,13 @@ /* Thumb mode instructions * - * FIXME there must be some reason all these opcodes are 32-bits - * not 16-bits ... this should get either an explanatory comment, - * or be changed not to duplicate the opcode. + * NOTE: these 16-bit opcodes fill both halves of a word with the same + * value. The reason for this is that when we need to execute Thumb + * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry), + * we must shift 32 bits to the bus using scan chain 1 ... if we write + * both halves, we don't need to track which half matters. On ARMv6 and + * ARMv7 we don't execute Thumb instructions in debug mode; the ITR + * register does not accept Thumb (or Thumb2) opcodes. */ /* Store register (Thumb mode) diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index eb04bd1..a705d7d 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -35,7 +35,8 @@ * * This provides lowlevel glue to the EmbeddedICE (or EmbeddedICE-RT) * module found on scan chain 2 in ARM7, ARM9, and some other families - * of ARM cores. + * of ARM cores. The module is called "EmbeddedICE-RT" if it has + * monitor mode support. * * EmbeddedICE provides basic watchpoint/breakpoint hardware and a Debug * Communications Channel (DCC) used to read or write 32-bit words to ----------------------------------------------------------------------- Summary of changes: src/flash/nand/driver.h | 2 +- src/flash/nor/imp.h | 4 +--- src/jtag/jtag.h | 31 +++++++++---------------------- src/target/arm_opcodes.h | 15 ++++++++++++--- src/target/embeddedice.c | 3 ++- 5 files changed, 25 insertions(+), 30 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Spencer O. <nt...@us...> - 2009-12-09 11:36:20
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 26d7ed08f9ff220be583179fdea76466739cf32d (commit) from 733ced125ae5434818a50151b15f78fd5b514807 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 26d7ed08f9ff220be583179fdea76466739cf32d Author: Spencer Oliver <nt...@us...> Date: Wed Dec 9 10:35:30 2009 +0000 ETM: only include oocd_trace.h when tracing enabled. Fixes build issue on systems that do not have <termios.h>, eg native win32. Signed-off-by: Spencer Oliver <nt...@us...> diff --git a/src/target/etm.c b/src/target/etm.c index e0671d5..9cb647c 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -28,7 +28,10 @@ #include "arm_disassembler.h" #include "register.h" #include "etm_dummy.h" + +#if BUILD_OOCD_TRACE == 1 #include "oocd_trace.h" +#endif /* ----------------------------------------------------------------------- Summary of changes: src/target/etm.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) hooks/post-receive -- Main OpenOCD repository |
From: Øyvind H. <go...@us...> - 2009-12-08 22:59:01
|
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "Main OpenOCD repository". The branch, master has been updated via 733ced125ae5434818a50151b15f78fd5b514807 (commit) from f0da635e554704f96b676406f433739a196afacd (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log ----------------------------------------------------------------- commit 733ced125ae5434818a50151b15f78fd5b514807 Author: Rafael Campos Las Heras <me...@gm...> Date: Tue Dec 8 20:25:50 2009 +0100 Fix compilation error with gcc 4.4.1 Signed-off-by: Rafael Campos Las Heras <me...@gm...> diff --git a/src/jtag/drivers/bitq.c b/src/jtag/drivers/bitq.c index d04a39e..bffc475 100644 --- a/src/jtag/drivers/bitq.c +++ b/src/jtag/drivers/bitq.c @@ -21,6 +21,7 @@ #include "config.h" #endif +#include <jtag/jtag.h> #include "bitq.h" #include <jtag/interface.h> ----------------------------------------------------------------------- Summary of changes: src/jtag/drivers/bitq.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) hooks/post-receive -- Main OpenOCD repository |