openocd-commit — OpenOCD commit maling list - read only

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-909-gf0da635

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit f0da635e554704f96b676406f433739a196afacd
Author: David Brownell <dbr...@us...>
Date:   Tue Dec 8 13:09:38 2009 -0800

    target: remove more exit() calls
    
    These were all basically "can't happen" cases ... like having
    state be corrupted by an alpha particle after the previous check
    for whether a value was in-range.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 5563a4e..280704e 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2362,10 +2362,6 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
 				}
 			}
 			break;
-		default:
-			LOG_ERROR("BUG: we shouldn't get here");
-			exit(-1);
-			break;
 	}
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -2546,10 +2542,6 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 				num_accesses += thisrun_accesses;
 			}
 			break;
-		default:
-			LOG_ERROR("BUG: we shouldn't get here");
-			exit(-1);
-			break;
 	}
 
 	/* Re-Set DBGACK */
diff --git a/src/target/target.c b/src/target/target.c
index a9f4dd8..70130d9 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2154,8 +2154,9 @@ static void handle_md_output(struct command_context *cmd_ctx,
 	case 2: value_fmt = "%4.2x "; break;
 	case 1: value_fmt = "%2.2x "; break;
 	default:
+		/* "can't happen", caller checked */
 		LOG_ERROR("invalid memory read size: %u", size);
-		exit(-1);
+		return;
 	}
 
 	for (unsigned i = 0; i < count; i++)

commit cbea1ed71febd8cf64482b36381765eaabfc66ec
Author: David Brownell <dbr...@us...>
Date:   Tue Dec 8 13:06:41 2009 -0800

    target: remove needless "extern"s
    
    Most of these happened to be in the target.h file.
    
    Some of those are associated with symbols that could be
    removed at some point ... e.g. NVP_ASSERT/true and its
    sibling NVP_DEASSERT/false.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_a8.h b/src/target/cortex_a8.h
index adffe93..82a34a7 100644
--- a/src/target/cortex_a8.h
+++ b/src/target/cortex_a8.h
@@ -31,8 +31,6 @@
 
 #include <target/armv7a.h>
 
-extern char* cortex_a8_state_strings[];
-
 #define CORTEX_A8_COMMON_MAGIC 0x411fc082
 
 /* See Cortex-A8 TRM section 12.5 */
diff --git a/src/target/etm.c b/src/target/etm.c
index 3aace81..e0671d5 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -27,6 +27,8 @@
 #include "image.h"
 #include "arm_disassembler.h"
 #include "register.h"
+#include "etm_dummy.h"
+#include "oocd_trace.h"
 
 
 /*
@@ -613,13 +615,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 }
 
 
-/* ETM trace analysis functionality
- *
- */
-extern struct etm_capture_driver etm_dummy_capture_driver;
-#if BUILD_OOCD_TRACE == 1
-extern struct etm_capture_driver oocd_trace_capture_driver;
-#endif
+/* ETM trace analysis functionality */
 
 static struct etm_capture_driver *etm_capture_drivers[] =
 {
diff --git a/src/target/target.c b/src/target/target.c
index f249d38..a9f4dd8 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -90,7 +90,7 @@ struct target *all_targets = NULL;
 struct target_event_callback *target_event_callbacks = NULL;
 struct target_timer_callback *target_timer_callbacks = NULL;
 
-const Jim_Nvp nvp_assert[] = {
+static const Jim_Nvp nvp_assert[] = {
 	{ .name = "assert", NVP_ASSERT },
 	{ .name = "deassert", NVP_DEASSERT },
 	{ .name = "T", NVP_ASSERT },
@@ -100,7 +100,7 @@ const Jim_Nvp nvp_assert[] = {
 	{ .name = NULL, .value = -1 }
 };
 
-const Jim_Nvp nvp_error_target[] = {
+static const Jim_Nvp nvp_error_target[] = {
 	{ .value = ERROR_TARGET_INVALID, .name = "err-invalid" },
 	{ .value = ERROR_TARGET_INIT_FAILED, .name = "err-init-failed" },
 	{ .value = ERROR_TARGET_TIMEOUT, .name = "err-timeout" },
@@ -178,7 +178,7 @@ static const Jim_Nvp nvp_target_event[] = {
 	{ .name = NULL, .value = -1 }
 };
 
-const Jim_Nvp nvp_target_state[] = {
+static const Jim_Nvp nvp_target_state[] = {
 	{ .name = "unknown", .value = TARGET_UNKNOWN },
 	{ .name = "running", .value = TARGET_RUNNING },
 	{ .name = "halted",  .value = TARGET_HALTED },
@@ -198,7 +198,7 @@ static const Jim_Nvp nvp_target_debug_reason [] = {
 	{ .name = NULL, .value = -1 },
 };
 
-const Jim_Nvp nvp_target_endian[] = {
+static const Jim_Nvp nvp_target_endian[] = {
 	{ .name = "big",    .value = TARGET_BIG_ENDIAN },
 	{ .name = "little", .value = TARGET_LITTLE_ENDIAN },
 	{ .name = "be",     .value = TARGET_BIG_ENDIAN },
@@ -206,7 +206,7 @@ const Jim_Nvp nvp_target_endian[] = {
 	{ .name = NULL,     .value = -1 },
 };
 
-const Jim_Nvp nvp_reset_modes[] = {
+static const Jim_Nvp nvp_reset_modes[] = {
 	{ .name = "unknown", .value = RESET_UNKNOWN },
 	{ .name = "run"    , .value = RESET_RUN },
 	{ .name = "halt"   , .value = RESET_HALT },
diff --git a/src/target/target.h b/src/target/target.h
index dd3d4f7..fededb9 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -61,15 +61,11 @@ enum target_state
 	TARGET_DEBUG_RUNNING = 4,
 };
 
-extern const Jim_Nvp nvp_target_state[];
-
 enum nvp_assert {
 	NVP_DEASSERT,
 	NVP_ASSERT,
 };
 
-extern const Jim_Nvp nvp_assert[];
-
 enum target_reset_mode
 {
 	RESET_UNKNOWN = 0,
@@ -78,8 +74,6 @@ enum target_reset_mode
 	RESET_INIT = 3,		/* reset and halt target out of reset, then run init script */
 };
 
-extern const Jim_Nvp nvp_reset_mode[];
-
 enum target_debug_reason
 {
 	DBG_REASON_DBGRQ = 0,
@@ -97,8 +91,6 @@ enum target_endianess
 	TARGET_BIG_ENDIAN = 1, TARGET_LITTLE_ENDIAN = 2
 };
 
-extern const Jim_Nvp nvp_target_endian[];
-
 struct working_area
 {
 	uint32_t address;
@@ -490,8 +482,6 @@ void target_all_handle_event(enum target_event e);
 #define ERROR_TARGET_NOT_RUNNING (-310)
 #define ERROR_TARGET_NOT_EXAMINED (-311)
 
-extern const Jim_Nvp nvp_error_target[];
-
 const char *target_strerror_safe(int err);
 
 #endif /* TARGET_H */

commit e7acbdf5dbfcea427fc8b0fc7e8dd2e1005a4cc8
Author: David Brownell <dbr...@us...>
Date:   Tue Dec 8 13:06:41 2009 -0800

    target: move 'extern' decls to *.h files
    
    The exception being declarations for drivers.  Those should
    be split out in some clean way -- like driver add/remove calls
    made by initialization code -- but that's for another day.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm.h b/src/target/arm.h
index 00dbe2d..36763b4 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -191,6 +191,13 @@ int armv4_5_run_algorithm(struct target *target,
 		int num_reg_params, struct reg_param *reg_params,
 		uint32_t entry_point, uint32_t exit_point,
 		int timeout_ms, void *arch_info);
+int armv4_5_run_algorithm_inner(struct target *target,
+		int num_mem_params, struct mem_param *mem_params,
+		int num_reg_params, struct reg_param *reg_params,
+		uint32_t entry_point, uint32_t exit_point,
+		int timeout_ms, void *arch_info,
+		int (*run_it)(struct target *target, uint32_t exit_point,
+				int timeout_ms, void *arch_info));
 
 int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum);
@@ -200,6 +207,8 @@ int arm_blank_check_memory(struct target *target,
 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 
+void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
+
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;
 
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 64a99fb..5563a4e 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2652,14 +2652,6 @@ static const uint32_t dcc_code[] =
 	0xeafffff9	/*    b   w                   */
 };
 
-extern int armv4_5_run_algorithm_inner(struct target *target,
-	int num_mem_params, struct mem_param *mem_params,
-	int num_reg_params, struct reg_param *reg_params,
-	uint32_t entry_point, uint32_t exit_point,
-	int timeout_ms, void *arch_info,
-	int (*run_it)(struct target *target, uint32_t exit_point,
-			int timeout_ms, void *arch_info));
-
 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
 	int retval;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 301412c..0e99cd1 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -269,8 +269,6 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	return ERROR_OK;
 }
 
-extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
-
 static int arm9endianness(jtag_callback_data_t arg,
 	jtag_callback_data_t size, jtag_callback_data_t be,
 	jtag_callback_data_t captured)
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index f662e16..07090b4 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -34,6 +34,12 @@
 #define ARMV7_GDB_HACKS
 #endif
 
+#ifdef ARMV7_GDB_HACKS
+extern uint8_t armv7m_gdb_dummy_cpsr_value[];
+extern struct reg armv7m_gdb_dummy_cpsr_reg;
+#endif
+
+
 enum armv7m_mode
 {
 	ARMV7M_MODE_THREAD = 0,
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index bdd3233..6bc427a 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -52,11 +52,6 @@ static void cortex_m3_enable_watchpoints(struct target *target);
 static int cortex_m3_store_core_reg_u32(struct target *target,
 		enum armv7m_regtype type, uint32_t num, uint32_t value);
 
-#ifdef ARMV7_GDB_HACKS
-extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern struct reg armv7m_gdb_dummy_cpsr_reg;
-#endif
-
 static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
 		uint32_t *value, int regnum)
 {

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm.h           |    9 +++++++++
 src/target/arm7_9_common.c |   16 ----------------
 src/target/arm9tdmi.c      |    2 --
 src/target/armv7m.h        |    6 ++++++
 src/target/cortex_a8.h     |    2 --
 src/target/cortex_m3.c     |    5 -----
 src/target/etm.c           |   10 +++-------
 src/target/target.c        |   13 +++++++------
 src/target/target.h        |   10 ----------
 9 files changed, 25 insertions(+), 48 deletions(-)


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Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-906-gac19fc0

[David B. <dbr...@us...>]

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The branch, master has been updated
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      from  96d2b61c049773c02a41b220a0104d24c75fd284 (commit)

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- Log -----------------------------------------------------------------
commit ac19fc0da7e9b5542d5bcb9d6a6370efdeb2f1ee
Author: David Brownell <dbr...@us...>
Date:   Tue Dec 8 02:00:35 2009 -0800

    ARM: cygwin complile fixes
    
    It's as if despite integers being 32-bits, GCC refuses to
    convert a "uint32_t" to one of them.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 407d290..5c8ad6a 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -158,14 +158,16 @@ static int evaluate_srs(uint32_t opcode,
 				"\t0x%8.8" PRIx32
 				"\tSRS%s\tSP%s, #%d",
 				address, opcode,
-				mode, wback, opcode & 0x1f);
+				mode, wback,
+				(unsigned)(opcode & 0x1f));
 		break;
 	case 0x08100000:
 		snprintf(instruction->text, 128, "0x%8.8" PRIx32
 				"\t0x%8.8" PRIx32
 				"\tRFE%s\tr%d%s",
 				address, opcode,
-				mode, (opcode >> 16) & 0xf, wback);
+				mode,
+				(unsigned)((opcode >> 16) & 0xf), wback);
 		break;
 	default:
 		return evaluate_unknown(opcode, address, instruction);
@@ -3467,14 +3469,14 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
 	case 6:
 		sprintf(cp, "SRS%s\tsp%s, #%d", mode,
 				t ? "!" : "",
-				opcode & 0x1f);
+				(unsigned) (opcode & 0x1f));
 		return ERROR_OK;
 	case 1:
 		mode = "DB";
 		/* FALL THROUGH */
 	case 7:
 		sprintf(cp, "RFE%s\tr%d%s", mode,
-				(opcode >> 16) & 0xf,
+				(unsigned) ((opcode >> 16) & 0xf),
 				t ? "!" : "");
 		return ERROR_OK;
 	case 2:

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_disassembler.c |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-905-g96d2b61

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
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      from  97de520bc02f96f31063175fbc9cad034e84055d (commit)

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- Log -----------------------------------------------------------------
commit 96d2b61c049773c02a41b220a0104d24c75fd284
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Dec 8 10:40:47 2009 +0100

    zy1000: some background info on the zy1000 file.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 5b6e4ea..5ddc7c5 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -16,6 +16,31 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
+/* This file supports the zy1000 debugger: http://www.zylin.com/zy1000.html
+ *
+ * The zy1000 is a standalone debugger that has a web interface and
+ * requires no drivers on the developer host as all communication
+ * is via TCP/IP. The zy1000 gets it performance(~400-700kBytes/s
+ * DCC downloads @ 16MHz target) as it has an FPGA to hardware
+ * accelerate the JTAG commands, while offering *very* low latency
+ * between OpenOCD and the FPGA registers.
+ *
+ * The disadvantage of the zy1000 is that it has a feeble CPU compared to
+ * a PC(ca. 50-500 DMIPS depending on how one counts it), whereas a PC
+ * is on the order of 10000 DMIPS(i.e. at a factor of 20-200).
+ *
+ * The zy1000 revc hardware is using an Altera Nios CPU, whereas the
+ * revb is using ARM7 + Xilinx.
+ *
+ * See Zylin web pages or contact Zylin for more information.
+ *
+ * The reason this code is in OpenOCD rather than OpenOCD linked with the
+ * ZY1000 code is that OpenOCD is the long road towards getting
+ * libopenocd into place. libopenocd will support both low performance,
+ * low latency systems(embedded) and high performance high latency
+ * systems(PCs).
+ */
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/zy1000/zy1000.c |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)


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[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit 97de520bc02f96f31063175fbc9cad034e84055d
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Dec 4 16:00:43 2009 +0100

    minidriver: fix inline capability of minidriver
    
    Low latency low CPU processing power systems(embedded)
    will benefit greatly from being able to inline certain
    jtag_add_xxx() fn's. The trick is that this has to be
    done in such a way as to allow implementing an OpenOCD
    API with a shared library(eventually) on a PC hosted
    OpenOCD.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/.gitignore b/.gitignore
index 114fc05..9928129 100644
--- a/.gitignore
+++ b/.gitignore
@@ -10,6 +10,10 @@
 *.la
 *.in
 
+# generated source files
+src/jtag/minidriver_imp.h
+src/jtag/jtag_minidriver.h
+
 # editor files
 *.swp
 
diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am
index da2eddd..3f132d4 100644
--- a/src/jtag/Makefile.am
+++ b/src/jtag/Makefile.am
@@ -9,33 +9,49 @@ SUBDIRS =
 DRIVERFILES =
 libjtag_la_LIBADD =
 
-if MINIDRIVER
+CLEANFILES =
+
+BUILT_SOURCES =
+
+BUILT_SOURCES += minidriver_imp.h
+CLEANFILES += minidriver_imp.h
 
-# for minidriver_imp.h
-AM_CPPFLAGS += -I$(srcdir)/minidriver
+if MINIDRIVER
 
 if ZY1000
 DRIVERFILES += zy1000/zy1000.c
-AM_CPPFLAGS += -I$(srcdir)/zy1000
+JTAG_MINIDRIVER_DIR = $(srcdir)/zy1000
 endif
 if MINIDRIVER_DUMMY
 DRIVERFILES += minidummy/minidummy.c commands.c
-AM_CPPFLAGS += -I$(srcdir)/minidummy
+JTAG_MINIDRIVER_DIR = $(srcdir)/minidummy
 endif
 
+MINIDRIVER_IMP_DIR = $(srcdir)/minidriver
+
+jtag_minidriver.h: $(JTAG_MINIDRIVER_DIR)/jtag_minidriver.h
+	cp $< $@
+
+BUILT_SOURCES += jtag_minidriver.h
+
+CLEANFILES += jtag_minidriver.h
+
 else
 
+MINIDRIVER_IMP_DIR = $(srcdir)/drivers
 DRIVERFILES += commands.c
 
 SUBDIRS += drivers
 libjtag_la_LIBADD += $(top_builddir)/src/jtag/drivers/libocdjtagdrivers.la
 
-# for minidriver_imp.h
-AM_CPPFLAGS += -I$(srcdir)/drivers
-
 endif
+
 # endif // MINIDRIVER
 
+minidriver_imp.h: $(MINIDRIVER_IMP_DIR)/minidriver_imp.h
+	cp $< $@
+
+
 libjtag_la_SOURCES = \
 	core.c \
 	interface.c \
diff --git a/src/jtag/commands.c b/src/jtag/commands.c
index 4e8ce40..6951f03 100644
--- a/src/jtag/commands.c
+++ b/src/jtag/commands.c
@@ -31,6 +31,7 @@
 #include "config.h"
 #endif
 
+#include <jtag/jtag.h>
 #include "commands.h"
 
 struct cmd_queue_page {
diff --git a/src/jtag/commands.h b/src/jtag/commands.h
index 86ded15..b10b545 100644
--- a/src/jtag/commands.h
+++ b/src/jtag/commands.h
@@ -26,8 +26,6 @@
 #ifndef JTAG_COMMANDS_H
 #define JTAG_COMMANDS_H
 
-#include <jtag/jtag.h>
-
 /**
  * The inferred type of a scan_command_s structure, indicating whether
  * the command has the host scan in from the device, the host scan out
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 373dd7e..77cf48a 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -32,7 +32,6 @@
 #endif
 
 #include "jtag.h"
-#include "minidriver.h"
 #include "interface.h"
 
 #ifdef HAVE_STRINGS_H
@@ -398,18 +397,6 @@ void jtag_add_plain_ir_scan(int in_num_fields, const struct scan_field *in_field
 	jtag_set_error(retval);
 }
 
-void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
-{
-	interface_jtag_add_callback(f, data0);
-}
-
-void jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0,
-		jtag_callback_data_t data1, jtag_callback_data_t data2,
-		jtag_callback_data_t data3)
-{
-	interface_jtag_add_callback4(f, data0, data1, data2, data3);
-}
-
 static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value,
 		uint8_t *in_check_mask, int num_bits);
 
@@ -491,20 +478,6 @@ void jtag_add_plain_dr_scan(int in_num_fields, const struct scan_field *in_field
 	jtag_set_error(retval);
 }
 
-void jtag_add_dr_out(struct jtag_tap* tap,
-		int num_fields, const int* num_bits, const uint32_t* value,
-		tap_state_t end_state)
-{
-	assert(end_state != TAP_RESET);
-	assert(end_state != TAP_INVALID);
-
-	cmd_queue_cur_state = end_state;
-
-	interface_jtag_add_dr_out(tap,
-			num_fields, num_bits, value,
-			end_state);
-}
-
 void jtag_add_tlr(void)
 {
 	jtag_prelude(TAP_RESET);
diff --git a/src/jtag/drivers/driver.c b/src/jtag/drivers/driver.c
index 7fa9ead..c57386a 100644
--- a/src/jtag/drivers/driver.c
+++ b/src/jtag/drivers/driver.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2009 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2009 SoftPLC Corporation                                *
@@ -31,7 +31,9 @@
 #include "config.h"
 #endif
 
+#include <jtag/jtag.h>
 #include <jtag/interface.h>
+#include <jtag/commands.h>
 #include <jtag/minidriver.h>
 #include <helper/command.h>
 
@@ -525,3 +527,30 @@ void interface_jtag_add_callback(jtag_callback1_t callback, jtag_callback_data_t
 	jtag_add_callback4(jtag_convert_to_callback4, data0, (jtag_callback_data_t)callback, 0, 0);
 }
 
+
+/* A minidriver can use use an inline versions of this API level fn */
+void jtag_add_dr_out(struct jtag_tap* tap,
+		int num_fields, const int* num_bits, const uint32_t* value,
+		tap_state_t end_state)
+{
+	assert(end_state != TAP_RESET);
+	assert(end_state != TAP_INVALID);
+
+	cmd_queue_cur_state = end_state;
+
+	interface_jtag_add_dr_out(tap,
+			num_fields, num_bits, value,
+			end_state);
+}
+
+void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0)
+{
+	interface_jtag_add_callback(f, data0);
+}
+
+void jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0,
+		jtag_callback_data_t data1, jtag_callback_data_t data2,
+		jtag_callback_data_t data3)
+{
+	interface_jtag_add_callback4(f, data0, data1, data2, data3);
+}
diff --git a/src/jtag/drivers/minidriver_imp.h b/src/jtag/drivers/minidriver_imp.h
index 1efd242..76cf9dd 100644
--- a/src/jtag/drivers/minidriver_imp.h
+++ b/src/jtag/drivers/minidriver_imp.h
@@ -1,6 +1,6 @@
 /***************************************************************************
  *   Copyright (C) 2005 by Dominic Rath <Dom...@gm...>              *
- *   Copyright (C) 2007,2008 Øyvind Harboe <oyv...@zy...>       *
+ *   Copyright (C) 2007-2009 Øyvind Harboe <oyv...@zy...>       *
  *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -44,4 +44,13 @@ void interface_jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0,
 		jtag_callback_data_t data1, jtag_callback_data_t data2,
 		jtag_callback_data_t data3);
 
+void jtag_add_dr_out(struct jtag_tap* tap,
+		int num_fields, const int* num_bits, const uint32_t* value,
+		tap_state_t end_state);
+
+
+void jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0,
+		jtag_callback_data_t data1, jtag_callback_data_t data2,
+		jtag_callback_data_t data3);
+
 #endif // MINIDRIVER_IMP_H
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index eaa0c7c..fece652 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -461,10 +461,6 @@ typedef int (*jtag_callback_t)(jtag_callback_data_t data0,
  * @param data3 An integer big enough to use as an @c int or a pointer.
  *
  */
-void jtag_add_callback4(jtag_callback_t f, jtag_callback_data_t data0,
-		jtag_callback_data_t data1, jtag_callback_data_t data2,
-		jtag_callback_data_t data3);
-
 
 /**
  * Run a TAP_RESET reset where the end state is TAP_RESET,
@@ -688,9 +684,6 @@ void jtag_sleep(uint32_t us);
  * There is no jtag_add_dr_outin() version of this fn that also allows
  * clocking data back in. Patches gladly accepted!
  */
-void jtag_add_dr_out(struct jtag_tap* tap,
-		int num_fields, const int* num_bits, const uint32_t* value,
-		tap_state_t end_state);
 
 
 /**
@@ -725,4 +718,9 @@ bool jtag_poll_get_enabled(void);
  */
 void jtag_poll_set_enabled(bool value);
 
+
+/* The minidriver may have inline versions of some of the low
+ * level APIs that are used in inner loops. */
+#include <jtag/minidriver.h>
+
 #endif /* JTAG_H */
diff --git a/src/jtag/minidriver.h b/src/jtag/minidriver.h
index ea780fa..2109c75 100644
--- a/src/jtag/minidriver.h
+++ b/src/jtag/minidriver.h
@@ -47,7 +47,7 @@
 
 // this header will be provided by the minidriver implementation,
 // and it may provide additional declarations that must be defined.
-#include "minidriver_imp.h"
+#include <jtag/minidriver_imp.h>
 
 int interface_jtag_add_ir_scan(
 		int num_fields, const struct scan_field* fields,
diff --git a/src/jtag/minidriver/minidriver_imp.h b/src/jtag/minidriver/minidriver_imp.h
index e371514..b6cdbea 100644
--- a/src/jtag/minidriver/minidriver_imp.h
+++ b/src/jtag/minidriver/minidriver_imp.h
@@ -21,7 +21,7 @@
 #ifndef MINIDRIVER_IMP_H
 #define MINIDRIVER_IMP_H
 
-#include "jtag_minidriver.h"
+#include <jtag/jtag_minidriver.h>
 
 static inline void interface_jtag_alloc_in_value32(struct scan_field *field)
 {
@@ -41,4 +41,21 @@ static inline void interface_jtag_add_scan_check_alloc(struct scan_field *field)
 		field->in_value = field->intmp;
 }
 
+static inline void jtag_add_dr_out(struct jtag_tap* tap,
+		int num_fields, const int* num_bits, const uint32_t* value,
+		tap_state_t end_state)
+{
+	cmd_queue_cur_state = end_state;
+
+	interface_jtag_add_dr_out(tap,
+			num_fields, num_bits, value,
+			end_state);
+}
+
+#define jtag_add_callback(callback, in) interface_jtag_add_callback(callback, in)
+
+#define jtag_add_callback4(callback, in, data1, data2, data3) interface_jtag_add_callback4(callback, in, data1, data2, data3)
+
+
+
 #endif // MINIDRIVER_IMP_H
diff --git a/src/jtag/minidummy/minidummy.c b/src/jtag/minidummy/minidummy.c
index e60e832..9c608cd 100644
--- a/src/jtag/minidummy/minidummy.c
+++ b/src/jtag/minidummy/minidummy.c
@@ -20,6 +20,7 @@
 #include "config.h"
 #endif
 
+#include <jtag/jtag.h>
 #include <target/embeddedice.h>
 #include <jtag/minidriver.h>
 #include <jtag/interface.h>

commit 304af6e7d87af60a4c807b940ff6102243d465a4
Author: Øyvind Harboe <oyv...@zy...>
Date:   Sat Dec 5 11:07:06 2009 +0100

    zy1000: remove unecessary include
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/ecosboard.c b/src/ecosboard.c
index 7d0c3d0..2e491c2 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -25,10 +25,6 @@
 #include <jtag/jtag.h>
 #include <helper/ioutil.h>
 #include <helper/configuration.h>
-#include <xsvf/xsvf.h>
-#include <svf/svf.h>
-#include <flash/nand.h>
-#include <pld/pld.h>
 
 #include <server/server.h>
 #include <server/telnet_server.h>

commit eb1bc657ae10f9e21304e068ca17dc0231a9b9c0
Author: Øyvind Harboe <oyv...@zy...>
Date:   Sat Dec 5 10:50:59 2009 +0100

    build: add build/src to include path
    
    This allows including generated include files.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/Makefile.am b/src/Makefile.am
index ea753bb..f60feac 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -32,7 +32,8 @@ noinst_HEADERS = \
 
 # set the include path found by configure
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 libopenocd_la_CPPFLAGS = -DPKGBLDDATE=\"`date +%F-%R`\"
 
diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index 646889e..9d983a8 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -3,7 +3,8 @@ SUBDIRS = \
 	nand
 
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libflash.la
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index a48b726..f3033b8 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -1,4 +1,6 @@
-AM_CPPFLAGS = -I$(top_srcdir)/src
+AM_CPPFLAGS = \
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 noinst_LTLIBRARIES = libocdflashnand.la
 
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index f185081..5d0a4df 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -1,4 +1,6 @@
-AM_CPPFLAGS = -I$(top_srcdir)/src
+AM_CPPFLAGS = \
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 noinst_LTLIBRARIES = libocdflashnor.la
 libocdflashnor_la_SOURCES = \
diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index 4f74b9a..244ada7 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -1,5 +1,6 @@
 AM_CPPFLAGS = \
 	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src \
 	-DPKGDATADIR=\"$(pkgdatadir)\"
 
 METASOURCES = AUTO
diff --git a/src/jtag/Makefile.am b/src/jtag/Makefile.am
index 39b4b59..da2eddd 100644
--- a/src/jtag/Makefile.am
+++ b/src/jtag/Makefile.am
@@ -1,5 +1,6 @@
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libjtag.la
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 92a96f3..8ee5ac5 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -1,4 +1,6 @@
-AM_CPPFLAGS = -I$(top_srcdir)/src
+AM_CPPFLAGS = \
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 noinst_LTLIBRARIES = libocdjtagdrivers.la
 
diff --git a/src/pld/Makefile.am b/src/pld/Makefile.am
index fa40e56..3993622 100644
--- a/src/pld/Makefile.am
+++ b/src/pld/Makefile.am
@@ -1,5 +1,6 @@
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libpld.la
diff --git a/src/server/Makefile.am b/src/server/Makefile.am
index de83a06..c6c946f 100644
--- a/src/server/Makefile.am
+++ b/src/server/Makefile.am
@@ -1,5 +1,6 @@
 AM_CPPFLAGS = \
 	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src \
 	-DPKGDATADIR=\"$(pkgdatadir)\"
 
 METASOURCES = AUTO
diff --git a/src/svf/Makefile.am b/src/svf/Makefile.am
index adc415f..398f967 100644
--- a/src/svf/Makefile.am
+++ b/src/svf/Makefile.am
@@ -1,5 +1,6 @@
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libsvf.la
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index f1d5d15..f1d4caa 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -6,7 +6,8 @@ OOCD_TRACE_FILES =
 endif
 
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 BIN2C		= $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
 
diff --git a/src/xsvf/Makefile.am b/src/xsvf/Makefile.am
index 3e2a04e..f96331c 100644
--- a/src/xsvf/Makefile.am
+++ b/src/xsvf/Makefile.am
@@ -1,5 +1,6 @@
 AM_CPPFLAGS = \
-	-I$(top_srcdir)/src
+	-I$(top_srcdir)/src \
+	-I$(top_builddir)/src
 
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libxsvf.la

-----------------------------------------------------------------------

Summary of changes:
 .gitignore                           |    4 +++
 src/Makefile.am                      |    3 +-
 src/ecosboard.c                      |    4 ---
 src/flash/Makefile.am                |    3 +-
 src/flash/nand/Makefile.am           |    4 ++-
 src/flash/nor/Makefile.am            |    4 ++-
 src/helper/Makefile.am               |    1 +
 src/jtag/Makefile.am                 |   35 +++++++++++++++++++++++++--------
 src/jtag/commands.c                  |    1 +
 src/jtag/commands.h                  |    2 -
 src/jtag/core.c                      |   27 --------------------------
 src/jtag/drivers/Makefile.am         |    4 ++-
 src/jtag/drivers/driver.c            |   31 +++++++++++++++++++++++++++++-
 src/jtag/drivers/minidriver_imp.h    |   11 +++++++++-
 src/jtag/jtag.h                      |   12 ++++------
 src/jtag/minidriver.h                |    2 +-
 src/jtag/minidriver/minidriver_imp.h |   19 +++++++++++++++++-
 src/jtag/minidummy/minidummy.c       |    1 +
 src/pld/Makefile.am                  |    3 +-
 src/server/Makefile.am               |    1 +
 src/svf/Makefile.am                  |    3 +-
 src/target/Makefile.am               |    3 +-
 src/xsvf/Makefile.am                 |    3 +-
 23 files changed, 119 insertions(+), 62 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-901-g456ec01

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  456ec016c2403ed95e0b8b33534ab53ed41d7c27 (commit)
      from  81aec6be045792f3ed6a2d8fdbf1f534993b5c14 (commit)

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- Log -----------------------------------------------------------------
commit 456ec016c2403ed95e0b8b33534ab53ed41d7c27
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 18:14:46 2009 -0800

    ARM: cope with stupidheaded compiler
    
    Some versions of GCC don't understand that if you mask with 0x3
    then have cases 0-3, it's not possible for a variable assigned in
    all those branches to have no value at end-of-case.  Feh.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index e76e385..407d290 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -135,7 +135,7 @@ static int evaluate_srs(uint32_t opcode,
 		uint32_t address, struct arm_instruction *instruction)
 {
 	const char *wback = (opcode & (1 << 21)) ? "!" : "";
-	const char *mode;
+	const char *mode = "";
 
 	switch ((opcode >> 23) & 0x3) {
 	case 0:
@@ -143,7 +143,6 @@ static int evaluate_srs(uint32_t opcode,
 		break;
 	case 1:
 		/* "IA" is default */
-		mode = "";
 		break;
 	case 2:
 		mode = "DB";

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_disassembler.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)


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The branch, master has been updated
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      from  30a6e683b85291b8248a2f6189aa292fdf43162d (commit)

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- Log -----------------------------------------------------------------
commit 81aec6be045792f3ed6a2d8fdbf1f534993b5c14
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:08 2009 -0800

    ARM: list number of HW breakpoints/watchpoints
    
    When starting up, say how many hardware breakpoints and watchpoints
    are available on various targets.
    
    This makes it easier to tell GDB how many of those resources exist.
    Its remote protocol currently has no way to ask OpenOCD for that
    information, so it must configured by hand (or not at all).
    
    Update the docs to mention this; remove obsolete "don't do this" info.
    Presentation of GDB setup information is still a mess, but at least
    it calls out the three components that need setup.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ef395ea..a83c966 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6497,6 +6497,21 @@ a bit of googling to find something that fits your requirements.
 @cindex GDB
 OpenOCD complies with the remote gdbserver protocol, and as such can be used
 to debug remote targets.
+Setting up GDB to work with OpenOCD can involve several components:
+
+@itemize
+@item OpenOCD itself may need to be configured.  @xref{GDB Configuration}.
+@item GDB itself may need configuration, as shown in this chapter.
+@item If you have a GUI environment like Eclipse,
+that also will probably need to be configured.
+@end itemize
+
+Of course, the version of GDB you use will need to be one which has
+been built to know about the target CPU you're using.  It's probably
+part of the tool chain you're using.  For example, if you are doing
+cross-development for ARM on an x86 PC, instead of using the native
+x86 @command{gdb} command you might use @command{arm-none-eabi-gdb}
+if that's the tool chain used to compile your code.
 
 @anchor{Connecting to GDB}
 @section Connecting to GDB
@@ -6528,19 +6543,34 @@ session.
 To list the available OpenOCD commands type @command{monitor help} on the
 GDB command line.
 
+@section Configuring GDB for OpenOCD
+
 OpenOCD supports the gdb @option{qSupported} packet, this enables information
 to be sent by the GDB remote server (i.e. OpenOCD) to GDB. Typical information includes
 packet size and the device's memory map.
+You do not need to configure the packet size by hand,
+and the relevant parts of the memory map should be automatically
+set up when you declare (NOR) flash banks.
+
+However, there are other things which GDB can't currently query.
+You may need to set those up by hand.
+As OpenOCD starts up, you will often see a line reporting
+something like:
 
-Previous versions of OpenOCD required the following GDB options to increase
-the packet size and speed up GDB communication:
 @example
-set remote memory-write-packet-size 1024
-set remote memory-write-packet-size fixed
-set remote memory-read-packet-size 1024
-set remote memory-read-packet-size fixed
+Info : lm3s.cpu: hardware has 6 breakpoints, 4 watchpoints
 @end example
-This is now handled in the @option{qSupported} PacketSize and should not be required.
+
+You can pass that information to GDB with these commands:
+
+@example
+set remote hardware-breakpoint-limit 6
+set remote hardware-watchpoint-limit 4
+@end example
+
+With that particular hardware (Cortex-M3) the hardware breakpoints
+only work for code running from flash memory.  Most other ARM systems
+do not have such restrictions.
 
 @section Programming using GDB
 @cindex Programming using GDB
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 558b211..bdd3233 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -1608,6 +1608,12 @@ static int cortex_m3_examine(struct target *target)
 
 		/* Setup DWT */
 		cortex_m3_dwt_setup(cortex_m3, target);
+
+		/* These hardware breakpoints only work for code in flash! */
+		LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
+				target_name(target),
+				cortex_m3->fp_num_code,
+				cortex_m3->dwt_num_comp);
 	}
 
 	return ERROR_OK;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index cca9cc0..eb04bd1 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -289,6 +289,9 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 				buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
+	LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
+			target_name(target));
+
 	return reg_cache;
 }
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index ac697da..9ed9eea 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2970,6 +2970,9 @@ static int xscale_init_arch_info(struct target *target,
 	xscale->dbr0_used = 0;
 	xscale->dbr1_used = 0;
 
+	LOG_INFO("%s: hardware has 2 breakpoints and 2 watchpoints",
+			target_name(target));
+
 	xscale->arm_bkpt = ARMV5_BKPT(0x0);
 	xscale->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 

commit bbb754aa395be74ceac0c01640fb33c0fae52c20
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:08 2009 -0800

    target: add debug_reason_name()
    
    Provide and use debug_reason_name() instead of expecting targets
    to call Jim_Nvp_value2name_simple().  Less dependency on Jim, and
    the code becomes more clear too.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index dce6d6a..1c4923b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -595,8 +595,7 @@ int arm_arch_state(struct target *target)
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
 			arm_state_strings[armv4_5->core_state],
-			Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-					target->debug_reason)->name,
+			debug_reason_name(target),
 			arm_mode_name(armv4_5->core_mode),
 			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index fc3f47c..d4f6309 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -480,8 +480,7 @@ int armv7m_arch_state(struct target *target)
 
 	LOG_USER("target halted due to %s, current mode: %s %s\n"
 		"xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32,
-		Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-				target->debug_reason)->name,
+		debug_reason_name(target),
 		armv7m_mode_strings[armv7m->core_mode],
 		armv7m_exception_string(armv7m->exception_number),
 		buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32),
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 48d0720..e8ea541 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -254,7 +254,7 @@ int mips32_arch_state(struct target *target)
 	}
 
 	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
-		Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
+		debug_reason_name(target),
 		buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 
 	return ERROR_OK;
diff --git a/src/target/target.c b/src/target/target.c
index 597046f..f249d38 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -187,7 +187,7 @@ const Jim_Nvp nvp_target_state[] = {
 	{ .name = NULL, .value = -1 },
 };
 
-const Jim_Nvp nvp_target_debug_reason [] = {
+static const Jim_Nvp nvp_target_debug_reason [] = {
 	{ .name = "debug-request"            , .value = DBG_REASON_DBGRQ },
 	{ .name = "breakpoint"               , .value = DBG_REASON_BREAKPOINT },
 	{ .name = "watchpoint"               , .value = DBG_REASON_WATCHPOINT },
@@ -214,6 +214,19 @@ const Jim_Nvp nvp_reset_modes[] = {
 	{ .name = NULL     , .value = -1 },
 };
 
+const char *debug_reason_name(struct target *t)
+{
+	const char *cp;
+
+	cp = Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+			t->debug_reason)->name;
+	if (!cp) {
+		LOG_ERROR("Invalid debug reason: %d", (int)(t->debug_reason));
+		cp = "(*BUG*unknown*BUG*)";
+	}
+	return cp;
+}
+
 const char *
 target_state_name( struct target *t )
 {
diff --git a/src/target/target.h b/src/target/target.h
index 7319069..dd3d4f7 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -91,8 +91,6 @@ enum target_debug_reason
 	DBG_REASON_UNDEFINED = 6
 };
 
-extern const Jim_Nvp nvp_target_debug_reason[];
-
 enum target_endianess
 {
 	TARGET_ENDIAN_UNKNOWN = 0,
@@ -165,6 +163,8 @@ static inline const char *target_name(struct target *target)
 	return target->cmd_name;
 }
 
+const char *debug_reason_name(struct target *t);
+
 enum target_event
 {
 	/* LD historical names

commit 19ad7f828ba36f398f52749c2f33e25a3ea78ac2
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:08 2009 -0800

    ARM: don't clone arm_arch_state() code
    
    Have various ARM cores delegate to arm_arch_state() to display
    basic information, instead of duplicating that logic.
    
    This shrinks the code, makes them all report when semihosting
    is active, and highlights which data are specific to this core.
    (Like ARM720 not having separate instruction and data caches.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 48f0358..84c66b8 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -235,14 +235,8 @@ static int arm720t_arch_state(struct target *target)
 
 	armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, Cache: %s",
 			 state[arm720t->armv4_5_mmu.mmu_enabled],
 			 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 217c63c..c5b7c88 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -449,14 +449,8 @@ int arm920t_arch_state(struct target *target)
 
 	armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm920t->armv4_5_mmu.mmu_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c7ef708..4ac92a2 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -505,14 +505,8 @@ int arm926ejs_arch_state(struct target *target)
 
 	armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm926ejs->armv4_5_mmu.mmu_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 61994dc..ac697da 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -865,15 +865,8 @@ static int xscale_arch_state(struct target *target)
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s"
-			"%s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 			 state[xscale->armv4_5_mmu.mmu_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],

commit 927ae6899df12e4667d181575cc0494bf12ff209
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:55:07 2009 -0800

    User's Guide: add quickie setup notes
    
    Add a brief "setup with no customization" note showing the
    how easily things can work if standard OpenOCD config scripts
    already exist.  We've had some new users comment that this
    information is needlessly hard to find, so that starting to
    use OpenOCD is more difficult than it should be.
    
    Plus describe a few other issues that come up when setting
    up an OpenOCD server.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index b0aa7c6..ef395ea 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -501,8 +501,43 @@ Configuration files and scripts are searched for in
 @end enumerate
 The first found file with a matching file name will be used.
 
+@section Simple setup, no customization
+
+In the best case, you can use two scripts from one of the script
+libraries, hook up your JTAG adapter, and start the server ... and
+your JTAG setup will just work "out of the box".  Always try to
+start by reusing those scripts, but assume you'll need more
+customization even if this works.  @xref{OpenOCD Project Setup}.
+
+If you find a script for your JTAG adapter, and for your board or
+target, you may be able to hook up your JTAG adapter then start
+the server like:
+
+@example
+openocd -f interface/ADAPTER.cfg -f board/MYBOARD.cfg
+@end example
+
+You might also need to configure which reset signals are present,
+using @option{-c 'reset_config trst_and_srst'} or something similar.
+If all goes well you'll see output something like
+
+@example
+Open On-Chip Debugger 0.4.0 (2010-01-14-15:06)
+For bug reports, read
+        http://openocd.berlios.de/doc/doxygen/bugs.html
+Info : JTAG tap: lm3s.cpu tap/device found: 0x3ba00477
+       (mfg: 0x23b, part: 0xba00, ver: 0x3)
+@end example
+
+Seeing that "tap/device found" message, and no warnings, means
+the JTAG communication is working.  That's a key milestone, but
+you'll probably need more project-specific setup.
+
+@section What OpenOCD does as it starts
+
 OpenOCD starts by processing the configuration commands provided
-on the command line or in @file{openocd.cfg}.
+on the command line or, if there were no @option{-c command} or
+@option{-f file.cfg} options given, in @file{openocd.cfg}.
 @xref{Configuration Stage}.
 At the end of the configuration stage it verifies the JTAG scan
 chain defined using those commands; your configuration should
@@ -548,6 +583,8 @@ just connecting the JTAG adapter hardware (dongle) to your development board
 and then starting the OpenOCD server.
 You also need to configure that server so that it knows
 about that adapter and board, and helps your work.
+You may also want to connect OpenOCD to GDB, possibly
+using Eclipse or some other GUI.
 
 @section Hooking up the JTAG Adapter
 
@@ -604,7 +641,8 @@ you are using to run OpenOCD.
 For Ethernet, consult the documentation and your network administrator.
 
 For USB based JTAG adapters you have an easy sanity check at this point:
-does the host operating system see the JTAG adapter?
+does the host operating system see the JTAG adapter?  If that host is an
+MS-Windows host, you'll need to install a driver before OpenOCD works.
 
 @item @emph{Connect the adapter's power supply, if needed.}
 This step is primarily for non-USB adapters,
@@ -629,6 +667,7 @@ A simple way to organize them all involves keeping a
 single directory for your work with a given board.
 When you start OpenOCD from that directory,
 it searches there first for configuration files, scripts,
+files accessed through semihosting,
 and for code you upload to the target board.
 It is also the natural place to write files,
 such as log files and data you download from the board.

commit 0a1b7dcfc40385f09b5eb088cd97d6ff25a5816d
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:54:13 2009 -0800

    ARM: use <target/arm.h> not armv4_5.h
    
    Move most declarations in <target/armv4_5.h> to <target/arm.h>
    and update users.
    
    What's left in the older file is stuff that I think should be
    removed ... the old register cache access stuff, which makes it
    awkward to support microcontroller profile (Cortex-M) cores.
    
    The armv4_5_run_algorithm() declaration was moved too, even
    though it's not yet as generic as it probably ought to be.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c
index 4c74675..0cd39c0 100644
--- a/src/flash/nand/arm_io.c
+++ b/src/flash/nand/arm_io.c
@@ -27,7 +27,7 @@
 #include "core.h"
 #include "arm_io.h"
 #include <helper/binarybuffer.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/algorithm.h>
 
 
diff --git a/src/flash/nand/orion.c b/src/flash/nand/orion.c
index 01d4a08..b46ffae 100644
--- a/src/flash/nand/orion.c
+++ b/src/flash/nand/orion.c
@@ -28,7 +28,7 @@
 
 #include "imp.h"
 #include "arm_io.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
 
 
 struct orion_nand_controller
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index 57018bb..211b54e 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -27,7 +27,7 @@
 #include <helper/binarybuffer.h>
 #include <helper/time_support.h>
 #include <target/algorithm.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 
 
 static int aduc702x_build_sector_list(struct flash_bank *bank);
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 1ab9341..71270b9 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -26,7 +26,7 @@
 #include "imp.h"
 #include "cfi.h"
 #include "non_cfi.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index ce74bbb..13dd731 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -26,7 +26,7 @@
 #include "imp.h"
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/image.h>
 
 
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index ef693e9..040097a 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -26,7 +26,7 @@
 
 #include "imp.h"
 #include "str7x.h"
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
 
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index bd7bf7a..f1d5d15 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -97,6 +97,7 @@ MIPS32_SRC = \
 
 noinst_HEADERS = \
 	algorithm.h \
+	arm.h \
 	arm_dpm.h \
 	arm_jtag.h \
 	arm_adi_v5.h \
diff --git a/src/target/armv4_5.h b/src/target/arm.h
similarity index 62%
copy from src/target/armv4_5.h
copy to src/target/arm.h
index c8882ed..00dbe2d 100644
--- a/src/target/armv4_5.h
+++ b/src/target/arm.h
@@ -1,36 +1,45 @@
-/***************************************************************************
- *   Copyright (C) 2005 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
- *                                                                         *
- *   Copyright (C) 2008 by Spencer Oliver                                  *
- *   sp...@sp...                                                  *
- *                                                                         *
- *   Copyright (C) 2009 by Øyvind Harboe                                   *
- *   oyv...@zy...                                               *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-#ifndef ARMV4_5_H
-#define ARMV4_5_H
+/*
+ * Copyright (C) 2005 by Dominic Rath
+ * Dom...@gm...
+ *
+ * Copyright (C) 2008 by Spencer Oliver
+ * sp...@sp...
+ *
+ * Copyright (C) 2009 by Øyvind Harboe
+ * oyv...@zy...
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef ARM_H
+#define ARM_H
 
 #include <target/target.h>
 #include <helper/command.h>
 
 
 /**
+ * @file
+ * Holds the interface to ARM cores.
+ *
+ * At this writing, only "classic ARM" cores built on the ARMv4 register
+ * and mode model are supported.  The Thumb2-only microcontroller profile
+ * support has not yet been integrated, affecting Cortex-M parts.
+ */
+
+/**
  * These numbers match the five low bits of the *PSR registers on
  * "classic ARM" processors, which build on the ARMv4 processor
  * modes and register set.
@@ -60,22 +69,6 @@ enum arm_state {
 
 extern const char *arm_state_strings[];
 
-/* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
- * index into the armv4_5_core_reg_map array.  Its remaining users are
- * remnants which could as easily walk * the register cache directly as
- * use the expensive ARMV4_5_CORE_REG_MODE() macro.
- */
-int arm_mode_to_number(enum arm_mode mode);
-enum arm_mode armv4_5_number_to_mode(int number);
-
-extern const int armv4_5_core_reg_map[8][17];
-
-#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
-
-/* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
-enum { ARMV4_5_CPSR = 31, };
-
 #define ARM_COMMON_MAGIC 0x0A450A45
 
 /**
@@ -85,8 +78,7 @@ enum { ARMV4_5_CPSR = 31, };
  * Cortex-M series cores do not support as many core states or shadowed
  * registers as traditional ARM cores, and only support Thumb2 instructions.
  */
-struct arm
-{
+struct arm {
 	int common_magic;
 	struct reg_cache *core_cache;
 
@@ -168,16 +160,14 @@ static inline bool is_arm(struct arm *arm)
 	return arm && arm->common_magic == ARM_COMMON_MAGIC;
 }
 
-struct arm_algorithm
-{
+struct arm_algorithm {
 	int common_magic;
 
 	enum arm_mode core_mode;
 	enum arm_state core_state;
 };
 
-struct arm_reg
-{
+struct arm_reg {
 	int num;
 	enum arm_mode mode;
 	struct target *target;
@@ -187,14 +177,15 @@ struct arm_reg
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 
+extern const struct command_registration arm_command_handlers[];
+
 int arm_arch_state(struct target *target);
 int arm_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
 
-extern const struct command_registration arm_command_handlers[];
-
 int arm_init_arch_info(struct target *target, struct arm *arm);
 
+/* REVISIT rename this once it's usable by ARMv7-M */
 int armv4_5_run_algorithm(struct target *target,
 		int num_mem_params, struct mem_param *mem_params,
 		int num_reg_params, struct reg_param *reg_params,
@@ -212,4 +203,4 @@ struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 extern struct reg arm_gdb_dummy_fp_reg;
 extern struct reg arm_gdb_dummy_fps_reg;
 
-#endif /* ARMV4_5_H */
+#endif /* ARM_H */
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 421f8d1..bce5bd9 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -23,7 +23,7 @@
 #ifndef ARM11_H
 #define ARM11_H
 
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/arm_dpm.h>
 
 #define ARM11_TAP_DEFAULT			TAP_INVALID
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 03071df..64a99fb 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -39,6 +39,7 @@
 #include "arm_semihosting.h"
 #include "algorithm.h"
 #include "register.h"
+#include "armv4_5.h"
 
 
 /**
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 7555bec..bce17ef 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -29,7 +29,7 @@
 #ifndef ARM7_9_COMMON_H
 #define ARM7_9_COMMON_H
 
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/arm_jtag.h>
 
 #define	ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 406e30a..bd9c5d1 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"		/* REVISIT to become arm.h */
+#include "arm.h"
 #include "arm_dpm.h"
 #include <jtag/jtag.h>
 #include "register.h"
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index d448d54..f4244c8 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -34,6 +34,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "register.h"
 #include "arm_semihosting.h"
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 443f29b..908c613 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -24,6 +24,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_disassembler.h"
 #include "arm_simulator.h"
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 7fec97b..dce6d6a 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "arm.h"
 #include "armv4_5.h"
 #include "arm_jtag.h"
 #include "breakpoints.h"
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index c8882ed..bacdb72 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -26,39 +26,10 @@
 #ifndef ARMV4_5_H
 #define ARMV4_5_H
 
-#include <target/target.h>
-#include <helper/command.h>
-
-
-/**
- * These numbers match the five low bits of the *PSR registers on
- * "classic ARM" processors, which build on the ARMv4 processor
- * modes and register set.
+/* This stuff "knows" that its callers aren't talking
+ * to microcontroller profile (current Cortex-M) parts.
+ * We want to phase it out so core code can be shared.
  */
-enum arm_mode {
-	ARM_MODE_USR = 16,
-	ARM_MODE_FIQ = 17,
-	ARM_MODE_IRQ = 18,
-	ARM_MODE_SVC = 19,
-	ARM_MODE_ABT = 23,
-	ARM_MODE_MON = 26,
-	ARM_MODE_UND = 27,
-	ARM_MODE_SYS = 31,
-	ARM_MODE_ANY = -1
-};
-
-const char *arm_mode_name(unsigned psr_mode);
-bool is_arm_mode(unsigned psr_mode);
-
-/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
-enum arm_state {
-	ARM_STATE_ARM,
-	ARM_STATE_THUMB,
-	ARM_STATE_JAZELLE,
-	ARM_STATE_THUMB_EE,
-};
-
-extern const char *arm_state_strings[];
 
 /* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
  * index into the armv4_5_core_reg_map array.  Its remaining users are
@@ -76,140 +47,4 @@ extern const int armv4_5_core_reg_map[8][17];
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };
 
-#define ARM_COMMON_MAGIC 0x0A450A45
-
-/**
- * Represents a generic ARM core, with standard application registers.
- *
- * There are sixteen application registers (including PC, SP, LR) and a PSR.
- * Cortex-M series cores do not support as many core states or shadowed
- * registers as traditional ARM cores, and only support Thumb2 instructions.
- */
-struct arm
-{
-	int common_magic;
-	struct reg_cache *core_cache;
-
-	/** Handle to the CPSR; valid in all core modes. */
-	struct reg *cpsr;
-
-	/** Handle to the SPSR; valid only in core modes with an SPSR. */
-	struct reg *spsr;
-
-	/** Support for arm_reg_current() */
-	const int *map;
-
-	/**
-	 * Indicates what registers are in the ARM state core register set.
-	 * ARM_MODE_ANY indicates the standard set of 37 registers,
-	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
-	 * more registers are shadowed, for "Secure Monitor" mode.
-	 */
-	enum arm_mode core_type;
-
-	/** Record the current core mode: SVC, USR, or some other mode. */
-	enum arm_mode core_mode;
-
-	/** Record the current core state: ARM, Thumb, or otherwise. */
-	enum arm_state core_state;
-
-	/** Flag reporting unavailability of the BKPT instruction. */
-	bool is_armv4;
-
-	/** Flag reporting whether semihosting is active. */
-	bool is_semihosting;
-
-	/** Value to be returned by semihosting SYS_ERRNO request. */
-	int semihosting_errno;
-
-	/** Backpointer to the target. */
-	struct target *target;
-
-	/** Handle for the debug module, if one is present. */
-	struct arm_dpm *dpm;
-
-	/** Handle for the Embedded Trace Module, if one is present. */
-	struct etm_context *etm;
-
-	/* FIXME all these methods should take "struct arm *" not target */
-
-	/** Retrieve all core registers, for display. */
-	int (*full_context)(struct target *target);
-
-	/** Retrieve a single core register. */
-	int (*read_core_reg)(struct target *target, struct reg *reg,
-			int num, enum arm_mode mode);
-	int (*write_core_reg)(struct target *target, struct reg *reg,
-			int num, enum arm_mode mode, uint32_t value);
-
-	/** Read coprocessor register.  */
-	int (*mrc)(struct target *target, int cpnum,
-			uint32_t op1, uint32_t op2,
-			uint32_t CRn, uint32_t CRm,
-			uint32_t *value);
-
-	/** Write coprocessor register.  */
-	int (*mcr)(struct target *target, int cpnum,
-			uint32_t op1, uint32_t op2,
-			uint32_t CRn, uint32_t CRm,
-			uint32_t value);
-
-	void *arch_info;
-};
-
-/** Convert target handle to generic ARM target state handle. */
-static inline struct arm *target_to_arm(struct target *target)
-{
-	return target->arch_info;
-}
-
-static inline bool is_arm(struct arm *arm)
-{
-	return arm && arm->common_magic == ARM_COMMON_MAGIC;
-}
-
-struct arm_algorithm
-{
-	int common_magic;
-
-	enum arm_mode core_mode;
-	enum arm_state core_state;
-};
-
-struct arm_reg
-{
-	int num;
-	enum arm_mode mode;
-	struct target *target;
-	struct arm *armv4_5_common;
-	uint32_t value;
-};
-
-struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
-
-int arm_arch_state(struct target *target);
-int arm_get_gdb_reg_list(struct target *target,
-		struct reg **reg_list[], int *reg_list_size);
-
-extern const struct command_registration arm_command_handlers[];
-
-int arm_init_arch_info(struct target *target, struct arm *arm);
-
-int armv4_5_run_algorithm(struct target *target,
-		int num_mem_params, struct mem_param *mem_params,
-		int num_reg_params, struct reg_param *reg_params,
-		uint32_t entry_point, uint32_t exit_point,
-		int timeout_ms, void *arch_info);
-
-int arm_checksum_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t *checksum);
-int arm_blank_check_memory(struct target *target,
-		uint32_t address, uint32_t count, uint32_t *blank);
-
-void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
-struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
-
-extern struct reg arm_gdb_dummy_fp_reg;
-extern struct reg arm_gdb_dummy_fps_reg;
-
 #endif /* ARMV4_5_H */
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 24ec819..663e5d9 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -20,7 +20,7 @@
 #define ARMV7A_H
 
 #include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/armv4_5_mmu.h>
 #include <target/armv4_5_cache.h>
 #include <target/arm_dpm.h>
@@ -114,22 +114,6 @@ target_to_armv7a(struct target *target)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8
 
-struct armv7a_algorithm
-{
-	int common_magic;
-
-	enum arm_mode core_mode;
-	enum arm_state core_state;
-};
-
-struct armv7a_core_reg
-{
-	int num;
-	enum arm_mode mode;
-	struct target *target;
-	struct armv7a_common *armv7a_common;
-};
-
 int armv7a_arch_state(struct target *target);
 struct reg_cache *armv7a_build_reg_cache(struct target *target,
 		struct armv7a_common *armv7a_common);
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index c60ab8c..f662e16 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -27,7 +27,7 @@
 #define ARMV7M_COMMON_H
 
 #include <target/arm_adi_v5.h>
-#include <target/armv4_5.h>
+#include <target/arm.h>
 
 /* define for enabling armv7 gdb workarounds */
 #if 1
diff --git a/src/target/etb.c b/src/target/etb.c
index bc0e1bf..3113eca 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "etm.h"
 #include "etb.h"
 #include "register.h"
diff --git a/src/target/etm.c b/src/target/etm.c
index b45fcf5..3aace81 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "etm.h"
 #include "etb.h"
 #include "image.h"
diff --git a/src/target/etm_dummy.c b/src/target/etm_dummy.c
index 647774f..19a078f 100644
--- a/src/target/etm_dummy.c
+++ b/src/target/etm_dummy.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "etm_dummy.h"
 
 
diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c
index ac79f18..ae3a5df 100644
--- a/src/target/oocd_trace.c
+++ b/src/target/oocd_trace.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include "armv4_5.h"
+#include "arm.h"
 #include "oocd_trace.h"
 
 /*
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 816579a..61994dc 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -37,6 +37,7 @@
 #include "register.h"
 #include "image.h"
 #include "arm_opcodes.h"
+#include "armv4_5.h"
 
 
 /*
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 43edeec..97038d8 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -23,7 +23,7 @@
 #ifndef XSCALE_H
 #define XSCALE_H
 
-#include <target/armv4_5.h>
+#include <target/arm.h>
 #include <target/armv4_5_mmu.h>
 #include <target/trace.h>
 

commit 0529c14bfeb113ee37f4d961f9309102d57a1e39
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:54:13 2009 -0800

    ARM: rename some generic routines
    
    Rename some (mostly) generic ARM functions:
    
        armv4_5_arch_state()       --> arm_arch_state()
        armv4_5_get_gdb_reg_list() --> arm_get_gdb_reg_list()
        armv4_5_init_arch_info()   --> arm_init_arch_info()
    
    Cores using the microcontroller profile may want a different
    arch_state() routine though.
    
    (Also fix strange indentation in arm_arch_state: use tabs only!
    And update a call to it, removing assignment-in-conditional.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 7868c23..7b29f53 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -373,7 +373,7 @@ static int arm11_arch_state(struct target *target)
 	struct arm11_common *arm11 = target_to_arm11(target);
 	int retval;
 
-	retval = armv4_5_arch_state(target);
+	retval = arm_arch_state(target);
 
 	/* REVISIT also display ARM11-specific MMU and cache status ... */
 
@@ -1150,7 +1150,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	if (!arm11)
 		return ERROR_FAIL;
 
-	armv4_5_init_arch_info(target, &arm11->arm);
+	arm_init_arch_info(target, &arm11->arm);
 
 	arm11->jtag_info.tap = target->tap;
 	arm11->jtag_info.scann_size = 5;
@@ -1387,7 +1387,7 @@ struct target_type arm11_target = {
 	.deassert_reset =	arm11_deassert_reset,
 	.soft_reset_halt =	arm11_soft_reset_halt,
 
-	.get_gdb_reg_list =	armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list =	arm_get_gdb_reg_list,
 
 	.read_memory =		arm11_read_memory,
 	.write_memory =		arm11_write_memory,
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 14d2184..48f0358 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -557,7 +557,7 @@ struct target_type arm720t_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm720t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm720t_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 905e108..03071df 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2885,7 +2885,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 	armv4_5->write_core_reg = arm7_9_write_core_reg;
 	armv4_5->full_context = arm7_9_full_context;
 
-	if ((retval = armv4_5_init_arch_info(target, armv4_5)) != ERROR_OK)
+	retval = arm_init_arch_info(target, armv4_5);
+	if (retval != ERROR_OK)
 		return retval;
 
 	return target_register_timer_callback(arm7_9_handle_target_request,
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index d204f95..d576d07 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -720,7 +720,7 @@ struct target_type arm7tdmi_target =
 	.name = "arm7tdmi",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -732,7 +732,7 @@ struct target_type arm7tdmi_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 1fcae43..217c63c 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1453,7 +1453,7 @@ struct target_type arm920t_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm920t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm920t_read_memory,
 	.write_memory = arm920t_write_memory,
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d882050..c7ef708 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -801,7 +801,7 @@ struct target_type arm926ejs_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index e4bfe57..82be738 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -252,7 +252,7 @@ struct target_type arm966e_target =
 	.name = "arm966e",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -264,7 +264,7 @@ struct target_type arm966e_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 05f0246..301412c 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -937,7 +937,7 @@ struct target_type arm9tdmi_target =
 	.name = "arm9tdmi",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -949,7 +949,7 @@ struct target_type arm9tdmi_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index ad89b2f..7fec97b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -581,7 +581,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 	return cache;
 }
 
-int armv4_5_arch_state(struct target *target)
+int arm_arch_state(struct target *target)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 
@@ -593,11 +593,11 @@ int armv4_5_arch_state(struct target *target)
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+			arm_state_strings[armv4_5->core_state],
+			Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 					target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
+			arm_mode_name(armv4_5->core_mode),
+			buf_get_u32(armv4_5->cpsr->value, 0, 32),
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
 					0, 32),
 			armv4_5->is_semihosting ? ", semihosting" : "");
@@ -972,7 +972,8 @@ const struct command_registration arm_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
+int arm_get_gdb_reg_list(struct target *target,
+		struct reg **reg_list[], int *reg_list_size)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 	int i;
@@ -1419,7 +1420,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
+int arm_init_arch_info(struct target *target, struct arm *armv4_5)
 {
 	target->arch_info = armv4_5;
 	armv4_5->target = target;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 4b2ccf8..c8882ed 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -187,13 +187,13 @@ struct arm_reg
 
 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 
-int armv4_5_arch_state(struct target *target);
-int armv4_5_get_gdb_reg_list(struct target *target,
+int arm_arch_state(struct target *target);
+int arm_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
 
 extern const struct command_registration arm_command_handlers[];
 
-int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
+int arm_init_arch_info(struct target *target, struct arm *arm);
 
 int armv4_5_run_algorithm(struct target *target,
 		int num_mem_params, struct mem_param *mem_params,
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 3cc86bc..31538c2 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -100,7 +100,7 @@ int armv7a_arch_state(struct target *target)
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	armv4_5_arch_state(target);
+	arm_arch_state(target);
 
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 		 state[armv7a->armv4_5_mmu.mmu_enabled],
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 1ac0a30..593e895 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1603,7 +1603,7 @@ static int cortex_a8_init_arch_info(struct target *target,
 //	arm7_9->handle_target_request = cortex_a8_handle_target_request;
 
 	/* REVISIT v7a setup should be in a v7a-specific routine */
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
 
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
@@ -1686,7 +1686,7 @@ struct target_type cortexa8_target = {
 	.deassert_reset = cortex_a8_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,
diff --git a/src/target/fa526.c b/src/target/fa526.c
index 9c01ec7..7c6cae6 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -370,7 +370,7 @@ struct target_type fa526_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm920t_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm920t_read_memory,
 	.write_memory = arm920t_write_memory,
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index c912137..19ed0cd 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -694,7 +694,7 @@ struct target_type feroceon_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm926ejs_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm926ejs_write_memory,
@@ -721,7 +721,7 @@ struct target_type dragonite_target =
 	.name = "dragonite",
 
 	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
+	.arch_state = arm_arch_state,
 
 	.target_request_data = arm7_9_target_request_data,
 
@@ -733,7 +733,7 @@ struct target_type dragonite_target =
 	.deassert_reset = arm7_9_deassert_reset,
 	.soft_reset_halt = arm7_9_soft_reset_halt,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = arm7_9_read_memory,
 	.write_memory = arm7_9_write_memory,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index b36d9fd..816579a 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2993,7 +2993,7 @@ static int xscale_init_arch_info(struct target *target,
 	armv4_5->write_core_reg = xscale_write_core_reg;
 	armv4_5->full_context = xscale_full_context;
 
-	armv4_5_init_arch_info(target, armv4_5);
+	arm_init_arch_info(target, armv4_5);
 
 	xscale->armv4_5_mmu.armv4_5_cache.ctype = -1;
 	xscale->armv4_5_mmu.get_ttb = xscale_get_ttb;
@@ -3722,7 +3722,7 @@ struct target_type xscale_target =
 	.deassert_reset = xscale_deassert_reset,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = arm_get_gdb_reg_list,
 
 	.read_memory = xscale_read_memory,
 	.read_phys_memory = xscale_read_phys_memory,

commit a4a2808c2a849eddd5d7d454c048ffdfd89ca9c6
Author: David Brownell <dbr...@us...>
Date:   Mon Dec 7 14:54:12 2009 -0800

    ARM: move opcode macros to <target/arm_opcodes.h>
    
    Move the ARM opcode macros from <target/armv4_5.h>, and a few
    Thumb2 ones from <target/armv7m.h>, to more appropriate homes
    in a new <target/arm_opcodes.h> file.
    
    Removed duplicate opcodes from that v7m/Thumb2 set.  Protected
    a few macro argument references by adding missing parentheses.
    
    Tightening up some of the line lengths turned up a curious artifact:
    the macros for the Thumb opcodes are all 32 bits wide, not 16 bits.
    There's currently no explanation for why it's done that way...
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 0caf3e0..18896f7 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -29,6 +29,7 @@
 #include "lpc2000.h"
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
+#include <target/arm_opcodes.h>
 #include <target/armv7m.h>
 
 
@@ -263,8 +264,10 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
 		switch(lpc2000_info->variant)
 		{
 			case lpc1700:
-				target_buffer_set_u32(target, jump_gate, ARMV7M_T_BX(12));
-				target_buffer_set_u32(target, jump_gate + 4, ARMV7M_T_B(0xfffffe));
+				target_buffer_set_u32(target, jump_gate,
+						ARMV4_5_T_BX(12));
+				target_buffer_set_u32(target, jump_gate + 4,
+						ARMV4_5_T_B(0xfffffe));
 				break;
 			case lpc2000_v1:
 			case lpc2000_v2:
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 0486b04..7868c23 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -34,6 +34,7 @@
 #include "target_type.h"
 #include "algorithm.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 #if 0
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 207db78..14d2184 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -28,6 +28,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index fffc632..d204f95 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -30,6 +30,7 @@
 #include "arm7tdmi.h"
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 6a005d6..1fcae43 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -25,6 +25,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index cacb942..d882050 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -28,6 +28,7 @@
 #include <helper/time_support.h>
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 9fe513c..e4bfe57 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -26,6 +26,7 @@
 
 #include "arm966e.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 
 #if 0
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 09199c7..05f0246 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -30,6 +30,7 @@
 #include "arm9tdmi.h"
 #include "target_type.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 /*
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 1ddf530..406e30a 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -27,6 +27,7 @@
 #include "register.h"
 #include "breakpoints.h"
 #include "target_type.h"
+#include "arm_opcodes.h"
 
 
 /**
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
new file mode 100644
index 0000000..b3b5143
--- /dev/null
+++ b/src/target/arm_opcodes.h
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2005 by Dominic Rath
+ * Dom...@gm...
+ *
+ * Copyright (C) 2008 by Spencer Oliver
+ * sp...@sp...
+ *
+ * Copyright (C) 2009 by Øyvind Harboe
+ * oyv...@zy...
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+#ifndef __ARM_OPCODES_H
+#define __ARM_OPCODES_H
+
+/* ARM mode instructions */
+
+/* Store multiple increment after
+ * Rn: base register
+ * List: for each bit in list: store register
+ * S: in priviledged mode: store user-mode registers
+ * W = 1: update the base register. W = 0: leave the base register untouched
+ */
+#define ARMV4_5_STMIA(Rn, List, S, W) \
+	(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+
+/* Load multiple increment after
+ * Rn: base register
+ * List: for each bit in list: store register
+ * S: in priviledged mode: store user-mode registers
+ * W = 1: update the base register. W = 0: leave the base register untouched
+ */
+#define ARMV4_5_LDMIA(Rn, List, S, W) \
+	(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
+
+/* MOV r8, r8 */
+#define ARMV4_5_NOP					(0xe1a08008)
+
+/* Move PSR to general purpose register
+ * R = 1: SPSR R = 0: CPSR
+ * Rn: target register
+ */
+#define ARMV4_5_MRS(Rn, R)	(0xe10f0000 | ((R) << 22) | ((Rn) << 12))
+
+/* Store register
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STR(Rd, Rn)	(0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Load register
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDR(Rd, Rn)	(0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Move general purpose register to PSR
+ * R = 1: SPSR R = 0: CPSR
+ * Field: Field mask
+ * 1: control field 2: extension field 4: status field 8: flags field
+ * Rm: source register
+ */
+#define ARMV4_5_MSR_GP(Rm, Field, R) \
+	(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
+#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
+	(0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
+
+/* Load Register Halfword Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRH_IP(Rd, Rn)	(0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Load Register Byte Immediate Post-Index
+ * Rd: register to load
+ * Rn: base register
+ */
+#define ARMV4_5_LDRB_IP(Rd, Rn)	(0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Store register Halfword Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRH_IP(Rd, Rn)	(0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Store register Byte Immediate Post-Index
+ * Rd: register to store
+ * Rn: base register
+ */
+#define ARMV4_5_STRB_IP(Rd, Rn)	(0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
+
+/* Branch (and Link)
+ * Im: Branch target (left-shifted by 2 bits, added to PC)
+ * L: 1: branch and link 0: branch only
+ */
+#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
+
+/* Branch and exchange (ARM state)
+ * Rm: register holding branch target address
+ */
+#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
+
+/* Move to ARM register from coprocessor
+ * CP: Coprocessor number
+ * op1: Coprocessor opcode
+ * Rd: destination register
+ * CRn: first coprocessor operand
+ * CRm: second coprocessor operand
+ * op2: Second coprocessor opcode
+ */
+#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
+	(0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
+	| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+
+/* Move to coprocessor from ARM register
+ * CP: Coprocessor number
+ * op1: Coprocessor opcode
+ * Rd: destination register
+ * CRn: first coprocessor operand
+ * CRm: second coprocessor operand
+ * op2: Second coprocessor opcode
+ */
+#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
+	(0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
+	| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
+
+/* Breakpoint instruction (ARMv5)
+ * Im: 16-bit immediate
+ */
+#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
+
+
+/* Thumb mode instructions
+ *
+ * FIXME there must be some reason all these opcodes are 32-bits
+ * not 16-bits ... this should get either an explanatory comment,
+ * or be changed not to duplicate the opcode.
+ */
+
+/* Store register (Thumb mode)
+ * Rd: source register
+ * Rn: base register
+ */
+#define ARMV4_5_T_STR(Rd, Rn) \
+	((0x6000 | (Rd) | ((Rn) << 3)) | \
+	((0x6000 | (Rd) | ((Rn) << 3)) << 16))
+
+/* Load register (Thumb state)
+ * Rd: destination register
+ * Rn: base register
+ */
+#define ARMV4_5_T_LDR(Rd, Rn) \
+	((0x6800 | ((Rn) << 3) | (Rd)) \
+	| ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
+
+/* Load multiple (Thumb state)
+ * Rn: base register
+ * List: for each bit in list: store register
+ */
+#define ARMV4_5_T_LDMIA(Rn, List) \
+	((0xc800 | ((Rn) << 8) | (List)) \
+	| ((0xc800 | ((Rn) << 8) | (List)) << 16))
+
+/* Load register with PC relative addressing
+ * Rd: register to load
+ */
+#define ARMV4_5_T_LDR_PCREL(Rd) \
+	((0x4800 | ((Rd) << 8)) \
+	| ((0x4800 | ((Rd) << 8)) << 16))
+
+/* Move hi register (Thumb mode)
+ * Rd: destination register
+ * Rm: source register
+ */
+#define ARMV4_5_T_MOV(Rd, Rm) \
+	((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
+		(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
+	| ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
+		(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
+
+/* No operation (Thumb mode)
+ * NOTE:  this is "MOV r8, r8" ... Thumb2 adds two
+ * architected NOPs, 16-bit and 32-bit.
+ */
+#define ARMV4_5_T_NOP	(0x46c0 | (0x46c0 << 16))
+
+/* Move immediate to register (Thumb state)
+ * Rd: destination register
+ * Im: 8-bit immediate value
+ */
+#define ARMV4_5_T_MOV_IM(Rd, Im) \
+	((0x2000 | ((Rd) << 8) | (Im)) \
+	| ((0x2000 | ((Rd) << 8) | (Im)) << 16))
+
+/* Branch and Exchange
+ * Rm: register containing branch target
+ */
+#define ARMV4_5_T_BX(Rm) \
+	((0x4700 | ((Rm) << 3)) \
+	| ((0x4700 | ((Rm) << 3)) << 16))
+
+/* Branch (Thumb state)
+ * Imm: Branch target
+ */
+#define ARMV4_5_T_B(Imm) \
+	((0xe000 | (Imm)) \
+	| ((0xe000 | (Imm)) << 16))
+
+/* Breakpoint instruction (ARMv5) (Thumb state)
+ * Im: 8-bit immediate
+ */
+#define ARMV5_T_BKPT(Im) \
+	((0xbe00 | (Im)) \
+	| ((0xbe00 | (Im)) << 16))
+
+/* Move to Register from Special Register
+ *	32 bit Thumb2 instruction
+ * Rd: destination register
+ * SYSm: source special register
+ */
+#define ARM_T2_MRS(Rd, SYSm) \
+	((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
+
+/* Move from Register from ...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-888-g30a6e68

[Zach W. <zw...@us...>]

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- Log -----------------------------------------------------------------
commit 30a6e683b85291b8248a2f6189aa292fdf43162d
Author: Zachary T Welch <zw...@su...>
Date:   Sun Dec 6 21:30:21 2009 -0800

    add 'flash list', rewrite 'flash banks'
    
    Rename the existing 'flash banks' implementation as 'flash list', and
    replace the broken 'flash_banks' TCL wrapper with a new command handler.
    
    Adds documentation for the new 'flash list' command in the user guide.

diff --git a/doc/openocd.texi b/doc/openocd.texi
index b6be87e..3651779 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3638,12 +3638,18 @@ Use it in board specific configuration files, not interactively.
 @comment the REAL name for this command is "ocd_flash_banks"
 @comment less confusing would be:  "flash list" (like "nand list")
 @deffn Command {flash banks}
-Prints a one-line summary of each device declared
-using @command{flash bank}, numbered from zero.
+Prints a one-line summary of each device that was 
+declared using @command{flash bank}, numbered from zero.
 Note that this is the @emph{plural} form;
 the @emph{singular} form is a very different command.
 @end deffn
 
+@deffn Command {flash list}
+Retrieves a list of associative arrays for each device that was 
+declared using @command{flash bank}, numbered from zero.
+This returned list can be manipulated easily from within scripts.
+@end deffn
+
 @deffn Command {flash probe} num
 Identify the flash, or validate the parameters of the configured flash. Operation
 depends on the flash type.
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index d417ca0..5ba941b 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -816,14 +816,30 @@ COMMAND_HANDLER(handle_flash_bank_command)
 	flash_bank_add(c);
 
 	return ERROR_OK;
-
 }
 
+COMMAND_HANDLER(handle_flash_banks_command)
+{
+	if (CMD_ARGC != 0)
+		return ERROR_INVALID_ARGUMENTS;
 
-static int jim_flash_banks(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+	unsigned n = 0;
+	for (struct flash_bank *p = flash_bank_list(); p; p = p->next, n++)
+	{
+		LOG_USER("#%u: %s at 0x%8.8" PRIx32 ", size 0x%8.8" PRIx32 ", "
+			"buswidth %u, chipwidth %u", n,
+			p->driver->name, p->base, p->size,
+			p->bus_width, p->chip_width);
+	}
+	return ERROR_OK;
+}
+
+static int jim_flash_list(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
-	if (argc != 1) {
-		Jim_WrongNumArgs(interp, 1, argv, "no arguments to flash_banks command");
+	if (argc != 1)
+	{
+		Jim_WrongNumArgs(interp, 1, argv,
+				"no arguments to 'flash list' command");
 		return JIM_ERR;
 	}
 
@@ -890,8 +906,14 @@ static const struct command_registration flash_config_command_handlers[] = {
 	{
 		.name = "banks",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_flash_banks,
-		.help = "return information about the flash banks",
+		.handler = &handle_flash_banks_command,
+		.help = "return readable information about the flash banks",
+	},
+	{
+		.name = "list",
+		.mode = COMMAND_ANY,
+		.jim_handler = &jim_flash_list,
+		.help = "returns a list of details about the flash banks",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 2c335d9..6cb7d8e 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -1,16 +1,2 @@
 # Defines basic Tcl procs for OpenOCD flash module
 
-# Show flash in human readable form
-# This is an example of a human readable form of a low level fn
-proc flash_banks {} {
-	set i 0
-	set result ""
-	foreach {a} [ocd_flash banks] {
-		if {$i > 0} {
-			set result "$result\n"
-		}
-		set result [format "$result#%d: %s at 0x%08x, size 0x%08x, buswidth %d, chipwidth %d" $i $a(name) $a(base) $a(size) $a(bus_width) $a(chip_width)]
-		set i [expr $i+1]
-	}
-	return $result
-}

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi      |   10 ++++++++--
 src/flash/nor/tcl.c   |   34 ++++++++++++++++++++++++++++------
 src/flash/startup.tcl |   14 --------------
 3 files changed, 36 insertions(+), 22 deletions(-)


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- Log -----------------------------------------------------------------
commit 2bc4dee7e64662c7ca24b83cfa566bcca68cb3b4
Author: Zachary T Welch <zw...@su...>
Date:   Sun Dec 6 20:19:18 2009 -0800

    allow 'flash_banks' command to give GDB output
    
    The 'flash banks' command produces a list that needs to be formatted
    properly for GDB's 'mem info' to work properly.  The flash_banks TCL
    wrapper provided this formatting, but wrappers no longer work for
    second-level commands as they did in the past.  With this patch,
    the 'flash_banks' command can be used with the new command syntax
    and display the required information.

diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index fcebbe0..2c335d9 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -5,7 +5,7 @@
 proc flash_banks {} {
 	set i 0
 	set result ""
-	foreach {a} [ocd_flash_banks] {
+	foreach {a} [ocd_flash banks] {
 		if {$i > 0} {
 			set result "$result\n"
 		}

commit 56c5f6361e43113846920552f5a5d2b3147ae16a
Author: Zachary T Welch <zw...@su...>
Date:   Sun Dec 6 20:15:08 2009 -0800

    fix NOR flash regression
    
    When factoring the bank setup command into flash_bank_add(), I forgot
    to include a call to the new helper.

diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 6598652..d417ca0 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -813,6 +813,8 @@ COMMAND_HANDLER(handle_flash_bank_command)
 		return retval;
 	}
 
+	flash_bank_add(c);
+
 	return ERROR_OK;
 
 }

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/tcl.c   |    2 ++
 src/flash/startup.tcl |    2 +-
 2 files changed, 3 insertions(+), 1 deletions(-)


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commit dd9d1a3459f7b38e2af99bdbafd322cacc9dacc2
Author: David Brownell <dbr...@us...>
Date:   Sat Dec 5 14:40:06 2009 -0800

    misc code review updates
    
    More updates from the code review by Steve Grubb <sg...@re...>.
    The Jim float-comparision bug just gets a comment not a fix, though.
    
    Cc: Steve Grubb <sg...@re...>.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/mflash.c b/src/flash/mflash.c
index aa02e15..123d61c 100644
--- a/src/flash/mflash.c
+++ b/src/flash/mflash.c
@@ -342,7 +342,8 @@ static int mg_dsk_drv_info(void)
 	if ((ret =  mg_dsk_io_cmd(0, 1, mg_io_cmd_identify)) != ERROR_OK)
 		return ret;
 
-	if ((ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL)) != ERROR_OK)
+	ret = mg_dsk_wait(mg_io_wait_drq, MG_OEM_DISK_WAIT_TIME_NORMAL);
+	if (ret != ERROR_OK)
 		return ret;
 
 	LOG_INFO("mflash: read drive info");
@@ -350,7 +351,8 @@ static int mg_dsk_drv_info(void)
 	if (! mflash_bank->drv_info)
 		mflash_bank->drv_info = malloc(sizeof(struct mg_drv_info));
 
-	target_read_memory(target, mg_buff, 2, sizeof(mg_io_type_drv_info) >> 1,
+	ret = target_read_memory(target, mg_buff, 2,
+			sizeof(mg_io_type_drv_info) >> 1,
 			(uint8_t *)&mflash_bank->drv_info->drv_id);
 	if (ret != ERROR_OK)
 		return ret;
diff --git a/src/helper/jim.c b/src/helper/jim.c
index 117ec56..c04acf0 100644
--- a/src/helper/jim.c
+++ b/src/helper/jim.c
@@ -6077,7 +6077,7 @@ int SetIndexFromAny(Jim_Interp *interp, Jim_Obj *objPtr)
             index = INT_MAX;
         else
             index = -(index + 1);
-    } else if (!end && index < 0)
+    } else if (index < 0)
         index = -INT_MAX;
     /* Free the old internal repr and set the new one. */
     Jim_FreeIntRep(interp, objPtr);
@@ -7063,7 +7063,6 @@ trydouble:
                     "Got floating-point value where integer was expected", -1);
                 error = 1;
                 goto err;
-                break;
             case JIM_EXPROP_ADD: dC = dA + dB; break;
             case JIM_EXPROP_SUB: dC = dA-dB; break;
             case JIM_EXPROP_MUL: dC = dA*dB; break;
@@ -7071,6 +7070,7 @@ trydouble:
             case JIM_EXPROP_GT: dC = dA > dB; break;
             case JIM_EXPROP_LTE: dC = dA <= dB; break;
             case JIM_EXPROP_GTE: dC = dA >= dB; break;
+	    /* FIXME comparing floats for equality/inequality is bad juju */
             case JIM_EXPROP_NUMEQ: dC = dA == dB; break;
             case JIM_EXPROP_NUMNE: dC = dA != dB; break;
             case JIM_EXPROP_LOGICAND_LEFT:
@@ -9889,8 +9889,7 @@ static int Jim_WhileCoreCommand(Jim_Interp *interp, int argc,
                         Jim_GetWide(interp, objPtr, &wideValueB) != JIM_OK)
                     {
                         Jim_DecrRefCount(interp, varAObjPtr);
-                        if (varBObjPtr)
-                            Jim_DecrRefCount(interp, varBObjPtr);
+                        Jim_DecrRefCount(interp, varBObjPtr);
                         goto noopt;
                     }
                 }
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 433b50b..373dd7e 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -762,8 +762,7 @@ static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value,
 		uint8_t *in_check_mask, int num_bits)
 {
 	int retval = ERROR_OK;
-
-	int compare_failed = 0;
+	int compare_failed;
 
 	if (in_check_mask)
 		compare_failed = buf_cmp_mask(captured, in_check_value, in_check_mask, num_bits);
diff --git a/src/svf/svf.c b/src/svf/svf.c
index e6d842b..1c746f3 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -1350,12 +1350,9 @@ static int svf_run_command(struct command_context *cmd_ctx, char *cmd_str)
 					return ERROR_FAIL;
 				}
 			}
-			// no need to keep this memory, in jtag_add_pathmove, path will be duplicated
-			if (NULL != path)
-			{
-				free(path);
-				path = NULL;
-			}
+
+			free(path);
+			path = NULL;
 		}
 		else
 		{

-----------------------------------------------------------------------

Summary of changes:
 src/flash/mflash.c |    6 ++++--
 src/helper/jim.c   |    7 +++----
 src/jtag/core.c    |    3 +--
 src/svf/svf.c      |    9 +++------
 4 files changed, 11 insertions(+), 14 deletions(-)


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commit 12b67a2b41557160b8daa23305cbc30a349588c1
Author: Mathias Kuester <ke...@fr...>
Date:   Sat Dec 5 14:55:24 2009 +0100

    NOR: add 29LV400BC flash device
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c
index 7e73afa..b49e441 100644
--- a/src/flash/nor/non_cfi.c
+++ b/src/flash/nor/non_cfi.c
@@ -281,6 +281,23 @@ static struct non_cfi non_cfi_flashes[] = {
 		}
 	},
 	{
+		.mfr = CFI_MFR_FUJITSU,
+		.id = 0xba,				/* 29LV400BC */
+		.pri_id = 0x02,
+		.dev_size = 512*KB,
+		.interface_desc = 0x1,		/* x8 or x16 device w/ nBYTE */
+		.max_buf_write_size = 0x00,
+		.status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7,
+		.num_erase_regions = 4,
+		.erase_region_info =
+		{
+			ERASE_REGION(1, 16*KB),
+			ERASE_REGION(2,  8*KB),
+			ERASE_REGION(1, 32*KB),
+			ERASE_REGION(7, 64*KB)
+		}
+	},
+	{
 		.mfr = CFI_MFR_AMIC,
 		.id = 0xb31a,				/* A29L800A */
 		.pri_id = 0x02,

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/non_cfi.c |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)


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commit ec8c3b5a678f3f236c3b574975eff6434e0aab60
Author: Nicolas Pitre <ni...@fl...>
Date:   Sat Dec 5 01:01:55 2009 -0500

    ARM semihosting: use breakpoint on ARM7
    
    Fall back to software breakpoint when vector catch isn't available.
    
    Possible enhancements:
    
     - add extra optional command parameter to select high vectors
     - add extra optional command parameter to select hardware breakpoint
    
    Signed-off-by: Nicolas Pitre <ni...@ma...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 25f8cb3..905e108 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2835,7 +2835,6 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
 
-		/* TODO: support other methods if vector catch is unavailable */
 		if (arm7_9->has_vector_catch) {
 			struct reg *vector_catch = &arm7_9->eice_cache
 					->reg_list[EICE_VEC_CATCH];
@@ -2844,14 +2843,17 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 				embeddedice_read_reg(vector_catch);
 			buf_set_u32(vector_catch->value, 2, 1, semihosting);
 			embeddedice_store_reg(vector_catch);
+		} else {
+			/* TODO: allow optional high vectors and/or BKPT_HARD */
+			if (semihosting)
+				breakpoint_add(target, 8, 4, BKPT_SOFT);
+			else
+				breakpoint_remove(target, 8); 
+		}
 
-			/* FIXME never let that "catch" be dropped! */
-
-			arm7_9->armv4_5_common.is_semihosting = semihosting;
+		/* FIXME never let that "catch" be dropped! */
+		arm7_9->armv4_5_common.is_semihosting = semihosting;
 
-		} else if (semihosting) {
-			command_print(CMD_CTX, "vector catch unavailable");
-		}
 	}
 
 	command_print(CMD_CTX, "semihosting is %s",

commit e8599cc3d81c659c3b8fdf65177006689865d4f4
Author: Nicolas Pitre <ni...@fl...>
Date:   Sat Dec 5 01:01:54 2009 -0500

    ARM semihosting: work with both low and high vectors
    
    Signed-off-by: Nicolas Pitre <ni...@ma...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 39625f6..d448d54 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -414,18 +414,16 @@ static int do_semihosting(struct target *target)
 int arm_semihosting(struct target *target, int *retval)
 {
 	struct arm *arm = target_to_arm(target);
-	uint32_t lr, spsr;
+	uint32_t pc, lr, spsr;
 	struct reg *r;
 
 	if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
 		return 0;
 
-	/* Check for PC == 8:  Supervisor Call vector
-	 * REVISIT:  assumes low exception vectors, not hivecs...
-	 * safer to test "was this entry from a vector catch".
-	 */
+	/* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
 	r = arm->core_cache->reg_list + 15;
-	if (buf_get_u32(r->value, 0, 32) != 0x08)
+	pc = buf_get_u32(r->value, 0, 32);
+	if (pc != 0x00000008 && pc != 0xffff0008)
 		return 0;
 
 	r = arm_reg_current(arm, 14);

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm7_9_common.c   |   16 +++++++++-------
 src/target/arm_semihosting.c |   10 ++++------
 2 files changed, 13 insertions(+), 13 deletions(-)


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commit 899c9975e750ff0144d4a4f63e0f2a619c0b0e58
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 22:04:37 2009 -0800

    rename nand.h to flash//nand/core.h
    
    Rename nand.h as flash/nand/core.h, chase consumers.  The public APIs
    need to be sorted out with imp.h, but this allows other changes to
    begin improving the separation between policy and mechanism.
    
    Moves #include <target/target.h> and #include "driver.h" into the
    internal headers or source files, removing it from <flash/nand/core.h>.

diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index f8d7088..646889e 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -17,8 +17,7 @@ libflash_la_LIBADD = \
 
 noinst_HEADERS = \
 	common.h \
-	mflash.h \
-	nand.h
+	mflash.h
 
 EXTRA_DIST = startup.tcl
 
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index 667ef8f..a48b726 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -26,6 +26,7 @@ NAND_DRIVERS = \
 
 noinst_HEADERS = \
 	arm_io.h \
+	core.h \
 	lpc3180.h \
 	driver.h \
 	mx3.h \
diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c
index cc565dc..4c74675 100644
--- a/src/flash/nand/arm_io.c
+++ b/src/flash/nand/arm_io.c
@@ -24,10 +24,13 @@
 #include "config.h"
 #endif
 
+#include "core.h"
 #include "arm_io.h"
+#include <helper/binarybuffer.h>
 #include <target/armv4_5.h>
 #include <target/algorithm.h>
 
+
 /**
  * Copies code to a working area.  This will allocate room for the code plus the
  * additional amount requested if the working area pointer is null.
diff --git a/src/flash/nand/arm_io.h b/src/flash/nand/arm_io.h
index d3504f4..2e825bf 100644
--- a/src/flash/nand/arm_io.h
+++ b/src/flash/nand/arm_io.h
@@ -19,9 +19,6 @@
 #ifndef __ARM_NANDIO_H
 #define __ARM_NANDIO_H
 
-#include <flash/nand.h>
-#include <helper/binarybuffer.h>
-
 /**
  * Available operational states the arm_nand_data struct can be in.
  */
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index 46f5454..d52cf5d 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -24,8 +24,6 @@
 #include "config.h"
 #endif
 
-#include <flash/nand.h>
-#include <flash/common.h>
 #include "imp.h"
 
 /* configured NAND devices and NAND Flash command handler */
diff --git a/src/flash/nand.h b/src/flash/nand/core.h
similarity index 96%
rename from src/flash/nand.h
rename to src/flash/nand/core.h
index d675b29..b8dc01c 100644
--- a/src/flash/nand.h
+++ b/src/flash/nand/core.h
@@ -1,6 +1,6 @@
 /***************************************************************************
- *   Copyright (C) 2007 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
+ *   Copyright (C) 2007 by Dominic Rath <Dom...@gm...>              *
+ *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
  *                                                                         *
  *   Partially based on linux/include/linux/mtd/nand.h                     *
  *   Copyright (C) 2000 David Woodhouse <dw...@mv...>                   *
@@ -22,14 +22,10 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
-#ifndef NAND_H
-#define NAND_H
+#ifndef FLASH_NAND_CORE_H
+#define FLASH_NAND_CORE_H
 
 #include <flash/common.h>
-// to be removed later
-#include <target/target.h>
-// to be removed later
-#include <flash/nand/driver.h>
 
 /**
  * Representation of a single NAND block in a NAND device.
@@ -243,4 +239,5 @@ COMMAND_HELPER(nand_command_get_device, unsigned name_index,
 #define		ERROR_NAND_ERROR_CORRECTION_FAILED	(-1105)
 #define		ERROR_NAND_NO_BUFFER			(-1106)
 
-#endif /* NAND_H */
+#endif // FLASH_NAND_CORE_H
+
diff --git a/src/flash/nand/davinci.c b/src/flash/nand/davinci.c
index 0152b4d..96cbfea 100644
--- a/src/flash/nand/davinci.c
+++ b/src/flash/nand/davinci.c
@@ -28,8 +28,9 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "arm_io.h"
-
+#include <target/target.h>
 
 enum ecc {
 	HWECC1,		/* all controllers support 1-bit ECC */
diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 717f5aa..1ccc4f4 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -23,7 +23,7 @@
 #ifdef HAVE_CONFIG_H
 #include <config.h>
 #endif
-#include <flash/nand.h>
+#include "core.h"
 #include "driver.h"
 
 /* NAND flash controller
diff --git a/src/flash/nand/ecc.c b/src/flash/nand/ecc.c
index 1e103d0..2de12d4 100644
--- a/src/flash/nand/ecc.c
+++ b/src/flash/nand/ecc.c
@@ -41,7 +41,7 @@
 #include "config.h"
 #endif
 
-#include <flash/nand.h>
+#include "core.h"
 
 /*
  * Pre-calculated 256-way 1 byte column parity
diff --git a/src/flash/nand/ecc_kw.c b/src/flash/nand/ecc_kw.c
index 55273c5..1c1a8ea 100644
--- a/src/flash/nand/ecc_kw.c
+++ b/src/flash/nand/ecc_kw.c
@@ -20,7 +20,7 @@
 #include "config.h"
 #endif
 
-#include <flash/nand.h>
+#include "core.h"
 
 /*****************************************************************************
  * Arithmetic in GF(2^10) ("F") modulo x^10 + x^3 + 1.
diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c
index fbaa8b4..3e397eb 100644
--- a/src/flash/nand/fileio.c
+++ b/src/flash/nand/fileio.c
@@ -24,7 +24,7 @@
 #include "config.h"
 #endif
 
-#include <flash/nand.h>
+#include "core.h"
 #include "fileio.h"
 
 static struct nand_ecclayout nand_oob_16 = {
diff --git a/src/flash/nand/imp.h b/src/flash/nand/imp.h
index b381b53..e0d411f 100644
--- a/src/flash/nand/imp.h
+++ b/src/flash/nand/imp.h
@@ -19,6 +19,9 @@
 #ifndef FLASH_NAND_IMP_H
 #define FLASH_NAND_IMP_H
 
+#include "core.h"
+#include "driver.h"
+
 int nand_write_page(struct nand_device *nand,
 		uint32_t page, uint8_t *data, uint32_t data_size,
 		uint8_t *oob, uint32_t oob_size);
diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c
index 80284cc..4268b66 100644
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -21,8 +21,10 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "lpc3180.h"
-#include <flash/nand.h>
+#include <target/target.h>
+
 
 static int lpc3180_reset(struct nand_device *nand);
 static int lpc3180_controller_ready(struct nand_device *nand, int timeout);
diff --git a/src/flash/nand/mx3.c b/src/flash/nand/mx3.c
index 21577a6..4823534 100644
--- a/src/flash/nand/mx3.c
+++ b/src/flash/nand/mx3.c
@@ -35,7 +35,9 @@ get_next_halfword_from_sram_buffer() not tested
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "mx3.h"
+#include <target/target.h>
 
 static const char target_not_halted_err_msg[] =
 	"target must be halted to use mx3 NAND flash controller";
diff --git a/src/flash/nand/mx3.h b/src/flash/nand/mx3.h
index 94dbf0c..f37fc32 100644
--- a/src/flash/nand/mx3.h
+++ b/src/flash/nand/mx3.h
@@ -25,7 +25,6 @@
  *
  * Many thanks to Ben Dooks for writing s3c24xx driver.
  */
-#include <flash/nand.h>
 
 #define		MX3_NF_BASE_ADDR		0xb8000000
 #define		MX3_NF_BUFSIZ			(MX3_NF_BASE_ADDR + 0xe00)
diff --git a/src/flash/nand/nonce.c b/src/flash/nand/nonce.c
index 8d15040..ab490ae 100644
--- a/src/flash/nand/nonce.c
+++ b/src/flash/nand/nonce.c
@@ -20,7 +20,8 @@
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
-#include <flash/nand.h>
+
+#include "imp.h"
 #include "hello.h"
 
 
diff --git a/src/flash/nand/orion.c b/src/flash/nand/orion.c
index 4b174da..01d4a08 100644
--- a/src/flash/nand/orion.c
+++ b/src/flash/nand/orion.c
@@ -26,6 +26,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "arm_io.h"
 #include <target/armv4_5.h>
 
diff --git a/src/flash/nand/s3c24xx.h b/src/flash/nand/s3c24xx.h
index f89bf6e..9424cb3 100644
--- a/src/flash/nand/s3c24xx.h
+++ b/src/flash/nand/s3c24xx.h
@@ -27,8 +27,9 @@
  * Many thanks to Simtec Electronics for sponsoring this work.
  */
 
-#include <flash/nand.h>
-#include <flash/nand/s3c24xx_regs.h>
+#include "imp.h"
+#include "s3c24xx_regs.h"
+#include <target/target.h>
 
 struct s3c24xx_nand_controller
 {
diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c
index 75a416f..e69882b 100644
--- a/src/flash/nand/tcl.c
+++ b/src/flash/nand/tcl.c
@@ -24,7 +24,7 @@
 #include "config.h"
 #endif
 
-#include <flash/nand.h>
+#include "core.h"
 #include "imp.h"
 #include "fileio.h"
 
diff --git a/src/openocd.c b/src/openocd.c
index e500ba6..8cb8674 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -35,7 +35,7 @@
 #include <xsvf/xsvf.h>
 #include <svf/svf.h>
 #include <flash/nor/core.h>
-#include <flash/nand.h>
+#include <flash/nand/core.h>
 #include <pld/pld.h>
 #include <flash/mflash.h>
 

commit da3bcb392e852214b0dda878f6161c8f1e8d15f3
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 21:38:13 2009 -0800

    move remaining nand helper files
    
    Move remaining NAND implementation files into src/flash/nand/.

diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index 2144ff2..f8d7088 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -9,9 +9,6 @@ METASOURCES = AUTO
 noinst_LTLIBRARIES = libflash.la
 libflash_la_SOURCES = \
 	common.c \
-	arm_nandio.c \
-	nand_ecc.c \
-	nand_ecc_kw.c \
 	mflash.c
 
 libflash_la_LIBADD = \
@@ -19,7 +16,6 @@ libflash_la_LIBADD = \
 	$(top_builddir)/src/flash/nand/libocdflashnand.la
 
 noinst_HEADERS = \
-	arm_nandio.h \
 	common.h \
 	mflash.h \
 	nand.h
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index 3885a7b..667ef8f 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -3,9 +3,12 @@ AM_CPPFLAGS = -I$(top_srcdir)/src
 noinst_LTLIBRARIES = libocdflashnand.la
 
 libocdflashnand_la_SOURCES = \
+	ecc.c \
+	ecc_kw.c \
 	core.c \
 	fileio.c \
 	tcl.c \
+	arm_io.c \
 	$(NAND_DRIVERS) \
 	driver.c
 
@@ -22,6 +25,7 @@ NAND_DRIVERS = \
 	s3c2443.c
 
 noinst_HEADERS = \
+	arm_io.h \
 	lpc3180.h \
 	driver.h \
 	mx3.h \
diff --git a/src/flash/arm_nandio.c b/src/flash/nand/arm_io.c
similarity index 99%
rename from src/flash/arm_nandio.c
rename to src/flash/nand/arm_io.c
index 67619d5..cc565dc 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/nand/arm_io.c
@@ -24,7 +24,7 @@
 #include "config.h"
 #endif
 
-#include "arm_nandio.h"
+#include "arm_io.h"
 #include <target/armv4_5.h>
 #include <target/algorithm.h>
 
diff --git a/src/flash/arm_nandio.h b/src/flash/nand/arm_io.h
similarity index 100%
rename from src/flash/arm_nandio.h
rename to src/flash/nand/arm_io.h
diff --git a/src/flash/nand/davinci.c b/src/flash/nand/davinci.c
index 6677073..0152b4d 100644
--- a/src/flash/nand/davinci.c
+++ b/src/flash/nand/davinci.c
@@ -28,7 +28,7 @@
 #include "config.h"
 #endif
 
-#include <flash/arm_nandio.h>
+#include "arm_io.h"
 
 
 enum ecc {
diff --git a/src/flash/nand_ecc.c b/src/flash/nand/ecc.c
similarity index 99%
rename from src/flash/nand_ecc.c
rename to src/flash/nand/ecc.c
index 7aa1519..1e103d0 100644
--- a/src/flash/nand_ecc.c
+++ b/src/flash/nand/ecc.c
@@ -41,7 +41,7 @@
 #include "config.h"
 #endif
 
-#include "nand.h"
+#include <flash/nand.h>
 
 /*
  * Pre-calculated 256-way 1 byte column parity
diff --git a/src/flash/nand_ecc_kw.c b/src/flash/nand/ecc_kw.c
similarity index 99%
rename from src/flash/nand_ecc_kw.c
rename to src/flash/nand/ecc_kw.c
index a809b32..55273c5 100644
--- a/src/flash/nand_ecc_kw.c
+++ b/src/flash/nand/ecc_kw.c
@@ -20,9 +20,7 @@
 #include "config.h"
 #endif
 
-#include <sys/types.h>
-#include "nand.h"
-
+#include <flash/nand.h>
 
 /*****************************************************************************
  * Arithmetic in GF(2^10) ("F") modulo x^10 + x^3 + 1.
diff --git a/src/flash/nand/orion.c b/src/flash/nand/orion.c
index b124dee..4b174da 100644
--- a/src/flash/nand/orion.c
+++ b/src/flash/nand/orion.c
@@ -26,7 +26,7 @@
 #include "config.h"
 #endif
 
-#include <flash/arm_nandio.h>
+#include "arm_io.h"
 #include <target/armv4_5.h>
 
 

commit 747d6f22868dd87cb54341cc22d9eb3687039735
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 19:28:18 2009 -0800

    split nand.c into nand/{core,fileio,tcl}.c
    
    Moves commands into nand/tcl.c and core implementation to 'nand/core.c'
    and 'nand/fileio.c'.  Eliminates 'flash/nand.c'.
    
    Adds 'nand/imp.h' to share routines between TCL commands and core.

diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index ba44adb..2144ff2 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -12,7 +12,6 @@ libflash_la_SOURCES = \
 	arm_nandio.c \
 	nand_ecc.c \
 	nand_ecc_kw.c \
-	nand.c \
 	mflash.c
 
 libflash_la_LIBADD = \
diff --git a/src/flash/nand.c b/src/flash/nand.c
deleted file mode 100644
index 9a220d2..0000000
--- a/src/flash/nand.c
+++ /dev/null
@@ -1,1766 +0,0 @@
-/***************************************************************************
- *   Copyright (C) 2007 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
- *                                                                         *
- *   Partially based on drivers/mtd/nand_ids.c from Linux.                 *
- *   Copyright (C) 2002 Thomas Gleixner <tg...@li...>               *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "nand.h"
-#include "common.h"
-#include <helper/time_support.h>
-#include <helper/fileio.h>
-
-static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
-//static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
-
-static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
-
-/* configured NAND devices and NAND Flash command handler */
-static struct nand_device *nand_devices = NULL;
-
-/*	Chip ID list
- *
- *	Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
- *	options
- *
- *	Pagesize; 0, 256, 512
- *	0	get this information from the extended chip ID
- *	256	256 Byte page size
- *	512	512 Byte page size
- */
-static struct nand_info nand_flash_ids[] =
-{
-	/* start "museum" IDs */
-	{"NAND 1MiB 5V 8-bit",		0x6e, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 5V 8-bit",		0x64, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 5V 8-bit",		0x6b, 512, 4, 0x2000, 0},
-	{"NAND 1MiB 3,3V 8-bit",	0xe8, 256, 1, 0x1000, 0},
-	{"NAND 1MiB 3,3V 8-bit",	0xec, 256, 1, 0x1000, 0},
-	{"NAND 2MiB 3,3V 8-bit",	0xea, 256, 2, 0x1000, 0},
-	{"NAND 4MiB 3,3V 8-bit",	0xd5, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit",	0xe3, 512, 4, 0x2000, 0},
-	{"NAND 4MiB 3,3V 8-bit",	0xe5, 512, 4, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit",	0xd6, 512, 8, 0x2000, 0},
-
-	{"NAND 8MiB 1,8V 8-bit",	0x39, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 3,3V 8-bit",	0xe6, 512, 8, 0x2000, 0},
-	{"NAND 8MiB 1,8V 16-bit",	0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-	{"NAND 8MiB 3,3V 16-bit",	0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
-	/* end "museum" IDs */
-
-	{"NAND 16MiB 1,8V 8-bit",	0x33, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 3,3V 8-bit",	0x73, 512, 16, 0x4000, 0},
-	{"NAND 16MiB 1,8V 16-bit",	0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 16MiB 3,3V 16-bit",	0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 32MiB 1,8V 8-bit",	0x35, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 3,3V 8-bit",	0x75, 512, 32, 0x4000, 0},
-	{"NAND 32MiB 1,8V 16-bit",	0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 32MiB 3,3V 16-bit",	0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 64MiB 1,8V 8-bit",	0x36, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 3,3V 8-bit",	0x76, 512, 64, 0x4000, 0},
-	{"NAND 64MiB 1,8V 16-bit",	0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 64MiB 3,3V 16-bit",	0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 128MiB 1,8V 8-bit",	0x78, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 1,8V 8-bit",	0x39, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 3,3V 8-bit",	0x79, 512, 128, 0x4000, 0},
-	{"NAND 128MiB 1,8V 16-bit",	0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 1,8V 16-bit",	0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 3,3V 16-bit",	0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-	{"NAND 128MiB 3,3V 16-bit",	0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
-
-	{"NAND 256MiB 3,3V 8-bit",	0x71, 512, 256, 0x4000, 0},
-
-	{"NAND 64MiB 1,8V 8-bit",	0xA2, 0,  64, 0, LP_OPTIONS},
-	{"NAND 64MiB 3,3V 8-bit",	0xF2, 0,  64, 0, LP_OPTIONS},
-	{"NAND 64MiB 1,8V 16-bit",	0xB2, 0,  64, 0, LP_OPTIONS16},
-	{"NAND 64MiB 3,3V 16-bit",	0xC2, 0,  64, 0, LP_OPTIONS16},
-
-	{"NAND 128MiB 1,8V 8-bit",	0xA1, 0, 128, 0, LP_OPTIONS},
-	{"NAND 128MiB 3,3V 8-bit",	0xF1, 0, 128, 0, LP_OPTIONS},
-	{"NAND 128MiB 1,8V 16-bit",	0xB1, 0, 128, 0, LP_OPTIONS16},
-	{"NAND 128MiB 3,3V 16-bit",	0xC1, 0, 128, 0, LP_OPTIONS16},
-
-	{"NAND 256MiB 1,8V 8-bit",	0xAA, 0, 256, 0, LP_OPTIONS},
-	{"NAND 256MiB 3,3V 8-bit",	0xDA, 0, 256, 0, LP_OPTIONS},
-	{"NAND 256MiB 1,8V 16-bit",	0xBA, 0, 256, 0, LP_OPTIONS16},
-	{"NAND 256MiB 3,3V 16-bit",	0xCA, 0, 256, 0, LP_OPTIONS16},
-
-	{"NAND 512MiB 1,8V 8-bit",	0xAC, 0, 512, 0, LP_OPTIONS},
-	{"NAND 512MiB 3,3V 8-bit",	0xDC, 0, 512, 0, LP_OPTIONS},
-	{"NAND 512MiB 1,8V 16-bit",	0xBC, 0, 512, 0, LP_OPTIONS16},
-	{"NAND 512MiB 3,3V 16-bit",	0xCC, 0, 512, 0, LP_OPTIONS16},
-
-	{"NAND 1GiB 1,8V 8-bit",	0xA3, 0, 1024, 0, LP_OPTIONS},
-	{"NAND 1GiB 3,3V 8-bit",	0xD3, 0, 1024, 0, LP_OPTIONS},
-	{"NAND 1GiB 1,8V 16-bit",	0xB3, 0, 1024, 0, LP_OPTIONS16},
-	{"NAND 1GiB 3,3V 16-bit",	0xC3, 0, 1024, 0, LP_OPTIONS16},
-
-	{"NAND 2GiB 1,8V 8-bit",	0xA5, 0, 2048, 0, LP_OPTIONS},
-	{"NAND 2GiB 3,3V 8-bit",	0xD5, 0, 2048, 0, LP_OPTIONS},
-	{"NAND 2GiB 1,8V 16-bit",	0xB5, 0, 2048, 0, LP_OPTIONS16},
-	{"NAND 2GiB 3,3V 16-bit",	0xC5, 0, 2048, 0, LP_OPTIONS16},
-
-	{NULL, 0, 0, 0, 0, 0 }
-};
-
-/* Manufacturer ID list
- */
-static struct nand_manufacturer nand_manuf_ids[] =
-{
-	{0x0, "unknown"},
-	{NAND_MFR_TOSHIBA, "Toshiba"},
-	{NAND_MFR_SAMSUNG, "Samsung"},
-	{NAND_MFR_FUJITSU, "Fujitsu"},
-	{NAND_MFR_NATIONAL, "National"},
-	{NAND_MFR_RENESAS, "Renesas"},
-	{NAND_MFR_STMICRO, "ST Micro"},
-	{NAND_MFR_HYNIX, "Hynix"},
-	{NAND_MFR_MICRON, "Micron"},
-	{0x0, NULL},
-};
-
-/*
- * Define default oob placement schemes for large and small page devices
- */
-
-#if 0
-static struct nand_ecclayout nand_oob_8 = {
-	.eccbytes = 3,
-	.eccpos = {0, 1, 2},
-	.oobfree = {
-		{.offset = 3,
-		 .length = 2},
-		{.offset = 6,
-		 .length = 2}}
-};
-#endif
-
-static struct nand_ecclayout nand_oob_16 = {
-	.eccbytes = 6,
-	.eccpos = {0, 1, 2, 3, 6, 7},
-	.oobfree = {
-		{.offset = 8,
-		 . length = 8}}
-};
-
-static struct nand_ecclayout nand_oob_64 = {
-	.eccbytes = 24,
-	.eccpos = {
-		   40, 41, 42, 43, 44, 45, 46, 47,
-		   48, 49, 50, 51, 52, 53, 54, 55,
-		   56, 57, 58, 59, 60, 61, 62, 63},
-	.oobfree = {
-		{.offset = 2,
-		 .length = 38}}
-};
-
-int nand_list_walker(struct nand_flash_controller *c, void *x)
-{
-	struct command_context *cmd_ctx = (struct command_context *)x;
-	command_print(cmd_ctx, "  %s", c->name);
-	return ERROR_OK;
-}
-COMMAND_HANDLER(handle_nand_list_drivers)
-{
-	command_print(CMD_CTX, "Available NAND flash controller drivers:");
-	return nand_driver_walk(&nand_list_walker, CMD_CTX);
-}
-
-static COMMAND_HELPER(create_nand_device, const char *bank_name,
-		struct nand_flash_controller *controller)
-{
-	if (NULL != controller->commands)
-	{
-		int retval = register_commands(CMD_CTX, NULL,
-				controller->commands);
-		if (ERROR_OK != retval)
-			return retval;
-	}
-	struct nand_device *c = malloc(sizeof(struct nand_device));
-
-	c->name = strdup(bank_name);
-	c->controller = controller;
-	c->controller_priv = NULL;
-	c->manufacturer = NULL;
-	c->device = NULL;
-	c->bus_width = 0;
-	c->address_cycles = 0;
-	c->page_size = 0;
-	c->use_raw = 0;
-	c->next = NULL;
-
-	int retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
-	if (ERROR_OK != retval)
-	{
-		LOG_ERROR("'%s' driver rejected nand flash", controller->name);
-		free(c);
-		return ERROR_OK;
-	}
-
-	if (nand_devices) {
-		struct nand_device *p = nand_devices;
-		while (p && p->next) p = p->next;
-		p->next = c;
-	} else
-		nand_devices = c;
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_device_command)
-{
-	if (CMD_ARGC < 1)
-	{
-		LOG_ERROR("incomplete nand device configuration");
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	// save name and increment (for compatibility) with drivers
-	const char *bank_name = *CMD_ARGV++;
-	CMD_ARGC--;
-
-	const char *driver_name = CMD_ARGV[0];
-	struct nand_flash_controller *controller;
-	controller = nand_driver_find_by_name(CMD_ARGV[0]);
-	if (NULL == controller)
-	{
-		LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
-		return CALL_COMMAND_HANDLER(handle_nand_list_drivers);
-	}
-	return CALL_COMMAND_HANDLER(create_nand_device, bank_name, controller);
-}
-
-
-COMMAND_HANDLER(handle_nand_init_command);
-
-static const struct command_registration nand_config_command_handlers[] = {
-	{
-		.name = "device",
-		.handler = &handle_nand_device_command,
-		.mode = COMMAND_CONFIG,
-		.help = "defines a new NAND bank",
-	},
-	{
-		.name = "drivers",
-		.handler = &handle_nand_list_drivers,
-		.mode = COMMAND_ANY,
-		.help = "lists available NAND drivers",
-	},
-	{
-		.name = "init",
-		.mode = COMMAND_CONFIG,
-		.handler = &handle_nand_init_command,
-		.help = "initialize NAND devices",
-	},
-	COMMAND_REGISTRATION_DONE
-};
-static const struct command_registration nand_command_handlers[] = {
-	{
-		.name = "nand",
-		.mode = COMMAND_ANY,
-		.help = "NAND flash command group",
-		.chain = nand_config_command_handlers,
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-int nand_register_commands(struct command_context *cmd_ctx)
-{
-	return register_commands(cmd_ctx, NULL, nand_command_handlers);
-}
-
-struct nand_device *get_nand_device_by_name(const char *name)
-{
-	unsigned requested = get_flash_name_index(name);
-	unsigned found = 0;
-
-	struct nand_device *nand;
-	for (nand = nand_devices; NULL != nand; nand = nand->next)
-	{
-		if (strcmp(nand->name, name) == 0)
-			return nand;
-		if (!flash_driver_name_matches(nand->controller->name, name))
-			continue;
-		if (++found < requested)
-			continue;
-		return nand;
-	}
-	return NULL;
-}
-
-struct nand_device *get_nand_device_by_num(int num)
-{
-	struct nand_device *p;
-	int i = 0;
-
-	for (p = nand_devices; p; p = p->next)
-	{
-		if (i++ == num)
-		{
-			return p;
-		}
-	}
-
-	return NULL;
-}
-
-COMMAND_HELPER(nand_command_get_device, unsigned name_index,
-		struct nand_device **nand)
-{
-	const char *str = CMD_ARGV[name_index];
-	*nand = get_nand_device_by_name(str);
-	if (*nand)
-		return ERROR_OK;
-
-	unsigned num;
-	COMMAND_PARSE_NUMBER(uint, str, num);
-	*nand = get_nand_device_by_num(num);
-	if (!*nand) {
-		command_print(CMD_CTX, "NAND flash device '%s' not found", str);
-		return ERROR_INVALID_ARGUMENTS;
-	}
-	return ERROR_OK;
-}
-
-static int nand_build_bbt(struct nand_device *nand, int first, int last)
-{
-	uint32_t page = 0x0;
-	int i;
-	uint8_t oob[6];
-
-	if ((first < 0) || (first >= nand->num_blocks))
-		first = 0;
-
-	if ((last >= nand->num_blocks) || (last == -1))
-		last = nand->num_blocks - 1;
-
-	for (i = first; i < last; i++)
-	{
-		nand_read_page(nand, page, NULL, 0, oob, 6);
-
-		if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
-			|| (((nand->page_size == 512) && (oob[5] != 0xff)) ||
-				((nand->page_size == 2048) && (oob[0] != 0xff))))
-		{
-			LOG_WARNING("bad block: %i", i);
-			nand->blocks[i].is_bad = 1;
-		}
-		else
-		{
-			nand->blocks[i].is_bad = 0;
-		}
-
-		page += (nand->erase_size / nand->page_size);
-	}
-
-	return ERROR_OK;
-}
-
-int nand_read_status(struct nand_device *nand, uint8_t *status)
-{
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	/* Send read status command */
-	nand->controller->command(nand, NAND_CMD_STATUS);
-
-	alive_sleep(1);
-
-	/* read status */
-	if (nand->device->options & NAND_BUSWIDTH_16)
-	{
-		uint16_t data;
-		nand->controller->read_data(nand, &data);
-		*status = data & 0xff;
-	}
-	else
-	{
-		nand->controller->read_data(nand, status);
-	}
-
-	return ERROR_OK;
-}
-
-static int nand_poll_ready(struct nand_device *nand, int timeout)
-{
-	uint8_t status;
-
-	nand->controller->command(nand, NAND_CMD_STATUS);
-	do {
-		if (nand->device->options & NAND_BUSWIDTH_16) {
-			uint16_t data;
-			nand->controller->read_data(nand, &data);
-			status = data & 0xff;
-		} else {
-			nand->controller->read_data(nand, &status);
-		}
-		if (status & NAND_STATUS_READY)
-			break;
-		alive_sleep(1);
-	} while (timeout--);
-
-	return (status & NAND_STATUS_READY) != 0;
-}
-
-int nand_probe(struct nand_device *nand)
-{
-	uint8_t manufacturer_id, device_id;
-	uint8_t id_buff[6];
-	int retval;
-	int i;
-
-	/* clear device data */
-	nand->device = NULL;
-	nand->manufacturer = NULL;
-
-	/* clear device parameters */
-	nand->bus_width = 0;
-	nand->address_cycles = 0;
-	nand->page_size = 0;
-	nand->erase_size = 0;
-
-	/* initialize controller (device parameters are zero, use controller default) */
-	if ((retval = nand->controller->init(nand) != ERROR_OK))
-	{
-		switch (retval)
-		{
-			case ERROR_NAND_OPERATION_FAILED:
-				LOG_DEBUG("controller initialization failed");
-				return ERROR_NAND_OPERATION_FAILED;
-			case ERROR_NAND_OPERATION_NOT_SUPPORTED:
-				LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
-				return ERROR_NAND_OPERATION_FAILED;
-			default:
-				LOG_ERROR("BUG: unknown controller initialization failure");
-				return ERROR_NAND_OPERATION_FAILED;
-		}
-	}
-
-	nand->controller->command(nand, NAND_CMD_RESET);
-	nand->controller->reset(nand);
-
-	nand->controller->command(nand, NAND_CMD_READID);
-	nand->controller->address(nand, 0x0);
-
-	if (nand->bus_width == 8)
-	{
-		nand->controller->read_data(nand, &manufacturer_id);
-		nand->controller->read_data(nand, &device_id);
-	}
-	else
-	{
-		uint16_t data_buf;
-		nand->controller->read_data(nand, &data_buf);
-		manufacturer_id = data_buf & 0xff;
-		nand->controller->read_data(nand, &data_buf);
-		device_id = data_buf & 0xff;
-	}
-
-	for (i = 0; nand_flash_ids[i].name; i++)
-	{
-		if (nand_flash_ids[i].id == device_id)
-		{
-			nand->device = &nand_flash_ids[i];
-			break;
-		}
-	}
-
-	for (i = 0; nand_manuf_ids[i].name; i++)
-	{
-		if (nand_manuf_ids[i].id == manufacturer_id)
-		{
-			nand->manufacturer = &nand_manuf_ids[i];
-			break;
-		}
-	}
-
-	if (!nand->manufacturer)
-	{
-		nand->manufacturer = &nand_manuf_ids[0];
-		nand->manufacturer->id = manufacturer_id;
-	}
-
-	if (!nand->device)
-	{
-		LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
-			manufacturer_id, device_id);
-		return ERROR_NAND_OPERATION_FAILED;
-	}
-
-	LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
-
-	/* initialize device parameters */
-
-	/* bus width */
-	if (nand->device->options & NAND_BUSWIDTH_16)
-		nand->bus_width = 16;
-	else
-		nand->bus_width = 8;
-
-	/* Do we need extended device probe information? */
-	if (nand->device->page_size == 0 ||
-	    nand->device->erase_size == 0)
-	{
-		if (nand->bus_width == 8)
-		{
-			nand->controller->read_data(nand, id_buff + 3);
-			nand->controller->read_data(nand, id_buff + 4);
-			nand->controller->read_data(nand, id_buff + 5);
-		}
-		else
-		{
-			uint16_t data_buf;
-
-			nand->controller->read_data(nand, &data_buf);
-			id_buff[3] = data_buf;
-
-			nand->controller->read_data(nand, &data_buf);
-			id_buff[4] = data_buf;
-
-			nand->controller->read_data(nand, &data_buf);
-			id_buff[5] = data_buf >> 8;
-		}
-	}
-
-	/* page size */
-	if (nand->device->page_size == 0)
-	{
-		nand->page_size = 1 << (10 + (id_buff[4] & 3));
-	}
-	else if (nand->device->page_size == 256)
-	{
-		LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
-		return ERROR_NAND_OPERATION_FAILED;
-	}
-	else
-	{
-		nand->page_size = nand->device->page_size;
-	}
-
-	/* number of address cycles */
-	if (nand->page_size <= 512)
-	{
-		/* small page devices */
-		if (nand->device->chip_size <= 32)
-			nand->address_cycles = 3;
-		else if (nand->device->chip_size <= 8*1024)
-			nand->address_cycles = 4;
-		else
-		{
-			LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
-			nand->address_cycles = 5;
-		}
-	}
-	else
-	{
-		/* large page devices */
-		if (nand->device->chip_size <= 128)
-			nand->address_cycles = 4;
-		else if (nand->device->chip_size <= 32*1024)
-			nand->address_cycles = 5;
-		else
-		{
-			LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
-			nand->address_cycles = 6;
-		}
-	}
-
-	/* erase size */
-	if (nand->device->erase_size == 0)
-	{
-		switch ((id_buff[4] >> 4) & 3) {
-		case 0:
-			nand->erase_size = 64 << 10;
-			break;
-		case 1:
-			nand->erase_size = 128 << 10;
-			break;
-		case 2:
-			nand->erase_size = 256 << 10;
-			break;
-		case 3:
-			nand->erase_size =512 << 10;
-			break;
-		}
-	}
-	else
-	{
-		nand->erase_size = nand->device->erase_size;
-	}
-
-	/* initialize controller, but leave parameters at the controllers default */
-	if ((retval = nand->controller->init(nand) != ERROR_OK))
-	{
-		switch (retval)
-		{
-			case ERROR_NAND_OPERATION_FAILED:
-				LOG_DEBUG("controller initialization failed");
-				return ERROR_NAND_OPERATION_FAILED;
-			case ERROR_NAND_OPERATION_NOT_SUPPORTED:
-				LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
-					nand->bus_width, nand->address_cycles, nand->page_size);
-				return ERROR_NAND_OPERATION_FAILED;
-			default:
-				LOG_ERROR("BUG: unknown controller initialization failure");
-				return ERROR_NAND_OPERATION_FAILED;
-		}
-	}
-
-	nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
-	nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
-
-	for (i = 0; i < nand->num_blocks; i++)
-	{
-		nand->blocks[i].size = nand->erase_size;
-		nand->blocks[i].offset = i * nand->erase_size;
-		nand->blocks[i].is_erased = -1;
-		nand->blocks[i].is_bad = -1;
-	}
-
-	return ERROR_OK;
-}
-
-static int nand_erase(struct nand_device *nand, int first_block, int last_block)
-{
-	int i;
-	uint32_t page;
-	uint8_t status;
-	int retval;
-
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	if ((first_block < 0) || (last_block > nand->num_blocks))
-		return ERROR_INVALID_ARGUMENTS;
-
-	/* make sure we know if a block is bad before erasing it */
-	for (i = first_block; i <= last_block; i++)
-	{
-		if (nand->blocks[i].is_bad == -1)
-		{
-			nand_build_bbt(nand, i, last_block);
-			break;
-		}
-	}
-
-	for (i = first_block; i <= last_block; i++)
-	{
-		/* Send erase setup command */
-		nand->controller->command(nand, NAND_CMD_ERASE1);
-
-		page = i * (nand->erase_size / nand->page_size);
-
-		/* Send page address */
-		if (nand->page_size <= 512)
-		{
-			/* row */
-			nand->controller->address(nand, page & 0xff);
-			nand->controller->address(nand, (page >> 8) & 0xff);
-
-			/* 3rd cycle only on devices with more than 32 MiB */
-			if (nand->address_cycles >= 4)
-				nand->controller->address(nand, (page >> 16) & 0xff);
-
-			/* 4th cycle only on devices with more than 8 GiB */
-			if (nand->address_cycles >= 5)
-				nand->controller->address(nand, (page >> 24) & 0xff);
-		}
-		else
-		{
-			/* row */
-			nand->controller->address(nand, page & 0xff);
-			nand->controller->address(nand, (page >> 8) & 0xff);
-
-			/* 3rd cycle only on devices with more than 128 MiB */
-			if (nand->address_cycles >= 5)
-				nand->controller->address(nand, (page >> 16) & 0xff);
-		}
-
-		/* Send erase confirm command */
-		nand->controller->command(nand, NAND_CMD_ERASE2);
-
-		retval = nand->controller->nand_ready ?
-				nand->controller->nand_ready(nand, 1000) :
-				nand_poll_ready(nand, 1000);
-		if (!retval) {
-			LOG_ERROR("timeout waiting for NAND flash block erase to complete");
-			return ERROR_NAND_OPERATION_TIMEOUT;
-		}
-
-		if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
-		{
-			LOG_ERROR("couldn't read status");
-			return ERROR_NAND_OPERATION_FAILED;
-		}
-
-		if (status & 0x1)
-		{
-			LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
-					(nand->blocks[i].is_bad == 1)
-						? "bad " : "",
-					i, status);
-			/* continue; other blocks might still be erasable */
-		}
-
-		nand->blocks[i].is_erased = 1;
-	}
-
-	return ERROR_OK;
-}
-
-#if 0
-static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
-{
-	uint8_t *page;
-
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	if (address % nand->page_size)
-	{
-		LOG_ERROR("reads need to be page aligned");
-		return ERROR_NAND_OPERATION_FAILED;
-	}
-
-	page = malloc(nand->page_size);
-
-	while (data_size > 0)
-	{
-		uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
-		uint32_t page_address;
-
-
-		page_address = address / nand->page_size;
-
-		nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
-
-		memcpy(data, page, thisrun_size);
-
-		address += thisrun_size;
-		data += thisrun_size;
-		data_size -= thisrun_size;
-	}
-
-	free(page);
-
-	return ERROR_OK;
-}
-
-static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
-{
-	uint8_t *page;
-
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	if (address % nand->page_size)
-	{
-		LOG_ERROR("writes need to be page aligned");
-		return ERROR_NAND_OPERATION_FAILED;
-	}
-
-	page = malloc(nand->page_size);
-
-	while (data_size > 0)
-	{
-		uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
-		uint32_t page_address;
-
-		memset(page, 0xff, nand->page_size);
-		memcpy(page, data, thisrun_size);
-
-		page_address = address / nand->page_size;
-
-		nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
-
-		address += thisrun_size;
-		data += thisrun_size;
-		data_size -= thisrun_size;
-	}
-
-	free(page);
-
-	return ERROR_OK;
-}
-#endif
-
-int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
-{
-	uint32_t block;
-
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	block = page / (nand->erase_size / nand->page_size);
-	if (nand->blocks[block].is_erased == 1)
-		nand->blocks[block].is_erased = 0;
-
-	if (nand->use_raw || nand->controller->write_page == NULL)
-		return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
-	else
-		return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
-}
-
-static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
-{
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	if (nand->use_raw || nand->controller->read_page == NULL)
-		return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
-	else
-		return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
-}
-
-int nand_page_command(struct nand_device *nand, uint32_t page,
-		uint8_t cmd, bool oob_only)
-{
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	if (oob_only && NAND_CMD_READ0 == cmd && nand->page_size <= 512)
-		cmd = NAND_CMD_READOOB;
-
-	nand->controller->command(nand, cmd);
-
-	if (nand->page_size <= 512) {
-		/* small page device */
-
-		/* column (always 0, we start at the beginning of a page/OOB area) */
-		nand->controller->address(nand, 0x0);
-
-		/* row */
-		nand->controller->address(nand, page & 0xff);
-		nand->controller->address(nand, (page >> 8) & 0xff);
-
-		/* 4th cycle only on devices with more than 32 MiB */
-		if (nand->address_cycles >= 4)
-			nand->controller->address(nand, (page >> 16) & 0xff);
-
-		/* 5th cycle only on devices with more than 8 GiB */
-		if (nand->address_cycles >= 5)
-			nand->controller->address(nand, (page >> 24) & 0xff);
-	} else {
-		/* large page device */
-
-		/* column (0 when we start at the beginning of a page,
-		 * or 2048 for the beginning of OOB area)
-		 */
-		nand->controller->address(nand, 0x0);
-		if (oob_only)
-			nand->controller->address(nand, 0x8);
-		else
-			nand->controller->address(nand, 0x0);
-
-		/* row */
-		nand->controller->address(nand, page & 0xff);
-		nand->controller->address(nand, (page >> 8) & 0xff);
-
-		/* 5th cycle only on devices with more than 128 MiB */
-		if (nand->address_cycles >= 5)
-			nand->controller->address(nand, (page >> 16) & 0xff);
-
-		/* large page devices need a start command if reading */
-		if (NAND_CMD_READ0 == cmd)
-			nand->controller->command(nand, NAND_CMD_READSTART);
-	}
-
-	if (nand->controller->nand_ready) {
-		if (!nand->controller->nand_ready(nand, 100))
-			return ERROR_NAND_OPERATION_TIMEOUT;
-	} else {
-		alive_sleep(1);
-	}
-
-	return ERROR_OK;
-}
-
-int nand_read_page_raw(struct nand_device *nand, uint32_t page,
-		uint8_t *data, uint32_t data_size,
-		uint8_t *oob, uint32_t oob_size)
-{
-	uint32_t i;
-	int retval;
-
-	retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (data)
-	{
-		if (nand->controller->read_block_data != NULL)
-			(nand->controller->read_block_data)(nand, data, data_size);
-		else
-		{
-			for (i = 0; i < data_size;)
-			{
-				if (nand->device->options & NAND_BUSWIDTH_16)
-				{
-					nand->controller->read_data(nand, data);
-					data += 2;
-					i += 2;
-				}
-				else
-				{
-					nand->controller->read_data(nand, data);
-					data += 1;
-					i += 1;
-				}
-			}
-		}
-	}
-
-	if (oob)
-	{
-		if (nand->controller->read_block_data != NULL)
-			(nand->controller->read_block_data)(nand, oob, oob_size);
-		else
-		{
-			for (i = 0; i < oob_size;)
-			{
-				if (nand->device->options & NAND_BUSWIDTH_16)
-				{
-					nand->controller->read_data(nand, oob);
-					oob += 2;
-					i += 2;
-				}
-				else
-				{
-					nand->controller->read_data(nand, oob);
-					oob += 1;
-					i += 1;
-				}
-			}
-		}
-	}
-
-	return ERROR_OK;
-}
-
-int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
-{
-	uint32_t i;
-	int retval;
-	uint8_t status;
-
-	retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (data)
-	{
-		if (nand->controller->write_block_data != NULL)
-			(nand->controller->write_block_data)(nand, data, data_size);
-		else
-		{
-			for (i = 0; i < data_size;)
-			{
-				if (nand->device->options & NAND_BUSWIDTH_16)
-				{
-					uint16_t data_buf = le_to_h_u16(data);
-					nand->controller->write_data(nand, data_buf);
-					data += 2;
-					i += 2;
-				}
-				else
-				{
-					nand->controller->write_data(nand, *data);
-					data += 1;
-					i += 1;
-				}
-			}
-		}
-	}
-
-	if (oob)
-	{
-		if (nand->controller->write_block_data != NULL)
-			(nand->controller->write_block_data)(nand, oob, oob_size);
-		else
-		{
-			for (i = 0; i < oob_size;)
-			{
-				if (nand->device->options & NAND_BUSWIDTH_16)
-				{
-					uint16_t oob_buf = le_to_h_u16(data);
-					nand->controller->write_data(nand, oob_buf);
-					oob += 2;
-					i += 2;
-				}
-				else
-				{
-					nand->controller->write_data(nand, *oob);
-					oob += 1;
-					i += 1;
-				}
-			}
-		}
-	}
-
-	nand->controller->command(nand, NAND_CMD_PAGEPROG);
-
-	retval = nand->controller->nand_ready ?
-			nand->controller->nand_ready(nand, 100) :
-			nand_poll_ready(nand, 100);
-	if (!retval)
-		return ERROR_NAND_OPERATION_TIMEOUT;
-
-	if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
-	{
-		LOG_ERROR("couldn't read status");
-		return ERROR_NAND_OPERATION_FAILED;
-	}
-
-	if (status & NAND_STATUS_FAIL)
-	{
-		LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
-		return ERROR_NAND_OPERATION_FAILED;
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_list_command)
-{
-	struct nand_device *p;
-	int i;
-
-	if (!nand_devices)
-	{
-		command_print(CMD_CTX, "no NAND flash devices configured");
-		return ERROR_OK;
-	}
-
-	for (p = nand_devices, i = 0; p; p = p->next, i++)
-	{
-		if (p->device)
-			command_print(CMD_CTX, "#%i: %s (%s) "
-				"pagesize: %i, buswidth: %i,\n\t"
-				"blocksize: %i, blocks: %i",
-				i, p->device->name, p->manufacturer->name,
-				p->page_size, p->bus_width,
-				p->erase_size, p->num_blocks);
-		else
-			command_print(CMD_CTX, "#%i: not probed", i);
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_info_command)
-{
-	int i = 0;
-	int j = 0;
-	int first = -1;
-	int last = -1;
-
-	switch (CMD_ARGC) {
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	case 1:
-		first = 0;
-		last = INT32_MAX;
-		break;
-	case 2:
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
-		first = last = i;
-		i = 0;
-		break;
-	case 3:
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
-		break;
-	}
-
-	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (NULL == p->device)
-	{
-		command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	if (first >= p->num_blocks)
-		first = p->num_blocks - 1;
-
-	if (last >= p->num_blocks)
-		last = p->num_blocks - 1;
-
-	command_print(CMD_CTX, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
-		i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
-
-	for (j = first; j <= last; j++)
-	{
-		char *erase_state, *bad_state;
-
-		if (p->blocks[j].is_erased == 0)
-			erase_state = "not erased";
-		else if (p->blocks[j].is_erased == 1)
-			erase_state = "erased";
-		else
-			erase_state = "erase state unknown";
-
-		if (p->blocks[j].is_bad == 0)
-			bad_state = "";
-		else if (p->blocks[j].is_bad == 1)
-			bad_state = " (marked bad)";
-		else
-			bad_state = " (block condition unknown)";
-
-		command_print(CMD_CTX,
-			      "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
-			      j,
-			      p->blocks[j].offset,
-			      p->blocks[j].size / 1024,
-			      erase_state,
-			      bad_state);
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_probe_command)
-{
-	if (CMD_ARGC != 1)
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if ((retval = nand_probe(p)) == ERROR_OK)
-	{
-		command_print(CMD_CTX, "NAND flash device '%s' found", p->device->name);
-	}
-	else if (retval == ERROR_NAND_OPERATION_FAILED)
-	{
-		command_print(CMD_CTX, "probing failed for NAND flash device");
-	}
-	else
-	{
-		command_print(CMD_CTX, "unknown error when probing NAND flash device");
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_erase_command)
-{
-	if (CMD_ARGC != 1 && CMD_ARGC != 3)
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	}
-
-	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
-	if (ERROR_OK != retval)
-		return retval;
-
-	unsigned long offset;
-	unsigned long length;
-
-	/* erase specified part of the chip; or else everything */
-	if (CMD_ARGC == 3) {
-		unsigned long size = p->erase_size * p->num_blocks;
-
-		COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
-		if ((offset % p->erase_size) != 0 || offset >= size)
-			return ERROR_INVALID_ARGUMENTS;
-
-		COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
-		if ((length == 0) || (length % p->erase_size) != 0
-				|| (length + offset) > size)
-			return ERROR_INVALID_ARGUMENTS;
-
-		offset /= p->erase_size;
-		length /= p->erase_size;
-	} else {
-		offset = 0;
-		length = p->num_blocks;
-	}
-
-	retval = nand_erase(p, offset, offset + length - 1);
-	if (retval == ERROR_OK)
-	{
-		command_print(CMD_CTX, "erased blocks %lu to %lu "
-				"on NAND flash device #%s '%s'",
-				offset, offset + length,
-				CMD_ARGV[0], p->device->name);
-	}
-	else if (retval == ERROR_NAND_OPERATION_FAILED)
-	{
-		command_print(CMD_CTX, "erase failed");
-	}
-	else
-	{
-		command_print(CMD_CTX, "unknown error when erasing NAND flash device");
-	}
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
-{
-	int first = -1;
-	int last = -1;
-
-	if ((CMD_ARGC < 1) || (CMD_ARGC > 3) || (CMD_ARGC == 2))
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	}
-
-	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (CMD_ARGC == 3)
-	{
-		unsigned long offset;
-		unsigned long length;
-
-		COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
-		if (offset % p->erase_size)
-			return ERROR_INVALID_ARGUMENTS;
-		offset /= p->erase_size;
-
-		COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
-		if (length % p->erase_size)
-			return ERROR_INVALID_ARGUMENTS;
-
-		length -= 1;
-		length /= p->erase_size;
-
-		first = offset;
-		last = offset + length;
-	}
-
-	retval = nand_build_bbt(p, first, last);
-	if (retval == ERROR_OK)
-	{
-		command_print(CMD_CTX, "checked NAND flash device for bad blocks, "
-				"use \"nand info\" command to list blocks");
-	}
-	else if (retval == ERROR_NAND_OPERATION_FAILED)
-	{
-		command_print(CMD_CTX, "error when checking for bad blocks on "
-				"NAND flash device");
-	}
-	else
-	{
-		command_print(CMD_CTX, "unknown error when checking for bad "
-				"blocks on NAND flash device");
-	}
-
-	return ERROR_OK;
-}
-
-struct nand_fileio_state {
-	uint32_t address;
-	uint32_t size;
-
-	uint8_t *page;
-	uint32_t page_size;
-
-	enum oob_formats oob_format;
-	uint8_t *oob;
-	uint32_t oob_size;
-
-	const int *eccpos;
-
-	bool file_opened;
-	struct fileio fileio;
-
-	struct duration bench;
-};
-
-static void nand_fileio_init(struct nand_fileio_state *state)
-{
-	memset(state, 0, sizeof(*state));
-	state->oob_format = NAND_OOB_NONE;
-}
-
-static int nand_fileio_start(struct command_context *cmd_ctx,
-		struct nand_device *nand, const char *filename, int filemode,
-		struct nand_fileio_state *state)
-{
-	if (state->address % nand->page_size)
-	{
-		command_print(cmd_ctx, "only page-aligned addresses are supported");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	duration_start(&state->bench);
-
-	if (NULL != filename)
-	{
-		int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
-		if (ERROR_OK != retval)
-		{
-			const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
-			command_print(cmd_ctx, "failed to open '%s' for %s access",
-					filename, msg);
-			return retval;
-		}
-		state->file_opened = true;
-	}
-
-	if (!(state->oob_format & NAND_OOB_ONLY))
-	{
-		state->page_size = nand->page_size;
-		state->page = malloc(nand->page_size);
-	}
-
-	if (state->oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
-	{
-		if (nand->page_size == 512)
-		{
-			state->oob_size = 16;
-			state->eccpos = nand_oob_16.eccpos;
-		}
-		else if (nand->page_size == 2048)
-		{
-			state->oob_size = 64;
-			state->eccpos = nand_oob_64.eccpos;
-		}
-		state->oob = malloc(state->oob_size);
-	}
-
-	return ERROR_OK;
-}
-static int nand_fileio_cleanup(struct nand_fileio_state *state)
-{
-	if (state->file_opened)
-		fileio_close(&state->fileio);
-
-	if (state->oob)
-	{
-		free(state->oob);
-		state->oob = NULL;
-	}
-	if (state->page)
-	{
-		free(state->page);
-		state->page = NULL;
-	}
-	return ERROR_OK;
-}
-static int nand_fileio_finish(struct nand_fileio_state *state)
-{
-	nand_fileio_cleanup(state);
-	return duration_measure(&state->bench);
-}
-
-static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
-		struct nand_device **dev, enum fileio_access filemode,
-		bool need_size, bool sw_ecc)
-{
-	nand_fileio_init(state);
-
-	unsigned minargs = need_size ? 4 : 3;
-	if (CMD_ARGC < minargs)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	struct nand_device *nand;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (NULL == nand->device)
-	{
-		command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
-	if (need_size)
-	{
-			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], state->size);
-			if (state->size % nand->page_size)
-			{
-				command_print(CMD_CTX, "only page-aligned sizes are supported");
-				return ERROR_COMMAND_SYNTAX_ERROR;
-			}
-	}
-
-	if (CMD_ARGC > minargs)
-	{
-		for (unsigned i = minargs; i < CMD_ARGC; i++)
-		{
-			if (!strcmp(CMD_ARGV[i], "oob_raw"))
-				state->oob_format |= NAND_OOB_RAW;
-			else if (!strcmp(CMD_ARGV[i], "oob_only"))
-				state->oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
-			else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc"))
-				state->oob_format |= NAND_OOB_SW_ECC;
-			else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc_kw"))
-				state->oob_format |= NAND_OOB_SW_ECC_KW;
-			else
-			{
-				command_print(CMD_CTX, "unknown option: %s", CMD_ARGV[i]);
-				return ERROR_COMMAND_SYNTAX_ERROR;
-			}
-		}
-	}
-
-	retval = nand_fileio_start(CMD_CTX, nand, CMD_ARGV[1], filemode, state);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (!need_size)
-		state->size = state->fileio.size;
-
-	*dev = nand;
-
-	return ERROR_OK;
-}
-
-/**
- * @returns If no error occurred, returns number of bytes consumed;
- * otherwise, returns a negative error code.)
- */
-static int nand_fileio_read(struct nand_device *nand,
-		struct nand_fileio_state *s)
-{
-	size_t total_read = 0;
-	size_t one_read;
-
-	if (NULL != s->page)
-	{
-		fileio_read(&s->fileio, s->page_size, s->page, &one_read);
-		if (one_read < s->page_size)
-			memset(s->page + one_read, 0xff, s->page_size - one_read);
-		total_read += one_read;
-	}
-
-	if (s->oob_format & NAND_OOB_SW_ECC)
-	{
-		uint8_t ecc[3];
-		memset(s->oob, 0xff, s->oob_size);
-		for (uint32_t i = 0, j = 0; i < s->page_size; i += 256)
-		{
-			nand_calculate_ecc(nand, s->page + i, ecc);
-			s->oob[s->eccpos[j++]] = ecc[0];
-			s->oob[s->eccpos[j++]] = ecc[1];
-			s->oob[s->eccpos[j++]] = ecc[2];
-		}
-	}
-	else if (s->oob_format & NAND_OOB_SW_ECC_KW)
-	{
-		/*
-		 * In this case eccpos is not used as
-		 * the ECC data is always stored contigously
-		 * at the end of the OOB area.  It consists
-		 * of 10 bytes per 512-byte data block.
-		 */
-		uint8_t *ecc = s->oob + s->oob_size - s->page_size / 512 * 10;
-		memset(s->oob, 0xff, s->oob_size);
-		for (uint32_t i = 0; i < s->page_size; i += 512)
-		{
-			nand_calculate_ecc_kw(nand, s->page + i, ecc);
-			ecc += 10;
-		}
-	}
-	else if (NULL != s->oob)
-	{
-		fileio_read(&s->fileio, s->oob_size, s->oob, &one_read);
-		if (one_read < s->oob_size)
-			memset(s->oob + one_read, 0xff, s->oob_size - one_read);
-		total_read += one_read;
-	}
-	return total_read;
-}
-
-COMMAND_HANDLER(handle_nand_write_command)
-{
-	struct nand_device *nand = NULL;
-	struct nand_fileio_state s;
-	int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
-			&s, &nand, FILEIO_READ, false, true);
-	if (ERROR_OK != retval)
-		return retval;
-
-	uint32_t total_bytes = s.size;
-	while (s.size > 0)
-	{
-		int bytes_read = nand_fileio_read(nand, &s);
-		if (bytes_read <= 0)
-		{
-			command_print(CMD_CTX, "error while reading file");
-			return nand_fileio_cleanup(&s);
-		}
-		s.size -= bytes_read;
-
-		retval = nand_write_page(nand, s.address / nand->page_size,
-				s.page, s.page_size, s.oob, s.oob_size);
-		if (ERROR_OK != retval)
-		{
-			command_print(CMD_CTX, "failed writing file %s "
-				"to NAND flash %s at offset 0x%8.8" PRIx32,
-				CMD_ARGV[1], CMD_ARGV[0], s.address);
-			return nand_fileio_cleanup(&s);
-		}
-		s.address += s.page_size;
-	}
-
-	if (nand_fileio_finish(&s))
-	{
-		command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
-				"offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
-				CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
-				duration_kbps(&s.bench, total_bytes));
-	}
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_verify_command)
-{
-	struct nand_device *nand = NULL;
-	struct nand_fileio_state file;
-	int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
-			&file, &nand, FILEIO_READ, false, true);
-	if (ERROR_OK != retval)
-		return retval;
-
-	struct nand_fileio_state dev;
-	nand_fileio_init(&dev);
-	dev.address = file.address;
-	dev.size = file.size;
-	dev.oob_format = file.oob_format;
-	retval = nand_fileio_start(CMD_CTX, nand, NULL, FILEIO_NONE, &dev);
-	if (ERROR_OK != retval)
-		return retval;
-
-	while (file.size > 0)
-	{
-		int retval = nand_read_page(nand, dev.address / dev.page_size,
-				dev.page, dev.page_size, dev.oob, dev.oob_size);
-		if (ERROR_OK != retval)
-		{
-			command_print(CMD_CTX, "reading NAND flash page failed");
-			nand_fileio_cleanup(&dev);
-			return nand_fileio_cleanup(&file);
-		}
-
-		int bytes_read = nand_fileio_read(nand, &file);
-		if (bytes_read <= 0)
-		{
-			command_print(CMD_CTX, "error while reading file");
-			nand_fileio_cleanup(&dev);
-			return nand_fileio_cleanup(&file);
-		}
-
-		if ((dev.page && memcmp(dev.page, file.page, dev.page_size)) ||
-		    (dev.oob && memcmp(dev.oob, file.oob, dev.oob_size)) )
-		{
-			command_print(CMD_CTX, "NAND flash contents differ "
-						"at 0x%8.8" PRIx32, dev.address);
-			nand_fileio_cleanup(&dev);
-			return nand_fileio_cleanup(&file);
-		}
-
-		file.size -= bytes_read;
-		dev.address += nand->page_size;
-	}
-
-	if (nand_fileio_finish(&file) == ERROR_OK)
-	{
-		command_print(CMD_CTX, "verified file %s in NAND flash %s "
-				"up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
-				CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
-				duration_kbps(&file.bench, dev.size));
-	}
-
-	return nand_fileio_cleanup(&dev);
-}
-
-COMMAND_HANDLER(handle_nand_dump_command)
-{
-	struct nand_device *nand = NULL;
-	struct nand_fileio_state s;
-	int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
-			&s, &nand, FILEIO_WRITE, true, false);
-	if (ERROR_OK != retval)
-		return retval;
-
-	while (s.size > 0)
-	{
-		size_t size_written;
-		int retval = nand_read_page(nand, s.address / nand->page_size,
-				s.page, s.page_size, s.oob, s.oob_size);
-		if (ERROR_OK != retval)
-		{
-			command_print(CMD_CTX, "reading NAND flash page failed");
-			return nand_fileio_cleanup(&s);
-		}
-
-		if (NULL != s.page)
-			fileio_write(&s.fileio, s.page_size, s.page, &size_written);
-
-		if (NULL != s.oob)
-			fileio_write(&s.fileio, s.oob_size, s.oob, &size_written);
-
-		s.size -= nand->page_size;
-		s.address += nand->page_size;
-	}
-
-	if (nand_fileio_finish(&s) == ERROR_OK)
-	{
-		command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)", 
-				s.fileio.size, duration_elapsed(&s.bench),
-				duration_kbps(&s.bench, s.fileio.size));
-	}
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_nand_raw_access_command)
-{
-	if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	struct nand_device *p;
-	int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
-	if (ERROR_OK != retval)
-		return retval;
-
-	if (NULL == p->device)
-	{
-		command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
-		return ERROR_OK;
-	}
-
-	if (CMD_ARGC == 2)
-		COMMAND_PARSE_ENABLE(CMD_ARGV[1], p->use_raw);
-
-	const char *msg = p->use_raw ? "enabled" : "disabled";
-	command_print(CMD_CTX, "raw access is %s", msg);
-
-	return ERROR_OK;
-}
-
-static const struct command_registration nand_exec_command_handlers[] = {
-	{
-		.name = "list",
-		.handler = &handle_nand_list_command,
-		.mode = COMMAND_EXEC,
-		.help = "list configured NAND flash devices",
-	},
-	{
-		.name = "info",
-		.handler = &handle_nand_info_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank>",
-		.help = "print info about a NAND flash device",
-	},
-	{
-		.name = "probe",
-		.handler = &handle_nand_probe_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank>",
-		.help = "identify NAND flash device <num>",
-
-	},
-	{
-		.name = "check_bad_blocks",
-		.handler = &handle_nand_check_bad_blocks_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank> [<offset> <length>]",
-		.help = "check NAND flash device <num> for bad blocks",
-	},
-	{
-		.name = "erase",
-		.handler = &handle_nand_erase_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank> [<offset> <length>]",
-		.help = "erase blocks on NAND flash device",
-	},
-	{
-		.name = "dump",
-		.handler = &handle_nand_dump_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank> <filename> <offset> <length> "
-			"[oob_raw | oob_only]",
-		.help = "dump from NAND flash device",
-	},
-	{
-		.name = "verify",
-		.handler = &handle_nand_verify_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank> <filename> <offset> "
-			"[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
-		.help = "verify NAND flash device",
-	},
-	{
-		.name = "write",
-		.handler = &handle_nand_write_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<bank> <filename> <offset> "
-			"[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
-		.help = "write to NAND flash device",
-	},
-	{
-		.name = "raw_access",
-		.handler = &handle_nand_raw_access_command,
-		.mode = COMMAND_EXEC,
-		.usage = "<num> ['enable'|'disable']",
-		.help = "raw access to NAND flash device",
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-int nand_init(struct command_context *cmd_ctx)
-{
-	if (!nand_devices)
-		return ERROR_OK;
-	struct command *parent = command_find_in_context(cmd_ctx, "nand");
-	return register_commands(cmd_ctx, parent, nand_exec_command_handlers);
-}
-
-COMMAND_HANDLER(handle_nand_init_command)
-{
-	if (CMD_ARGC != 0)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	static bool nand_initialized = false;
-	if (nand_initialized)
-	{
-		LOG_INFO("'nand init' has already been called");
-		return ERROR_OK;
-	}
-	nand_initialized = true;
-
-	LOG_DEBUG("Initializing NAND devices...");
-	return nand_init(CMD_CTX);
-}
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index 7d250f6..3885a7b 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -3,6 +3,9 @@ AM_CPPFLAGS = -I$(top_srcdir)/src
 noinst_LTLIBRARIES = libocdflashnand.la
 
 libocdflashnand_la_SOURCES = \
+	core.c \
+	fileio.c \
+	tcl.c \
 	$(NAND_DRIVERS) \
 	driver.c
 
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
new file mode 100644
index 0000000..46f5454
--- /dev/null
+++ b/src/flash/nand/core.c
@@ -0,0 +1,917 @@
+/***************************************************************************
+ *   Copyright (C) 2007 by Dominic Rath <Dom...@gm...>              *
+ *   Copyright (C) 2002 Thomas Gleixner <tg...@li...>               *
+ *   Copyright (C) 2009 Zachary T Welch <zw@superlucid...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-877-gaf1d759

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit af1d7590edf04077aa8f22fba9097e0c68431f68
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 20:44:29 2009 -0800

    ARM: doc updates for main header
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 56461e7..a93087e 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,7 +30,8 @@
 #include <helper/command.h>
 
 
-/* These numbers match the five low bits of the *PSR registers on
+/**
+ * These numbers match the five low bits of the *PSR registers on
  * "classic ARM" processors, which build on the ARMv4 processor
  * modes and register set.
  */
@@ -49,7 +50,7 @@ enum arm_mode {
 const char *arm_mode_name(unsigned psr_mode);
 bool is_arm_mode(unsigned psr_mode);
 
-/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
 enum arm_state {
 	ARM_STATE_ARM,
 	ARM_STATE_THUMB,
@@ -95,6 +96,7 @@ struct arm
 	/** Handle to the SPSR; valid only in core modes with an SPSR. */
 	struct reg *spsr;
 
+	/** Support for arm_reg_current() */
 	const int *map;
 
 	/**
@@ -105,7 +107,10 @@ struct arm
 	 */
 	enum arm_mode core_type;
 
+	/** Record the current core mode: SVC, USR, or some other mode. */
 	enum arm_mode core_mode;
+
+	/** Record the current core state: ARM, Thumb, or otherwise. */
 	enum arm_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
@@ -128,7 +133,10 @@ struct arm
 
 	/* FIXME all these methods should take "struct arm *" not target */
 
+	/** Retrieve all core registers, for display. */
 	int (*full_context)(struct target *target);
+
+	/** Retrieve a single core register. */
 	int (*read_core_reg)(struct target *target, struct reg *reg,
 			int num, enum arm_mode mode);
 	int (*write_core_reg)(struct target *target, struct reg *reg,
@@ -140,7 +148,7 @@ struct arm
 			uint32_t CRn, uint32_t CRm,
 			uint32_t *value);
 
-	/* Write coprocessor register.  */
+	/** Write coprocessor register.  */
 	int (*mcr)(struct target *target, int cpnum,
 			uint32_t op1, uint32_t op2,
 			uint32_t CRn, uint32_t CRm,

commit 3edcff8b8efff841dfe601e87f42de7fe7b4792b
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 20:33:02 2009 -0800

    ARM: rename armv4_5_build_reg_cache() as arm_*()
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index a0b12b9..fffc632 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -643,7 +643,7 @@ static void arm7tdmi_build_reg_cache(struct target *target)
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct arm *armv4_5 = target_to_arm(target);
 
-	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+	(*cache_p) = arm_build_reg_cache(target, armv4_5);
 }
 
 int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 10f88f7..09199c7 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -753,7 +753,7 @@ static void arm9tdmi_build_reg_cache(struct target *target)
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
 	struct arm *armv4_5 = target_to_arm(target);
 
-	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+	(*cache_p) = arm_build_reg_cache(target, armv4_5);
 }
 
 int arm9tdmi_init_target(struct command_context *cmd_ctx,
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index b65e922..ff89c47 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -819,7 +819,7 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 	arm->read_core_reg = arm_dpm_read_core_reg;
 	arm->write_core_reg = arm_dpm_write_core_reg;
 
-	cache = armv4_5_build_reg_cache(target, arm);
+	cache = arm_build_reg_cache(target, arm);
 	if (!cache)
 		return ERROR_FAIL;
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index e07f606..ad89b2f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -533,7 +533,7 @@ static const struct reg_arch_type arm_reg_type = {
 	.set = armv4_5_set_core_reg,
 };
 
-struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
 {
 	int num_regs = ARRAY_SIZE(arm_core_regs);
 	struct reg_cache *cache = malloc(sizeof(struct reg_cache));
@@ -557,7 +557,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 	{
 		/* Skip registers this core doesn't expose */
 		if (arm_core_regs[i].mode == ARM_MODE_MON
-				&& armv4_5_common->core_type != ARM_MODE_MON)
+				&& arm->core_type != ARM_MODE_MON)
 			continue;
 
 		/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -565,7 +565,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		arch_info[i].num = arm_core_regs[i].cookie;
 		arch_info[i].mode = arm_core_regs[i].mode;
 		arch_info[i].target = target;
-		arch_info[i].armv4_5_common = armv4_5_common;
+		arch_info[i].armv4_5_common = arm;
 
 		reg_list[i].name = (char *) arm_core_regs[i].name;
 		reg_list[i].size = 32;
@@ -576,8 +576,8 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 		cache->num_regs++;
 	}
 
-	armv4_5_common->cpsr = reg_list + ARMV4_5_CPSR;
-	armv4_5_common->core_cache = cache;
+	arm->cpsr = reg_list + ARMV4_5_CPSR;
+	arm->core_cache = cache;
 	return cache;
 }
 
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 0b28301..56461e7 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -177,8 +177,7 @@ struct arm_reg
 	uint32_t value;
 };
 
-struct reg_cache* armv4_5_build_reg_cache(struct target *target,
-		struct arm *armv4_5_common);
+struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 
 int armv4_5_arch_state(struct target *target);
 int armv4_5_get_gdb_reg_list(struct target *target,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 352e159..d5b1d63 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2859,7 +2859,7 @@ static void xscale_build_reg_cache(struct target *target)
 	int i;
 	int num_regs = ARRAY_SIZE(xscale_reg_arch_info);
 
-	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+	(*cache_p) = arm_build_reg_cache(target, armv4_5);
 
 	(*cache_p)->next = malloc(sizeof(struct reg_cache));
 	cache_p = &(*cache_p)->next;

commit c2cc677056f8b383ff8f88ed8a16f1aa4b530ae2
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 20:19:49 2009 -0800

    ARM: rename armv4_5_algorithm as arm_algorithm
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 12c4b2f..67619d5 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -93,7 +93,7 @@ int arm_code_to_working_area(struct target *target,
 int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 {
 	struct target		*target = nand->target;
-	struct armv4_5_algorithm	algo;
+	struct arm_algorithm	algo;
 	struct arm		*armv4_5 = target->arch_info;
 	struct reg_param	reg_params[3];
 	uint32_t		target_buf;
@@ -177,7 +177,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 {
 	struct target *target = nand->target;
-	struct armv4_5_algorithm algo;
+	struct arm_algorithm algo;
 	struct arm *armv4_5 = target->arch_info;
 	struct reg_param reg_params[3];
 	uint32_t target_buf;
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index de362cb..57018bb 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -165,7 +165,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
 	struct working_area *source;
 	uint32_t address = bank->base + offset;
 	struct reg_param reg_params[6];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	int retval = ERROR_OK;
 
 	if (((count%2)!=0)||((offset%2)!=0))
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index cffc22a..1ab9341 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1012,7 +1012,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
 	struct cfi_flash_bank *cfi_info = bank->driver_priv;
 	struct target *target = bank->target;
 	struct reg_param reg_params[7];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	struct working_area *source;
 	uint32_t buffer_size = 32768;
 	uint32_t write_command_val, busy_pattern_val, error_pattern_val;
@@ -1257,7 +1257,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
 	struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 	struct target *target = bank->target;
 	struct reg_param reg_params[10];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	struct working_area *source;
 	uint32_t buffer_size = 32768;
 	uint32_t status;
diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index b216903..b51e0a0 100644
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -209,7 +209,7 @@ static int runCode(struct ecosflash_flash_bank *info,
 	struct target *target = info->target;
 
 	struct reg_param reg_params[3];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 6888b76..0caf3e0 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -242,7 +242,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
 	struct target *target = bank->target;
 	struct mem_param mem_params[2];
 	struct reg_param reg_params[5];
-	struct armv4_5_algorithm armv4_5_info; /* for LPC2000 */
+	struct arm_algorithm armv4_5_info; /* for LPC2000 */
 	struct armv7m_algorithm armv7m_info;   /* for LPC1700 */
  	uint32_t status_code;
 	uint32_t iap_entry_point = 0; /* to make compiler happier */
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index 1ef759e..ce74bbb 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -1302,7 +1302,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer,
 	if( warea )
 	{
 		struct reg_param reg_params[5];
-		struct armv4_5_algorithm armv4_5_info;
+		struct arm_algorithm armv4_5_info;
 
 		/* We can use target mode. Download the algorithm. */
 		retval = target_write_buffer( target,
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index 45aa657..ef693e9 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -318,7 +318,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
 	struct working_area *source;
 	uint32_t address = bank->base + offset;
 	struct reg_param reg_params[6];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	int retval = ERROR_OK;
 
 	uint32_t str7x_flash_write_code[] = {
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index 95da3e2..9cddb50 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -356,7 +356,7 @@ static int str9x_write_block(struct flash_bank *bank,
 	struct working_area *source;
 	uint32_t address = bank->base + offset;
 	struct reg_param reg_params[4];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	int retval = ERROR_OK;
 
 	uint32_t str9x_flash_write_code[] = {
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 68005c0..25f8cb3 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2693,7 +2693,7 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
 		}
 	}
 
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	struct reg_param reg_params[1];
 
 	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6941c16..e07f606 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1037,7 +1037,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 				int timeout_ms, void *arch_info))
 {
 	struct arm *armv4_5 = target_to_arm(target);
-	struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
+	struct arm_algorithm *arm_algorithm_info = arch_info;
 	enum arm_state core_state = armv4_5->core_state;
 	uint32_t context[17];
 	uint32_t cpsr;
@@ -1047,7 +1047,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
 	LOG_DEBUG("Running algorithm");
 
-	if (armv4_5_algorithm_info->common_magic != ARM_COMMON_MAGIC)
+	if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("current target isn't an ARMV4/5 target");
 		return ERROR_TARGET_INVALID;
@@ -1077,10 +1077,10 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		struct reg *r;
 
 		r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
-				armv4_5_algorithm_info->core_mode, i);
+				arm_algorithm_info->core_mode, i);
 		if (!r->valid)
 			armv4_5->read_core_reg(target, r, i,
-					armv4_5_algorithm_info->core_mode);
+					arm_algorithm_info->core_mode);
 		context[i] = buf_get_u32(r->value, 0, 32);
 	}
 	cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
@@ -1114,7 +1114,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		}
 	}
 
-	armv4_5->core_state = armv4_5_algorithm_info->core_state;
+	armv4_5->core_state = arm_algorithm_info->core_state;
 	if (armv4_5->core_state == ARM_STATE_ARM)
 		exit_breakpoint_size = 4;
 	else if (armv4_5->core_state == ARM_STATE_THUMB)
@@ -1125,12 +1125,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	if (armv4_5_algorithm_info->core_mode != ARM_MODE_ANY)
+	if (arm_algorithm_info->core_mode != ARM_MODE_ANY)
 	{
 		LOG_DEBUG("setting core_mode: 0x%2.2x",
-				armv4_5_algorithm_info->core_mode);
+				arm_algorithm_info->core_mode);
 		buf_set_u32(armv4_5->cpsr->value, 0, 5,
-				armv4_5_algorithm_info->core_mode);
+				arm_algorithm_info->core_mode);
 		armv4_5->cpsr->dirty = 1;
 		armv4_5->cpsr->valid = 1;
 	}
@@ -1193,13 +1193,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	for (i = 0; i <= 16; i++)
 	{
 		uint32_t regvalue;
-		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
+		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32);
 		if (regvalue != context[i])
 		{
-			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
-			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
-			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).name, context[i]);
+			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).valid = 1;
+			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).dirty = 1;
 		}
 	}
 
@@ -1225,7 +1225,7 @@ int arm_checksum_memory(struct target *target,
 		uint32_t address, uint32_t count, uint32_t *checksum)
 {
 	struct working_area *crc_algorithm;
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	struct reg_param reg_params[2];
 	int retval;
 	uint32_t i;
@@ -1320,7 +1320,7 @@ int arm_blank_check_memory(struct target *target,
 {
 	struct working_area *check_algorithm;
 	struct reg_param reg_params[3];
-	struct armv4_5_algorithm armv4_5_info;
+	struct arm_algorithm armv4_5_info;
 	int retval;
 	uint32_t i;
 
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index b56a1f1..0b28301 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -160,7 +160,7 @@ static inline bool is_arm(struct arm *arm)
 	return arm && arm->common_magic == ARM_COMMON_MAGIC;
 }
 
-struct armv4_5_algorithm
+struct arm_algorithm
 {
 	int common_magic;
 

commit 340e2eb7629fc1fdb6d2ead2952982584abdcefa
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 20:14:46 2009 -0800

    ARM: misc generic cleanup
    
    Remove an undesirable use of the CPSR symbol ... it needs to vanish.
    Flag mode-to-number stuff as obsolete; say why ... should also vanish.
    
    Get rid of no-longer-used mode and state typedefs.
    
    Comment a few of the implicit ties to "classic ARM".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index d71fbae..39625f6 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -379,15 +379,22 @@ static int do_semihosting(struct target *target)
 	}
 
 	/* resume execution to the original mode */
+
+	/* return value in R0 */
 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
 	armv4_5->core_cache->reg_list[0].dirty = 1;
+
+	/* LR --> PC */
 	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
 	armv4_5->core_cache->reg_list[15].dirty = 1;
-	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
-	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+
+	/* saved PSR --> current PSR */
+	buf_set_u32(armv4_5->cpsr->value, 0, 32, spsr);
+	armv4_5->cpsr->dirty = 1;
 	armv4_5->core_mode = spsr & 0x1f;
 	if (spsr & 0x20)
 		armv4_5->core_state = ARM_STATE_THUMB;
+
 	return target_resume(target, 1, 0, 0, 0);
 }
 
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 6a082a5..b56a1f1 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,8 +30,11 @@
 #include <helper/command.h>
 
 
-typedef enum arm_mode
-{
+/* These numbers match the five low bits of the *PSR registers on
+ * "classic ARM" processors, which build on the ARMv4 processor
+ * modes and register set.
+ */
+enum arm_mode {
 	ARM_MODE_USR = 16,
 	ARM_MODE_FIQ = 17,
 	ARM_MODE_IRQ = 18,
@@ -41,24 +44,29 @@ typedef enum arm_mode
 	ARM_MODE_UND = 27,
 	ARM_MODE_SYS = 31,
 	ARM_MODE_ANY = -1
-} arm_mode_t;
+};
 
 const char *arm_mode_name(unsigned psr_mode);
 bool is_arm_mode(unsigned psr_mode);
 
-int arm_mode_to_number(enum arm_mode mode);
-enum arm_mode armv4_5_number_to_mode(int number);
-
-typedef enum arm_state
-{
+/* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
+enum arm_state {
 	ARM_STATE_ARM,
 	ARM_STATE_THUMB,
 	ARM_STATE_JAZELLE,
 	ARM_STATE_THUMB_EE,
-} arm_state_t;
+};
 
 extern const char *arm_state_strings[];
 
+/* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
+ * index into the armv4_5_core_reg_map array.  Its remaining users are
+ * remnants which could as easily walk * the register cache directly as
+ * use the expensive ARMV4_5_CORE_REG_MODE() macro.
+ */
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
+
 extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
diff --git a/src/target/etm.h b/src/target/etm.h
index 92df0bf..5aea657 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -164,7 +164,7 @@ struct etm_context
 	uint32_t trace_depth;		/* number of cycles to be analyzed, 0 if no data available */
 	etm_portmode_t portmode;	/* normal, multiplexed or demultiplexed */
 	etmv1_tracemode_t tracemode;	/* type of info trace contains */
-	int /*arm_state_t*/ core_state;	/* current core state */
+	int /*arm_state*/ core_state;	/* current core state */
 	struct image *image;		/* source for target opcodes */
 	uint32_t pipe_index;		/* current trace cycle */
 	uint32_t data_index;		/* cycle holding next data packet */
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 2bb2ba5..43edeec 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -79,7 +79,7 @@ struct xscale_trace
 	int buffer_fill;				/* maximum number of trace runs to read (-1 for wrap-around) */
 	int pc_ok;
 	uint32_t current_pc;
-	arm_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
+	enum arm_state core_state;	/* current core state (ARM, Thumb) */
 };
 
 struct xscale_common

commit e51b9a4ac7afa0fde11690268ba88861e1000f60
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 19:46:44 2009 -0800

    ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGIC
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 3991c0f..12c4b2f 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -136,7 +136,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 		return retval;
 
 	/* set up algorithm and parameters */
-	algo.common_magic = ARMV4_5_COMMON_MAGIC;
+	algo.common_magic = ARM_COMMON_MAGIC;
 	algo.core_mode = ARM_MODE_SVC;
 	algo.core_state = ARM_STATE_ARM;
 
@@ -212,7 +212,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 	target_buf = nand->copy_area->address + sizeof(code);
 
 	/* set up algorithm and parameters */
-	algo.common_magic = ARMV4_5_COMMON_MAGIC;
+	algo.common_magic = ARM_COMMON_MAGIC;
 	algo.core_mode = ARM_MODE_SVC;
 	algo.core_state = ARM_STATE_ARM;
 
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index 69c8274..de362cb 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -241,7 +241,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
 		}
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 16ba999..cffc22a 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1085,7 +1085,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
 
 	cfi_intel_clear_status_register(bank);
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
@@ -1408,7 +1408,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
 		0xeafffffe 	/* b	8204 <sp_8_done>               */
 	};
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index 2524ae7..b216903 100644
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -210,7 +210,7 @@ static int runCode(struct ecosflash_flash_bank *info,
 
 	struct reg_param reg_params[3];
 	struct armv4_5_algorithm armv4_5_info;
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index c14df1f..6888b76 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -292,7 +292,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
 			break;
 		case lpc2000_v1:
 		case lpc2000_v2:
-			armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+			armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 			armv4_5_info.core_mode = ARM_MODE_SVC;
 			armv4_5_info.core_state = ARM_STATE_ARM;
 			iap_entry_point = 0x7ffffff1;
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index aec8bcd..1ef759e 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -1423,7 +1423,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer,
 			buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time);
 
 			/* Execute algorithm, assume breakpoint for last instruction */
-			armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+			armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 			armv4_5_info.core_mode = ARM_MODE_SVC;
 			armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index 5767b93..45aa657 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -371,7 +371,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
 		}
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index 60367cb..95da3e2 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -408,7 +408,7 @@ static int str9x_write_block(struct flash_bank *bank,
 		}
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 408259e..68005c0 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2696,7 +2696,7 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
 	struct armv4_5_algorithm armv4_5_info;
 	struct reg_param reg_params[1];
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 4fc8c82..6941c16 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -585,7 +585,7 @@ int armv4_5_arch_state(struct target *target)
 {
 	struct arm *armv4_5 = target_to_arm(target);
 
-	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+	if (armv4_5->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("BUG: called for a non-ARM target");
 		return ERROR_FAIL;
@@ -1047,7 +1047,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
 	LOG_DEBUG("Running algorithm");
 
-	if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
+	if (armv4_5_algorithm_info->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("current target isn't an ARMV4/5 target");
 		return ERROR_TARGET_INVALID;
@@ -1273,7 +1273,7 @@ int arm_checksum_memory(struct target *target,
 			return retval;
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
@@ -1350,7 +1350,7 @@ int arm_blank_check_memory(struct target *target,
 			return retval;
 	}
 
-	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
 	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
@@ -1424,7 +1424,7 @@ int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
 	target->arch_info = armv4_5;
 	armv4_5->target = target;
 
-	armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
+	armv4_5->common_magic = ARM_COMMON_MAGIC;
 	arm_set_cpsr(armv4_5, ARM_MODE_USR);
 
 	/* core_type may be overridden by subtype logic */
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 42fbeac..6a082a5 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -67,7 +67,7 @@ extern const int armv4_5_core_reg_map[8][17];
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };
 
-#define ARMV4_5_COMMON_MAGIC 0x0A450A45
+#define ARM_COMMON_MAGIC 0x0A450A45
 
 /**
  * Represents a generic ARM core, with standard application registers.
@@ -149,7 +149,7 @@ static inline struct arm *target_to_arm(struct target *target)
 
 static inline bool is_arm(struct arm *arm)
 {
-	return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
+	return arm && arm->common_magic == ARM_COMMON_MAGIC;
 }
 
 struct armv4_5_algorithm
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 0fa3270..352e159 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -857,7 +857,7 @@ static int xscale_arch_state(struct target *target)
 		"", "\n(processor reset)", "\n(trace buffer full)"
 	};
 
-	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+	if (armv4_5->common_magic != ARM_COMMON_MAGIC)
 	{
 		LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 		return ERROR_INVALID_ARGUMENTS;

commit 87589043faf8cdb954c602c988698c40fcf9c108
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 19:43:03 2009 -0800

    ARM: switch target_to_armv4_5() to target_to_arm()
    
    And remove that old symbol.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 7d14ed6..a0b12b9 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -641,7 +641,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target)
 static void arm7tdmi_build_reg_cache(struct target *target)
 {
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 }
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 6a5faff..305f0de 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -212,7 +212,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 static int arm920t_read_cp15_interpreted(struct target *target,
 		uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	uint32_t* regs_p[1];
 	uint32_t regs[2];
 	uint32_t cp15c15 = 0x0;
@@ -259,7 +259,7 @@ int arm920t_write_cp15_interpreted(struct target *target,
 		uint32_t cp15_opcode, uint32_t value, uint32_t address)
 {
 	uint32_t cp15c15 = 0x0;
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	uint32_t regs[2];
 	struct reg *r = armv4_5->core_cache->reg_list;
 
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 7eb5641..10f88f7 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -751,7 +751,7 @@ void arm9tdmi_disable_single_step(struct target *target)
 static void arm9tdmi_build_reg_cache(struct target *target)
 {
 	struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 }
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index dd6a669..d71fbae 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -43,7 +43,7 @@
 
 static int do_semihosting(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
 	uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
 	uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARM_MODE_SVC, 14).value, 0, 32);
@@ -406,7 +406,7 @@ static int do_semihosting(struct target *target)
  */
 int arm_semihosting(struct target *target, int *retval)
 {
-	struct arm *arm = target_to_armv4_5(target);
+	struct arm *arm = target_to_arm(target);
 	uint32_t lr, spsr;
 	struct reg *r;
 
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index cb1f651..443f29b 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -850,7 +850,7 @@ static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
 
 int arm_simulate_step(struct target *target, uint32_t *dry_run_pc)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	struct arm_sim_interface sim;
 
 	sim.user_data = armv4_5;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 102913b..4fc8c82 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -491,7 +491,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 {
 	struct arm_reg *armv4_5 = reg->arch_info;
 	struct target *target = armv4_5->target;
-	struct arm *armv4_5_target = target_to_armv4_5(target);
+	struct arm *armv4_5_target = target_to_arm(target);
 	uint32_t value = buf_get_u32(buf, 0, 32);
 
 	if (target->state != TARGET_HALTED)
@@ -583,7 +583,7 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
 
 int armv4_5_arch_state(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 	{
@@ -611,7 +611,7 @@ int armv4_5_arch_state(struct target *target)
 COMMAND_HANDLER(handle_armv4_5_reg_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	unsigned num_regs;
 	struct reg *regs;
 
@@ -698,7 +698,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 COMMAND_HANDLER(handle_armv4_5_core_state_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	if (!is_arm(armv4_5))
 	{
@@ -974,7 +974,7 @@ const struct command_registration arm_command_handlers[] = {
 
 int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	int i;
 
 	if (!is_arm_mode(armv4_5->core_mode))
@@ -999,7 +999,7 @@ int armv4_5_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
 static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
 {
 	int retval;
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
 	{
@@ -1036,7 +1036,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		int (*run_it)(struct target *target, uint32_t exit_point,
 				int timeout_ms, void *arch_info))
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
 	enum arm_state core_state = armv4_5->core_state;
 	uint32_t context[17];
@@ -1388,7 +1388,7 @@ int arm_blank_check_memory(struct target *target,
 
 static int arm_full_context(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	unsigned num_regs = armv4_5->core_cache->num_regs;
 	struct reg *reg = armv4_5->core_cache->reg_list;
 	int retval = ERROR_OK;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 5d58aa3..42fbeac 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -141,8 +141,6 @@ struct arm
 	void *arch_info;
 };
 
-#define target_to_armv4_5 target_to_arm
-
 /** Convert target handle to generic ARM target state handle. */
 static inline struct arm *target_to_arm(struct target *target)
 {
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 253decb..0fa3270 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1429,7 +1429,7 @@ static int xscale_step_inner(struct target *target, int current,
 static int xscale_step(struct target *target, int current,
 		uint32_t address, int handle_breakpoints)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 	struct breakpoint *breakpoint = target->breakpoints;
 
 	uint32_t current_pc;
@@ -1675,7 +1675,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r,
 
 static int xscale_full_context(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	uint32_t *buffer;
 
@@ -1757,7 +1757,7 @@ static int xscale_full_context(struct target *target)
 
 static int xscale_restore_banked(struct target *target)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *armv4_5 = target_to_arm(target);
 
 	int i, j;
 

commit 56e01714203406b50b40dd7738983e3b019d4df2
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 19:39:25 2009 -0800

    ARM: rename armv4_5_state_* as arm_state_*
    
    And make arm_state_strings[] be const.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index a4d274e..48cfdf0 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -237,7 +237,7 @@ static int arm720t_arch_state(struct target *target)
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, Cache: %s",
-			 armv4_5_state_strings[armv4_5->core_state],
+			 arm_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 			 arm_mode_name(armv4_5->core_mode),
 			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index e8c1950..6a5faff 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -451,7 +451,7 @@ int arm920t_arch_state(struct target *target)
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 armv4_5_state_strings[armv4_5->core_state],
+			 arm_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
 			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 4dec23d..cacb942 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -507,7 +507,7 @@ int arm926ejs_arch_state(struct target *target)
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 armv4_5_state_strings[armv4_5->core_state],
+			 arm_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
 			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index c252b44..cb1f651 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -824,14 +824,14 @@ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bit
 	return buf_get_u32(armv4_5->cpsr->value, pos, bits);
 }
 
-static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim)
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
 	return armv4_5->core_state;
 }
 
-static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode)
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
diff --git a/src/target/arm_simulator.h b/src/target/arm_simulator.h
index ae3afad..bd5458e 100644
--- a/src/target/arm_simulator.h
+++ b/src/target/arm_simulator.h
@@ -32,8 +32,8 @@ struct arm_sim_interface
 	uint32_t (*get_reg_mode)(struct arm_sim_interface *sim, int reg);
 	void (*set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value);
 	uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
-	enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
-	void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
+	enum arm_state (*get_state)(struct arm_sim_interface *sim);
+	void (*set_state)(struct arm_sim_interface *sim, enum arm_state mode);
 	enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
 };
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 15c0a7f..102913b 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -216,7 +216,7 @@ enum arm_mode armv4_5_number_to_mode(int number)
 	}
 }
 
-char* armv4_5_state_strings[] =
+const char *arm_state_strings[] =
 {
 	"ARM", "Thumb", "Jazelle", "ThumbEE",
 };
@@ -374,7 +374,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 			: arm->core_cache->reg_list + arm->map[16];
 
 	/* Older ARMs won't have the J bit */
-	enum armv4_5_state state;
+	enum arm_state state;
 
 	if (cpsr & (1 << 5)) {	/* T */
 		if (cpsr & (1 << 24)) {	/* J */
@@ -393,7 +393,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 
 	LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
 			arm_mode_name(mode),
-			armv4_5_state_strings[arm->core_state]);
+			arm_state_strings[arm->core_state]);
 }
 
 /**
@@ -593,7 +593,7 @@ int armv4_5_arch_state(struct target *target)
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
-			 armv4_5_state_strings[armv4_5->core_state],
+			 arm_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
 					target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
@@ -718,7 +718,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 		}
 	}
 
-	command_print(CMD_CTX, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
+	command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]);
 
 	return ERROR_OK;
 }
@@ -1038,7 +1038,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 {
 	struct arm *armv4_5 = target_to_armv4_5(target);
 	struct armv4_5_algorithm *armv4_5_algorithm_info = arch_info;
-	enum armv4_5_state core_state = armv4_5->core_state;
+	enum arm_state core_state = armv4_5->core_state;
 	uint32_t context[17];
 	uint32_t cpsr;
 	int exit_breakpoint_size = 0;
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index e2b7b5a..5d58aa3 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -49,15 +49,15 @@ bool is_arm_mode(unsigned psr_mode);
 int arm_mode_to_number(enum arm_mode mode);
 enum arm_mode armv4_5_number_to_mode(int number);
 
-typedef enum armv4_5_state
+typedef enum arm_state
 {
 	ARM_STATE_ARM,
 	ARM_STATE_THUMB,
 	ARM_STATE_JAZELLE,
 	ARM_STATE_THUMB_EE,
-} armv4_5_state_t;
+} arm_state_t;
 
-extern char* armv4_5_state_strings[];
+extern const char *arm_state_strings[];
 
 extern const int armv4_5_core_reg_map[8][17];
 
@@ -98,7 +98,7 @@ struct arm
 	enum arm_mode core_type;
 
 	enum arm_mode core_mode;
-	enum armv4_5_state core_state;
+	enum arm_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
@@ -159,7 +159,7 @@ struct armv4_5_algorithm
 	int common_magic;
 
 	enum arm_mode core_mode;
-	enum armv4_5_state core_state;
+	enum arm_state core_state;
 };
 
 struct arm_reg
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index ad1f094..24ec819 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -119,7 +119,7 @@ struct armv7a_algorithm
 	int common_magic;
 
 	enum arm_mode core_mode;
-	enum armv4_5_state core_state;
+	enum arm_state core_state;
 };
 
 struct armv7a_core_reg
diff --git a/src/target/etm.h b/src/target/etm.h
index 656e04b..92df0bf 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -164,7 +164,7 @@ struct etm_context
 	uint32_t trace_depth;		/* number of cycles to be analyzed, 0 if no data available */
 	etm_portmode_t portmode;	/* normal, multiplexed or demultiplexed */
 	etmv1_tracemode_t tracemode;	/* type of info trace contains */
-	int /*armv4_5_state_t*/ core_state;	/* current core state */
+	int /*arm_state_t*/ core_state;	/* current core state */
 	struct image *image;		/* source for target opcodes */
 	uint32_t pipe_index;		/* current trace cycle */
 	uint32_t data_index;		/* cycle holding next data packet */
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 2644560..1c70154 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -455,7 +455,7 @@ int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t
 	int retval;
 	struct arm *armv4_5 = target->arch_info;
 	struct arm7_9_common *arm7_9 = armv4_5->arch_info;
-	enum armv4_5_state core_state = armv4_5->core_state;
+	enum arm_state core_state = armv4_5->core_state;
 	uint32_t x, flip, shift, save[7];
 	uint32_t i;
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 45692b8..253decb 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -867,7 +867,7 @@ static int xscale_arch_state(struct target *target)
 			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s"
 			"%s",
-			 armv4_5_state_strings[armv4_5->core_state],
+			 arm_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
 			 arm_mode_name(armv4_5->core_mode),
 			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 6f81178..2bb2ba5 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -79,7 +79,7 @@ struct xscale_trace
 	int buffer_fill;				/* maximum number of trace runs to read (-1 for wrap-around) */
 	int pc_ok;
 	uint32_t current_pc;
-	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
+	arm_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
 };
 
 struct xscale_common

commit d4d16f1036bff4ce3c36edd1995e579fbf64e1c9
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 19:33:33 2009 -0800

    ARM: rename armv4_5_mode_* AS arm_mode_*
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 928923d..408259e 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1582,7 +1582,7 @@ int arm7_9_restore_context(struct target *target)
 	struct arm *armv4_5 = &arm7_9->armv4_5_common;
 	struct reg *reg;
 	struct arm_reg *reg_arch_info;
-	enum armv4_5_mode current_mode = armv4_5->core_mode;
+	enum arm_mode current_mode = armv4_5->core_mode;
 	int i, j;
 	int dirty;
 	int mode_change;
@@ -2093,7 +2093,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 }
 
 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
-		int num, enum armv4_5_mode mode)
+		int num, enum arm_mode mode)
 {
 	uint32_t* reg_p[16];
 	uint32_t value;
@@ -2157,7 +2157,7 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
-		int num, enum armv4_5_mode mode, uint32_t value)
+		int num, enum arm_mode mode, uint32_t value)
 {
 	uint32_t reg[16];
 	struct arm_reg *areg = r->arch_info;
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 7cc48ab..b65e922 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -102,7 +102,7 @@ static int dpm_mcr(struct target *target, int cpnum,
 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  * Routines *must* restore the original mode before returning!!
  */
-static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
+static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 {
 	int retval;
 	uint32_t cpsr;
@@ -348,7 +348,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	 * actually find anything to do...
 	 */
 	do {
-		enum armv4_5_mode mode = ARM_MODE_ANY;
+		enum arm_mode mode = ARM_MODE_ANY;
 
 		did_write = false;
 
@@ -370,7 +370,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
 			/* may need to pick and set a mode */
 			if (!did_write) {
-				enum armv4_5_mode tmode;
+				enum arm_mode tmode;
 
 				did_write = true;
 				mode = tmode = r->mode;
@@ -432,10 +432,10 @@ done:
  * Caller already filtered out SPSR access; mode is never MODE_SYS
  * or MODE_ANY.
  */
-static enum armv4_5_mode dpm_mapmode(struct arm *arm,
-		unsigned num, enum armv4_5_mode mode)
+static enum arm_mode dpm_mapmode(struct arm *arm,
+		unsigned num, enum arm_mode mode)
 {
-	enum armv4_5_mode amode = arm->core_mode;
+	enum arm_mode amode = arm->core_mode;
 
 	/* don't switch if the mode is already correct */
 	if (amode == ARM_MODE_SYS)
@@ -473,7 +473,7 @@ static enum armv4_5_mode dpm_mapmode(struct arm *arm,
  */
 
 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
-		int regnum, enum armv4_5_mode mode)
+		int regnum, enum arm_mode mode)
 {
 	struct arm_dpm *dpm = target_to_arm(target)->dpm;
 	int retval;
@@ -513,7 +513,7 @@ fail:
 }
 
 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
-		int regnum, enum armv4_5_mode mode, uint32_t value)
+		int regnum, enum arm_mode mode, uint32_t value)
 {
 	struct arm_dpm *dpm = target_to_arm(target)->dpm;
 	int retval;
@@ -566,7 +566,7 @@ static int arm_dpm_full_context(struct target *target)
 		goto done;
 
 	do {
-		enum armv4_5_mode mode = ARM_MODE_ANY;
+		enum arm_mode mode = ARM_MODE_ANY;
 
 		did_read = false;
 
diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 326240b..c252b44 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -665,7 +665,7 @@ int arm_simulate_step_core(struct target *target,
 		}
 		else
 		{
-			enum armv4_5_mode mode = sim->get_mode(sim);
+			enum arm_mode mode = sim->get_mode(sim);
 			int update_cpsr = 0;
 
 			if (instruction.info.load_store_multiple.S)
@@ -721,7 +721,7 @@ int arm_simulate_step_core(struct target *target,
 			uint32_t Rn = sim->get_reg_mode(sim,
 					instruction.info.load_store_multiple.Rn);
 			int bits_set = 0;
-			enum armv4_5_mode mode = sim->get_mode(sim);
+			enum arm_mode mode = sim->get_mode(sim);
 
 			for (i = 0; i < 16; i++)
 			{
@@ -839,7 +839,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state
 }
 
 
-static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim)
 {
 	struct arm *armv4_5 = (struct arm *)sim->user_data;
 
diff --git a/src/target/arm_simulator.h b/src/target/arm_simulator.h
index daca371..ae3afad 100644
--- a/src/target/arm_simulator.h
+++ b/src/target/arm_simulator.h
@@ -34,7 +34,7 @@ struct arm_sim_interface
 	uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
 	enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
 	void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
-	enum armv4_5_mode (*get_mode)(struct arm_sim_interface *sim);
+	enum arm_mode (*get_mode)(struct arm_sim_interface *sim);
 };
 
 /* armv4_5 version */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 1a92374..15c0a7f 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -163,7 +163,7 @@ bool is_arm_mode(unsigned psr_mode)
 }
 
 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
-int armv4_5_mode_to_number(enum armv4_5_mode mode)
+int arm_mode_to_number(enum arm_mode mode)
 {
 	switch (mode) {
 	case ARM_MODE_ANY:
@@ -191,7 +191,7 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
 }
 
 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
-enum armv4_5_mode armv4_5_number_to_mode(int number)
+enum arm_mode armv4_5_number_to_mode(int number)
 {
 	switch (number) {
 	case 0:
@@ -243,7 +243,7 @@ static const struct {
 	 * (Exception modes have both CPSR and SPSR registers ...)
 	 */
 	unsigned cookie;
-	enum armv4_5_mode mode;
+	enum arm_mode mode;
 } arm_core_regs[] = {
 	/* IMPORTANT:  we guarantee that the first eight cached registers
 	 * correspond to r0..r7, and the fifteenth to PC, so that callers
@@ -346,7 +346,7 @@ const int armv4_5_core_reg_map[8][17] =
  */
 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 {
-	enum armv4_5_mode mode = cpsr & 0x1f;
+	enum arm_mode mode = cpsr & 0x1f;
 	int num;
 
 	/* NOTE:  this may be called very early, before the register
@@ -362,7 +362,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 	arm->core_mode = mode;
 
 	/* mode_to_number() warned; set up a somewhat-sane mapping */
-	num = armv4_5_mode_to_number(mode);
+	num = arm_mode_to_number(mode);
 	if (num < 0) {
 		mode = ARM_MODE_USR;
 		num = 0;
@@ -512,7 +512,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 		 * it won't hurt since CPSR is always flushed anyway.
 		 */
 		if (armv4_5_target->core_mode !=
-				(enum armv4_5_mode)(value & 0x1f)) {
+				(enum arm_mode)(value & 0x1f)) {
 			LOG_DEBUG("changing ARM core mode to '%s'",
 					arm_mode_name(value & 0x1f));
 			value &= ~((1 << 24) | (1 << 5));
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 8e2fca2..e2b7b5a 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -30,7 +30,7 @@
 #include <helper/command.h>
 
 
-typedef enum armv4_5_mode
+typedef enum arm_mode
 {
 	ARM_MODE_USR = 16,
 	ARM_MODE_FIQ = 17,
@@ -41,13 +41,13 @@ typedef enum armv4_5_mode
 	ARM_MODE_UND = 27,
 	ARM_MODE_SYS = 31,
 	ARM_MODE_ANY = -1
-} armv4_5_mode_t;
+} arm_mode_t;
 
 const char *arm_mode_name(unsigned psr_mode);
 bool is_arm_mode(unsigned psr_mode);
 
-int armv4_5_mode_to_number(enum armv4_5_mode mode);
-enum armv4_5_mode armv4_5_number_to_mode(int number);
+int arm_mode_to_number(enum arm_mode mode);
+enum arm_mode armv4_5_number_to_mode(int number);
 
 typedef enum armv4_5_state
 {
@@ -62,7 +62,7 @@ extern char* armv4_5_state_strings[];
 extern const int armv4_5_core_reg_map[8][17];
 
 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
-		cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
+		cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
 
 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
 enum { ARMV4_5_CPSR = 31, };
@@ -95,9 +95,9 @@ struct arm
 	 * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 	 * more registers are shadowed, for "Secure Monitor" mode.
 	 */
-	enum armv4_5_mode core_type;
+	enum arm_mode core_type;
 
-	enum armv4_5_mode core_mode;
+	enum arm_mode core_mode;
 	enum armv4_5_state core_state;
 
 	/** Flag reporting unavailability of the BKPT instruction. */
@@ -122,9 +122,9 @@ struct arm
 
 	int (*full_context)(struct target *target);
 	int (*read_core_reg)(struct target *target, struct reg *reg,
-			int num, enum armv4_5_mode mode);
+			int num, enum arm_mode mode);
 	int (*write_core_reg)(struct target *target, struct reg *reg,
-			int num, enum armv4_5_mode mode, uint32_t value);
+			int num, enum arm_mode mode, uint32_t value);
 
 	/** Read coprocessor register.  */
 	int (*mrc)(struct target *target, int cpnum,
@@ -158,14 +158,14 @@ struct armv4_5_algorithm
 {
 	int common_magic;
 
-	enum armv4_5_mode core_mode;
+	enum arm_mode core_mode;
 	enum armv4_5_state core_state;
 };
 
 struct arm_reg
 {
 	int num;
-	enum armv4_5_mode mode;
+	enum arm_mode mode;
 	struct target *target;
 	struct arm *armv4_5_common;
 	uint32_t value;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index f089c5c..ad1f094 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -118,14 +118,14 @@ struct armv7a_algorithm
 {
 	int common_magic;
 
-	enum armv4_5_mode core_mode;
+	enum arm_mode core_mode;
 	enum armv4_5_state core_state;
 };
 
 struct armv7a_core_reg
 {
 	int num;
-	enum armv4_5_mode mode;
+	enum arm_mode mode;
 	struct target *target;
 	struct armv7a_common *armv7a_common;
 };
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 57b1081..45692b8 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1658,7 +1658,7 @@ static int xscale_deassert_reset(struct target *target)
 }
 
 static int xscale_read_core_reg(struct target *target, struct reg *r,
-		int num, enum armv4_5_mode mode)
+		int num, enum arm_mode mode)
 {
 	/** \todo add debug handler support for core register reads */
 	LOG_ERROR("not implemented");
@@ -1666,7 +1666,7 @@ static int xscale_read_core_reg(struct target *target, struct reg *r,
 }
 
 static int xscale_write_core_reg(struct target *target, struct reg *r,
-		int num, enum armv4_5_mode mode, uint32_t value)
+		int num, enum arm_mode mode, uint32_t value)
 {
 	/** \todo add debug handler support for core register writes */
 	LOG_ERROR("not implemented");
@@ -1697,7 +1697,7 @@ static int xscale_full_context(struct target *target)
 	 */
 	for (i = 1; i < 7; i++)
 	{
-		enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+		enum arm_mode mode = armv4_5_number_to_mode(i);
 		bool valid = true;
 		struct reg *r;
 
@@ -1774,7 +1774,7 @@ static int xscale_restore_banked(struct target *target)
 	 */
 	for (i = 1; i < 7; i++)
 	{
-		enum armv4_5_mode mode = armv4_5_number_to_mode(i);
+		enum arm_mode mode = armv4_5_number_to_mode(i);
 		struct reg *r;
 
 		if (mode == ARM_MODE_USR)

commit 0073e7a69e55eb435fc2e274ba245a27779963e4
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 19:21:14 2009 -0800

    ARM: rename ARMV4_5_MODE_* as ARM_MODE_*
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index 558ed94..3991c0f 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -137,7 +137,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 
 	/* set up algorithm and parameters */
 	algo.common_magic = ARMV4_5_COMMON_MAGIC;
-	algo.core_mode = ARMV4_5_MODE_SVC;
+	algo.core_mode = ARM_MODE_SVC;
 	algo.core_state = ARM_STATE_ARM;
 
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
@@ -213,7 +213,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 
 	/* set up algorithm and parameters */
 	algo.common_magic = ARMV4_5_COMMON_MAGIC;
-	algo.core_mode = ARMV4_5_MODE_SVC;
+	algo.core_mode = ARM_MODE_SVC;
 	algo.core_state = ARM_STATE_ARM;
 
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index c223ec4..69c8274 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -242,7 +242,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
 	}
 
 	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+	armv4_5_info.core_mode = ARM_MODE_SVC;
 	armv4_5_info.core_state = ARM_STATE_ARM;
 
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 991110b..16ba999 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1086,7 +1086,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
 	cfi_intel_clear_status_register(bank);
 
 	armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-	armv4_5_info...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-867-gf67f6fe

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  f67f6fe5bb8a466cc4d49f83608f026c4b233949 (commit)
       via  a0edb8a328ceea23186ab74c941454fb146c9a48 (commit)
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- Log -----------------------------------------------------------------
commit f67f6fe5bb8a466cc4d49f83608f026c4b233949
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 18:57:31 2009 -0800

    ARM11: report watchpoint trigger insn
    
    As with Cortex-A8, the WFAR register holds useful information
    that should be recorded and, where relevant, displayed.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 943ab8a..0486b04 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -217,6 +217,19 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 
 	}
 
+	if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
+		uint32_t wfar;
+
+		/* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
+		retval = arm11_run_instr_data_from_core_via_r0(arm11,
+				ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
+				&wfar);
+		if (retval != ERROR_OK)
+			return retval;
+		arm_dpm_report_wfar(arm11->arm.dpm, wfar);
+	}
+
+
 	retval = arm11_run_instr_data_finish(arm11);
 	if (retval != ERROR_OK)
 		return retval;
@@ -356,12 +369,17 @@ static int arm11_poll(struct target *target)
 /* architecture specific status reply */
 static int arm11_arch_state(struct target *target)
 {
+	struct arm11_common *arm11 = target_to_arm11(target);
 	int retval;
 
 	retval = armv4_5_arch_state(target);
 
 	/* REVISIT also display ARM11-specific MMU and cache status ... */
 
+	if (target->debug_reason == DBG_REASON_WATCHPOINT)
+		LOG_USER("Watchpoint triggered at PC %#08x",
+				(unsigned) arm11->dpm.wp_pc);
+
 	return retval;
 }
 

commit a0edb8a328ceea23186ab74c941454fb146c9a48
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 18:57:31 2009 -0800

    ARM11: basic watchpoint support
    
    Use the DPM watchpoint support; remove old incomplete stubs.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWS b/NEWS
index 38ae4da..498797b 100644
--- a/NEWS
+++ b/NEWS
@@ -24,10 +24,12 @@ Target Layer:
 		- accelerated GDB memory checksum
 		- support "arm regs" command
 		- can access all core modes and registers
+		- watchpoint support
 	Cortex-A8
 		- support "arm regs" command
 		- can access all core modes and registers
 		- supports "reset-assert" event (used on OMAP3530)
+		- watchpoint support
 	Cortex-M3
 		- Exposed DWT registers like cycle counter
 
diff --git a/src/target/arm11.c b/src/target/arm11.c
index b05ef30..943ab8a 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -286,6 +286,8 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 	 */
 	retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 
+	retval = arm11_bpwp_flush(arm11);
+
 	register_cache_invalidate(arm11->arm.core_cache);
 
 	/* restore DSCR */
@@ -1212,7 +1214,6 @@ static int arm11_examine(struct target *target)
 	}
 
 	arm11->brp = ((didr >> 24) & 0x0F) + 1;
-	arm11->wrp = ((didr >> 28) & 0x0F) + 1;
 
 	/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
 	arm11->free_brps = arm11->brp;
diff --git a/src/target/arm11.h b/src/target/arm11.h
index f3f0644..421f8d1 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -53,9 +53,10 @@ struct arm11_common
 
 	/** Debug module state. */
 	struct arm_dpm dpm;
+	struct arm11_sc7_action *bpwp_actions;
+	unsigned bpwp_n;
 
 	size_t	brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
-	size_t	wrp;			/**< Number of Watchpoint Register Pairs from DIDR	*/
 	size_t	free_brps;		/**< Number of breakpoints allocated */
 
 	uint32_t dscr;			/**< Last retrieved DSCR value. */
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index e37ad56..9ad5662 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -892,7 +892,7 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
  */
 void arm11_sc7_clear_vbw(struct arm11_common * arm11)
 {
-	size_t clear_bw_size = arm11->brp + arm11->wrp + 1;
+	size_t clear_bw_size = arm11->brp + 1;
 	struct arm11_sc7_action		*clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
 	struct arm11_sc7_action *	pos = clear_bw;
 
@@ -905,11 +905,6 @@ void arm11_sc7_clear_vbw(struct arm11_common * arm11)
 	for (size_t i = 0; i < arm11->brp; i++)
 		(pos++)->address = ARM11_SC7_BCR0 + i;
 
-
-	for (size_t i = 0; i < arm11->wrp; i++)
-		(pos++)->address = ARM11_SC7_WCR0 + i;
-
-
 	(pos++)->address = ARM11_SC7_VCR;
 
 	arm11_sc7_run(arm11, clear_bw, clear_bw_size);
@@ -1013,6 +1008,88 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
 			opcode, data);
 }
 
+/* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint
+ * and watchpoint operations instead of running them right away.  Since we
+ * pre-allocated our vector, we don't need to worry about space.
+ */
+static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index,
+		uint32_t addr, uint32_t control)
+{
+	struct arm11_common *arm11 = dpm_to_arm11(dpm);
+	struct arm11_sc7_action *action;
+
+	action = arm11->bpwp_actions + arm11->bpwp_n;
+
+	/* Invariant:  this bp/wp is disabled.
+	 * It also happens that the core is halted here, but for
+	 * DPM-based cores we don't actually care about that.
+	 */
+
+	action[0].write = action[1].write = true;
+
+	action[0].value = addr;
+	action[1].value = control;
+
+	switch (index) {
+	case 0 ... 15:
+		action[0].address = ARM11_SC7_BVR0 + index;
+		action[1].address = ARM11_SC7_BCR0 + index;
+		break;
+	case 16 ... 32:
+		index -= 16;
+		action[0].address = ARM11_SC7_WVR0 + index;
+		action[1].address = ARM11_SC7_WCR0 + index;
+		break;
+	default:
+		return ERROR_FAIL;
+	}
+
+	arm11->bpwp_n += 2;
+
+	return ERROR_OK;
+}
+
+static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index)
+{
+	struct arm11_common *arm11 = dpm_to_arm11(dpm);
+	struct arm11_sc7_action *action;
+
+	action = arm11->bpwp_actions + arm11->bpwp_n;
+
+	action[0].write = true;
+	action[0].value = 0;
+
+	switch (index) {
+	case 0 ... 15:
+		action[0].address = ARM11_SC7_BCR0 + index;
+		break;
+	case 16 ... 32:
+		index -= 16;
+		action[0].address = ARM11_SC7_WCR0 + index;
+		break;
+	default:
+		return ERROR_FAIL;
+	}
+
+	arm11->bpwp_n += 1;
+
+	return ERROR_OK;
+}
+
+/** Flush any pending breakpoint and watchpoint updates. */
+int arm11_bpwp_flush(struct arm11_common *arm11)
+{
+	int retval;
+
+	if (!arm11->bpwp_n)
+		return ERROR_OK;
+
+	retval = arm11_sc7_run(arm11, arm11->bpwp_actions, arm11->bpwp_n);
+	arm11->bpwp_n = 0;
+
+	return retval;
+}
+
 /** Set up high-level debug module utilities */
 int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
 {
@@ -1032,11 +1109,22 @@ int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
 	dpm->instr_read_data_dcc = arm11_dpm_instr_read_data_dcc;
 	dpm->instr_read_data_r0 = arm11_dpm_instr_read_data_r0;
 
+	dpm->bpwp_enable = arm11_bpwp_enable;
+	dpm->bpwp_disable = arm11_bpwp_disable;
+
 	retval = arm_dpm_setup(dpm);
 	if (retval != ERROR_OK)
 		return retval;
 
+	/* alloc enough to enable all breakpoints and watchpoints at once */
+	arm11->bpwp_actions = calloc(2 * (dpm->nbp + dpm->nwp),
+			sizeof *arm11->bpwp_actions);
+	if (!arm11->bpwp_actions)
+		return ERROR_FAIL;
+
 	retval = arm_dpm_initialize(dpm);
+	if (retval != ERROR_OK)
+		return retval;
 
-	return retval;
+	return arm11_bpwp_flush(arm11);
 }
diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h
index 2c586cc..3139a09 100644
--- a/src/target/arm11_dbgtap.h
+++ b/src/target/arm11_dbgtap.h
@@ -59,5 +59,6 @@ int arm11_read_memory_word(struct arm11_common *arm11,
 		uint32_t address, uint32_t *result);
 
 int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr);
+int arm11_bpwp_flush(struct arm11_common *arm11);
 
 #endif // ARM11_DBGTAP_H

commit f4651c869fb0bbe00495a09470af0a934814c92a
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 18:57:30 2009 -0800

    ARM11: tweak TAP ops and debugging
    
    Tweak scanchain 7 debug messaging:
    
     - show register addresses in decimal, matching ARM docs;
     - remove some pointless noise
    
    Avoid some needless roundtrips:
    
     - skip SCAN_N when SCREG already holds that number (speeds up
       polling and other common operations)
     - avoid zeroing vcr twice on resume
    
    Show the IR opcode as a label ("RESTART") too; and in decimal,
    matching ARM docs.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 20ad22d..b05ef30 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -513,7 +513,8 @@ static int arm11_resume(struct target *target, int current,
 			brp_num++;
 		}
 
-		arm11_sc7_set_vcr(arm11, arm11_vcr);
+		if (arm11_vcr)
+			arm11_sc7_set_vcr(arm11, arm11_vcr);
 	}
 
 	arm11_leave_debug_state(arm11, handle_breakpoints);
@@ -1133,7 +1134,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 	arm11->jtag_info.tap = target->tap;
 	arm11->jtag_info.scann_size = 5;
 	arm11->jtag_info.scann_instr = ARM11_SCAN_N;
-	/* cur_scan_chain == 0 */
+	arm11->jtag_info.cur_scan_chain = ~0;	/* invalid/unknown */
 	arm11->jtag_info.intest_instr = ARM11_INTEST;
 
 	return ERROR_OK;
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index e5d3f80..e37ad56 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -91,6 +91,38 @@ void arm11_setup_field(struct arm11_common * arm11, int num_bits, void * out_dat
 	field->in_value			= in_data;
 }
 
+static const char *arm11_ir_to_string(uint8_t ir)
+{
+	const char *s = "unknown";
+
+	switch (ir) {
+	case ARM11_EXTEST:
+		s = "EXTEST";
+		break;
+	case ARM11_SCAN_N:
+		s = "SCAN_N";
+		break;
+	case ARM11_RESTART:
+		s = "RESTART";
+		break;
+	case ARM11_HALT:
+		s = "HALT";
+		break;
+	case ARM11_INTEST:
+		s = "INTEST";
+		break;
+	case ARM11_ITRSEL:
+		s = "ITRSEL";
+		break;
+	case ARM11_IDCODE:
+		s = "IDCODE";
+		break;
+	case ARM11_BYPASS:
+		s = "BYPASS";
+		break;
+	}
+	return s;
+}
 
 /** Write JTAG instruction register
  *
@@ -110,7 +142,7 @@ void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
 		return;
 	}
 
-	JTAG_DEBUG("IR <= 0x%02x", instr);
+	JTAG_DEBUG("IR <= %s (0x%02x)", arm11_ir_to_string(instr), instr);
 
 	struct scan_field field;
 
@@ -135,7 +167,8 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
 		jtag_set_error(ERROR_FAIL);
 	}
 
-	JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
+	if (v != 0x10)
+		JTAG_DEBUG("SCREG SCAN OUT 0x%02x", v);
 }
 
 /** Select and write to Scan Chain Register (SCREG)
@@ -150,6 +183,9 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
  * \param state	    Pass the final TAP state or ARM11_TAP_DEFAULT for the default
  *					value (Pause-DR).
  *
+ * Changes the current scan chain if needed, transitions to the specified
+ * TAP state, and leaves the IR undefined.
+ *
  * The chain takes effect when Update-DR is passed (usually when subsequently
  * the INTEXT/EXTEST instructions are written).
  *
@@ -162,9 +198,19 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
  * \remarks			This adds to the JTAG command queue but does \em not execute it.
  */
 
-int arm11_add_debug_SCAN_N(struct arm11_common * arm11, uint8_t chain, tap_state_t state)
+int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
+		uint8_t chain, tap_state_t state)
 {
-	JTAG_DEBUG("SCREG <= 0x%02x", chain);
+	/* Don't needlessly switch the scan chain.
+	 * NOTE:  the ITRSEL instruction fakes SCREG changing;
+	 * but leaves its actual value unchanged.
+	 */
+	if (arm11->jtag_info.cur_scan_chain == chain) {
+		JTAG_DEBUG("SCREG <= %d SKIPPED", chain);
+		return jtag_add_statemove((state == ARM11_TAP_DEFAULT)
+					? TAP_DRPAUSE : state);
+	}
+	JTAG_DEBUG("SCREG <= %d", chain);
 
 	arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
 
@@ -791,30 +837,31 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
 		}
 		else
 		{
-			nRW			= 0;
+			nRW			= 1;
 			DataOut		= 0;
 			AddressOut	= 0;
 		}
 
 		do
 		{
-			JTAG_DEBUG("SC7 <= Address %02x  Data %08x    nRW %d",
+			JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
 					(unsigned) AddressOut,
 					(unsigned) DataOut,
-					nRW);
+					nRW ? "write" : "read");
 
 			arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields),
 					chain7_fields, TAP_DRPAUSE);
 
 			CHECK_RETVAL(jtag_execute_queue());
 
-			JTAG_DEBUG("SC7 => Address %02x  Data %08x  Ready %d",
-					(unsigned) AddressIn,
-					(unsigned) DataIn,
-					Ready);
+			if (!Ready)
+				JTAG_DEBUG("SC7 => !ready");
 		}
 		while (!Ready); /* 'nRW' is 'Ready' on read out */
 
+		if (!nRW)
+			JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn);
+
 		if (i > 0)
 		{
 			if (actions[i - 1].address != AddressIn)
@@ -835,15 +882,6 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
 			}
 		}
 	}
-
-	for (size_t i = 0; i < count; i++)
-	{
-		JTAG_DEBUG("SC7 %02d: %02x %s %08x",
-			(unsigned) i, actions[i].address,
-			actions[i].write ? "<=" : "=>",
-			(unsigned) actions[i].value);
-	}
-
 	return ERROR_OK;
 }
 
@@ -892,7 +930,6 @@ void arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
 	set_vcr.address		= ARM11_SC7_VCR;
 	set_vcr.value		= value;
 
-
 	arm11_sc7_run(arm11, &set_vcr, 1);
 }
 

-----------------------------------------------------------------------

Summary of changes:
 NEWS                      |    2 +
 src/target/arm11.c        |   26 ++++++-
 src/target/arm11.h        |    3 +-
 src/target/arm11_dbgtap.c |  181 ++++++++++++++++++++++++++++++++++++++-------
 src/target/arm11_dbgtap.h |    1 +
 5 files changed, 181 insertions(+), 32 deletions(-)


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- Log -----------------------------------------------------------------
commit 87a0119fa24fe0fc904dcf2e6569cc0b9cb580ed
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 04:42:38 2009 -0800

    reorder build order of src directory
    
    Descend into the library modules in order, from bottom-to-top.

diff --git a/src/Makefile.am b/src/Makefile.am
index e6462c1..ea753bb 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -1,4 +1,12 @@
-SUBDIRS = helper jtag xsvf svf target server flash pld
+SUBDIRS = \
+	helper \
+	jtag \
+	target \
+	flash \
+	svf \
+	xsvf \
+	pld \
+	server
 
 lib_LTLIBRARIES = libopenocd.la
 bin_PROGRAMS = openocd

commit f3e6f584f12dbde9ba9806ed4a412db0524d438c
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 16:40:19 2009 -0800

    remove flash.h from tree
    
    Remove the now vestigial <flash/flash.h> header from the tree,
    replacing a few references with <flash/nor/core.h>

diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index b5cd526..ba44adb 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -22,7 +22,6 @@ libflash_la_LIBADD = \
 noinst_HEADERS = \
 	arm_nandio.h \
 	common.h \
-	flash.h \
 	mflash.h \
 	nand.h
 
diff --git a/src/flash/flash.h b/src/flash/flash.h
deleted file mode 100644
index 056e1ae..0000000
--- a/src/flash/flash.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/***************************************************************************
- *   Copyright (C) 2005 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
- *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
- *   oyv...@zy...                                               *
- *                                                                         *
- *   Copyright (C) 2008 by Spencer Oliver                                  *
- *   sp...@sp...                                                  *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-#ifndef FLASH_H
-#define FLASH_H
-
-// this file will be removed
-
-#include <flash/nor/core.h>
-
-#endif /* FLASH_H */
diff --git a/src/flash/nor/at91sam7.h b/src/flash/nor/at91sam7.h
index 8077879..eb35433 100644
--- a/src/flash/nor/at91sam7.h
+++ b/src/flash/nor/at91sam7.h
@@ -23,8 +23,6 @@
 #ifndef AT91SAM7_H
 #define AT91SAM7_H
 
-#include <flash/flash.h>
-
 struct at91sam7_flash_bank
 {
 	/* chip id register */
diff --git a/src/flash/nor/avrf.h b/src/flash/nor/avrf.h
index 0f270e6..1a69e86 100644
--- a/src/flash/nor/avrf.h
+++ b/src/flash/nor/avrf.h
@@ -20,8 +20,6 @@
 #ifndef AVRF_H
 #define AVRF_H
 
-#include <helper/types.h>
-
 struct avrf_type
 {
 	char name[15];
diff --git a/src/flash/nor/cfi.h b/src/flash/nor/cfi.h
index 565a2b6..fa717dc 100644
--- a/src/flash/nor/cfi.h
+++ b/src/flash/nor/cfi.h
@@ -20,8 +20,6 @@
 #ifndef CFI_H
 #define CFI_H
 
-#include <flash/flash.h>
-
 #define CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7 0xE0 /* DQ5..DQ7 */
 #define CFI_STATUS_POLL_MASK_DQ6_DQ7     0xC0 /* DQ6..DQ7 */
 
diff --git a/src/flash/nor/lpc2000.h b/src/flash/nor/lpc2000.h
index 30be304..f1f90e7 100644
--- a/src/flash/nor/lpc2000.h
+++ b/src/flash/nor/lpc2000.h
@@ -23,8 +23,6 @@
 #ifndef LPC2000_H
 #define LPC2000_H
 
-#include <flash/flash.h>
-
 typedef enum
 {
 	lpc2000_v1,
diff --git a/src/flash/nor/lpc288x.h b/src/flash/nor/lpc288x.h
index 06f634a..cd5fb73 100644
--- a/src/flash/nor/lpc288x.h
+++ b/src/flash/nor/lpc288x.h
@@ -21,8 +21,6 @@
 #ifndef lpc288x_H
 #define lpc288x_H
 
-#include <flash/flash.h>
-
 struct lpc288x_flash_bank
 {
 	uint32_t working_area;
diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c
index f98b108..7e73afa 100644
--- a/src/flash/nor/non_cfi.c
+++ b/src/flash/nor/non_cfi.c
@@ -23,8 +23,9 @@
 #include "config.h"
 #endif
 
-#include "non_cfi.h"
+#include "imp.h"
 #include "cfi.h"
+#include "non_cfi.h"
 
 
 #define KB 1024
diff --git a/src/flash/nor/non_cfi.h b/src/flash/nor/non_cfi.h
index cc6004e..0219333 100644
--- a/src/flash/nor/non_cfi.h
+++ b/src/flash/nor/non_cfi.h
@@ -20,8 +20,6 @@
 #ifndef NON_CFI_H
 #define NON_CFI_H
 
-#include <flash/flash.h>
-
 struct non_cfi
 {
 	uint16_t mfr;
diff --git a/src/flash/nor/pic32mx.h b/src/flash/nor/pic32mx.h
index b33e831..b3bdad2 100644
--- a/src/flash/nor/pic32mx.h
+++ b/src/flash/nor/pic32mx.h
@@ -26,8 +26,6 @@
 #ifndef PIC32MX_H
 #define PIC32MX_H
 
-#include <flash/flash.h>
-
 struct pic32mx_flash_bank
 {
 	struct working_area *write_algorithm;
diff --git a/src/flash/nor/stellaris.h b/src/flash/nor/stellaris.h
index 85b709c..a5f04e4 100644
--- a/src/flash/nor/stellaris.h
+++ b/src/flash/nor/stellaris.h
@@ -20,8 +20,6 @@
 #ifndef STELLARIS_FLASH_H
 #define STELLARIS_FLASH_H
 
-#include <flash/flash.h>
-
 struct stellaris_flash_bank
 {
 	/* chip id register */
diff --git a/src/flash/nor/stm32x.h b/src/flash/nor/stm32x.h
index b6e00ed..fcf895c 100644
--- a/src/flash/nor/stm32x.h
+++ b/src/flash/nor/stm32x.h
@@ -23,8 +23,6 @@
 #ifndef STM32X_H
 #define STM32X_H
 
-#include <flash/flash.h>
-
 struct stm32x_options
 {
 	uint16_t RDP;
diff --git a/src/flash/nor/str7x.h b/src/flash/nor/str7x.h
index 4daafb7..77dfee6 100644
--- a/src/flash/nor/str7x.h
+++ b/src/flash/nor/str7x.h
@@ -23,8 +23,6 @@
 #ifndef STR7X_H
 #define STR7X_H
 
-#include <flash/flash.h>
-
 struct str7x_flash_bank
 {
 	uint32_t *sector_bits;
diff --git a/src/flash/nor/str9x.h b/src/flash/nor/str9x.h
index 29adecf..ba5386f 100644
--- a/src/flash/nor/str9x.h
+++ b/src/flash/nor/str9x.h
@@ -23,8 +23,6 @@
 #ifndef STR9X_H
 #define STR9X_H
 
-#include <flash/flash.h>
-
 struct str9x_flash_bank
 {
 	uint32_t *sector_bits;
diff --git a/src/flash/nor/str9xpec.h b/src/flash/nor/str9xpec.h
index cb2ac78..6eecd8a 100644
--- a/src/flash/nor/str9xpec.h
+++ b/src/flash/nor/str9xpec.h
@@ -23,8 +23,6 @@
 #ifndef STR9XPEC_H
 #define STR9XPEC_H
 
-#include <flash/flash.h>
-#include <jtag/jtag.h>
 
 struct str9xpec_flash_controller
 {
diff --git a/src/flash/nor/tms470.h b/src/flash/nor/tms470.h
index b2fea1b..ecbfad8 100644
--- a/src/flash/nor/tms470.h
+++ b/src/flash/nor/tms470.h
@@ -20,8 +20,6 @@
 #ifndef TMS470_DOT_H
 #define TMS470_DOT_H
 
-#include <flash/flash.h>
-
 struct tms470_flash_bank
 {
 	unsigned ordinal;
diff --git a/src/openocd.c b/src/openocd.c
index b6dc010..e500ba6 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -34,7 +34,7 @@
 #include <helper/configuration.h>
 #include <xsvf/xsvf.h>
 #include <svf/svf.h>
-#include <flash/flash.h>
+#include <flash/nor/core.h>
 #include <flash/nand.h>
 #include <pld/pld.h>
 #include <flash/mflash.h>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 21cd0fe..f9cca99 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -31,7 +31,7 @@
 #include <target/target_request.h>
 #include <target/register.h>
 #include "server.h"
-#include <flash/flash.h>
+#include <flash/nor/core.h>
 #include "gdb_server.h"
 #include <target/image.h>
 #include <jtag/jtag.h>

commit ae6374e25dae7b02636e440549b87040d03cc5aa
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 16:07:47 2009 -0800

    split flash.h into into flash/nor/*.h
    
    Move the bulk of the flash.h file into flash/nor/core.h, leaving an
    empty husk that will be removed in the next patch.
    
    The NOR driver structure is an implementation detail, so move it into
    its own private header file <flash/nor/driver.h> along with helper
    declaration for finding them by name.

diff --git a/src/flash/flash.h b/src/flash/flash.h
index 8cd50f6..056e1ae 100644
--- a/src/flash/flash.h
+++ b/src/flash/flash.h
@@ -26,326 +26,8 @@
 #ifndef FLASH_H
 #define FLASH_H
 
-#include <flash/common.h>
+// this file will be removed
 
-struct image;
-
-#define FLASH_MAX_ERROR_STR	(128)
-
-/**
- * Describes the geometry and status of a single flash sector
- * within a flash bank.  A single bank typically consists of multiple
- * sectors, each of which can be erased and protected independently.
- */
-struct flash_sector
-{
-	/// Bus offset from start of the flash chip (in bytes).
-	uint32_t offset;
-	/// Number of bytes in this flash sector.
-	uint32_t size;
-	/**
-	 * Indication of erasure status: 0 = not erased, 1 = erased,
-	 * other = unknown.  Set by @c flash_driver_s::erase_check.
-	 */
-	int is_erased;
-	/**
-	 * Indication of protection status: 0 = unprotected/unlocked,
-	 * 1 = protected/locked, other = unknown.  Set by
-	 * @c flash_driver_s::protect_check.
-	 */
-	int is_protected;
-};
-
-struct flash_bank;
-
-#define __FLASH_BANK_COMMAND(name) \
-		COMMAND_HELPER(name, struct flash_bank *bank)
-
-/**
- * @brief Provides the implementation-independent structure that defines
- * all of the callbacks required by OpenOCD flash drivers.
- *
- * Driver authors must implement the routines defined here, providing an
- * instance with the fields filled out.  After that, the instance must
- * be registered in flash.c, so it can be used by the driver lookup system.
- *
- * Specifically, the user can issue the command: @par
- * @code
- * flash bank DRIVERNAME ...parameters...
- * @endcode
- *
- * OpenOCD will search for the driver with a @c flash_driver_s::name
- * that matches @c DRIVERNAME.
- *
- * The flash subsystem calls some of the other drivers routines a using
- * corresponding static <code>flash_driver_<i>callback</i>()</code>
- * routine in flash.c.
- */
-struct flash_driver
-{
-	/**
-	 * Gives a human-readable name of this flash driver,
-	 * This field is used to select and initialize the driver.
-	 */
-	char *name;
-
-	/**
-	 * An array of driver-specific commands to register.  When called
-	 * during the "flash bank" command, the driver can register addition
-	 * commands to support new flash chip functions.
-	 */
-	const struct command_registration *commands;
-
-	/**
-	 * Finish the "flash bank" command for @a bank.  The
-	 * @a bank parameter will have been filled in by the core flash
-	 * layer when this routine is called, and the driver can store
-	 * additional information in its struct flash_bank::driver_priv field.
-	 *
-	 * The CMD_ARGV are: @par
-	 * @code
-	 * CMD_ARGV[0] = bank
-	 * CMD_ARGV[1] = drivername {name above}
-	 * CMD_ARGV[2] = baseaddress
-	 * CMD_ARGV[3] = lengthbytes
-	 * CMD_ARGV[4] = chip_width_in bytes
-	 * CMD_ARGV[5] = bus_width_bytes
-	 * CMD_ARGV[6] = driver-specific parameters
-	 * @endcode
-	 *
-	 * For example, CMD_ARGV[4] = 16 bit flash, CMD_ARGV[5] = 32bit bus.
-	 *
-	 * If extra arguments are provided (@a CMD_ARGC > 6), they will
-	 * start in @a CMD_ARGV[6].  These can be used to implement
-	 * driver-specific extensions.
-	 *
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	__FLASH_BANK_COMMAND((*flash_bank_command));
-
-	/**
-	 * Bank/sector erase routine (target-specific).  When
-	 * called, the flash driver should erase the specified sectors
-	 * using whatever means are at its disposal.
-	 *
-	 * @param bank The bank of flash to be erased.
-	 * @param first The number of the first sector to erase, typically 0.
-	 * @param last The number of the last sector to erase, typically N-1.
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*erase)(struct flash_bank *bank, int first, int last);
-
-	/**
-	 * Bank/sector protection routine (target-specific).
-	 * When called, the driver should disable 'flash write' bits (or
-	 * enable 'erase protection' bits) for the given @a bank and @a
-	 * sectors.
-	 *
-	 * @param bank The bank to protect or unprotect.
-	 * @param set If non-zero, enable protection; if 0, disable it.
-	 * @param first The first sector to (un)protect, typicaly 0.
-	 * @param last The last sector to (un)project, typically N-1.
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*protect)(struct flash_bank *bank, int set, int first, int last);
-
-	/**
-	 * Program data into the flash.  Note CPU address will be
-	 * "bank->base + offset", while the physical address is
-	 * dependent upon current target MMU mappings.
-	 *
-	 * @param bank The bank to program
-	 * @param buffer The data bytes to write.
-	 * @param offset The offset into the chip to program.
-	 * @param count The number of bytes to write.
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*write)(struct flash_bank *bank,
-			uint8_t *buffer, uint32_t offset, uint32_t count);
-
-	/**
-	 * Probe to determine what kind of flash is present.
-	 * This is invoked by the "probe" script command.
-	 *
-	 * @param bank The bank to probe
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*probe)(struct flash_bank *bank);
-
-	/**
-	 * Check the erasure status of a flash bank.
-	 * When called, the driver routine must perform the required
-	 * checks and then set the @c flash_sector_s::is_erased field
-	 * for each of the flash banks's sectors.
-	 *
-	 * @param bank The bank to check
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*erase_check)(struct flash_bank *bank);
-
-	/**
-	 * Determine if the specific bank is "protected" or not.
-	 * When called, the driver routine must must perform the
-	 * required protection check(s) and then set the @c
-	 * flash_sector_s::is_protected field for each of the flash
-	 * bank's sectors.
-	 *
-	 * @param bank - the bank to check
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*protect_check)(struct flash_bank *bank);
-
-	/**
-	 * Display human-readable information about the flash
-	 * bank into the given buffer.  Drivers must be careful to avoid
-	 * overflowing the buffer.
-	 *
-	 * @param bank - the bank to get info about
-	 * @param char - where to put the text for the human to read
-	 * @param buf_size - the size of the human buffer.
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*info)(struct flash_bank *bank, char *buf, int buf_size);
-
-	/**
-	 * A more gentle flavor of filash_driver_s::probe, performing
-	 * setup with less noise.  Generally, driver routines should test
-	 * to seee if the bank has already been probed; if it has, the
-	 * driver probably should not perform its probe a second time.
-	 *
-	 * This callback is often called from the inside of other
-	 * routines (e.g. GDB flash downloads) to autoprobe the flash as
-	 * it is programing the flash.
-	 *
-	 * @param bank - the bank to probe
-	 * @returns ERROR_OK if successful; otherwise, an error code.
-	 */
-	int (*auto_probe)(struct flash_bank *bank);
-};
-
-#define FLASH_BANK_COMMAND_HANDLER(name) static __FLASH_BANK_COMMAND(name)
-
-/**
- * Provides details of a flash bank, available either on-chip or through
- * a major interface.
- *
- * This structure will be passed as a parameter to the callbacks in the
- * flash_driver_s structure, some of which may modify the contents of
- * this structure of the area of flash that it defines.  Driver writers
- * may use the @c driver_priv member to store additional data on a
- * per-bank basis, if required.
- */
-struct flash_bank
-{
-	char *name;
-
-	struct target *target; /**< Target to which this bank belongs. */
-
-	struct flash_driver *driver; /**< Driver for this bank. */
-	void *driver_priv; /**< Private driver storage pointer */
-
-	int bank_number; /**< The 'bank' (or chip number) of this instance. */
-	uint32_t base; /**< The base address of this bank */
-	uint32_t size; /**< The size of this chip bank, in bytes */
-
-	int chip_width; /**< Width of the chip in bytes (1,2,4 bytes) */
-	int bus_width; /**< Maximum bus width, in bytes (1,2,4 bytes) */
-
-	/**
-	 * The number of sectors on this chip.  This value will
-	 * be set intially to 0, and the flash driver must set this to
-	 * some non-zero value during "probe()" or "auto_probe()".
-	 */
-	int num_sectors;
-	/// Array of sectors, allocated and initilized by the flash driver
-	struct flash_sector *sectors;
-
-	struct flash_bank *next; /**< The next flash bank on this chip */
-};
-
-/// Registers the 'flash' subsystem commands
-int flash_register_commands(struct command_context *cmd_ctx);
-/// Initializes the 'flash' subsystem drivers
-int flash_init_drivers(struct command_context *cmd_ctx);
-
-/**
- * Erases @a length bytes in the @a target flash, starting at @a addr.
- * @returns ERROR_OK if successful; otherwise, an error code.
- */
-int flash_erase_address_range(struct target *target,
-		uint32_t addr, uint32_t length);
-/**
- * Writes @a image into the @a target flash.  The @a written parameter
- * will contain the
- * @param target The target with the flash to be programmed.
- * @param image The image that will be programmed to flash.
- * @param written On return, contains the number of bytes written.
- * @param erase If non-zero, indicates the flash driver should first
- * erase the corresponding banks or sectors before programming.
- * @returns ERROR_OK if successful; otherwise, an error code.
- */
-int flash_write(struct target *target,
-		struct image *image, uint32_t *written, int erase);
-/**
- * Forces targets to re-examine their erase/protection state.
- * This routine must be called when the system may modify the status.
- */
-void flash_set_dirty(void);
-/// @returns The number of flash banks currently defined.
-int flash_get_bank_count(void);
-/**
- * Provides default erased-bank check handling. Checks to see if
- * the flash driver knows they are erased; if things look uncertain,
- * this routine will call default_flash_mem_blank_check() to confirm.
- * @returns ERROR_OK if successful; otherwise, an error code.
- */
-int default_flash_blank_check(struct flash_bank *bank);
-/**
- * Provides a default blank flash memory check.  Ensures the contents
- * of the given bank have truly been erased.
- * @param bank The flash bank.
- * @returns ERROR_OK if successful; otherwise, an error code.
- */
-int default_flash_mem_blank_check(struct flash_bank *bank);
-
-/**
- * Returns the flash bank specified by @a name, which matches the
- * driver name and a suffix (option) specify the driver-specific
- * bank number. The suffix consists of the '.' and the driver-specific
- * bank number: when two str9x banks are defined, then 'str9x.1' refers
- * to the second.
- */
-struct flash_bank *get_flash_bank_by_name(const char *name);
-/**
- * Returns a flash bank by the specified flash_bank_s bank_number, @a num.
- * @param num The flash bank number.
- * @returns A struct flash_bank for flash bank @a num, or NULL
- */
-struct flash_bank *get_flash_bank_by_num(int num);
-/**
- * Retreives @a bank from a command argument, reporting errors parsing
- * the bank identifier or retreiving the specified bank.  The bank
- * may be identified by its bank number or by @c name.instance, where
- * @a instance is driver-specific.
- * @param name_index The index to the string in args containing the
- * bank identifier.
- * @param bank On output, contians a pointer to the bank or NULL.
- * @returns ERROR_OK on success, or an error indicating the problem.
- */
-COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
-		struct flash_bank **bank);
-/**
- * Returns the flash bank like get_flash_bank_by_num(), without probing.
- * @param num The flash bank number.
- * @returns A struct flash_bank for flash bank @a num, or NULL.
- */
-struct flash_bank *get_flash_bank_by_num_noprobe(int num);
-/**
- * Returns the flash bank located at a specified address.
- * @param target The target, presumed to contain one or more banks.
- * @param addr An address that is within the range of the bank.
- * @returns The struct flash_bank located at @a addr, or NULL.
- */
-struct flash_bank *get_flash_bank_by_addr(struct target *target, uint32_t addr);
+#include <flash/nor/core.h>
 
 #endif /* FLASH_H */
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index bafe424..f185081 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -34,6 +34,7 @@ noinst_HEADERS = \
 	avrf.h \
 	core.h \
 	cfi.h \
+	driver.h \
 	imp.h \
 	lpc2000.h \
 	lpc288x.h \
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index 0c6a804..c1e26cd 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -1,4 +1,7 @@
 /***************************************************************************
+ *   Copyright (C) 2005 by Dominic Rath <Dom...@gm...>              *
+ *   Copyright (C) 2007,2008 Øyvind Harboe <oyv...@zy...>       *
+ *   Copyright (C) 2008 by Spencer Oliver <sp...@sp...>           *
  *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -19,13 +22,157 @@
 #ifndef FLASH_NOR_CORE_H
 #define FLASH_NOR_CORE_H
 
-#include <flash/flash.h>
+#include <flash/common.h>
 
+struct image;
+
+#define FLASH_MAX_ERROR_STR	(128)
+
+/**
+ * Describes the geometry and status of a single flash sector
+ * within a flash bank.  A single bank typically consists of multiple
+ * sectors, each of which can be erased and protected independently.
+ */
+struct flash_sector
+{
+	/// Bus offset from start of the flash chip (in bytes).
+	uint32_t offset;
+	/// Number of bytes in this flash sector.
+	uint32_t size;
+	/**
+	 * Indication of erasure status: 0 = not erased, 1 = erased,
+	 * other = unknown.  Set by @c flash_driver_s::erase_check.
+	 */
+	int is_erased;
+	/**
+	 * Indication of protection status: 0 = unprotected/unlocked,
+	 * 1 = protected/locked, other = unknown.  Set by
+	 * @c flash_driver_s::protect_check.
+	 */
+	int is_protected;
+};
+
+/**
+ * Provides details of a flash bank, available either on-chip or through
+ * a major interface.
+ *
+ * This structure will be passed as a parameter to the callbacks in the
+ * flash_driver_s structure, some of which may modify the contents of
+ * this structure of the area of flash that it defines.  Driver writers
+ * may use the @c driver_priv member to store additional data on a
+ * per-bank basis, if required.
+ */
+struct flash_bank
+{
+	char *name;
+
+	struct target *target; /**< Target to which this bank belongs. */
+
+	struct flash_driver *driver; /**< Driver for this bank. */
+	void *driver_priv; /**< Private driver storage pointer */
+
+	int bank_number; /**< The 'bank' (or chip number) of this instance. */
+	uint32_t base; /**< The base address of this bank */
+	uint32_t size; /**< The size of this chip bank, in bytes */
+
+	int chip_width; /**< Width of the chip in bytes (1,2,4 bytes) */
+	int bus_width; /**< Maximum bus width, in bytes (1,2,4 bytes) */
+
+	/**
+	 * The number of sectors on this chip.  This value will
+	 * be set intially to 0, and the flash driver must set this to
+	 * some non-zero value during "probe()" or "auto_probe()".
+	 */
+	int num_sectors;
+	/// Array of sectors, allocated and initilized by the flash driver
+	struct flash_sector *sectors;
+
+	struct flash_bank *next; /**< The next flash bank on this chip */
+};
+
+/// Registers the 'flash' subsystem commands
+int flash_register_commands(struct command_context *cmd_ctx);
+/// Initializes the 'flash' subsystem drivers
+int flash_init_drivers(struct command_context *cmd_ctx);
+
+/**
+ * Erases @a length bytes in the @a target flash, starting at @a addr.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
+int flash_erase_address_range(struct target *target,
+		uint32_t addr, uint32_t length);
+/**
+ * Writes @a image into the @a target flash.  The @a written parameter
+ * will contain the
+ * @param target The target with the flash to be programmed.
+ * @param image The image that will be programmed to flash.
+ * @param written On return, contains the number of bytes written.
+ * @param erase If non-zero, indicates the flash driver should first
+ * erase the corresponding banks or sectors before programming.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
+int flash_write(struct target *target,
+		struct image *image, uint32_t *written, int erase);
+/**
+ * Forces targets to re-examine their erase/protection state.
+ * This routine must be called when the system may modify the status.
+ */
+void flash_set_dirty(void);
+/// @returns The number of flash banks currently defined.
+int flash_get_bank_count(void);
+/**
+ * Provides default erased-bank check handling. Checks to see if
+ * the flash driver knows they are erased; if things look uncertain,
+ * this routine will call default_flash_mem_blank_check() to confirm.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
+int default_flash_blank_check(struct flash_bank *bank);
+/**
+ * Provides a default blank flash memory check.  Ensures the contents
+ * of the given bank have truly been erased.
+ * @param bank The flash bank.
+ * @returns ERROR_OK if successful; otherwise, an error code.
+ */
+int default_flash_mem_blank_check(struct flash_bank *bank);
+
+/**
+ * Returns the flash bank specified by @a name, which matches the
+ * driver name and a suffix (option) specify the driver-specific
+ * bank number. The suffix consists of the '.' and the driver-specific
+ * bank number: when two str9x banks are defined, then 'str9x.1' refers
+ * to the second.
+ */
+struct flash_bank *get_flash_bank_by_name(const char *name);
+/**
+ * Returns a flash bank by the specified flash_bank_s bank_number, @a num.
+ * @param num The flash bank number.
+ * @returns A struct flash_bank for flash bank @a num, or NULL
+ */
+struct flash_bank *get_flash_bank_by_num(int num);
+/**
+ * Retreives @a bank from a command argument, reporting errors parsing
+ * the bank identifier or retreiving the specified bank.  The bank
+ * may be identified by its bank number or by @c name.instance, where
+ * @a instance is driver-specific.
+ * @param name_index The index to the string in args containing the
+ * bank identifier.
+ * @param bank On output, contians a pointer to the bank or NULL.
+ * @returns ERROR_OK on success, or an error indicating the problem.
+ */
+COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
+		struct flash_bank **bank);
+/**
+ * Returns the flash bank like get_flash_bank_by_num(), without probing.
+ * @param num The flash bank number.
+ * @returns A struct flash_bank for flash bank @a num, or NULL.
+ */
+struct flash_bank *get_flash_bank_by_num_noprobe(int num);
 /**
- * Find a NOR flash driver by its name.
- * @param name The name of the requested driver.
- * @returns The flash_driver called @c name, or NULL if not found.
+ * Returns the flash bank located at a specified address.
+ * @param target The target, presumed to contain one or more banks.
+ * @param addr An address that is within the range of the bank.
+ * @returns The struct flash_bank located at @a addr, or NULL.
  */
-struct flash_driver *flash_driver_find_by_name(const char *name);
+struct flash_bank *get_flash_bank_by_addr(struct target *target, uint32_t addr);
 
 #endif // FLASH_NOR_CORE_H
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
new file mode 100644
index 0000000..de71a39
--- /dev/null
+++ b/src/flash/nor/driver.h
@@ -0,0 +1,201 @@
+/***************************************************************************
+ *   Copyright (C) 2005 by Dominic Rath <Dom...@gm...>              *
+ *   Copyright (C) 2007,2008 Øyvind Harboe <oyv...@zy...>       *
+ *   Copyright (C) 2008 by Spencer Oliver <sp...@sp...>           *
+ *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifndef FLASH_NOR_DRIVER_H
+#define FLASH_NOR_DRIVER_H
+
+struct flash_bank;
+
+#define __FLASH_BANK_COMMAND(name) \
+		COMMAND_HELPER(name, struct flash_bank *bank)
+
+/**
+ * @brief Provides the implementation-independent structure that defines
+ * all of the callbacks required by OpenOCD flash drivers.
+ *
+ * Driver authors must implement the routines defined here, providing an
+ * instance with the fields filled out.  After that, the instance must
+ * be registered in flash.c, so it can be used by the driver lookup system.
+ *
+ * Specifically, the user can issue the command: @par
+ * @code
+ * flash bank DRIVERNAME ...parameters...
+ * @endcode
+ *
+ * OpenOCD will search for the driver with a @c flash_driver_s::name
+ * that matches @c DRIVERNAME.
+ *
+ * The flash subsystem calls some of the other drivers routines a using
+ * corresponding static <code>flash_driver_<i>callback</i>()</code>
+ * routine in flash.c.
+ */
+struct flash_driver
+{
+	/**
+	 * Gives a human-readable name of this flash driver,
+	 * This field is used to select and initialize the driver.
+	 */
+	char *name;
+
+	/**
+	 * An array of driver-specific commands to register.  When called
+	 * during the "flash bank" command, the driver can register addition
+	 * commands to support new flash chip functions.
+	 */
+	const struct command_registration *commands;
+
+	/**
+	 * Finish the "flash bank" command for @a bank.  The
+	 * @a bank parameter will have been filled in by the core flash
+	 * layer when this routine is called, and the driver can store
+	 * additional information in its struct flash_bank::driver_priv field.
+	 *
+	 * The CMD_ARGV are: @par
+	 * @code
+	 * CMD_ARGV[0] = bank
+	 * CMD_ARGV[1] = drivername {name above}
+	 * CMD_ARGV[2] = baseaddress
+	 * CMD_ARGV[3] = lengthbytes
+	 * CMD_ARGV[4] = chip_width_in bytes
+	 * CMD_ARGV[5] = bus_width_bytes
+	 * CMD_ARGV[6] = driver-specific parameters
+	 * @endcode
+	 *
+	 * For example, CMD_ARGV[4] = 16 bit flash, CMD_ARGV[5] = 32bit bus.
+	 *
+	 * If extra arguments are provided (@a CMD_ARGC > 6), they will
+	 * start in @a CMD_ARGV[6].  These can be used to implement
+	 * driver-specific extensions.
+	 *
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	__FLASH_BANK_COMMAND((*flash_bank_command));
+
+	/**
+	 * Bank/sector erase routine (target-specific).  When
+	 * called, the flash driver should erase the specified sectors
+	 * using whatever means are at its disposal.
+	 *
+	 * @param bank The bank of flash to be erased.
+	 * @param first The number of the first sector to erase, typically 0.
+	 * @param last The number of the last sector to erase, typically N-1.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*erase)(struct flash_bank *bank, int first, int last);
+
+	/**
+	 * Bank/sector protection routine (target-specific).
+	 * When called, the driver should disable 'flash write' bits (or
+	 * enable 'erase protection' bits) for the given @a bank and @a
+	 * sectors.
+	 *
+	 * @param bank The bank to protect or unprotect.
+	 * @param set If non-zero, enable protection; if 0, disable it.
+	 * @param first The first sector to (un)protect, typicaly 0.
+	 * @param last The last sector to (un)project, typically N-1.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*protect)(struct flash_bank *bank, int set, int first, int last);
+
+	/**
+	 * Program data into the flash.  Note CPU address will be
+	 * "bank->base + offset", while the physical address is
+	 * dependent upon current target MMU mappings.
+	 *
+	 * @param bank The bank to program
+	 * @param buffer The data bytes to write.
+	 * @param offset The offset into the chip to program.
+	 * @param count The number of bytes to write.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*write)(struct flash_bank *bank,
+			uint8_t *buffer, uint32_t offset, uint32_t count);
+
+	/**
+	 * Probe to determine what kind of flash is present.
+	 * This is invoked by the "probe" script command.
+	 *
+	 * @param bank The bank to probe
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*probe)(struct flash_bank *bank);
+
+	/**
+	 * Check the erasure status of a flash bank.
+	 * When called, the driver routine must perform the required
+	 * checks and then set the @c flash_sector_s::is_erased field
+	 * for each of the flash banks's sectors.
+	 *
+	 * @param bank The bank to check
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*erase_check)(struct flash_bank *bank);
+
+	/**
+	 * Determine if the specific bank is "protected" or not.
+	 * When called, the driver routine must must perform the
+	 * required protection check(s) and then set the @c
+	 * flash_sector_s::is_protected field for each of the flash
+	 * bank's sectors.
+	 *
+	 * @param bank - the bank to check
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*protect_check)(struct flash_bank *bank);
+
+	/**
+	 * Display human-readable information about the flash
+	 * bank into the given buffer.  Drivers must be careful to avoid
+	 * overflowing the buffer.
+	 *
+	 * @param bank - the bank to get info about
+	 * @param char - where to put the text for the human to read
+	 * @param buf_size - the size of the human buffer.
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*info)(struct flash_bank *bank, char *buf, int buf_size);
+
+	/**
+	 * A more gentle flavor of filash_driver_s::probe, performing
+	 * setup with less noise.  Generally, driver routines should test
+	 * to seee if the bank has already been probed; if it has, the
+	 * driver probably should not perform its probe a second time.
+	 *
+	 * This callback is often called from the inside of other
+	 * routines (e.g. GDB flash downloads) to autoprobe the flash as
+	 * it is programing the flash.
+	 *
+	 * @param bank - the bank to probe
+	 * @returns ERROR_OK if successful; otherwise, an error code.
+	 */
+	int (*auto_probe)(struct flash_bank *bank);
+};
+
+#define FLASH_BANK_COMMAND_HANDLER(name) static __FLASH_BANK_COMMAND(name)
+
+/**
+ * Find a NOR flash driver by its name.
+ * @param name The name of the requested driver.
+ * @returns The flash_driver called @c name, or NULL if not found.
+ */
+struct flash_driver *flash_driver_find_by_name(const char *name);
+
+#endif // FLASH_NOR_DRIVER_H
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index be72b5c..7f71d83 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -19,7 +19,7 @@
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
-#include <flash/nor/core.h>
+#include "imp.h"
 
 extern struct flash_driver lpc2000_flash;
 extern struct flash_driver lpc288x_flash;
diff --git a/src/flash/nor/imp.h b/src/flash/nor/imp.h
index 84ef871..4c849fe 100644
--- a/src/flash/nor/imp.h
+++ b/src/flash/nor/imp.h
@@ -21,6 +21,7 @@
 
 // this is an internal header
 #include "core.h"
+#include "driver.h"
 // common flash internals
 #include <flash/common.h>
 // almost all drivers will need this file

commit d9dc604a4d790f557a7ba502babdabffa27eaa17
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 14:06:20 2009 -0800

    remove target.h from flash.h
    
    The flash.h header does not require the target.h header file, but
    its implementation source files do.  Move it to flash/nor/imp.h.

diff --git a/src/flash/flash.h b/src/flash/flash.h
index 1e1be85..8cd50f6 100644
--- a/src/flash/flash.h
+++ b/src/flash/flash.h
@@ -27,7 +27,6 @@
 #define FLASH_H
 
 #include <flash/common.h>
-#include <target/target.h>
 
 struct image;
 
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index 6696912..1b9f5c0 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -23,11 +23,11 @@
 #include "config.h"
 #endif
 
-#include <flash/flash.h>
-#include <target/armv4_5.h>
+#include "imp.h"
 #include <helper/binarybuffer.h>
 #include <helper/time_support.h>
 #include <target/algorithm.h>
+#include <target/armv4_5.h>
 
 
 static int aduc702x_build_sector_list(struct flash_bank *bank);
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index dd4f347..1194e25 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -57,13 +57,9 @@
 #endif
 
 
-#include <stdio.h>
-#include <string.h>
-#include <stddef.h>
-#include <helper/types.h>
-#include <flash/flash.h>
-#include <helper/membuf.h>
+#include "imp.h"
 #include "at91sam3.h"
+#include <helper/membuf.h>
 #include <helper/time_support.h>
 
 #define REG_NAME_WIDTH  (12)
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 3201737..97d6b56 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -49,6 +49,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "at91sam7.h"
 #include <helper/binarybuffer.h>
 
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index fbc9277..6c2d17f 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -21,9 +21,9 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "avrf.h"
 #include <target/avrt.h>
-#include <flash/flash.h>
 
 
 /* AVR_JTAG_Instructions */
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 61b5d4c..c00d65f 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -23,6 +23,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "cfi.h"
 #include "non_cfi.h"
 #include <target/armv4_5.h>
diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index 8f8f746..799015e 100644
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -21,10 +21,10 @@
 #include "config.h"
 #endif
 
-#include <flash/flash.h>
+#include "imp.h"
 #include <target/embeddedice.h>
-#include <target/image.h>
 #include <target/algorithm.h>
+#include <target/image.h>
 
 
 #if 0
diff --git a/src/flash/nor/faux.c b/src/flash/nor/faux.c
index c996522..948f305 100644
--- a/src/flash/nor/faux.c
+++ b/src/flash/nor/faux.c
@@ -21,7 +21,7 @@
 #include "config.h"
 #endif
 
-#include <flash/flash.h>
+#include "imp.h"
 #include <target/image.h>
 #include "hello.h"
 
diff --git a/src/flash/nor/imp.h b/src/flash/nor/imp.h
index ade7297..84ef871 100644
--- a/src/flash/nor/imp.h
+++ b/src/flash/nor/imp.h
@@ -21,6 +21,10 @@
 
 // this is an internal header
 #include "core.h"
+// common flash internals
+#include <flash/common.h>
+// almost all drivers will need this file
+#include <target/target.h>
 
 /**
  * Adds a new NOR bank to the global list of banks.
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 295e3e7..d824c37 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -25,10 +25,11 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "lpc2000.h"
-#include <target/armv7m.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
+#include <target/armv7m.h>
 
 
 /* flash programming support for NXP LPC17xx and LPC2xxx devices
diff --git a/src/flash/nor/lpc288x.c b/src/flash/nor/lpc288x.c
index 252a813..5cb36d0 100644
--- a/src/flash/nor/lpc288x.c
+++ b/src/flash/nor/lpc288x.c
@@ -31,6 +31,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "lpc288x.h"
 #include <helper/binarybuffer.h>
 
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index dc466f8..0b42d48 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -23,11 +23,11 @@
 #endif
 
 
-#include <target/image.h>
-#include <flash/flash.h>
+#include "imp.h"
 #include <helper/binarybuffer.h>
-#include <target/armv4_5.h>
 #include <target/algorithm.h>
+#include <target/armv4_5.h>
+#include <target/image.h>
 
 
 /* 1024 bytes */
diff --git a/src/flash/nor/ocl.c b/src/flash/nor/ocl.c
index 6e3ad1c..961537e 100644
--- a/src/flash/nor/ocl.c
+++ b/src/flash/nor/ocl.c
@@ -21,8 +21,8 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "ocl.h"
-#include <flash/flash.h>
 #include <target/embeddedice.h>
 
 
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index d2289b2..7d98af3 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "pic32mx.h"
 #include <target/mips32.h>
 
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index f0028ea..3988542 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -28,10 +28,11 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "stellaris.h"
-#include <target/armv7m.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
+#include <target/armv7m.h>
 
 
 #define DID0_VER(did0) ((did0 >> 28)&0x07)
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index 3792547..9e761f9 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -24,10 +24,11 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "stm32x.h"
-#include <target/armv7m.h>
 #include <helper/binarybuffer.h>
 #include <target/algorithm.h>
+#include <target/armv7m.h>
 
 
 static int stm32x_mass_erase(struct flash_bank *bank);
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index c5a1c34..4f93ec9 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -24,6 +24,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "str7x.h"
 #include <target/armv4_5.h>
 #include <helper/binarybuffer.h>
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index 045ab20..36096ff 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -27,6 +27,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "str9x.h"
 #include <target/arm966e.h>
 #include <target/algorithm.h>
diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index 87a4b06..734f2d1 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -24,6 +24,7 @@
 #include "config.h"
 #endif
 
+#include "imp.h"
 #include "str9xpec.h"
 #include <target/arm7_9_common.h>
 
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 5965934..7efcbd4 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -22,6 +22,7 @@
 #endif
 
 #include "tms470.h"
+#include "imp.h"
 
 
 /* ----------------------------------------------------------------------
diff --git a/src/server/gdb_server.h b/src/server/gdb_server.h
index 0414975..05666a5 100644
--- a/src/server/gdb_server.h
+++ b/src/server/gdb_server.h
@@ -27,6 +27,7 @@
 #define GDB_SERVER_H
 
 struct image;
+#include <target/target.h>
 
 #define GDB_BUFFER_SIZE	16384
 

commit 1527272fb21beee7839335ea5587e879163d2ed1
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 13:42:09 2009 -0800

    split NOR and NAND flash headers
    
    Moves common flash errors to <flash/common.h> to decouple these two
    mostly unrelated trees of code.

diff --git a/src/flash/common.h b/src/flash/common.h
index e0dcdb3..4098873 100644
--- a/src/flash/common.h
+++ b/src/flash/common.h
@@ -19,7 +19,7 @@
 #ifndef FLASH_COMMON_H
 #define FLASH_COMMON_H
 
-#include <helper/types.h>
+#include <helper/log.h>
 
 /**
  * Parses the optional '.index' portion of a flash bank identifier.
@@ -36,4 +36,13 @@ unsigned get_flash_name_index(const char *name);
  */
 bool flash_driver_name_matches(const char *name, const char *expected);
 
+#define ERROR_FLASH_BANK_INVALID -900
+#define ERROR_FLASH_SECTOR_INVALID -901
+#define ERROR_FLASH_OPERATION_FAILED -902
+#define ERROR_FLASH_DST_OUT_OF_BANK -903
+#define ERROR_FLASH_DST_BREAKS_ALIGNMENT -904
+#define ERROR_FLASH_BUSY -905
+#define ERROR_FLASH_SECTOR_NOT_ERASED -906
+#define ERROR_FLASH_BANK_NOT_PROBED -907
+
 #endif // FLASH_COMMON_H
diff --git a/src/flash/flash.h b/src/flash/flash.h
index 5e31c48..1e1be85 100644
--- a/src/flash/flash.h
+++ b/src/flash/flash.h
@@ -26,8 +26,8 @@
 #ifndef FLASH_H
 #define FLASH_H
 
+#include <flash/common.h>
 #include <target/target.h>
-#include <helper/log.h>
 
 struct image;
 
@@ -349,13 +349,4 @@ struct flash_bank *get_flash_bank_by_num_noprobe(int num);
  */
 struct flash_bank *get_flash_bank_by_addr(struct target *target, uint32_t addr);
 
-#define ERROR_FLASH_BANK_INVALID			(-900)
-#define ERROR_FLASH_SECTOR_INVALID			(-901)
-#define ERROR_FLASH_OPERATION_FAILED		(-902)
-#define ERROR_FLASH_DST_OUT_OF_BANK			(-903)
-#define ERROR_FLASH_DST_BREAKS_ALIGNMENT	(-904)
-#define ERROR_FLASH_BUSY					(-905)
-#define ERROR_FLASH_SECTOR_NOT_ERASED		(-906)
-#define ERROR_FLASH_BANK_NOT_PROBED			(-907)
-
 #endif /* FLASH_H */
diff --git a/src/flash/nand.h b/src/flash/nand.h
index 230cf50..f91deda 100644
--- a/src/flash/nand.h
+++ b/src/flash/nand.h
@@ -25,7 +25,9 @@
 #ifndef NAND_H
 #define NAND_H
 
-#include <flash/flash.h>
+#include <flash/common.h>
+// to be removed later
+#include <target/target.h>
 
 struct nand_device;
 
diff --git a/src/openocd.c b/src/openocd.c
index 0ae0d19..b6dc010 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -34,6 +34,7 @@
 #include <helper/configuration.h>
 #include <xsvf/xsvf.h>
 #include <svf/svf.h>
+#include <flash/flash.h>
 #include <flash/nand.h>
 #include <pld/pld.h>
 #include <flash/mflash.h>

commit 5fdee60fd4d38e59c7b5f7aca5ad50b90e7d61ee
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 04:37:27 2009 -0800

    eliminate src/flash/flash.c
    
    Move remaining NOR flash implemenation into flash/nor/core.c
    Removes flash.c from the build, leaving only its header to split.

diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index cda59e4..b5cd526 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -9,7 +9,6 @@ METASOURCES = AUTO
 noinst_LTLIBRARIES = libflash.la
 libflash_la_SOURCES = \
 	common.c \
-	flash.c \
 	arm_nandio.c \
 	nand_ecc.c \
 	nand_ecc_kw.c \
diff --git a/src/flash/flash.c b/src/flash/flash.c
deleted file mode 100644
index dfeea5b..0000000
--- a/src/flash/flash.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/***************************************************************************
- *   Copyright (C) 2005 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
- *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
- *   oyv...@zy...                                               *
- *                                                                         *
- *   Copyright (C) 2008 by Spencer Oliver                                  *
- *   sp...@sp...                                                  *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "flash.h"
-#include "common.h"
-#include <target/image.h>
-#include <helper/time_support.h>
-
-struct flash_bank *flash_banks;
-
-struct flash_bank *get_flash_bank_by_num_noprobe(int num)
-{
-	struct flash_bank *p;
-	int i = 0;
-
-	for (p = flash_banks; p; p = p->next)
-	{
-		if (i++ == num)
-		{
-			return p;
-		}
-	}
-	LOG_ERROR("flash bank %d does not exist", num);
-	return NULL;
-}
-
-int flash_get_bank_count(void)
-{
-	struct flash_bank *p;
-	int i = 0;
-	for (p = flash_banks; p; p = p->next)
-	{
-		i++;
-	}
-	return i;
-}
-
-struct flash_bank *get_flash_bank_by_name(const char *name)
-{
-	unsigned requested = get_flash_name_index(name);
-	unsigned found = 0;
-
-	struct flash_bank *bank;
-	for (bank = flash_banks; NULL != bank; bank = bank->next)
-	{
-		if (strcmp(bank->name, name) == 0)
-			return bank;
-		if (!flash_driver_name_matches(bank->driver->name, name))
-			continue;
-		if (++found < requested)
-			continue;
-		return bank;
-	}
-	return NULL;
-}
-
-struct flash_bank *get_flash_bank_by_num(int num)
-{
-	struct flash_bank *p = get_flash_bank_by_num_noprobe(num);
-	int retval;
-
-	if (p == NULL)
-		return NULL;
-
-	retval = p->driver->auto_probe(p);
-
-	if (retval != ERROR_OK)
-	{
-		LOG_ERROR("auto_probe failed %d\n", retval);
-		return NULL;
-	}
-	return p;
-}
-
-/* lookup flash bank by address */
-struct flash_bank *get_flash_bank_by_addr(struct target *target, uint32_t addr)
-{
-	struct flash_bank *c;
-
-	/* cycle through bank list */
-	for (c = flash_banks; c; c = c->next)
-	{
-		int retval;
-		retval = c->driver->auto_probe(c);
-
-		if (retval != ERROR_OK)
-		{
-			LOG_ERROR("auto_probe failed %d\n", retval);
-			return NULL;
-		}
-		/* check whether address belongs to this flash bank */
-		if ((addr >= c->base) && (addr <= c->base + (c->size - 1)) && target == c->target)
-			return c;
-	}
-	LOG_ERROR("No flash at address 0x%08" PRIx32 "\n", addr);
-	return NULL;
-}
-
-int default_flash_mem_blank_check(struct flash_bank *bank)
-{
-	struct target *target = bank->target;
-	const int buffer_size = 1024;
-	int i;
-	uint32_t nBytes;
-	int retval = ERROR_OK;
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	uint8_t *buffer = malloc(buffer_size);
-
-	for (i = 0; i < bank->num_sectors; i++)
-	{
-		uint32_t j;
-		bank->sectors[i].is_erased = 1;
-
-		for (j = 0; j < bank->sectors[i].size; j += buffer_size)
-		{
-			uint32_t chunk;
-			chunk = buffer_size;
-			if (chunk > (j - bank->sectors[i].size))
-			{
-				chunk = (j - bank->sectors[i].size);
-			}
-
-			retval = target_read_memory(target, bank->base + bank->sectors[i].offset + j, 4, chunk/4, buffer);
-			if (retval != ERROR_OK)
-			{
-				goto done;
-			}
-
-			for (nBytes = 0; nBytes < chunk; nBytes++)
-			{
-				if (buffer[nBytes] != 0xFF)
-				{
-					bank->sectors[i].is_erased = 0;
-					break;
-				}
-			}
-		}
-	}
-
-	done:
-	free(buffer);
-
-	return retval;
-}
-
-int default_flash_blank_check(struct flash_bank *bank)
-{
-	struct target *target = bank->target;
-	int i;
-	int retval;
-	int fast_check = 0;
-	uint32_t blank;
-
-	if (bank->target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	for (i = 0; i < bank->num_sectors; i++)
-	{
-		uint32_t address = bank->base + bank->sectors[i].offset;
-		uint32_t size = bank->sectors[i].size;
-
-		if ((retval = target_blank_check_memory(target, address, size, &blank)) != ERROR_OK)
-		{
-			fast_check = 0;
-			break;
-		}
-		if (blank == 0xFF)
-			bank->sectors[i].is_erased = 1;
-		else
-			bank->sectors[i].is_erased = 0;
-		fast_check = 1;
-	}
-
-	if (!fast_check)
-	{
-		LOG_USER("Running slow fallback erase check - add working memory");
-		return default_flash_mem_blank_check(bank);
-	}
-
-	return ERROR_OK;
-}
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 0fff8ef..c2ea134 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -1,4 +1,7 @@
 /***************************************************************************
+ *   Copyright (C) 2005 by Dominic Rath <Dom...@gm...>              *
+ *   Copyright (C) 2007,2008 Øyvind Harboe <oyv...@zy...>       *
+ *   Copyright (C) 2008 by Spencer Oliver <sp...@sp...>           *
  *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -20,12 +23,13 @@
 #ifdef HAVE_CONFIG_H
 #include <config.h>
 #endif
-#include <flash/flash.h>
+#include <flash/common.h>
+#include <flash/nor/core.h>
 #include <flash/nor/imp.h>
 #include <target/image.h>
 
-// in flash.c, to be moved here
-extern struct flash_bank *flash_banks;
+
+struct flash_bank *flash_banks;
 
 int flash_driver_erase(struct flash_bank *bank, int first, int last)
 {
@@ -68,7 +72,6 @@ int flash_driver_write(struct flash_bank *bank,
 	return retval;
 }
 
-
 void flash_bank_add(struct flash_bank *bank)
 {
 	/* put flash bank in linked list */
@@ -96,6 +99,186 @@ struct flash_bank *flash_bank_list(void)
 	return flash_banks;
 }
 
+struct flash_bank *get_flash_bank_by_num_noprobe(int num)
+{
+	struct flash_bank *p;
+	int i = 0;
+
+	for (p = flash_banks; p; p = p->next)
+	{
+		if (i++ == num)
+		{
+			return p;
+		}
+	}
+	LOG_ERROR("flash bank %d does not exist", num);
+	return NULL;
+}
+
+int flash_get_bank_count(void)
+{
+	struct flash_bank *p;
+	int i = 0;
+	for (p = flash_banks; p; p = p->next)
+	{
+		i++;
+	}
+	return i;
+}
+
+struct flash_bank *get_flash_bank_by_name(const char *name)
+{
+	unsigned requested = get_flash_name_index(name);
+	unsigned found = 0;
+
+	struct flash_bank *bank;
+	for (bank = flash_banks; NULL != bank; bank = bank->next)
+	{
+		if (strcmp(bank->name, name) == 0)
+			return bank;
+		if (!flash_driver_name_matches(bank->driver->name, name))
+			continue;
+		if (++found < requested)
+			continue;
+		return bank;
+	}
+	return NULL;
+}
+
+struct flash_bank *get_flash_bank_by_num(int num)
+{
+	struct flash_bank *p = get_flash_bank_by_num_noprobe(num);
+	int retval;
+
+	if (p == NULL)
+		return NULL;
+
+	retval = p->driver->auto_probe(p);
+
+	if (retval != ERROR_OK)
+	{
+		LOG_ERROR("auto_probe failed %d\n", retval);
+		return NULL;
+	}
+	return p;
+}
+
+/* lookup flash bank by address */
+struct flash_bank *get_flash_bank_by_addr(struct target *target, uint32_t addr)
+{
+	struct flash_bank *c;
+
+	/* cycle through bank list */
+	for (c = flash_banks; c; c = c->next)
+	{
+		int retval;
+		retval = c->driver->auto_probe(c);
+
+		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("auto_probe failed %d\n", retval);
+			return NULL;
+		}
+		/* check whether address belongs to this flash bank */
+		if ((addr >= c->base) && (addr <= c->base + (c->size - 1)) && target == c->target)
+			return c;
+	}
+	LOG_ERROR("No flash at address 0x%08" PRIx32 "\n", addr);
+	return NULL;
+}
+
+int default_flash_mem_blank_check(struct flash_bank *bank)
+{
+	struct target *target = bank->target;
+	const int buffer_size = 1024;
+	int i;
+	uint32_t nBytes;
+	int retval = ERROR_OK;
+
+	if (bank->target->state != TARGET_HALTED)
+	{
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	uint8_t *buffer = malloc(buffer_size);
+
+	for (i = 0; i < bank->num_sectors; i++)
+	{
+		uint32_t j;
+		bank->sectors[i].is_erased = 1;
+
+		for (j = 0; j < bank->sectors[i].size; j += buffer_size)
+		{
+			uint32_t chunk;
+			chunk = buffer_size;
+			if (chunk > (j - bank->sectors[i].size))
+			{
+				chunk = (j - bank->sectors[i].size);
+			}
+
+			retval = target_read_memory(target, bank->base + bank->sectors[i].offset + j, 4, chunk/4, buffer);
+			if (retval != ERROR_OK)
+			{
+				goto done;
+			}
+
+			for (nBytes = 0; nBytes < chunk; nBytes++)
+			{
+				if (buffer[nBytes] != 0xFF)
+				{
+					bank->sectors[i].is_erased = 0;
+					break;
+				}
+			}
+		}
+	}
+
+	done:
+	free(buffer);
+
+	return retval;
+}
+
+int default_flash_blank_check(struct flash_bank *bank)
+{
+	struct target *target = bank->target;
+	int i;
+	int retval;
+	int fast_check = 0;
+	uint32_t blank;
+
+	if (bank->target->state != TARGET_HALTED)
+	{
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	for (i = 0; i < bank->num_sectors; i++)
+	{
+		uint32_t address = bank->base + bank->sectors[i].offset;
+		uint32_t size = bank->sectors[i].size;
+
+		if ((retval = target_blank_check_memory(target, address, size, &blank)) != ERROR_OK)
+		{
+			fast_check = 0;
+			break;
+		}
+		if (blank == 0xFF)
+			bank->sectors[i].is_erased = 1;
+		else
+			bank->sectors[i].is_erased = 0;
+		fast_check = 1;
+	}
+
+	if (!fast_check)
+	{
+		LOG_USER("Running slow fallback erase check - add working memory");
+		return default_flash_mem_blank_check(bank);
+	}
+
+	return ERROR_OK;
+}
 /* erase given flash region, selects proper bank according to target and address */
 static int flash_iterate_address_range(struct target *target, uint32_t addr, uint32_t length,
 		int (*callback)(struct flash_bank *bank, int first, int last))

commit c90702eaa7e7c4e7dd6d1efea61387a62748cfad
Author: Zachary T Welch <zw...@su...>
Date:   Fri Dec 4 04:10:42 2009 -0800

    add flash/nor/drivers.c
    
    Encapsulates access to the flash_drivers array, providing a base
    of operations for future dynamic driver module loading features.

diff --git a/src/flash/flash.c b/src/flash/flash.c
index 2cf56ed..dfeea5b 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -32,49 +32,6 @@
 #include <target/image.h>
 #include <helper/time_support.h>
 
-/* flash drivers
- */
-extern struct flash_driver lpc2000_flash;
-extern struct flash_driver lpc288x_flash;
-extern struct flash_driver lpc2900_flash;
-extern struct flash_driver cfi_flash;
-extern struct flash_dri...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-856-g32f961d

[David B. <dbr...@us...>]

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generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  32f961daba1301ac22ed53c9bc0822effff168cf (commit)
       via  bdde9460b923ab61fad678bf1e3f0da04e1d94ee (commit)
      from  acd6d3399486110e69db8d5ec752e10067c29ad0 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 32f961daba1301ac22ed53c9bc0822effff168cf
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 16:51:48 2009 -0800

    ARM: semihosting entry cleanup
    
    Clean up arm_semihosting() entry a bit, comment some issues and just
    which SVC opcodes are getting intercepted.  Microcontroller profile
    cores will need a new entry, since they use BKPT instead (and don't
    have either SVC mode or an SPSR register).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 4788686..7fe0a97 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -56,6 +56,9 @@ static int do_semihosting(struct target *target)
 	 * - no validation on target provided file descriptors
 	 * - no safety checks on opened/deleted/renamed file paths
 	 * Beware the target app you use this support with.
+	 *
+	 * TODO: explore mapping requests to GDB's "File-I/O Remote
+	 * Protocol Extension" ... when GDB is active.
 	 */
 	switch (r0) {
 	case 0x01:	/* SYS_OPEN */
@@ -396,42 +399,70 @@ static int do_semihosting(struct target *target)
  * or an error was encountered, in which case the caller must return
  * immediately.
  *
- * @param target Pointer to the ARM target to process
+ * @param target Pointer to the ARM target to process.  This target must
+ *	not represent an ARMv6-M or ARMv7-M processor.
  * @param retval Pointer to a location where the return code will be stored
  * @return non-zero value if a request was processed or an error encountered
  */
 int arm_semihosting(struct target *target, int *retval)
 {
-	struct arm *armv4_5 = target_to_armv4_5(target);
+	struct arm *arm = target_to_armv4_5(target);
 	uint32_t lr, spsr;
+	struct reg *r;
+
+	if (!arm->is_semihosting || arm->core_mode != ARMV4_5_MODE_SVC)
+		return 0;
 
-	if (!armv4_5->is_semihosting ||
-	    armv4_5->core_mode != ARMV4_5_MODE_SVC ||
-	    buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != 0x08)
+	/* Check for PC == 8:  Supervisor Call vector
+	 * REVISIT:  assumes low exception vectors, not hivecs...
+	 * safer to test "was this entry from a vector catch".
+	 */
+	r = arm->core_cache->reg_list + 15;
+	if (buf_get_u32(r->value, 0, 32) != 0x08)
 		return 0;
 
-	lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARMV4_5_MODE_SVC, 14).value, 0, 32);
-	spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);
+	r = arm_reg_current(arm, 14);
+	lr = buf_get_u32(r->value, 0, 32);
+
+	/* Core-specific code should make sure SPSR is retrieved
+	 * when the above checks pass...
+	 */
+	if (!arm->spsr->valid) {
+		LOG_ERROR("SPSR not valid!");
+		*retval = ERROR_FAIL;
+		return 1;
+	}
+
+	spsr = buf_get_u32(arm->spsr->value, 0, 32);
 
 	/* check instruction that triggered this trap */
 	if (spsr & (1 << 5)) {
-		/* was in Thumb mode */
+		/* was in Thumb (or ThumbEE) mode */
 		uint8_t insn_buf[2];
 		uint16_t insn;
+
 		*retval = target_read_memory(target, lr-2, 2, 1, insn_buf);
 		if (*retval != ERROR_OK)
 			return 1;
 		insn = target_buffer_get_u16(target, insn_buf);
+
+		/* SVC 0xab */
 		if (insn != 0xDFAB)
 			return 0;
+	} else if (spsr & (1 << 24)) {
+		/* was in Jazelle mode */
+		return 0;
 	} else {
 		/* was in ARM mode */
 		uint8_t insn_buf[4];
 		uint32_t insn;
+
 		*retval = target_read_memory(target, lr-4, 4, 1, insn_buf);
 		if (*retval != ERROR_OK)
 			return 1;
 		insn = target_buffer_get_u32(target, insn_buf);
+
+		/* SVC 0x123456 */
 		if (insn != 0xEF123456)
 			return 0;
 	}

commit bdde9460b923ab61fad678bf1e3f0da04e1d94ee
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 16:51:48 2009 -0800

    ARM: remove semihosting globals
    
    Store a flag and errno in in "struct arm".
    Have "poll" output report when semihosting is active.
    Shrink some of the affected lines.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 7318b5f..b411672 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2831,22 +2831,32 @@ COMMAND_HANDLER(handle_arm7_9_semihosting_command)
 
 	if (CMD_ARGC > 0)
 	{
-		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting_active);
+		int semihosting;
+
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
 
 		/* TODO: support other methods if vector catch is unavailable */
 		if (arm7_9->has_vector_catch) {
-			struct reg *vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
+			struct reg *vector_catch = &arm7_9->eice_cache
+					->reg_list[EICE_VEC_CATCH];
+
 			if (!vector_catch->valid)
 				embeddedice_read_reg(vector_catch);
-			buf_set_u32(vector_catch->value, 2, 1, semihosting_active);
+			buf_set_u32(vector_catch->value, 2, 1, semihosting);
 			embeddedice_store_reg(vector_catch);
-		} else if (semihosting_active) {
+
+			/* FIXME never let that "catch" be dropped! */
+
+			arm7_9->armv4_5_common.is_semihosting = semihosting;
+
+		} else if (semihosting) {
 			command_print(CMD_CTX, "vector catch unavailable");
-			semihosting_active = 0;
 		}
 	}
 
-	command_print(CMD_CTX, "semihosting is %s", (semihosting_active) ? "enabled" : "disabled");
+	command_print(CMD_CTX, "semihosting is %s",
+			arm7_9->armv4_5_common.is_semihosting
+			? "enabled" : "disabled");
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 2aa684f..4788686 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -40,9 +40,6 @@
 #include <helper/binarybuffer.h>
 #include <helper/log.h>
 
-/* TODO: this needs to be per target */
-int semihosting_active;
-int semihosting_errno;
 
 static int do_semihosting(struct target *target)
 {
@@ -93,10 +90,10 @@ static int do_semihosting(struct target *target)
 						result = dup(1);
 				} else
 					result = open((char *)fn, mode);
-				semihosting_errno =  errno;
+				armv4_5->semihosting_errno =  errno;
 			} else {
 				result = -1;
-				semihosting_errno = EINVAL;
+				armv4_5->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -108,7 +105,7 @@ static int do_semihosting(struct target *target)
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
 			result = close(fd);
-			semihosting_errno = errno;
+			armv4_5->semihosting_errno = errno;
 		}
 		break;
 
@@ -147,7 +144,7 @@ static int do_semihosting(struct target *target)
 			uint8_t *buf = malloc(l);
 			if (!buf) {
 				result = -1;
-				semihosting_errno = ENOMEM;
+				armv4_5->semihosting_errno = ENOMEM;
 			} else {
 				retval = target_read_buffer(target, a, l, buf);
 				if (retval != ERROR_OK) {
@@ -155,7 +152,7 @@ static int do_semihosting(struct target *target)
 					return retval;
 				}
 				result = write(fd, buf, l);
-				semihosting_errno = errno;
+				armv4_5->semihosting_errno = errno;
 				if (result >= 0)
 					result = l - result;
 				free(buf);
@@ -174,10 +171,10 @@ static int do_semihosting(struct target *target)
 			uint8_t *buf = malloc(l);
 			if (!buf) {
 				result = -1;
-				semihosting_errno = ENOMEM;
+				armv4_5->semihosting_errno = ENOMEM;
 			} else {
 				result = read(fd, buf, l);
-				semihosting_errno = errno;
+				armv4_5->semihosting_errno = errno;
 				if (result > 0) {
 					retval = target_write_buffer(target, a, result, buf);
 					if (retval != ERROR_OK) {
@@ -217,7 +214,7 @@ static int do_semihosting(struct target *target)
 			int fd = target_buffer_get_u32(target, params+0);
 			off_t pos = target_buffer_get_u32(target, params+4);
 			result = lseek(fd, pos, SEEK_SET);
-			semihosting_errno = errno;
+			armv4_5->semihosting_errno = errno;
 			if (result == pos)
 				result = 0;
 		}
@@ -231,14 +228,14 @@ static int do_semihosting(struct target *target)
 			int fd = target_buffer_get_u32(target, params+0);
 			off_t cur = lseek(fd, 0, SEEK_CUR);
 			if (cur == (off_t)-1) {
-				semihosting_errno = errno;
+				armv4_5->semihosting_errno = errno;
 				result = -1;
 				break;
 			}
 			result = lseek(fd, 0, SEEK_END);
-			semihosting_errno = errno;
+			armv4_5->semihosting_errno = errno;
 			if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
-				semihosting_errno = errno;
+				armv4_5->semihosting_errno = errno;
 				result = -1;
 			}
 		}
@@ -258,10 +255,10 @@ static int do_semihosting(struct target *target)
 					return retval;
 				fn[l] = 0;
 				result = remove((char *)fn);
-				semihosting_errno =  errno;
+				armv4_5->semihosting_errno =  errno;
 			} else {
 				result = -1;
-				semihosting_errno = EINVAL;
+				armv4_5->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -286,10 +283,10 @@ static int do_semihosting(struct target *target)
 				fn1[l1] = 0;
 				fn2[l2] = 0;
 				result = rename((char *)fn1, (char *)fn2);
-				semihosting_errno =  errno;
+				armv4_5->semihosting_errno =  errno;
 			} else {
 				result = -1;
-				semihosting_errno = EINVAL;
+				armv4_5->semihosting_errno = EINVAL;
 			}
 		}
 		break;
@@ -299,7 +296,7 @@ static int do_semihosting(struct target *target)
 		break;
 
 	case 0x13:	/* SYS_ERRNO */
-		result = semihosting_errno;
+		result = armv4_5->semihosting_errno;
 		break;
 
 	case 0x15:	/* SYS_GET_CMDLINE */
@@ -375,7 +372,7 @@ static int do_semihosting(struct target *target)
 		fprintf(stderr, "semihosting: unsupported call %#x\n",
 				(unsigned) r0);
 		result = -1;
-		semihosting_errno = ENOTSUP;
+		armv4_5->semihosting_errno = ENOTSUP;
 	}
 
 	/* resume execution to the original mode */
@@ -408,7 +405,7 @@ int arm_semihosting(struct target *target, int *retval)
 	struct arm *armv4_5 = target_to_armv4_5(target);
 	uint32_t lr, spsr;
 
-	if (!semihosting_active ||
+	if (!armv4_5->is_semihosting ||
 	    armv4_5->core_mode != ARMV4_5_MODE_SVC ||
 	    buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != 0x08)
 		return 0;
diff --git a/src/target/arm_semihosting.h b/src/target/arm_semihosting.h
index 6b9ac56..80cad39 100644
--- a/src/target/arm_semihosting.h
+++ b/src/target/arm_semihosting.h
@@ -21,8 +21,6 @@
 #ifndef ARM_SEMIHOSTING_H
 #define ARM_SEMIHOSTING_H
 
-extern int semihosting_active;
-
 int arm_semihosting(struct target *target, int *retval);
 
 #endif
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 80c06ef..412b829 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -587,16 +587,20 @@ int armv4_5_arch_state(struct target *target)
 
 	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 	{
-		LOG_ERROR("BUG: called for a non-ARMv4/5 target");
+		LOG_ERROR("BUG: called for a non-ARM target");
 		return ERROR_FAIL;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
+	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s",
 			 armv4_5_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
+			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+					target->debug_reason)->name,
 			 arm_mode_name(armv4_5->core_mode),
 			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+			buf_get_u32(armv4_5->core_cache->reg_list[15].value,
+					0, 32),
+			armv4_5->is_semihosting ? ", semihosting" : "");
 
 	return ERROR_OK;
 }
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 6c83c3b..615e486 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -103,6 +103,12 @@ struct arm
 	/** Flag reporting unavailability of the BKPT instruction. */
 	bool is_armv4;
 
+	/** Flag reporting whether semihosting is active. */
+	bool is_semihosting;
+
+	/** Value to be returned by semihosting SYS_ERRNO request. */
+	int semihosting_errno;
+
 	/** Backpointer to the target. */
 	struct target *target;
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm7_9_common.c   |   22 ++++++++---
 src/target/arm_semihosting.c |   84 ++++++++++++++++++++++++++++--------------
 src/target/arm_semihosting.h |    2 -
 src/target/armv4_5.c         |   12 ++++--
 src/target/armv4_5.h         |    6 +++
 5 files changed, 86 insertions(+), 40 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-854-gacd6d33

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  acd6d3399486110e69db8d5ec752e10067c29ad0 (commit)
      from  146e841fc920e1caea702ef42e2088244b9b8464 (commit)

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- Log -----------------------------------------------------------------
commit acd6d3399486110e69db8d5ec752e10067c29ad0
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 10:11:31 2009 -0800

    User's Guide: more semihosting info
    
    List it in the concept index, in the section about target software
    changes a project might want to consider, and in the section about
    debug messaging.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4d13f07..b6be87e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -873,6 +873,20 @@ handling issues like:
 
 @itemize @bullet
 
+@item @b{ARM Semihosting}...
+@cindex ARM semihosting
+When linked with a special runtime library provided with many
+toolchains@footnote{See chapter 8 "Semihosting" in
+@uref{http://infocenter.arm.com/help/topic/com.arm.doc.dui0203i/DUI0203I_rvct_developer_guide.pdf,
+ARM DUI 0203I}, the "RealView Compilation Tools Developer Guide".
+The CodeSourcery EABI toolchain also includes a semihosting library.},
+your target code can use I/O facilities on the debug host.  That library
+provides a small set of system calls which are handled by OpenOCD.
+It can let the debugger provide your system console and a file system,
+helping with early debugging or providing a more capable environment
+for sometimes-complex tasks like installing system firmware onto
+NAND or SPI flash.
+
 @item @b{ARM Wait-For-Interrupt}...
 Many ARM chips synchronize the JTAG clock using the core clock.
 Low power states which stop that core clock thus prevent JTAG access.
@@ -5675,6 +5689,7 @@ speeds, like the 32kHz startup clock of an AT91RM9200.
 @end deffn
 
 @deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
+@cindex ARM semihosting
 Display status of semihosting, after optionally changing that status.
 
 Semihosting allows for code executing on an ARM target to use the
@@ -6049,8 +6064,12 @@ This finishes by listing the current vector catch configuration.
 @cindex tracing
 @cindex libdcc
 @cindex DCC
-OpenOCD can process certain requests from target software.  Currently
-@command{target_request debugmsgs}
+OpenOCD can process certain requests from target software, when
+the target uses appropriate libraries.
+The most powerful mechanism is semihosting, but there is also
+a lighter weight mechanism using only the DCC channel.
+
+Currently @command{target_request debugmsgs}
 is supported only for @option{arm7_9} and @option{cortex_m3} cores.
 These messages are received as part of target polling, so
 you need to have @command{poll on} active to receive them.

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |   23 +++++++++++++++++++++--
 1 files changed, 21 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-853-g146e841

[Øyvind H. <go...@us...>]

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The branch, master has been updated
       via  146e841fc920e1caea702ef42e2088244b9b8464 (commit)
      from  c65d94f7d0e0c511794ea1f42ddf01e66f97e236 (commit)

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- Log -----------------------------------------------------------------
commit 146e841fc920e1caea702ef42e2088244b9b8464
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Dec 4 09:50:55 2009 +0100

    bootstrap: stop execution upon error
    
    When tools are not installed, exit immediately. This makes
    the error messages clearer.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/bootstrap b/bootstrap
index 7684dc4..268d07c 100755
--- a/bootstrap
+++ b/bootstrap
@@ -1,6 +1,9 @@
 #!/bin/sh -e
 # Run the autotools bootstrap sequence to create the configure script
 
+# Stop execution as soon as we have an unknown command 
+set -e
+
 if libtoolize --version >/dev/null 2>&1; then
 	libtoolize="libtoolize"
 elif glibtoolize --version >/dev/null 2>&1; then

-----------------------------------------------------------------------

Summary of changes:
 bootstrap |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)


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- Log -----------------------------------------------------------------
commit c65d94f7d0e0c511794ea1f42ddf01e66f97e236
Author: Zachary T Welch <zw...@su...>
Date:   Thu Dec 3 17:14:07 2009 -0800

    add flash/nor/core.[ch]
    
    The newly moved flash TCL routines access the internals of the module
    too much.  Fix the layering issues by adding new core NOR flash APIs:
    
    <flash/nor/core.h>:
      - flash_driver_find_by_name() - self-descriptive
    
    <flash/nor/imp.h>:
      - flash_bank_add()            - encapsulates adding banks to bank list
      - flash_bank_list()           - encapsulates retreiving bank list
    
    This allows the externs in flash/nor/imp.h to be removed, and
    these mechanisms may now be re-used by other flash module code.

diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index ed9ebb3..499ebfa 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -2,6 +2,7 @@ AM_CPPFLAGS = -I$(top_srcdir)/src
 
 noinst_LTLIBRARIES = libocdflashnor.la
 libocdflashnor_la_SOURCES = \
+	core.c \
 	tcl.c \
 	$(NOR_DRIVERS)
 
diff --git a/src/flash/nor/imp.h b/src/flash/nor/core.c
similarity index 66%
copy from src/flash/nor/imp.h
copy to src/flash/nor/core.c
index 29d7f7e..a69c3f4 100644
--- a/src/flash/nor/imp.h
+++ b/src/flash/nor/core.c
@@ -16,12 +16,50 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
-#ifndef FLASH_NOR_IMP_H
-#define FLASH_NOR_IMP_H
 
+#ifdef HAVE_CONFIG_H
+#include <config.h>
+#endif
 #include <flash/flash.h>
+#include <flash/nor/imp.h>
 
+// in flash.c, to be moved here
 extern struct flash_driver *flash_drivers[];
 extern struct flash_bank *flash_banks;
 
-#endif // FLASH_NOR_IMP_H
+struct flash_driver *flash_driver_find_by_name(const char *name)
+{
+	for (unsigned i = 0; flash_drivers[i]; i++)
+	{
+		if (strcmp(name, flash_drivers[i]->name) == 0)
+			return flash_drivers[i];
+	}
+	return NULL;
+}
+
+void flash_bank_add(struct flash_bank *bank)
+{
+	/* put flash bank in linked list */
+	unsigned bank_num = 0;
+	if (flash_banks)
+	{
+		/* find last flash bank */
+		struct flash_bank *p = flash_banks;
+		while (NULL != p->next)
+		{
+			bank_num += 1;
+			p = p->next;
+		}
+		p->next = bank;
+		bank_num += 1;
+	}
+	else
+		flash_banks = bank;
+
+	bank->bank_number = bank_num;
+}
+
+struct flash_bank *flash_bank_list(void)
+{
+	return flash_banks;
+}
diff --git a/src/flash/nor/imp.h b/src/flash/nor/core.h
similarity index 82%
copy from src/flash/nor/imp.h
copy to src/flash/nor/core.h
index 29d7f7e..0c6a804 100644
--- a/src/flash/nor/imp.h
+++ b/src/flash/nor/core.h
@@ -16,12 +16,16 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
-#ifndef FLASH_NOR_IMP_H
-#define FLASH_NOR_IMP_H
+#ifndef FLASH_NOR_CORE_H
+#define FLASH_NOR_CORE_H
 
 #include <flash/flash.h>
 
-extern struct flash_driver *flash_drivers[];
-extern struct flash_bank *flash_banks;
+/**
+ * Find a NOR flash driver by its name.
+ * @param name The name of the requested driver.
+ * @returns The flash_driver called @c name, or NULL if not found.
+ */
+struct flash_driver *flash_driver_find_by_name(const char *name);
 
-#endif // FLASH_NOR_IMP_H
+#endif // FLASH_NOR_CORE_H
diff --git a/src/flash/nor/imp.h b/src/flash/nor/imp.h
index 29d7f7e..23ac476 100644
--- a/src/flash/nor/imp.h
+++ b/src/flash/nor/imp.h
@@ -19,9 +19,18 @@
 #ifndef FLASH_NOR_IMP_H
 #define FLASH_NOR_IMP_H
 
-#include <flash/flash.h>
+// this is an internal header
+#include "core.h"
 
-extern struct flash_driver *flash_drivers[];
-extern struct flash_bank *flash_banks;
+/**
+ * Adds a new NOR bank to the global list of banks.
+ * @params bank The bank that should be added.
+ */
+void flash_bank_add(struct flash_bank *bank);
+
+/**
+ * @return The first bank in the global list.
+ */
+struct flash_bank *flash_bank_list(void);
 
 #endif // FLASH_NOR_IMP_H
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 8c13241..b00516d 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -44,84 +44,65 @@ COMMAND_HANDLER(handle_flash_bank_command)
 	}
 
 	const char *driver_name = CMD_ARGV[0];
-	for (unsigned i = 0; flash_drivers[i]; i++)
+	struct flash_driver *driver = flash_driver_find_by_name(driver_name);
+	if (NULL == driver)
 	{
-		if (strcmp(driver_name, flash_drivers[i]->name) != 0)
-			continue;
-
-		/* register flash specific commands */
-		if (NULL != flash_drivers[i]->commands)
-		{
-			int retval = register_commands(CMD_CTX, NULL,
-					flash_drivers[i]->commands);
-			if (ERROR_OK != retval)
-			{
-				LOG_ERROR("couldn't register '%s' commands",
-						driver_name);
-				return ERROR_FAIL;
-			}
-		}
+		/* no matching flash driver found */
+		LOG_ERROR("flash driver '%s' not found", driver_name);
+		return ERROR_FAIL;
+	}
 
-		struct flash_bank *p, *c;
-		c = malloc(sizeof(struct flash_bank));
-		c->name = strdup(bank_name);
-		c->target = target;
-		c->driver = flash_drivers[i];
-		c->driver_priv = NULL;
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
-		c->num_sectors = 0;
-		c->sectors = NULL;
-		c->next = NULL;
-
-		int retval;
-		retval = CALL_COMMAND_HANDLER(flash_drivers[i]->flash_bank_command, c);
+	/* register flash specific commands */
+	if (NULL != driver->commands)
+	{
+		int retval = register_commands(CMD_CTX, NULL,
+				driver->commands);
 		if (ERROR_OK != retval)
 		{
-			LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32,
-					driver_name, c->base);
-			free(c);
-			return retval;
-		}
-
-		/* put flash bank in linked list */
-		if (flash_banks)
-		{
-			int	bank_num = 0;
-			/* find last flash bank */
-			for (p = flash_banks; p && p->next; p = p->next) bank_num++;
-			if (p)
-				p->next = c;
-			c->bank_number = bank_num + 1;
-		}
-		else
-		{
-			flash_banks = c;
-			c->bank_number = 0;
+			LOG_ERROR("couldn't register '%s' commands",
+					driver_name);
+			return ERROR_FAIL;
 		}
+	}
 
-		return ERROR_OK;
+	struct flash_bank *c = malloc(sizeof(*c));
+	c->name = strdup(bank_name);
+	c->target = target;
+	c->driver = driver;
+	c->driver_priv = NULL;
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
+	COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
+	COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
+	c->num_sectors = 0;
+	c->sectors = NULL;
+	c->next = NULL;
+
+	int retval;
+	retval = CALL_COMMAND_HANDLER(driver->flash_bank_command, c);
+	if (ERROR_OK != retval)
+	{
+		LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32,
+				driver_name, c->base);
+		free(c);
+		return retval;
 	}
 
-	/* no matching flash driver found */
-	LOG_ERROR("flash driver '%s' not found", driver_name);
-	return ERROR_FAIL;
+	return ERROR_OK;
+
 }
 
 
 static int jim_flash_banks(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
-	struct flash_bank *p;
-
 	if (argc != 1) {
 		Jim_WrongNumArgs(interp, 1, argv, "no arguments to flash_banks command");
 		return JIM_ERR;
 	}
 
 	Jim_Obj *list = Jim_NewListObj(interp, NULL, 0);
-	for (p = flash_banks; p; p = p->next)
+
+	for (struct flash_bank *p = flash_bank_list(); p; p = p->next)
 	{
 		Jim_Obj *elem = Jim_NewListObj(interp, NULL, 0);
 

commit 3cb0b56005059314c8d09d2f8574042a4352dab4
Author: Zachary T Welch <zw...@su...>
Date:   Thu Dec 3 16:47:49 2009 -0800

    add flash/nor/{tcl.c,imp.h} from flash/flash.c
    
    Moves the top-level 'flash' command handlers into flash/nor/tcl.c,
    with flash/nor/imp.h providing an internal implementation header
    to share non-public API components.

diff --git a/src/flash/flash.c b/src/flash/flash.c
index d16949d..b21838c 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -120,39 +120,6 @@ int flash_driver_protect(struct flash_bank *bank, int set, int first, int last)
 	return retval;
 }
 
-static int jim_flash_banks(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
-{
-	struct flash_bank *p;
-
-	if (argc != 1) {
-		Jim_WrongNumArgs(interp, 1, argv, "no arguments to flash_banks command");
-		return JIM_ERR;
-	}
-
-	Jim_Obj *list = Jim_NewListObj(interp, NULL, 0);
-	for (p = flash_banks; p; p = p->next)
-	{
-		Jim_Obj *elem = Jim_NewListObj(interp, NULL, 0);
-
-		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "name", -1));
-		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, p->driver->name, -1));
-		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "base", -1));
-		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->base));
-		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "size", -1));
-		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->size));
-		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "bus_width", -1));
-		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->bus_width));
-		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "chip_width", -1));
-		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->chip_width));
-
-		Jim_ListAppendElement(interp, list, elem);
-	}
-
-	Jim_SetResult(interp, list);
-
-	return JIM_OK;
-}
-
 struct flash_bank *get_flash_bank_by_num_noprobe(int num)
 {
 	struct flash_bank *p;
@@ -238,92 +205,6 @@ COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
 }
 
 
-COMMAND_HANDLER(handle_flash_bank_command)
-{
-	if (CMD_ARGC < 7)
-	{
-		LOG_ERROR("usage: flash bank <name> <driver> "
-				"<base> <size> <chip_width> <bus_width>");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-	// save bank name and advance arguments for compatibility
-	const char *bank_name = *CMD_ARGV++;
-	CMD_ARGC--;
-
-	struct target *target;
-	if ((target = get_target(CMD_ARGV[5])) == NULL)
-	{
-		LOG_ERROR("target '%s' not defined", CMD_ARGV[5]);
-		return ERROR_FAIL;
-	}
-
-	const char *driver_name = CMD_ARGV[0];
-	for (unsigned i = 0; flash_drivers[i]; i++)
-	{
-		if (strcmp(driver_name, flash_drivers[i]->name) != 0)
-			continue;
-
-		/* register flash specific commands */
-		if (NULL != flash_drivers[i]->commands)
-		{
-			int retval = register_commands(CMD_CTX, NULL,
-					flash_drivers[i]->commands);
-			if (ERROR_OK != retval)
-			{
-				LOG_ERROR("couldn't register '%s' commands",
-						driver_name);
-				return ERROR_FAIL;
-			}
-		}
-
-		struct flash_bank *p, *c;
-		c = malloc(sizeof(struct flash_bank));
-		c->name = strdup(bank_name);
-		c->target = target;
-		c->driver = flash_drivers[i];
-		c->driver_priv = NULL;
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
-		c->num_sectors = 0;
-		c->sectors = NULL;
-		c->next = NULL;
-
-		int retval;
-		retval = CALL_COMMAND_HANDLER(flash_drivers[i]->flash_bank_command, c);
-		if (ERROR_OK != retval)
-		{
-			LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32,
-					driver_name, c->base);
-			free(c);
-			return retval;
-		}
-
-		/* put flash bank in linked list */
-		if (flash_banks)
-		{
-			int	bank_num = 0;
-			/* find last flash bank */
-			for (p = flash_banks; p && p->next; p = p->next) bank_num++;
-			if (p)
-				p->next = c;
-			c->bank_number = bank_num + 1;
-		}
-		else
-		{
-			flash_banks = c;
-			c->bank_number = 0;
-		}
-
-		return ERROR_OK;
-	}
-
-	/* no matching flash driver found */
-	LOG_ERROR("flash driver '%s' not found", driver_name);
-	return ERROR_FAIL;
-}
-
 COMMAND_HANDLER(handle_flash_info_command)
 {
 	struct flash_bank *p;
@@ -1375,59 +1256,3 @@ int flash_init_drivers(struct command_context *cmd_ctx)
 	return register_commands(cmd_ctx, parent, flash_exec_command_handlers);
 }
 
-COMMAND_HANDLER(handle_flash_init_command)
-{
-	if (CMD_ARGC != 0)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	static bool flash_initialized = false;
-	if (flash_initialized)
-	{
-		LOG_INFO("'flash init' has already been called");
-		return ERROR_OK;
-	}
-	flash_initialized = true;
-
-	LOG_DEBUG("Initializing flash devices...");
-	return flash_init_drivers(CMD_CTX);
-}
-
-static const struct command_registration flash_config_command_handlers[] = {
-	{
-		.name = "bank",
-		.handler = &handle_flash_bank_command,
-		.mode = COMMAND_CONFIG,
-		.usage = "<name> <driver> <base> <size> "
-			"<chip_width> <bus_width> <target> "
-			"[driver_options ...]",
-		.help = "Define a new bank with the given name, "
-			"using the specified NOR flash driver.",
-	},
-	{
-		.name = "init",
-		.mode = COMMAND_CONFIG,
-		.handler = &handle_flash_init_command,
-		.help = "initialize flash devices",
-	},
-	{
-		.name = "banks",
-		.mode = COMMAND_ANY,
-		.jim_handler = &jim_flash_banks,
-		.help = "return information about the flash banks",
-	},
-	COMMAND_REGISTRATION_DONE
-};
-static const struct command_registration flash_command_handlers[] = {
-	{
-		.name = "flash",
-		.mode = COMMAND_ANY,
-		.help = "NOR flash command group",
-		.chain = flash_config_command_handlers,
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-int flash_register_commands(struct command_context *cmd_ctx)
-{
-	return register_commands(cmd_ctx, NULL, flash_command_handlers);
-}
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 211366b..ed9ebb3 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -2,6 +2,10 @@ AM_CPPFLAGS = -I$(top_srcdir)/src
 
 noinst_LTLIBRARIES = libocdflashnor.la
 libocdflashnor_la_SOURCES = \
+	tcl.c \
+	$(NOR_DRIVERS)
+
+NOR_DRIVERS = \
 	aduc702x.c \
 	at91sam3.c \
 	at91sam7.c \
@@ -27,6 +31,7 @@ noinst_HEADERS = \
 	at91sam3.h \
 	avrf.h \
 	cfi.h \
+	imp.h \
 	lpc2000.h \
 	lpc288x.h \
 	non_cfi.h \
diff --git a/src/flash/nor/imp.h b/src/flash/nor/imp.h
new file mode 100644
index 0000000..29d7f7e
--- /dev/null
+++ b/src/flash/nor/imp.h
@@ -0,0 +1,27 @@
+/***************************************************************************
+ *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifndef FLASH_NOR_IMP_H
+#define FLASH_NOR_IMP_H
+
+#include <flash/flash.h>
+
+extern struct flash_driver *flash_drivers[];
+extern struct flash_bank *flash_banks;
+
+#endif // FLASH_NOR_IMP_H
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
new file mode 100644
index 0000000..8c13241
--- /dev/null
+++ b/src/flash/nor/tcl.c
@@ -0,0 +1,203 @@
+/***************************************************************************
+ *   Copyright (C) 2005 by Dominic Rath <Dom...@gm...>              *
+ *   Copyright (C) 2007,2008 Øyvind Harboe <oyv...@zy...>       *
+ *   Copyright (C) 2008 by Spencer Oliver <sp...@sp...>           *
+ *   Copyright (C) 2009 Zachary T Welch <zw...@su...>             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+#include "imp.h"
+
+COMMAND_HANDLER(handle_flash_bank_command)
+{
+	if (CMD_ARGC < 7)
+	{
+		LOG_ERROR("usage: flash bank <name> <driver> "
+				"<base> <size> <chip_width> <bus_width>");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+	// save bank name and advance arguments for compatibility
+	const char *bank_name = *CMD_ARGV++;
+	CMD_ARGC--;
+
+	struct target *target;
+	if ((target = get_target(CMD_ARGV[5])) == NULL)
+	{
+		LOG_ERROR("target '%s' not defined", CMD_ARGV[5]);
+		return ERROR_FAIL;
+	}
+
+	const char *driver_name = CMD_ARGV[0];
+	for (unsigned i = 0; flash_drivers[i]; i++)
+	{
+		if (strcmp(driver_name, flash_drivers[i]->name) != 0)
+			continue;
+
+		/* register flash specific commands */
+		if (NULL != flash_drivers[i]->commands)
+		{
+			int retval = register_commands(CMD_CTX, NULL,
+					flash_drivers[i]->commands);
+			if (ERROR_OK != retval)
+			{
+				LOG_ERROR("couldn't register '%s' commands",
+						driver_name);
+				return ERROR_FAIL;
+			}
+		}
+
+		struct flash_bank *p, *c;
+		c = malloc(sizeof(struct flash_bank));
+		c->name = strdup(bank_name);
+		c->target = target;
+		c->driver = flash_drivers[i];
+		c->driver_priv = NULL;
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], c->base);
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], c->size);
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], c->chip_width);
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], c->bus_width);
+		c->num_sectors = 0;
+		c->sectors = NULL;
+		c->next = NULL;
+
+		int retval;
+		retval = CALL_COMMAND_HANDLER(flash_drivers[i]->flash_bank_command, c);
+		if (ERROR_OK != retval)
+		{
+			LOG_ERROR("'%s' driver rejected flash bank at 0x%8.8" PRIx32,
+					driver_name, c->base);
+			free(c);
+			return retval;
+		}
+
+		/* put flash bank in linked list */
+		if (flash_banks)
+		{
+			int	bank_num = 0;
+			/* find last flash bank */
+			for (p = flash_banks; p && p->next; p = p->next) bank_num++;
+			if (p)
+				p->next = c;
+			c->bank_number = bank_num + 1;
+		}
+		else
+		{
+			flash_banks = c;
+			c->bank_number = 0;
+		}
+
+		return ERROR_OK;
+	}
+
+	/* no matching flash driver found */
+	LOG_ERROR("flash driver '%s' not found", driver_name);
+	return ERROR_FAIL;
+}
+
+
+static int jim_flash_banks(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+{
+	struct flash_bank *p;
+
+	if (argc != 1) {
+		Jim_WrongNumArgs(interp, 1, argv, "no arguments to flash_banks command");
+		return JIM_ERR;
+	}
+
+	Jim_Obj *list = Jim_NewListObj(interp, NULL, 0);
+	for (p = flash_banks; p; p = p->next)
+	{
+		Jim_Obj *elem = Jim_NewListObj(interp, NULL, 0);
+
+		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "name", -1));
+		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, p->driver->name, -1));
+		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "base", -1));
+		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->base));
+		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "size", -1));
+		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->size));
+		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "bus_width", -1));
+		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->bus_width));
+		Jim_ListAppendElement(interp, elem, Jim_NewStringObj(interp, "chip_width", -1));
+		Jim_ListAppendElement(interp, elem, Jim_NewIntObj(interp, p->chip_width));
+
+		Jim_ListAppendElement(interp, list, elem);
+	}
+
+	Jim_SetResult(interp, list);
+
+	return JIM_OK;
+}
+
+
+COMMAND_HANDLER(handle_flash_init_command)
+{
+	if (CMD_ARGC != 0)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	static bool flash_initialized = false;
+	if (flash_initialized)
+	{
+		LOG_INFO("'flash init' has already been called");
+		return ERROR_OK;
+	}
+	flash_initialized = true;
+
+	LOG_DEBUG("Initializing flash devices...");
+	return flash_init_drivers(CMD_CTX);
+}
+
+static const struct command_registration flash_config_command_handlers[] = {
+	{
+		.name = "bank",
+		.handler = &handle_flash_bank_command,
+		.mode = COMMAND_CONFIG,
+		.usage = "<name> <driver> <base> <size> "
+			"<chip_width> <bus_width> <target> "
+			"[driver_options ...]",
+		.help = "Define a new bank with the given name, "
+			"using the specified NOR flash driver.",
+	},
+	{
+		.name = "init",
+		.mode = COMMAND_CONFIG,
+		.handler = &handle_flash_init_command,
+		.help = "initialize flash devices",
+	},
+	{
+		.name = "banks",
+		.mode = COMMAND_ANY,
+		.jim_handler = &jim_flash_banks,
+		.help = "return information about the flash banks",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration flash_command_handlers[] = {
+	{
+		.name = "flash",
+		.mode = COMMAND_ANY,
+		.help = "NOR flash command group",
+		.chain = flash_config_command_handlers,
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+int flash_register_commands(struct command_context *cmd_ctx)
+{
+	return register_commands(cmd_ctx, NULL, flash_command_handlers);
+}

commit 79a73a786ee0f95b49d86abbdea1e985049c5b1f
Author: Zachary T Welch <zw...@su...>
Date:   Thu Dec 3 16:25:51 2009 -0800

    separate Jim from jtag/core.c
    
    After previous efforts, only one Jim routine remained in jtag/core.c,
    and moving it to jtag/tcl.c painlessly finishes separating these layers.
    The headers need separating, but the implementation is clean.

diff --git a/src/jtag/core.c b/src/jtag/core.c
index 9230cc2..433b50b 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -244,17 +244,6 @@ struct jtag_tap *jtag_tap_by_string(const char *s)
 	return t;
 }
 
-struct jtag_tap *jtag_tap_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
-{
-	const char *cp = Jim_GetString(o, NULL);
-	struct jtag_tap *t = cp ? jtag_tap_by_string(cp) : NULL;
-	if (NULL == cp)
-		cp = "(unknown)";
-	if (NULL == t)
-		Jim_SetResult_sprintf(interp, "Tap '%s' could not be found", cp);
-	return t;
-}
-
 struct jtag_tap* jtag_tap_next_enabled(struct jtag_tap* p)
 {
 	p = p ? p->next_tap : jtag_all_taps();
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 81bafbb..9704c30 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -51,6 +51,17 @@ static const Jim_Nvp nvp_jtag_tap_event[] = {
 
 extern struct jtag_interface *jtag_interface;
 
+struct jtag_tap *jtag_tap_by_jim_obj(Jim_Interp *interp, Jim_Obj *o)
+{
+	const char *cp = Jim_GetString(o, NULL);
+	struct jtag_tap *t = cp ? jtag_tap_by_string(cp) : NULL;
+	if (NULL == cp)
+		cp = "(unknown)";
+	if (NULL == t)
+		Jim_SetResult_sprintf(interp, "Tap '%s' could not be found", cp);
+	return t;
+}
+
 static bool scan_is_safe(tap_state_t state)
 {
 	switch (state)

commit b58c1d808fcdeb7a751c1ecf4e5512a8943ec263
Author: Zachary T Welch <zw...@su...>
Date:   Thu Dec 3 16:22:46 2009 -0800

    switch 'rm' command away from using Jim
    
    Commands that do not need to use Jim should be registered as
    high-level command handlers.

diff --git a/src/helper/ioutil.c b/src/helper/ioutil.c
index ed82ba1..27bffad 100644
--- a/src/helper/ioutil.c
+++ b/src/helper/ioutil.c
@@ -401,25 +401,18 @@ void copydir(char *name, char *destdir)
 
 
 
-static int
-zylinjtag_Jim_Command_rm(Jim_Interp *interp,
-                                   int argc,
-		Jim_Obj * const *argv)
+COMMAND_HANDLER(handle_rm_command)
 {
-	int del;
-	if (argc != 2)
-	{
-		Jim_WrongNumArgs(interp, 1, argv, "rm ?dirorfile?");
-		return JIM_ERR;
-	}
+	if (CMD_ARGC != 1)
+		return ERROR_INVALID_ARGUMENTS;
 
-	del = 0;
-	if (unlink(Jim_GetString(argv[1], NULL)) == 0)
-		del = 1;
-	if (rmdir(Jim_GetString(argv[1], NULL)) == 0)
-		del = 1;
+	bool del = false;
+	if (rmdir(CMD_ARGV[0]) == 0)
+		del = true;
+	else if (unlink(CMD_ARGV[0]) == 0)
+		del = true;
 
-	return del ? JIM_OK : JIM_ERR;
+	return del ? ERROR_OK : ERROR_FAIL;
 }
 
 
@@ -658,14 +651,14 @@ static const struct command_registration ioutil_command_handlers[] = {
 		.mode = COMMAND_ANY,
 		.help = "display available ram memory",
 	},
-	// jim handlers
 	{
 		.name = "rm",
 		.mode = COMMAND_ANY,
-		.jim_handler = &zylinjtag_Jim_Command_rm,
+		.handler = &handle_rm_command,
 		.help = "remove a file",
 		.usage = "<file>",
 	},
+	// jim handlers
 	{
 		.name = "peek",
 		.mode = COMMAND_ANY,

-----------------------------------------------------------------------

Summary of changes:
 src/flash/flash.c                               |  175 ---------------------
 src/flash/nor/Makefile.am                       |    6 +
 src/{server/server_stubs.c => flash/nor/core.c} |   43 +++++-
 src/{helper/ioutil_stubs.c => flash/nor/core.h} |   21 ++--
 src/{helper/ioutil.h => flash/nor/imp.h}        |   19 ++-
 src/flash/nor/tcl.c                             |  184 +++++++++++++++++++++++
 src/helper/ioutil.c                             |   29 ++---
 src/jtag/core.c                                 |   11 --
 src/jtag/tcl.c                                  |   11 ++
 9 files changed, 275 insertions(+), 224 deletions(-)
 copy src/{server/server_stubs.c => flash/nor/core.c} (64%)
 copy src/{helper/ioutil_stubs.c => flash/nor/core.h} (80%)
 copy src/{helper/ioutil.h => flash/nor/imp.h} (78%)
 create mode 100644 src/flash/nor/tcl.c


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-848-gc5eb8e2

[Zach W. <zw...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c5eb8e29bdc296c2d0b25cc771639567b5f7707f (commit)
       via  eae56d27c3892188560918526710d44d147b0c8d (commit)
      from  a535d2f64337f39902aebd1a5e9488a85f542b7f (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit c5eb8e29bdc296c2d0b25cc771639567b5f7707f
Author: Zachary T Welch <zw...@su...>
Date:   Thu Dec 3 17:38:24 2009 -0800

    check top-level command registrations
    
    When calling module_register_commands, the return value needs to be
    checked for failures.  Instead of duplicating code, use an array of
    function pointers to the identical registration functions to iterate
    over during startup.

diff --git a/src/openocd.c b/src/openocd.c
index da15969..0ae0d19 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -184,6 +184,11 @@ static const struct command_registration openocd_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
+int openocd_register_commands(struct command_context *cmd_ctx)
+{
+	return register_commands(cmd_ctx, NULL, openocd_command_handlers);
+}
+
 struct command_context *global_cmd_ctx;
 
 /* NB! this fn can be invoked outside this file for non PC hosted builds */
@@ -192,28 +197,41 @@ struct command_context *setup_command_handler(Jim_Interp *interp)
 	log_init();
 	LOG_DEBUG("log_init: complete");
 
-	struct command_context *cmd_ctx;
-
-	global_cmd_ctx = cmd_ctx = command_init(openocd_startup_tcl, interp);
+	const char *startup = openocd_startup_tcl;
+	struct command_context *cmd_ctx = command_init(startup, interp);
 
-	register_commands(cmd_ctx, NULL, openocd_command_handlers);
 	/* register subsystem commands */
-	server_register_commands(cmd_ctx);
-	gdb_register_commands(cmd_ctx);
-	log_register_commands(cmd_ctx);
-	jtag_register_commands(cmd_ctx);
-	xsvf_register_commands(cmd_ctx);
-	svf_register_commands(cmd_ctx);
-	target_register_commands(cmd_ctx);
-	flash_register_commands(cmd_ctx);
-	nand_register_commands(cmd_ctx);
-	pld_register_commands(cmd_ctx);
-	mflash_register_commands(cmd_ctx);
-
+	typedef int (*command_registrant_t)(struct command_context *cmd_ctx);
+	command_registrant_t command_registrants[] = {
+		&openocd_register_commands,
+		&server_register_commands,
+		&gdb_register_commands,
+		&log_register_commands,
+		&jtag_register_commands,
+		&xsvf_register_commands,
+		&svf_register_commands,
+		&target_register_commands,
+		&flash_register_commands,
+		&nand_register_commands,
+		&pld_register_commands,
+		&mflash_register_commands,
+		NULL
+	};
+	for (unsigned i = 0; NULL != command_registrants[i]; i++)
+	{
+		int retval = (*command_registrants[i])(cmd_ctx);
+		if (ERROR_OK != retval)
+		{
+			command_done(cmd_ctx);
+			return NULL;
+		}
+	}
 	LOG_DEBUG("command registration: complete");
 
 	LOG_OUTPUT(OPENOCD_VERSION "\n");
 
+	global_cmd_ctx = cmd_ctx;
+
 	return cmd_ctx;
 }
 

commit eae56d27c3892188560918526710d44d147b0c8d
Author: Zachary T Welch <zw...@su...>
Date:   Thu Dec 3 17:41:39 2009 -0800

    allow 'jtag init' to be run in any mode
    
    Help alleviate further potential problems with interactive startup.

diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index cc89080..81bafbb 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -828,7 +828,7 @@ COMMAND_HANDLER(handle_jtag_init_command)
 static const struct command_registration jtag_subcommand_handlers[] = {
 	{
 		.name = "init",
-		.mode = COMMAND_CONFIG,
+		.mode = COMMAND_ANY,
 		.handler = &handle_jtag_init_command,
 		.help = "initialize jtag scan chain",
 	},

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/tcl.c |    2 +-
 src/openocd.c  |   50 ++++++++++++++++++++++++++++++++++----------------
 2 files changed, 35 insertions(+), 17 deletions(-)


hooks/post-receive
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Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-846-ga535d2f

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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a535d2f64337f39902aebd1a5e9488a85f542b7f (commit)
      from  24551b7b92725fb2b26d042c2e88330e3d1d4d21 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit a535d2f64337f39902aebd1a5e9488a85f542b7f
Author: David Brownell <dbr...@us...>
Date:   Fri Dec 4 00:42:36 2009 -0800

    target: cygwin build fixes
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index c5d797e..a9ce880 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -55,7 +55,9 @@ static int dpm_mrc(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
+	LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
+			(int) op1, (int) CRn,
+			(int) CRm, (int) op2);
 
 	/* read coprocessor register into R0; return via DCC */
 	retval = dpm->instr_read_data_r0(dpm,
@@ -78,7 +80,9 @@ static int dpm_mcr(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum, op1, CRn, CRm, op2);
+	LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
+			(int) op1, (int) CRn,
+			(int) CRm, (int) op2);
 
 	/* read DCC into r0; then write coprocessor register from R0 */
 	retval = dpm->instr_write_data_r0(dpm,
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 5e0a2be..2aa684f 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -360,7 +360,8 @@ static int do_semihosting(struct target *target)
 		case 0x20028:	/* ADP_Stopped_DivisionByZero */
 		case 0x20029:	/* ADP_Stopped_OSSpecific */
 		default:
-			fprintf(stderr, "semihosting: exception %#x\n", r1);
+			fprintf(stderr, "semihosting: exception %#x\n",
+					(unsigned) r1);
 		}
 		return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
@@ -371,7 +372,8 @@ static int do_semihosting(struct target *target)
 	case 0x30:	/* SYS_ELAPSED */
 	case 0x31:	/* SYS_TICKFREQ */
 	default:
-		fprintf(stderr, "semihosting: unsupported call %#x\n", r0);
+		fprintf(stderr, "semihosting: unsupported call %#x\n",
+				(unsigned) r0);
 		result = -1;
 		semihosting_errno = ENOTSUP;
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_dpm.c         |    8 ++++++--
 src/target/arm_semihosting.c |    6 ++++--
 2 files changed, 10 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-845-g24551b7

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  24551b7b92725fb2b26d042c2e88330e3d1d4d21 (commit)
      from  ed59dfc80aa6fc48a0894c8e46cee675f38ac949 (commit)

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- Log -----------------------------------------------------------------
commit 24551b7b92725fb2b26d042c2e88330e3d1d4d21
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Dec 4 08:20:38 2009 +0100

    zy1000: FPGA revC wip
    
    The bug in revC register memory access is pretty much
    cornered now.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/jtag_minidriver.h b/src/jtag/zy1000/jtag_minidriver.h
index afbea13..536c677 100644
--- a/src/jtag/zy1000/jtag_minidriver.h
+++ b/src/jtag/zy1000/jtag_minidriver.h
@@ -18,6 +18,7 @@
  ***************************************************************************/
 
 #include <cyg/hal/hal_io.h>             // low level i/o
+#include <cyg/hal/hal_intr.h>             // low level i/o
 
 //#define VERBOSE(a) a
 #define VERBOSE(a)
@@ -31,10 +32,16 @@ int  diag_printf(const char *fmt, ...);
 #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b); diag_printf("peek 0x%08x = 0x%08x\n", a, b)
 #else
 #define ZY1000_PEEK(a, b) HAL_READ_UINT32(a, b)
-#define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b);\
- {/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
- flush every "often". No precise system has been found, but 4 seems solid. \
-  */ \
+
+#ifdef CYGPKG_HAL_NIOS2
+#define ZY1000_POKE(a, b) \
+		 {/* This will flush the bridge FIFO. Overflowed bridge FIFO fails. We must \
+		 flush every "often". No precise system has been found, but 4 seems solid. \
+		  This code goes away once the FPGA has been fixed. */ \
+\
+CYG_INTERRUPT_STATE _old_; \
+HAL_DISABLE_INTERRUPTS(_old_); \
+HAL_WRITE_UINT32(a, b);\
  static int overflow_counter = 0; \
    if (++overflow_counter >= 1) \
    { \
@@ -42,7 +49,14 @@ int  diag_printf(const char *fmt, ...);
 	   cyg_uint32 empty; ZY1000_PEEK(ZY1000_JTAG_BASE + 0x10, empty); \
 	   overflow_counter = 0; \
    } \
- }
+   /* NB! interrupts must be restored *after* read */ \
+   HAL_RESTORE_INTERRUPTS(_old_); \
+}\
+
+#else
+#define ZY1000_POKE(a, b) HAL_WRITE_UINT32(a, b)
+#endif
+
 #endif
 
 // FIFO empty?

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/zy1000/jtag_minidriver.h |   24 +++++++++++++++++++-----
 1 files changed, 19 insertions(+), 5 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.3.0-844-ged59dfc

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       via  f62c035c5277871193fa9904f430cf57221c0b89 (commit)
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- Log -----------------------------------------------------------------
commit ed59dfc80aa6fc48a0894c8e46cee675f38ac949
Author: Nicolas Pitre <ni...@fl...>
Date:   Thu Dec 3 17:27:13 2009 -0500

    basic ARM semihosting support
    
    Semihosting enables code running on an ARM target to use the
    I/O facilities on the host computer. The target application must
    be linked against a library that forwards operation requests by
    using the SVC instruction that is trapped at the Supervisor Call
    vector by the debugger.  The "hosted" library version provided
    with CodeSourcery's Sourcery G++ Lite for ARM EABI is one example.
    
    This is currently available for ARM9 processors, but any ARM
    variant should be able to support this with little additional work.
    
    Tested using binaries compiled with Sourcery G++ Lite 2009q1-161
    and ARM RVCT 3.0.
    
    [dbr...@us...: doc tweaks, NEWS]
    
    Signed-off-by: Nicolas Pitre <ni...@ma...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWS b/NEWS
index 1af1331..38ae4da 100644
--- a/NEWS
+++ b/NEWS
@@ -17,6 +17,7 @@ Target Layer:
 		- register names use "sp" not "r13"
 		- add top-level "mcr" and "mrc" commands, replacing
 		  various core-specific operations
+		- basic semihosting support
 	ARM11
 		- Preliminary ETM and ETB hookup
 		- accelerated "flash erase_check"
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7e23211..4d13f07 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5674,6 +5674,17 @@ cables (FT2232), but might be unsafe if used with targets running at very low
 speeds, like the 32kHz startup clock of an AT91RM9200.
 @end deffn
 
+@deffn Command {arm7_9 semihosting} [@option{enable}|@option{disable}]
+Display status of semihosting, after optionally changing that status.
+
+Semihosting allows for code executing on an ARM target to use the
+I/O facilities on the host computer i.e. the system where OpenOCD
+is running. The target application must be linked against a library
+implementing the ARM semihosting convention that forwards operation
+requests by using a special SVC instruction that is trapped at the
+Supervisor Call vector by OpenOCD.
+@end deffn
+
 @subsection ARM720T specific commands
 @cindex ARM720T
 
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 7631bea..bd7bf7a 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -78,6 +78,7 @@ ARM_DEBUG_SRC = \
 	arm_jtag.c \
 	arm_disassembler.c \
 	arm_simulator.c \
+	arm_semihosting.c \
 	arm_adi_v5.c \
 	embeddedice.c \
 	trace.c \
@@ -101,6 +102,7 @@ noinst_HEADERS = \
 	arm_adi_v5.h \
 	arm_disassembler.h \
 	arm_simulator.h \
+	arm_semihosting.h \
 	arm7_9_common.h \
 	arm7tdmi.h \
 	arm720t.h \
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 255a85f..7318b5f 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -36,6 +36,7 @@
 #include "etm.h"
 #include <helper/time_support.h>
 #include "arm_simulator.h"
+#include "arm_semihosting.h"
 #include "algorithm.h"
 #include "register.h"
 
@@ -915,6 +916,9 @@ int arm7_9_poll(struct target *target)
 				}
 			}
 
+			if (arm_semihosting(target, &retval) != 0)
+				return retval;
+
 			if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 			{
 				return retval;
@@ -2814,6 +2818,39 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_arm7_9_semihosting_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+	if (!is_arm7_9(arm7_9))
+	{
+		command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+		return ERROR_TARGET_INVALID;
+	}
+
+	if (CMD_ARGC > 0)
+	{
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting_active);
+
+		/* TODO: support other methods if vector catch is unavailable */
+		if (arm7_9->has_vector_catch) {
+			struct reg *vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
+			if (!vector_catch->valid)
+				embeddedice_read_reg(vector_catch);
+			buf_set_u32(vector_catch->value, 2, 1, semihosting_active);
+			embeddedice_store_reg(vector_catch);
+		} else if (semihosting_active) {
+			command_print(CMD_CTX, "vector catch unavailable");
+			semihosting_active = 0;
+		}
+	}
+
+	command_print(CMD_CTX, "semihosting is %s", (semihosting_active) ? "enabled" : "disabled");
+
+	return ERROR_OK;
+}
+
 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 {
 	int retval = ERROR_OK;
@@ -2867,6 +2904,13 @@ static const struct command_registration arm7_9_any_command_handlers[] = {
 		.usage = "<enable | disable>",
 		.help = "use DCC downloads for larger memory writes",
 	},
+	{
+		"semihosting",
+		.handler = &handle_arm7_9_semihosting_command,
+		.mode = COMMAND_EXEC,
+		.usage = "<enable | disable>",
+		.help = "activate support for semihosting operations",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 const struct command_registration arm7_9_command_handlers[] = {
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
new file mode 100644
index 0000000..5e0a2be
--- /dev/null
+++ b/src/target/arm_semihosting.c
@@ -0,0 +1,442 @@
+/***************************************************************************
+ *   Copyright (C) 2009 by Marvell Technology Group Ltd.                   *
+ *   Written by Nicolas Pitre <ni...@ma...>                           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+/**
+ * @file
+ * Hold ARM semihosting support.
+ *
+ * Semihosting enables code running on an ARM target to use the I/O
+ * facilities on the host computer. The target application must be linked
+ * against a library that forwards operation requests by using the SVC
+ * instruction trapped at the Supervisor Call vector by the debugger.
+ * Details can be found in chapter 8 of DUI0203I_rvct_developer_guide.pdf
+ * from ARM Ltd.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "armv4_5.h"
+#include "register.h"
+#include "arm_semihosting.h"
+#include <helper/binarybuffer.h>
+#include <helper/log.h>
+
+/* TODO: this needs to be per target */
+int semihosting_active;
+int semihosting_errno;
+
+static int do_semihosting(struct target *target)
+{
+	struct arm *armv4_5 = target_to_armv4_5(target);
+	uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
+	uint32_t r1 = buf_get_u32(armv4_5->core_cache->reg_list[1].value, 0, 32);
+	uint32_t lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARMV4_5_MODE_SVC, 14).value, 0, 32);
+	uint32_t spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);;
+	uint8_t params[16];
+	int retval, result;
+
+	/*
+	 * TODO: lots of security issues are not considered yet, such as:
+	 * - no validation on target provided file descriptors
+	 * - no safety checks on opened/deleted/renamed file paths
+	 * Beware the target app you use this support with.
+	 */
+	switch (r0) {
+	case 0x01:	/* SYS_OPEN */
+		retval = target_read_memory(target, r1, 4, 3, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			uint32_t a = target_buffer_get_u32(target, params+0);
+			uint32_t m = target_buffer_get_u32(target, params+4);
+			uint32_t l = target_buffer_get_u32(target, params+8);
+			if (l <= 255 && m <= 11) {
+				uint8_t fn[256];
+				int mode;
+				retval = target_read_memory(target, a, 1, l, fn);
+				if (retval != ERROR_OK)
+					return retval;
+				fn[l] = 0;
+				if (m & 0x2)
+					mode = O_RDWR;
+				else if (m & 0xc)
+					mode = O_WRONLY;
+				else
+					mode = O_RDONLY;
+				if (m >= 8)
+					mode |= O_CREAT|O_APPEND;
+				else if (m >= 4)
+					mode |= O_CREAT|O_TRUNC;
+				if (strcmp((char *)fn, ":tt") == 0) {
+					if ((mode & 3) == 0)
+						result = dup(0);
+					else
+						result = dup(1);
+				} else
+					result = open((char *)fn, mode);
+				semihosting_errno =  errno;
+			} else {
+				result = -1;
+				semihosting_errno = EINVAL;
+			}
+		}
+		break;
+
+	case 0x02:	/* SYS_CLOSE */
+		retval = target_read_memory(target, r1, 4, 1, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			int fd = target_buffer_get_u32(target, params+0);
+			result = close(fd);
+			semihosting_errno = errno;
+		}
+		break;
+
+	case 0x03:	/* SYS_WRITEC */
+		{
+			unsigned char c;
+			retval = target_read_memory(target, r1, 1, 1, &c);
+			if (retval != ERROR_OK)
+				return retval;
+			putchar(c);
+			result = 0;
+		}
+		break;
+
+	case 0x04:	/* SYS_WRITE0 */
+		do {
+			unsigned char c;
+			retval = target_read_memory(target, r1, 1, 1, &c);
+			if (retval != ERROR_OK)
+				return retval;
+			if (!c)
+				break;
+			putchar(c);
+		} while (1);
+		result = 0;
+		break;
+
+	case 0x05:	/* SYS_WRITE */
+		retval = target_read_memory(target, r1, 4, 3, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			int fd = target_buffer_get_u32(target, params+0);
+			uint32_t a = target_buffer_get_u32(target, params+4);
+			size_t l = target_buffer_get_u32(target, params+8);
+			uint8_t *buf = malloc(l);
+			if (!buf) {
+				result = -1;
+				semihosting_errno = ENOMEM;
+			} else {
+				retval = target_read_buffer(target, a, l, buf);
+				if (retval != ERROR_OK) {
+					free(buf);
+					return retval;
+				}
+				result = write(fd, buf, l);
+				semihosting_errno = errno;
+				if (result >= 0)
+					result = l - result;
+				free(buf);
+			}
+		}
+		break;
+
+	case 0x06:	/* SYS_READ */
+		retval = target_read_memory(target, r1, 4, 3, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			int fd = target_buffer_get_u32(target, params+0);
+			uint32_t a = target_buffer_get_u32(target, params+4);
+			ssize_t l = target_buffer_get_u32(target, params+8);
+			uint8_t *buf = malloc(l);
+			if (!buf) {
+				result = -1;
+				semihosting_errno = ENOMEM;
+			} else {
+				result = read(fd, buf, l);
+				semihosting_errno = errno;
+				if (result > 0) {
+					retval = target_write_buffer(target, a, result, buf);
+					if (retval != ERROR_OK) {
+						free(buf);
+						return retval;
+					}
+					result = l - result;
+				}
+				free(buf);
+			}
+		}
+		break;
+
+	case 0x07:	/* SYS_READC */
+		result = getchar();
+		break;
+
+	case 0x08:	/* SYS_ISERROR */
+		retval = target_read_memory(target, r1, 4, 1, params);
+		if (retval != ERROR_OK)
+			return retval;
+		result = (target_buffer_get_u32(target, params+0) != 0);
+		break;
+
+	case 0x09:	/* SYS_ISTTY */
+		retval = target_read_memory(target, r1, 4, 1, params);
+		if (retval != ERROR_OK)
+			return retval;
+		result = isatty(target_buffer_get_u32(target, params+0));
+		break;
+
+	case 0x0a:	/* SYS_SEEK */
+		retval = target_read_memory(target, r1, 4, 2, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			int fd = target_buffer_get_u32(target, params+0);
+			off_t pos = target_buffer_get_u32(target, params+4);
+			result = lseek(fd, pos, SEEK_SET);
+			semihosting_errno = errno;
+			if (result == pos)
+				result = 0;
+		}
+		break;
+
+	case 0x0c:	/* SYS_FLEN */
+		retval = target_read_memory(target, r1, 4, 1, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			int fd = target_buffer_get_u32(target, params+0);
+			off_t cur = lseek(fd, 0, SEEK_CUR);
+			if (cur == (off_t)-1) {
+				semihosting_errno = errno;
+				result = -1;
+				break;
+			}
+			result = lseek(fd, 0, SEEK_END);
+			semihosting_errno = errno;
+			if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
+				semihosting_errno = errno;
+				result = -1;
+			}
+		}
+		break;
+
+	case 0x0e:	/* SYS_REMOVE */
+		retval = target_read_memory(target, r1, 4, 2, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			uint32_t a = target_buffer_get_u32(target, params+0);
+			uint32_t l = target_buffer_get_u32(target, params+4);
+			if (l <= 255) {
+				uint8_t fn[256];
+				retval = target_read_memory(target, a, 1, l, fn);
+				if (retval != ERROR_OK)
+					return retval;
+				fn[l] = 0;
+				result = remove((char *)fn);
+				semihosting_errno =  errno;
+			} else {
+				result = -1;
+				semihosting_errno = EINVAL;
+			}
+		}
+		break;
+
+	case 0x0f:	/* SYS_RENAME */
+		retval = target_read_memory(target, r1, 4, 4, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			uint32_t a1 = target_buffer_get_u32(target, params+0);
+			uint32_t l1 = target_buffer_get_u32(target, params+4);
+			uint32_t a2 = target_buffer_get_u32(target, params+8);
+			uint32_t l2 = target_buffer_get_u32(target, params+12);
+			if (l1 <= 255 && l2 <= 255) {
+				uint8_t fn1[256], fn2[256];
+				retval = target_read_memory(target, a1, 1, l1, fn1);
+				if (retval != ERROR_OK)
+					return retval;
+				retval = target_read_memory(target, a2, 1, l2, fn2);
+				if (retval != ERROR_OK)
+					return retval;
+				fn1[l1] = 0;
+				fn2[l2] = 0;
+				result = rename((char *)fn1, (char *)fn2);
+				semihosting_errno =  errno;
+			} else {
+				result = -1;
+				semihosting_errno = EINVAL;
+			}
+		}
+		break;
+
+	case 0x11:	/* SYS_TIME */
+		result = time(NULL);
+		break;
+
+	case 0x13:	/* SYS_ERRNO */
+		result = semihosting_errno;
+		break;
+
+	case 0x15:	/* SYS_GET_CMDLINE */
+		retval = target_read_memory(target, r1, 4, 2, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			uint32_t a = target_buffer_get_u32(target, params+0);
+			uint32_t l = target_buffer_get_u32(target, params+4);
+			char *arg = "foobar";
+			uint32_t s = strlen(arg) + 1;
+			if (l < s)
+				result = -1;
+			else {
+				retval = target_write_buffer(target, a, s, (void*)arg);
+				if (retval != ERROR_OK)
+					return retval;
+				result = 0;
+			}
+		}
+		break;
+
+	case 0x16:	/* SYS_HEAPINFO */
+		retval = target_read_memory(target, r1, 4, 1, params);
+		if (retval != ERROR_OK)
+			return retval;
+		else {
+			uint32_t a = target_buffer_get_u32(target, params+0);
+			/* tell the remote we have no idea */
+			memset(params, 0, 4*4);
+			retval = target_write_memory(target, a, 4, 4, params);
+			if (retval != ERROR_OK)
+				return retval;
+			result = 0;
+		}
+		break;
+
+	case 0x18:	/* angel_SWIreason_ReportException */
+		switch (r1) {
+		case 0x20026:	/* ADP_Stopped_ApplicationExit */
+			fprintf(stderr, "semihosting: *** application exited ***\n");
+			break;
+		case 0x20000:	/* ADP_Stopped_BranchThroughZero */
+		case 0x20001:	/* ADP_Stopped_UndefinedInstr */
+		case 0x20002:	/* ADP_Stopped_SoftwareInterrupt */
+		case 0x20003:	/* ADP_Stopped_PrefetchAbort */
+		case 0x20004:	/* ADP_Stopped_DataAbort */
+		case 0x20005:	/* ADP_Stopped_AddressException */
+		case 0x20006:	/* ADP_Stopped_IRQ */
+		case 0x20007:	/* ADP_Stopped_FIQ */
+		case 0x20020:	/* ADP_Stopped_BreakPoint */
+		case 0x20021:	/* ADP_Stopped_WatchPoint */
+		case 0x20022:	/* ADP_Stopped_StepComplete */
+		case 0x20023:	/* ADP_Stopped_RunTimeErrorUnknown */
+		case 0x20024:	/* ADP_Stopped_InternalError */
+		case 0x20025:	/* ADP_Stopped_UserInterruption */
+		case 0x20027:	/* ADP_Stopped_StackOverflow */
+		case 0x20028:	/* ADP_Stopped_DivisionByZero */
+		case 0x20029:	/* ADP_Stopped_OSSpecific */
+		default:
+			fprintf(stderr, "semihosting: exception %#x\n", r1);
+		}
+		return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+
+	case 0x0d:	/* SYS_TMPNAM */
+	case 0x10:	/* SYS_CLOCK */
+	case 0x12:	/* SYS_SYSTEM */
+	case 0x17:	/* angel_SWIreason_EnterSVC */
+	case 0x30:	/* SYS_ELAPSED */
+	case 0x31:	/* SYS_TICKFREQ */
+	default:
+		fprintf(stderr, "semihosting: unsupported call %#x\n", r0);
+		result = -1;
+		semihosting_errno = ENOTSUP;
+	}
+
+	/* resume execution to the original mode */
+	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, result);
+	armv4_5->core_cache->reg_list[0].dirty = 1;
+	buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, lr);
+	armv4_5->core_cache->reg_list[15].dirty = 1;
+	buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
+	armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
+	armv4_5->core_mode = spsr & 0x1f;
+	if (spsr & 0x20)
+		armv4_5->core_state = ARMV4_5_STATE_THUMB;
+	return target_resume(target, 1, 0, 0, 0);
+}
+
+/**
+ * Checks for and processes an ARM semihosting request.  This is meant
+ * to be called when the target is stopped due to a debug mode entry.
+ * If the value 0 is returned then there was nothing to process. A non-zero
+ * return value signifies that a request was processed and the target resumed,
+ * or an error was encountered, in which case the caller must return
+ * immediately.
+ *
+ * @param target Pointer to the ARM target to process
+ * @param retval Pointer to a location where the return code will be stored
+ * @return non-zero value if a request was processed or an error encountered
+ */
+int arm_semihosting(struct target *target, int *retval)
+{
+	struct arm *armv4_5 = target_to_armv4_5(target);
+	uint32_t lr, spsr;
+
+	if (!semihosting_active ||
+	    armv4_5->core_mode != ARMV4_5_MODE_SVC ||
+	    buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != 0x08)
+		return 0;
+
+	lr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, ARMV4_5_MODE_SVC, 14).value, 0, 32);
+	spsr = buf_get_u32(armv4_5->spsr->value, 0, 32);
+
+	/* check instruction that triggered this trap */
+	if (spsr & (1 << 5)) {
+		/* was in Thumb mode */
+		uint8_t insn_buf[2];
+		uint16_t insn;
+		*retval = target_read_memory(target, lr-2, 2, 1, insn_buf);
+		if (*retval != ERROR_OK)
+			return 1;
+		insn = target_buffer_get_u16(target, insn_buf);
+		if (insn != 0xDFAB)
+			return 0;
+	} else {
+		/* was in ARM mode */
+		uint8_t insn_buf[4];
+		uint32_t insn;
+		*retval = target_read_memory(target, lr-4, 4, 1, insn_buf);
+		if (*retval != ERROR_OK)
+			return 1;
+		insn = target_buffer_get_u32(target, insn_buf);
+		if (insn != 0xEF123456)
+			return 0;
+	}
+
+	*retval = do_semihosting(target);
+	return 1;
+}
diff --git a/src/target/arm_semihosting.h b/src/target/arm_semihosting.h
new file mode 100644
index 0000000..6b9ac56
--- /dev/null
+++ b/src/target/arm_semihosting.h
@@ -0,0 +1,28 @@
+/***************************************************************************
+ *   Copyright (C) 2009 by Marvell Technology Group Ltd.                   *
+ *   Written by Nicolas Pitre <ni...@ma...>                           *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+#ifndef ARM_SEMIHOSTING_H
+#define ARM_SEMIHOSTING_H
+
+extern int semihosting_active;
+
+int arm_semihosting(struct target *target, int *retval);
+
+#endif

commit f62c035c5277871193fa9904f430cf57221c0b89
Author: David Brownell <dbr...@us...>
Date:   Thu Dec 3 18:31:38 2009 -0800

    doxygen: remove some warnings
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/helper/command.h b/src/helper/command.h
index 5504608..aaba9b0 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -340,7 +340,7 @@ struct command_context* copy_command_context(struct command_context* cmd_ctx);
 /**
  * Frees the resources associated with a command context.  The commands
  * are not removed, so unregister_all_commands() must be called first.
- * @param cmd_ctx The command_context that will be destroyed.
+ * @param context The command_context that will be destroyed.
  */
 void command_done(struct command_context *context);
 
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index b02baa3..c5d797e 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -276,6 +276,7 @@ fail:
  * Writes all modified core registers for all processor modes.  In normal
  * operation this is called on exit from halting debug state.
  *
+ * @param dpm: represents the processor
  * @param bpwp: true ensures breakpoints and watchpoints are set,
  *	false ensures they are cleared
  */

-----------------------------------------------------------------------

Summary of changes:
 NEWS                                          |    1 +
 doc/openocd.texi                              |   11 +
 src/helper/command.h                          |    2 +-
 src/target/Makefile.am                        |    2 +
 src/target/arm7_9_common.c                    |   44 +++
 src/target/arm_dpm.c                          |    1 +
 src/target/arm_semihosting.c                  |  442 +++++++++++++++++++++++++
 src/target/{etm_dummy.h => arm_semihosting.h} |   15 +-
 8 files changed, 510 insertions(+), 8 deletions(-)
 create mode 100644 src/target/arm_semihosting.c
 copy src/target/{etm_dummy.h => arm_semihosting.h} (82%)


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- Log -----------------------------------------------------------------
commit cf2cb0fc84d262069282a7363944663c8d2505d3
Author: Dean Glazeski <dn...@gm...>
Date:   Mon Nov 16 13:40:46 2009 -0600

    Make ARM NAND I/O operations aware of last op
    
    Updates the ARM NAND I/O code to look at and update the op
    field of arm_nand_data to reflect the last operation performed.
    It uses this field to copy the correct code to the target in the
    case where the struct is used for reads and writes.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c
index fdf2109..1b43b5f 100644
--- a/src/flash/arm_nandio.c
+++ b/src/flash/arm_nandio.c
@@ -40,7 +40,8 @@
  * @param area Pointer to a pointer to a working area to copy code to
  * @return Success or failure of the operation
  */
-int arm_code_to_working_area(struct target *target, const uint32_t *code, unsigned code_size,
+int arm_code_to_working_area(struct target *target,
+		const uint32_t *code, unsigned code_size,
 		unsigned additional, struct working_area **area)
 {
 	uint8_t code_buf[code_size];
@@ -48,6 +49,11 @@ int arm_code_to_working_area(struct target *target, const uint32_t *code, unsign
 	int retval;
 	unsigned size = code_size + additional;
 
+	/* REVISIT this assumes size doesn't ever change.
+	 * That's usually correct; but there are boards with
+	 * both large and small page chips, where it won't be...
+	 */
+
 	/* make sure we have a working area */
 	if (NULL == *area) {
 		retval = target_alloc_working_area(target, size, area);
@@ -109,7 +115,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 		0xe1200070,	/* e: bkpt  #0           */
 	};
 
-	if (!nand->copy_area) {
+	if (nand->op != ARM_NAND_WRITE || !nand->copy_area) {
 		retval = arm_code_to_working_area(target, code, sizeof(code),
 				nand->chunk_size, &nand->copy_area);
 		if (retval != ERROR_OK) {
@@ -117,6 +123,8 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
 		}
 	}
 
+	nand->op = ARM_NAND_WRITE;
+
 	/* copy data to work area */
 	target_buf = nand->copy_area->address + sizeof(code);
 	retval = target_bulk_write_memory(target, target_buf, size / 4, data);
@@ -192,7 +200,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 	};
 
 	/* create the copy area if not yet available */
-	if (!nand->copy_area) {
+	if (nand->op != ARM_NAND_READ || !nand->copy_area) {
 		retval = arm_code_to_working_area(target, code, sizeof(code),
 				nand->chunk_size, &nand->copy_area);
 		if (retval != ERROR_OK) {
@@ -200,6 +208,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 		}
 	}
 
+	nand->op = ARM_NAND_READ;
 	target_buf = nand->copy_area->address + sizeof(code);
 
 	/* set up algorithm and parameters */
@@ -223,7 +232,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
 	retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
 			nand->copy_area->address, exit, 1000, &algo);
 	if (retval != ERROR_OK)
-		LOG_ERROR("error executing hosted NAND write");
+		LOG_ERROR("error executing hosted NAND read");
 
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);

commit 66985bb30619c412984a2cfa1c0b3c4a324dbe78
Author: Dean Glazeski <dn...@gm...>
Date:   Mon Nov 16 13:34:24 2009 -0600

    ARM NAND I/O interface update
    
    Modify the arm_nand_data struct to better support both read and
    write operations while using the same struct.  An additional
    field was added, and initialized, to record the last operation
    so that the correct code can be loaded to the working area.
    
    [dbr...@us...: merge init patch, tweak GPL note]
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/arm_nandio.h b/src/flash/arm_nandio.h
index 27b3ad3..d3504f4 100644
--- a/src/flash/arm_nandio.h
+++ b/src/flash/arm_nandio.h
@@ -1,3 +1,21 @@
+/*
+ * Copyright (C) 2009 by David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
 #ifndef __ARM_NANDIO_H
 #define __ARM_NANDIO_H
 
@@ -5,21 +23,33 @@
 #include <helper/binarybuffer.h>
 
 /**
+ * Available operational states the arm_nand_data struct can be in.
+ */
+enum arm_nand_op {
+	ARM_NAND_NONE, /**< No operation performed. */
+	ARM_NAND_READ, /**< Read operation performed. */
+	ARM_NAND_WRITE, /**< Write operation performed. */
+};
+
+/**
  * The arm_nand_data struct is used for defining NAND I/O operations on an ARM
  * core.
  */
 struct arm_nand_data {
-	/** target is proxy for some ARM core */
-	struct target		*target;
+	/** Target is proxy for some ARM core. */
+	struct target *target;
 
-	/** copy_area holds write-to-NAND loop and data to write */
+	/** The copy area holds code loop and data for I/O operations. */
 	struct working_area	*copy_area;
 
-	/** chunk_size == page or ECC unit */
-	unsigned		chunk_size;
+	/** The chunk size is the page size or ECC chunk. */
+	unsigned chunk_size;
+
+	/** Where data is read from or written to. */
+	uint32_t data;
 
-	/** data == where to write the data */
-	uint32_t		data;
+	/** Last operation executed using this struct. */
+	enum arm_nand_op op;
 
 	/* currently implicit:  data width == 8 bits (not 16) */
 };
diff --git a/src/flash/nand/davinci.c b/src/flash/nand/davinci.c
index 40be36d..6677073 100644
--- a/src/flash/nand/davinci.c
+++ b/src/flash/nand/davinci.c
@@ -710,6 +710,7 @@ NAND_DEVICE_COMMAND_HANDLER(davinci_nand_device_command)
 
 	info->io.target = target;
 	info->io.data = info->data;
+	info->io.op = ARM_NAND_NONE;
 
 	/* NOTE:  for now we don't do any error correction on read.
 	 * Nothing else in OpenOCD currently corrects read errors,
diff --git a/src/flash/nand/orion.c b/src/flash/nand/orion.c
index 436151f..b124dee 100644
--- a/src/flash/nand/orion.c
+++ b/src/flash/nand/orion.c
@@ -155,6 +155,7 @@ NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
 
 	hw->io.target = hw->target;
 	hw->io.data = hw->data;
+	hw->io.op = ARM_NAND_NONE;
 
 	return ERROR_OK;
 }

commit 9a51b8b0e3d0b629915a8248e2c112a01ffc93dc
Author: Dean Glazeski <dn...@gm...>
Date:   Fri Nov 20 00:19:39 2009 -0600

    NAND page command refactoring.
    
    Created a new function that handles sending a command and the address
    information for pages to a NAND device.
    
    [dbr...@us...: tweaked line lengths, name 'oob_only']
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nand.c b/src/flash/nand.c
index 5bcbea4..2f0f503 100644
--- a/src/flash/nand.c
+++ b/src/flash/nand.c
@@ -863,20 +863,19 @@ static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data
 		return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
 }
 
-int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+int nand_page_command(struct nand_device *nand, uint32_t page,
+		uint8_t cmd, bool oob_only)
 {
-	uint32_t i;
-
 	if (!nand->device)
 		return ERROR_NAND_DEVICE_NOT_PROBED;
 
-	if (nand->page_size <= 512)
-	{
+	if (oob_only && NAND_CMD_READ0 == cmd && nand->page_size <= 512)
+		cmd = NAND_CMD_READOOB;
+
+	nand->controller->command(nand, cmd);
+
+	if (nand->page_size <= 512) {
 		/* small page device */
-		if (data)
-			nand->controller->command(nand, NAND_CMD_READ0);
-		else
-			nand->controller->command(nand, NAND_CMD_READOOB);
 
 		/* column (always 0, we start at the beginning of a page/OOB area) */
 		nand->controller->address(nand, 0x0);
@@ -892,20 +891,17 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, u
 		/* 5th cycle only on devices with more than 8 GiB */
 		if (nand->address_cycles >= 5)
 			nand->controller->address(nand, (page >> 24) & 0xff);
-	}
-	else
-	{
+	} else {
 		/* large page device */
-		nand->controller->command(nand, NAND_CMD_READ0);
 
 		/* column (0 when we start at the beginning of a page,
 		 * or 2048 for the beginning of OOB area)
 		 */
 		nand->controller->address(nand, 0x0);
-		if (data)
-			nand->controller->address(nand, 0x0);
-		else
+		if (oob_only)
 			nand->controller->address(nand, 0x8);
+		else
+			nand->controller->address(nand, 0x0);
 
 		/* row */
 		nand->controller->address(nand, page & 0xff);
@@ -915,8 +911,9 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, u
 		if (nand->address_cycles >= 5)
 			nand->controller->address(nand, (page >> 16) & 0xff);
 
-		/* large page devices need a start command */
-		nand->controller->command(nand, NAND_CMD_READSTART);
+		/* large page devices need a start command if reading */
+		if (NAND_CMD_READ0 == cmd)
+			nand->controller->command(nand, NAND_CMD_READSTART);
 	}
 
 	if (nand->controller->nand_ready) {
@@ -926,6 +923,20 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, u
 		alive_sleep(1);
 	}
 
+	return ERROR_OK;
+}
+
+int nand_read_page_raw(struct nand_device *nand, uint32_t page,
+		uint8_t *data, uint32_t data_size,
+		uint8_t *oob, uint32_t oob_size)
+{
+	uint32_t i;
+	int retval;
+
+	retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
+	if (ERROR_OK != retval)
+		return retval;
+
 	if (data)
 	{
 		if (nand->controller->read_block_data != NULL)
@@ -983,47 +994,9 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data,
 	int retval;
 	uint8_t status;
 
-	if (!nand->device)
-		return ERROR_NAND_DEVICE_NOT_PROBED;
-
-	nand->controller->command(nand, NAND_CMD_SEQIN);
-
-	if (nand->page_size <= 512)
-	{
-		/* column (always 0, we start at the beginning of a page/OOB area) */
-		nand->controller->address(nand, 0x0);
-
-		/* row */
-		nand->controller->address(nand, page & 0xff);
-		nand->controller->address(nand, (page >> 8) & 0xff);
-
-		/* 4th cycle only on devices with more than 32 MiB */
-		if (nand->address_cycles >= 4)
-			nand->controller->address(nand, (page >> 16) & 0xff);
-
-		/* 5th cycle only on devices with more than 8 GiB */
-		if (nand->address_cycles >= 5)
-			nand->controller->address(nand, (page >> 24) & 0xff);
-	}
-	else
-	{
-		/* column (0 when we start at the beginning of a page,
-		 * or 2048 for the beginning of OOB area)
-		 */
-		nand->controller->address(nand, 0x0);
-		if (data)
-			nand->controller->address(nand, 0x0);
-		else
-			nand->controller->address(nand, 0x8);
-
-		/* row */
-		nand->controller->address(nand, page & 0xff);
-		nand->controller->address(nand, (page >> 8) & 0xff);
-
-		/* 5th cycle only on devices with more than 128 MiB */
-		if (nand->address_cycles >= 5)
-			nand->controller->address(nand, (page >> 16) & 0xff);
-	}
+	retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
+	if (ERROR_OK != retval)
+		return retval;
 
 	if (data)
 	{
diff --git a/src/flash/nand.h b/src/flash/nand.h
index d73aee1..230cf50 100644
--- a/src/flash/nand.h
+++ b/src/flash/nand.h
@@ -270,6 +270,9 @@ struct nand_device *get_nand_device_by_name(const char *name);
 
 struct nand_device *get_nand_device_by_num(int num);
 
+int nand_page_command(struct nand_device *nand, uint32_t page,
+		uint8_t cmd, bool oob_only);
+
 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
 		uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
 int nand_write_page_raw(struct nand_device *nand, uint32_t page,

-----------------------------------------------------------------------

Summary of changes:
 src/flash/arm_nandio.c   |   17 +++++++--
 src/flash/arm_nandio.h   |   44 +++++++++++++++++++----
 src/flash/nand.c         |   91 ++++++++++++++++------------------------------
 src/flash/nand.h         |    3 ++
 src/flash/nand/davinci.c |    1 +
 src/flash/nand/orion.c   |    1 +
 6 files changed, 87 insertions(+), 70 deletions(-)


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- Log -----------------------------------------------------------------
commit 7e2dffbbff2534ca5afa52aa3d811b3599d2ca77
Author: David Brownell <dbr...@us...>
Date:   Thu Dec 3 16:18:24 2009 -0800

    ARMv7-A: tweak arch_state()
    
    Punt to the armv4_5_arch_state() for all the common stuff, to
    shrink code and so we will get any improvements it provides.
    
    Don't hide watchpoint status if we happen to be in "abort" mode.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 5d3976f..e889a8a 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -98,22 +98,16 @@ int armv7a_arch_state(struct target *target)
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			 "MMU: %s, D-Cache: %s, I-Cache: %s",
-		 armv4_5_state_strings[armv4_5->core_state],
-		 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
-				target->debug_reason)->name,
-		 arm_mode_name(armv4_5->core_mode),
-		 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-		 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	armv4_5_arch_state(target);
+
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 		 state[armv7a->armv4_5_mmu.mmu_enabled],
 		 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 		 state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 
 	if (armv4_5->core_mode == ARMV4_5_MODE_ABT)
 		armv7a_show_fault_registers(target);
-	else if (target->debug_reason == DBG_REASON_WATCHPOINT)
+	if (target->debug_reason == DBG_REASON_WATCHPOINT)
 		LOG_USER("Watchpoint triggered at PC %#08x",
 				(unsigned) armv7a->dpm.wp_pc);
 

commit ea7a49cb9b46ccc27daf6c9b306290c7e905a9fc
Author: David Brownell <dbr...@us...>
Date:   Thu Dec 3 16:08:04 2009 -0800

    ARM DPM: share debug reason logic
    
    No point in both ARM11 and Cortex-A8 having private copies
    of the logic sorting out e.g. DBG_REASON_WATCHPOINT.
    
    Add and use a shared routine for this ... there's actually
    a bunch more debug entry logic that could be shared, this
    is just a start on that.  Note that this routine fixes a
    bug observed in the ARM11 code, where some abort mode quirks
    were displayed as being an unknown debug reason; and also
    silences needless ARM11 chatter.
    
    Likewise with private copies of DSCR ... add one to the DPM
    struct.  Save it as part of setting DBG_REASON_* so later
    patches can switch over to using that copy.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index b01e33b..20ad22d 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -83,8 +83,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 			  */
 
 			arm11->arm.target->state = TARGET_HALTED;
-			arm11->arm.target->debug_reason =
-					arm11_get_DSCR_debug_reason(arm11->dscr);
+			arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
 		}
 		else
 		{
@@ -108,8 +107,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 	int retval;
 
 	arm11->arm.target->state = TARGET_HALTED;
-	arm11->arm.target->debug_reason =
-			arm11_get_DSCR_debug_reason(arm11->dscr);
+	arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
 
 	/* REVISIT entire cache should already be invalid !!! */
 	register_cache_invalidate(arm11->arm.core_cache);
@@ -551,20 +549,12 @@ static int arm11_resume(struct target *target, int current,
 		i++;
 	}
 
+	target->debug_reason = DBG_REASON_NOTHALTED;
 	if (!debug_execution)
-	{
-		target->state			= TARGET_RUNNING;
-		target->debug_reason	= DBG_REASON_NOTHALTED;
-
-		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
-	}
+		target->state = TARGET_RUNNING;
 	else
-	{
-		target->state			= TARGET_DEBUG_RUNNING;
-		target->debug_reason	= DBG_REASON_NOTHALTED;
-
-		CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
-	}
+		target->state = TARGET_DEBUG_RUNNING;
+	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
 
 	return ERROR_OK;
 }
@@ -728,7 +718,7 @@ static int arm11_step(struct target *target, int current,
 
 	}
 
-	target->debug_reason	= DBG_REASON_SINGLESTEP;
+	target->debug_reason = DBG_REASON_SINGLESTEP;
 
 	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 5f78db5..f3f0644 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -94,18 +94,6 @@ enum arm11_instructions
 	ARM11_BYPASS    = 0x1F,
 };
 
-enum arm11_dscr
-{
-
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK					= 0x0F << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT					= 0x00 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT				= 0x01 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT				= 0x02 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION		= 0x03 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ					= 0x04 << 2,
-	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH			= 0x05 << 2,
-};
-
 enum arm11_sc7
 {
 	ARM11_SC7_NULL				= 0,
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 3df1c65..e5d3f80 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -288,50 +288,6 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
 	return ERROR_OK;
 }
 
-
-
-/** Get the debug reason from Debug Status and Control Register (DSCR)
- *
- * \param dscr		DSCR value to analyze
- * \return			Debug reason
- *
- */
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr)
-{
-	switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
-	{
-	case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
-		LOG_INFO("Debug entry: JTAG HALT");
-		return DBG_REASON_DBGRQ;
-
-	case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
-		LOG_INFO("Debug entry: breakpoint");
-		return DBG_REASON_BREAKPOINT;
-
-	case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
-		LOG_INFO("Debug entry: watchpoint");
-		return DBG_REASON_WATCHPOINT;
-
-	case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
-		LOG_INFO("Debug entry: BKPT instruction");
-		return DBG_REASON_BREAKPOINT;
-
-	case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
-		LOG_INFO("Debug entry: EDBGRQ signal");
-		return DBG_REASON_DBGRQ;
-
-	case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
-		LOG_INFO("Debug entry: VCR vector catch");
-		return DBG_REASON_BREAKPOINT;
-
-	default:
-		LOG_INFO("Debug entry: unknown");
-		return DBG_REASON_DBGRQ;
-	}
-};
-
-
-
 /** Prepare the stage for ITR/DTR operations
  * from the arm11_run_instr... group of functions.
  *
diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h
index a6b9bbd..2c586cc 100644
--- a/src/target/arm11_dbgtap.h
+++ b/src/target/arm11_dbgtap.h
@@ -14,8 +14,6 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
 int arm11_read_DSCR(struct arm11_common *arm11);
 int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr);
 
-enum target_debug_reason arm11_get_DSCR_debug_reason(uint32_t dscr);
-
 int arm11_run_instr_data_prepare(struct arm11_common *arm11);
 int arm11_run_instr_data_finish(struct arm11_common *arm11);
 int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode);
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index ca3930f..b02baa3 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -756,6 +756,42 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
 /*----------------------------------------------------------------------*/
 
 /*
+ * Other debug and support utilities
+ */
+
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
+{
+	struct target *target = dpm->arm->target;
+
+	dpm->dscr = dscr;
+
+	/* Examine debug reason */
+	switch (DSCR_ENTRY(dscr)) {
+	case 6:		/* Data abort (v6 only) */
+	case 7:		/* Prefetch abort (v6 only) */
+		/* FALL THROUGH -- assume a v6 core in abort mode */
+	case 0:		/* HALT request from debugger */
+	case 4:		/* EDBGRQ */
+		target->debug_reason = DBG_REASON_DBGRQ;
+		break;
+	case 1:		/* HW breakpoint */
+	case 3:		/* SW BKPT */
+	case 5:		/* vector catch */
+		target->debug_reason = DBG_REASON_BREAKPOINT;
+		break;
+	case 2:		/* asynch watchpoint */
+	case 10:	/* precise watchpoint */
+		target->debug_reason = DBG_REASON_WATCHPOINT;
+		break;
+	default:
+		target->debug_reason = DBG_REASON_UNDEFINED;
+		break;
+	}
+}
+
+/*----------------------------------------------------------------------*/
+
+/*
  * Setup and management support.
  */
 
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 11213a3..135e3db 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -125,6 +125,9 @@ struct arm_dpm {
 	/** Address of the instruction which triggered a watchpoint. */
 	uint32_t wp_pc;
 
+	/** Recent value of DSCR. */
+	uint32_t dscr;
+
 	// FIXME -- read/write DCSR methods and symbols
 };
 
@@ -151,4 +154,6 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 
 #define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
 
+void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
+
 #endif /* __ARM_DPM_H */
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 14cbb9d..eb42a5d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -782,7 +782,7 @@ static int cortex_a8_resume(struct target *target, int current,
 static int cortex_a8_debug_entry(struct target *target)
 {
 	int i;
-	uint32_t regfile[16], wfar, cpsr, dscr;
+	uint32_t regfile[16], cpsr, dscr;
 	int retval = ERROR_OK;
 	struct working_area *regfile_working_area = NULL;
 	struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target);
@@ -793,6 +793,7 @@ static int cortex_a8_debug_entry(struct target *target)
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+	/* REVISIT surely we should not re-read DSCR !! */
 	mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 
@@ -807,30 +808,16 @@ static int cortex_a8_debug_entry(struct target *target)
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
 
 	/* Examine debug reason */
-	switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
-	{
-		case 0:		/* DRCR[0] write */
-		case 4:		/* EDBGRQ */
-			target->debug_reason = DBG_REASON_DBGRQ;
-			break;
-		case 1:		/* HW breakpoint */
-		case 3:		/* SW BKPT */
-		case 5:		/* vector catch */
-			target->debug_reason = DBG_REASON_BREAKPOINT;
-			break;
-		case 2:		/* asynch watchpoint */
-		case 10:	/* precise watchpoint */
-			target->debug_reason = DBG_REASON_WATCHPOINT;
-
-			/* save address of faulting instruction */
-			retval = mem_ap_read_atomic_u32(swjdp,
-					armv7a->debug_base + CPUDBG_WFAR,
-					&wfar);
-			arm_dpm_report_wfar(&armv7a->dpm, wfar);
-			break;
-		default:
-			target->debug_reason = DBG_REASON_UNDEFINED;
-			break;
+	arm_dpm_report_dscr(&armv7a->dpm, cortex_a8->cpudbg_dscr);
+
+	/* save address of instruction that triggered the watchpoint? */
+	if (target->debug_reason == DBG_REASON_WATCHPOINT) {
+		uint32_t wfar;
+
+		retval = mem_ap_read_atomic_u32(swjdp,
+				armv7a->debug_base + CPUDBG_WFAR,
+				&wfar);
+		arm_dpm_report_wfar(&armv7a->dpm, wfar);
 	}
 
 	/* REVISIT fast_reg_read is never set ... */

commit 6eee0729d79eab496d1d4368a2bae7e4e2d19876
Author: David Brownell <dbr...@us...>
Date:   Thu Dec 3 16:08:04 2009 -0800

    ARM11: use shared DSCR bit names
    
    For the bits now defined in "arm_dpm.h", switch to the
    shared DSCR_* symbol and remove the ARM11_DSCR_* version.
    
    Define DSCR_INT_DIS and use it instead of the ARM11_DSCR_*
    sibling symbol.  (Note:  for both ARM11 and Cortex-A8, this
    should arguably be enabled by default when single stepping.)
    
    Remove some other unused declarations in "arm11.h".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 124868e..b01e33b 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -40,6 +40,10 @@
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
+
+/* FIXME none of these flags should be global to all ARM11 cores!
+ * Most of them shouldn't exist at all, once the code works...
+ */
 static bool arm11_config_memwrite_burst = true;
 static bool arm11_config_memwrite_error_fatal = true;
 static uint32_t arm11_vcr = 0;
@@ -59,18 +63,18 @@ static int arm11_check_init(struct arm11_common *arm11)
 	CHECK_RETVAL(arm11_read_DSCR(arm11));
 	LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 
-	if (!(arm11->dscr & ARM11_DSCR_MODE_SELECT))
+	if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
 	{
 		LOG_DEBUG("Bringing target into debug mode");
 
-		arm11->dscr |= ARM11_DSCR_MODE_SELECT;		/* Halt debug-mode */
+		arm11->dscr |= DSCR_HALT_DBG_MODE;
 		arm11_write_DSCR(arm11, arm11->dscr);
 
 		/* add further reset initialization here */
 
 		arm11->simulate_reset_on_next_halt = true;
 
-		if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+		if (arm11->dscr & DSCR_CORE_HALTED)
 		{
 			/** \todo TODO: this needs further scrutiny because
 			  * arm11_debug_entry() never gets called.  (WHY NOT?)
@@ -113,7 +117,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 	/* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
 
 	/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
-	arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL);
+	arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
 	if (arm11->is_wdtr_saved)
 	{
 		arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
@@ -131,15 +135,13 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 
 	}
 
-	/* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
+	/* DSCR: set the Execute ARM instruction enable bit.
 	 *
 	 * ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
-	 * but not to issue ITRs. ARM1136 seems to require this to issue
-	 * ITR's as well...
+	 * but not to issue ITRs(?).  The ARMv7 arch spec says it's required
+	 * for executing instructions via ITR.
 	 */
-
-	arm11_write_DSCR(arm11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
-				| arm11->dscr);
+	arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
 
 
 	/* From the spec:
@@ -188,7 +190,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 		return retval;
 
 	/* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
-	arm11->is_rdtr_saved = !!(arm11->dscr & ARM11_DSCR_RDTR_FULL);
+	arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
 	if (arm11->is_rdtr_saved)
 	{
 		/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
@@ -248,7 +250,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
 	{
 		CHECK_RETVAL(arm11_read_DSCR(arm11));
 
-		if (arm11->dscr & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
+		if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
 		{
 			/*
 			The wDTR/rDTR two registers that are used to send/receive data to/from
@@ -324,7 +326,7 @@ static int arm11_poll(struct target *target)
 
 	CHECK_RETVAL(arm11_check_init(arm11));
 
-	if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+	if (arm11->dscr & DSCR_CORE_HALTED)
 	{
 		if (target->state != TARGET_HALTED)
 		{
@@ -401,7 +403,7 @@ static int arm11_halt(struct target *target)
 	{
 		CHECK_RETVAL(arm11_read_DSCR(arm11));
 
-		if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+		if (arm11->dscr & DSCR_CORE_HALTED)
 			break;
 
 
@@ -529,7 +531,7 @@ static int arm11_resume(struct target *target, int current,
 
 		LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 
-		if (arm11->dscr & ARM11_DSCR_CORE_RESTARTED)
+		if (arm11->dscr & DSCR_CORE_RESTARTED)
 			break;
 
 
@@ -674,9 +676,9 @@ static int arm11_step(struct target *target, int current,
 
 		if (arm11_config_step_irq_enable)
 			/* this disable should be redundant ... */
-			arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
+			arm11->dscr &= ~DSCR_INT_DIS;
 		else
-			arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE;
+			arm11->dscr |= DSCR_INT_DIS;
 
 
 		CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
@@ -690,8 +692,8 @@ static int arm11_step(struct target *target, int current,
 
 		while (1)
 		{
-			const uint32_t mask = ARM11_DSCR_CORE_RESTARTED
-					| ARM11_DSCR_CORE_HALTED;
+			const uint32_t mask = DSCR_CORE_RESTARTED
+					| DSCR_CORE_HALTED;
 
 			CHECK_RETVAL(arm11_read_DSCR(arm11));
 			LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
@@ -722,7 +724,7 @@ static int arm11_step(struct target *target, int current,
 		CHECK_RETVAL(arm11_debug_entry(arm11));
 
 		/* restore default state */
-		arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
+		arm11->dscr &= ~DSCR_INT_DIS;
 
 	}
 
diff --git a/src/target/arm11.h b/src/target/arm11.h
index b118e1c..5f78db5 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -38,6 +38,7 @@
 		}				\
 	} while (0)
 
+/* bits from ARMv7 DIDR */
 enum arm11_debug_version
 {
 	ARM11_DEBUG_V6			= 0x01,
@@ -95,8 +96,6 @@ enum arm11_instructions
 
 enum arm11_dscr
 {
-	ARM11_DSCR_CORE_HALTED									= 1 << 0,
-	ARM11_DSCR_CORE_RESTARTED								= 1 << 1,
 
 	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK					= 0x0F << 2,
 	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT					= 0x00 << 2,
@@ -105,20 +104,6 @@ enum arm11_dscr
 	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION		= 0x03 << 2,
 	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ					= 0x04 << 2,
 	ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH			= 0x05 << 2,
-
-	ARM11_DSCR_STICKY_PRECISE_DATA_ABORT					= 1 << 6,
-	ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT					= 1 << 7,
-	ARM11_DSCR_INTERRUPTS_DISABLE							= 1 << 11,
-	ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE				= 1 << 13,
-	ARM11_DSCR_MODE_SELECT									= 1 << 14,
-	ARM11_DSCR_WDTR_FULL									= 1 << 29,
-	ARM11_DSCR_RDTR_FULL									= 1 << 30,
-};
-
-enum arm11_cpsr
-{
-	ARM11_CPSR_T				= 1 << 5,
-	ARM11_CPSR_J				= 1 << 24,
 };
 
 enum arm11_sc7
@@ -132,10 +117,4 @@ enum arm11_sc7
 	ARM11_SC7_WCR0				= 112,
 };
 
-struct arm11_reg_state
-{
-	uint32_t				def_index;
-	struct target *			target;
-};
-
 #endif /* ARM11_H */
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 1f32e8b..11213a3 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -141,6 +141,7 @@ void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
  */
 #define DSCR_CORE_HALTED	(1 << 0)
 #define DSCR_CORE_RESTARTED	(1 << 1)
+#define DSCR_INT_DIS		(1 << 11)
 #define DSCR_ITR_EN		(1 << 13)
 #define DSCR_HALT_DBG_MODE	(1 << 14)
 #define DSCR_MON_DBG_MODE	(1 << 15)

commit eb6c880ddcb06cb011ebd4557d9057d04ab9b4fb
Author: David Brownell <dbr...@us...>
Date:   Thu Dec 3 16:08:04 2009 -0800

    ARM DPM: make DSCR bit defs sharable
    
    Move the symbols for these bits from "armv7a.h" to "arm_dpm.h",
    where they can be seen and used not just by Cortex-A but also
    by the ARM11 (armv6) code.
    
    Change them from bit numbers to bit masks ... this matches the
    usage in ARM11 code, and also makes it easier to read.
    
    Rename DSCR_EXT_INT_EN as DSCR_ITR_EN to match the docs; it's
    enabling ITR functionality, not external interrupts, so this
    changes the name to be less misleading.  (There *IS* a bit
    affecting interrupts, and this isn't it.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index c284144..1f32e8b 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -136,4 +136,18 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 
 void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
 
+/* Subset of DSCR bits; see ARMv7a arch spec section C10.3.1.
+ * Not all v7 bits are valid in v6.
+ */
+#define DSCR_CORE_HALTED	(1 << 0)
+#define DSCR_CORE_RESTARTED	(1 << 1)
+#define DSCR_ITR_EN		(1 << 13)
+#define DSCR_HALT_DBG_MODE	(1 << 14)
+#define DSCR_MON_DBG_MODE	(1 << 15)
+#define DSCR_INSTR_COMP		(1 << 24)
+#define DSCR_DTR_TX_FULL	(1 << 29)
+#define DSCR_DTR_RX_FULL	(1 << 30)
+
+#define DSCR_ENTRY(dscr) (((dscr) >> 2) & 0xf)
+
 #endif /* __ARM_DPM_H */
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 0d5da86..f089c5c 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -114,16 +114,6 @@ target_to_armv7a(struct target *target)
 /* See ARMv7a arch spec section C10.8 */
 #define CPUDBG_AUTHSTATUS	0xFB8
 
-/* DSCR bit numbers (See ARMv7a arch spec section 12.4.5) */
-#define DSCR_CORE_HALTED	0
-#define DSCR_CORE_RESTARTED	1
-#define DSCR_EXT_INT_EN		13
-#define DSCR_HALT_DBG_MODE	14
-#define DSCR_MON_DBG_MODE	15
-#define DSCR_INSTR_COMP		24
-#define DSCR_DTR_TX_FULL	29
-#define DSCR_DTR_RX_FULL	30
-
 struct armv7a_algorithm
 {
 	int common_magic;
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 9ca072e..14cbb9d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -91,8 +91,8 @@ static int cortex_a8_init_debug_access(struct target *target)
 
 /* To reduce needless round-trips, pass in a pointer to the current
  * DSCR value.  Initialize it to zero if you just need to know the
- * value on return from this function; or (1 << DSCR_INSTR_COMP) if
- * you happen to know that no instruction is pending.
+ * value on return from this function; or DSCR_INSTR_COMP if you
+ * happen to know that no instruction is pending.
  */
 static int cortex_a8_exec_opcode(struct target *target,
 		uint32_t opcode, uint32_t *dscr_p)
@@ -107,7 +107,7 @@ static int cortex_a8_exec_opcode(struct target *target,
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 
 	/* Wait for InstrCompl bit to be set */
-	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0)
+	while ((dscr & DSCR_INSTR_COMP) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -130,7 +130,7 @@ static int cortex_a8_exec_opcode(struct target *target,
 			return retval;
 		}
 	}
-	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
+	while ((dscr & DSCR_INSTR_COMP) == 0); /* Wait for InstrCompl bit to be set */
 
 	if (dscr_p)
 		*dscr_p = dscr;
@@ -198,7 +198,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
 	}
 
 	/* Wait for DTRRXfull then read DTRRTX */
-	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0)
+	while ((dscr & DSCR_DTR_TX_FULL) == 0)
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
@@ -225,7 +225,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
 	/* Check that DCCRX is not full */
 	retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	if (dscr & (1 << DSCR_DTR_RX_FULL))
+	if (dscr & DSCR_DTR_RX_FULL)
 	{
 		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
@@ -315,14 +315,14 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
 		uint32_t *dscr_p)
 {
 	struct swjdp_common *swjdp = &a8->armv7a_common.swjdp_info;
-	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_INSTR_COMP;
 	int retval;
 
 	if (dscr_p)
 		dscr = *dscr_p;
 
 	/* Wait for DTRRXfull */
-	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0) {
+	while ((dscr & DSCR_DTR_TX_FULL) == 0) {
 		retval = mem_ap_read_atomic_u32(swjdp,
 				a8->armv7a_common.debug_base + CPUDBG_DSCR,
 				&dscr);
@@ -350,10 +350,10 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
 		retval = mem_ap_read_atomic_u32(swjdp,
 				a8->armv7a_common.debug_base + CPUDBG_DSCR,
 				&dscr);
-	} while ((dscr & (1 << DSCR_INSTR_COMP)) == 0);
+	} while ((dscr & DSCR_INSTR_COMP) == 0);
 
 	/* this "should never happen" ... */
-	if (dscr & (1 << DSCR_DTR_RX_FULL)) {
+	if (dscr & DSCR_DTR_RX_FULL) {
 		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
 		/* Clear DCCRX */
 		retval = cortex_a8_exec_opcode(
@@ -376,7 +376,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
 {
 	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
 	int retval;
-	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_INSTR_COMP;
 
 	retval = cortex_a8_write_dcc(a8, data);
 
@@ -390,7 +390,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
 		uint32_t opcode, uint32_t data)
 {
 	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
-	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_INSTR_COMP;
 	int retval;
 
 	retval = cortex_a8_write_dcc(a8, data);
@@ -413,7 +413,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
 static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
 {
 	struct target *target = dpm->arm->target;
-	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_INSTR_COMP;
 
 	/* "Prefetch flush" after modifying execution status in CPSR */
 	return cortex_a8_exec_opcode(target,
@@ -426,7 +426,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
 {
 	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
 	int retval;
-	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_INSTR_COMP;
 
 	/* the opcode, writing data to DCC */
 	retval = cortex_a8_exec_opcode(
@@ -442,7 +442,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
 		uint32_t opcode, uint32_t *data)
 {
 	struct cortex_a8_common *a8 = dpm_to_a8(dpm);
-	uint32_t dscr = 1 << DSCR_INSTR_COMP;
+	uint32_t dscr = DSCR_INSTR_COMP;
 	int retval;
 
 	/* the opcode, writing data to R0 */
@@ -639,7 +639,7 @@ static int cortex_a8_halt(struct target *target)
 	 */
 	mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	retval = mem_ap_write_atomic_u32(swjdp,
-		armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+		armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
 
 	if (retval != ERROR_OK)
 		goto out;
@@ -647,7 +647,7 @@ static int cortex_a8_halt(struct target *target)
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
+	} while ((dscr & DSCR_CORE_HALTED) == 0);
 
 	target->debug_reason = DBG_REASON_DBGRQ;
 
@@ -742,13 +742,18 @@ static int cortex_a8_resume(struct target *target, int current,
 	}
 
 #endif
-	/* Restart core and wait for it to be started */
+	/* Restart core and wait for it to be started
+	 * NOTE: this clears DSCR_ITR_EN and other bits.
+	 *
+	 * REVISIT: for single stepping, we probably want to
+	 * disable IRQs by default, with optional override...
+	 */
 	mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
 
 	do {
 		mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, &dscr);
-	} while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
+	} while ((dscr & DSCR_CORE_RESTARTED) == 0);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	target->state = TARGET_RUNNING;
@@ -788,7 +793,6 @@ static int cortex_a8_debug_entry(struct target *target)
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
-	/* Enable the ITR execution once we are in debug mode */
 	mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 
@@ -797,12 +801,13 @@ static int cortex_a8_debug_entry(struct target *target)
 	 * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
 	 */
 
-	dscr |= (1 << DSCR_EXT_INT_EN);
+	/* Enable the ITR execution once we are in debug mode */
+	dscr |= DSCR_ITR_EN;
 	retval = mem_ap_write_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DSCR, dscr);
 
 	/* Examine debug reason */
-	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
+	switch (DSCR_ENTRY(cortex_a8->cpudbg_dscr))
 	{
 		case 0:		/* DRCR[0] write */
 		case 4:		/* EDBGRQ */
@@ -1005,7 +1010,8 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address,
 	}
 
 	cortex_a8_unset_breakpoint(target, &stepbreakpoint);
-	if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
+	if (timeout > 0)
+		target->debug_reason = DBG_REASON_BREAKPOINT;
 
 	if (breakpoint)
 		cortex_a8_set_breakpoint(target, breakpoint, 0);

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c        |   66 +++++++++++++++-------------------
 src/target/arm11.h        |   35 +-----------------
 src/target/arm11_dbgtap.c |   44 -----------------------
 src/target/arm11_dbgtap.h |    2 -
 src/target/arm_dpm.c      |   36 ++++++++++++++++++
 src/target/arm_dpm.h      |   20 ++++++++++
 src/target/armv7a.c       |   14 ++-----
 src/target/armv7a.h       |   10 -----
 src/target/cortex_a8.c    |   87 ++++++++++++++++++++------------------------
 9 files changed, 130 insertions(+), 184 deletions(-)


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