myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] Question about conversion of slice types

[Martin S. <ha...@se...>]

Hi list,

for a few reasons, one of them being switchable external definitions,
I'd like to define slice types as follows:

OP_INDEX = slice(11, 8)
OP_MODE = slice(8, 6)

and use them later in the HDL. No problem in the native simulation, but
obviously, myhdl would not convert the slice type into VHDL. I've done
some patching in the AST-featured visitors to turn the slice into a subtype:

    subtype OP_INDEX is integer range 11-1 downto 8;

to be used by the HDL conversion as:

        index := resize(opcode(OP_INDEX), 11);

Now with the new shadow signals, in particular the slice signal, a
presumably much more elegant solution is possible, but when I tried
last, it wouldn't infer the signal for some reason (not investigated
further). I'm using the 0.8 sourceforge distribution.

Apology if I'm bringing up some FAQ, but does anyone see reasons not to
do it this way or problems for the Verilog conversion side?

Cheers,

- Strubi

Re: [myhdl-list] MEP 107 Initial support

[Christopher F. <chr...@gm...>]

On 7/4/13 9:37 PM, Keerthan jai.c wrote:
> I have also added support for inferring portnames from objects.
> There is no depth restriction, You can safely use something like
> instance.attr1.attr2.next = something.
>
> Feel free to try it out and let me know if you experience any errors.
>
>
> On Wed, Jul 3, 2013 at 10:44 PM, Keerthan jai.c <jck...@gm...
> <mailto:jck...@gm...>> wrote:
>
>     Hi,
>
>     I've added inital support for conversion of attribute references. So
>     far, it does not support inferring port names at the top level.
>     However, it does support attribute referencing in lower levels of
>     the hierarchy. I have not yet tested it extensively, but I did
>     confirm it does not break any older tests.
>
>     You can find it in the MEP107 branch here:
>     https://bitbucket.org/jck2/myhdl
>
>     --
>     have a nice day
>     -jck
>
>

I have not had time to review the changes line-by-line
but I have added a couple unit tests [1] and tested on
a project [2][3].

jck has added the unit tests to the repository mentioned
above [4].  See jck's repo for the latest implementation.

Functionally this implementation looks complete and has
tested well.  Thanks for the implementation jck!  This
is really exciting.  All the tests in conversion/general
appear to pass, need to run the other tests when we have
a chance.

Regards,
Chris Felton

[1] https://bitbucket.org/cfelton/myhdl_interfaces_09dev
[2] https://github.com/cfelton/minnesota/tree/myhdl_09
 
https://github.com/cfelton/minnesota/blob/myhdl_09/mn/cores/usb_ext/fpgalink/_fpgalink_fx2.py
[3] https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
[4] https://bitbucket.org/jck2/myhdl

Re: [myhdl-list] MyHDL Questions

[Christopher F. <chr...@gm...>]

<snip>
>
>
> The second question:
>
> There seems to be a Problem with the translation of the following line:
> led_bit_mem.next = (1 << MB-2)
> After using toVhdl() to generate a vhdl file
>
>    myhdl will translate this to:
>
> led_bit_mem <= to_unsigned(shift_left(1, (MB - 2)), 16);

This one we will have to look at some more, as
you point out the shift_* expected signed/unsigned
and to_unsigned wants a natural.

I modified the original example to do the bit position
calculation in elaboration instead of inline in the
assignment.  The update code can be viewed here:

http://www.fpgarelated.com/showarticle/25.php

The conversion avoids the above issue.

Regards,
Chris

>
> This generates a compiler error.(We use Altium Designer with xilinx
> Tools)
> The problem ist that the shift_left from numeric_std needs as the
> first
> argument a signed or a unsigned type. It doesn't work with a
> integerconstant.
>

[myhdl-list] [dev] GHDL simulator

[Christopher F. <chr...@gm...>]

When I add unit tests I typically have an issue
trying to use the GHDL simulator.  I don't have
an issue with the GHDL simulator itself but the
commands embedded in /_verify.py/ doesn't seem
to work on my system(s).

I am using GHDL version 0.29.  I typically need
to make the following modifications to the GHDL
commands:

     registerSimulator(
         name="GHDL",
         hdl="VHDL",
         analyze="ghdl -a --workdir=work
            pck_myhdl_%(version)s.vhd %(topname)s.vhd",
         elaborate="ghdl -e --workdir=work
            -o %(unitname)s_ghdl %(topname)s",
         simulate="ghdl -r %(unitname)s_ghdl"
     )

to:
     registerSimulator(
         name="GHDL",
         hdl="VHDL",
         analyze="ghdl -a --workdir=work
            pck_myhdl_%(version)s.vhd     %(topname)s.vhd",
         elaborate="ghdl -e --workdir=work
            -o %(unitname)s %(topname)s",
         simulate="ghdl -r --workdir=work %(unitname)s"
     )


After I make the changes, the test I add run
successfully and *most* of the current tests pass.

Any insight to my system setup issue would be
appreciated.

Regards,
Chris Felton

Re: [myhdl-list] MyHDL Questions

[Christopher F. <chr...@gm...>]

On 7/12/13 5:23 AM, Jan Coombs wrote:
> On 11/07/13 08:53, Michael Tissen wrote:
>> Hello,
> hi Michael,
> Your post has an unusual format, is this a feature of Altium?  I've
> shortened it to read, though not yet looked at your question:

Thanks Jan C.!

>
> Hello,
> i am a Computer science student  and we want to use myhdl for
> a Project.
>
> We have noticed that in most of your examples you are using verilog
> but we
> want to use vhdl.
>
> Below i have included a sample vhdl code for a wishbone slave which
> we try
> to rebuild with myHDL.
>
> With the following python code:
>
>    @always_comb
>    def hdl_map_output():
>     if stb_i == 1:
>      ack_o.next = 1
>     else:
>      ack_o.next = 0
>    return FSM,hdl_map_output
>
>
> we expected to create the following code:
> (1) ack_o <= '1' when (S = S1 and stb_i = '1') else '0';
> But MyHDL creates a new process! But we Need it outside of a process!
>
> WB_SLAVE_CTRL_HDL_MAP_OUTPUT: process (stb_i) is
>    begin
>       if (stb_i = '1') then
>           ack_o <= '1';
>       else
>           ack_o <= '0';
>       end if;
> end process WB_SLAVE_CTRL_HDL_MAP_OUTPUT;
> end architecture MyHDL;

Why do you think this is an error and why do you
expect a concurrent signal assignment outside of
the process?

Re: [myhdl-list] MyHDL Questions

[Jan C. <jen...@mu...>]

On 11/07/13 08:53, Michael Tissen wrote:
> Hello,
hi Michael,
Your post has an unusual format, is this a feature of Altium?  I've 
shortened it to read, though not yet looked at your question:

Hello,
i am a Computer science student  and we want to use myhdl for
a Project.

We have noticed that in most of your examples you are using verilog 
but we
want to use vhdl.

Below i have included a sample vhdl code for a wishbone slave which 
we try
to rebuild with myHDL.

With the following python code:

  @always_comb
  def hdl_map_output():
   if stb_i == 1:
    ack_o.next = 1
   else:
    ack_o.next = 0
  return FSM,hdl_map_output


we expected to create the following code:
(1) ack_o <= '1' when (S = S1 and stb_i = '1') else '0';
But MyHDL creates a new process! But we Need it outside of a process!

WB_SLAVE_CTRL_HDL_MAP_OUTPUT: process (stb_i) is
  begin
     if (stb_i = '1') then
         ack_o <= '1';
     else
         ack_o <= '0';
     end if;
end process WB_SLAVE_CTRL_HDL_MAP_OUTPUT;
end architecture MyHDL;


Why? Is it possible to create code like (1) ? Or it doesnt work 
because
verilog not uses it?

Do you have a suggestion for our Problem? We need the (1) Statement 
ouside
the previous process.


The second question:

There seems to be a Problem with the translation of the following line:
led_bit_mem.next = (1 << MB-2)
After using toVhdl() to generate a vhdl file

  myhdl will translate this to:

led_bit_mem <= to_unsigned(shift_left(1, (MB - 2)), 16);

This generates a compiler error.(We use Altium Designer with xilinx 
Tools)
The problem ist that the shift_left from numeric_std needs as the 
first
argument a signed or a unsigned type. It doesn't work with a 
integerconstant.

Is the Verilog converter working better than the VHDL converter?
I hope you can give us some help.
We really like the idea of MyHDL it reduce a lot of time.

VHDL-CODE:

entity WB_Slave_Ctrl is
   port (
     clk, res: in std_logic;
     stb_i:    in std_logic; -- strobe input signal
     full_i:   in std_logic; -- full flag from HW_Proc
     ack_o:   out std_logic  -- ack output signal
   );
end WB_Slave_Ctrl;

architecture fsm_slave of WB_Slave_Ctrl is
   type States is (S1, S2);
   signal S: States := S2;

begin
   fsm: process(clk, res)
     begin
       if res = '1' then
         S <= S2;
       elsif clk'event and clk = '1' then
         case S is
         when S1 =>
           if stb_i = '1' and full_i = '0' then
             S <= S2;
           end if;
         when  S2 =>
           if full_i = '0' then
             S <= S1;
           end if;
         end case;
       end if;
   end process;
   ack_o <= '1' when (S = S1 and stb_i = '1') else '0';
end fsm_slave;

Best Regards


Kind regards, Jan Coombs








Jan Coombs

Re: [myhdl-list] MEP 107 Initial support

[Christopher F. <chr...@gm...>]

On 7/6/2013 4:58 PM, Keerthan jai.c wrote:
> Thanks!
>
> Don't forget to sync your fork with mine before running your tests..
>
>

I was unable to find the tests I thought I had created
in the past (more than likely never existed).  I will
provide some feedback ASAP.

Regards,
Chris

[myhdl-list] MyHDL Questions

[Michael T. <mic...@gm...>]

Hello,







i am a Computer science student  and we want to use myhdl for 







a Project.







We have noticed that in most of your examples you are using verilog but we 

want to use vhdl.







Below i have included a sample vhdl code for a wishbone slave which we try 

to rebuild with myHDL. 







With the following python code:



 







 @always_comb



 def hdl_map_output():



  if stb_i == 1:



   ack_o.next = 1



  else:



   ack_o.next = 0



 return FSM,hdl_map_output 







we expected to create the following code:







 



(1) ack_o <= '1' when (S = S1 and stb_i = '1') else '0';











But MyHDL creates a new process! But we Need it outside of a process! 







WB_SLAVE_CTRL_HDL_MAP_OUTPUT: process (stb_i) is



 begin



    if (stb_i = '1') then



        ack_o <= '1';



    else



        ack_o <= '0';



    end if;



end process WB_SLAVE_CTRL_HDL_MAP_OUTPUT;







end architecture MyHDL;











Why? Is it possible to create code like (1) ? Or it doesnt work because 

verilog not uses it?











Do you have a suggestion for our Problem? We need the (1) Statement ouside 

the previous process.











The second question:







There seems to be a Problem with the translation of the following line:







led_bit_mem.next = (1 << MB-2)







After using toVhdl() to generate a vhdl file



 myhdl will translate this to:







led_bit_mem <= to_unsigned(shift_left(1, (MB - 2)), 16);







This generates a compiler error.(We use Altium Designer with xilinx Tools)



The problem ist that the shift_left from numeric_std needs as the first 

argument a signed or a unsigned type.



 It doesn't work with a integerconstant. 







Is the Verilog converter working better than the VHDL converter?







I hope you can give us some help. 







We really like the idea of MyHDL it reduce a lot of time.







VHDL-CODE:



entity WB_Slave_Ctrl is



  port (



    clk, res: in std_logic;



    stb_i:    in std_logic; -- strobe input signal



    full_i:   in std_logic; -- full flag from HW_Proc



    ack_o:   out std_logic  -- ack output signal



  );



end WB_Slave_Ctrl;







architecture fsm_slave of WB_Slave_Ctrl is



  type States is (S1, S2);



  signal S: States := S2;



begin



  fsm: process(clk, res)



    begin



      if res = '1' then



        S <= S2;



      elsif clk'event and clk = '1' then



        case S is



        when S1 =>



          if stb_i = '1' and full_i = '0' then



            S <= S2;



          end if;



        when  S2 =>



          if full_i = '0' then



            S <= S1;



          end if;



        end case;



      end if;



  end process;



  ack_o <= '1' when (S = S1 and stb_i = '1') else '0';



end fsm_slave;



 







Best Regards

Re: [myhdl-list] MEP 107 Initial support

[Keerthan jai.c <jck...@gm...>]

Thanks!

Don't forget to sync your fork with mine before running your tests..


On Fri, Jul 5, 2013 at 11:25 AM, Christopher Felton
<chr...@gm...>wrote:

> On 7/5/13 10:11 AM, Christopher Felton wrote:
> > On 7/3/13 9:44 PM, Keerthan jai.c wrote:
> >> Hi,
> >>
> >> I've added inital support for conversion of attribute references. So
> >> far, it does not support inferring port names at the top level. However,
> >> it does support attribute referencing in lower levels of the hierarchy.
> >> I have not yet tested it extensively, but I did confirm it does not
> >> break any older tests.
> >>
> >> You can find it in the MEP107 branch here:
> https://bitbucket.org/jck2/myhdl
> >>
> >> --
> >> have a nice day
> >> -jck
> >
> >
> > One logistical nit.  You made the changes to the default
> > branch.  We have been doing all our development on a branch
> > (so that bug fixes can be made on the default branch).  This
> > enhancement implementation should be on a 0.9-dev branch.
> > I don't know if anyone can create the branch or if Jan needs
> > to create it?
> >
>
> My bad, I see you created a mep107 branch.  This should
> work fine.
>
> > Regards,
> > Chris Felton
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> > This SF.net email is sponsored by Windows:
> >
> > Build for Windows Store.
> >
> > http://p.sf.net/sfu/windows-dev2dev
> >
>
>
>
>
> ------------------------------------------------------------------------------
> This SF.net email is sponsored by Windows:
>
> Build for Windows Store.
>
> http://p.sf.net/sfu/windows-dev2dev
> _______________________________________________
> myhdl-list mailing list
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] MEP 107 Initial support

[Christopher F. <chr...@gm...>]

On 7/5/13 10:11 AM, Christopher Felton wrote:
> On 7/3/13 9:44 PM, Keerthan jai.c wrote:
>> Hi,
>>
>> I've added inital support for conversion of attribute references. So
>> far, it does not support inferring port names at the top level. However,
>> it does support attribute referencing in lower levels of the hierarchy.
>> I have not yet tested it extensively, but I did confirm it does not
>> break any older tests.
>>
>> You can find it in the MEP107 branch here: https://bitbucket.org/jck2/myhdl
>>
>> --
>> have a nice day
>> -jck
>
>
> One logistical nit.  You made the changes to the default
> branch.  We have been doing all our development on a branch
> (so that bug fixes can be made on the default branch).  This
> enhancement implementation should be on a 0.9-dev branch.
> I don't know if anyone can create the branch or if Jan needs
> to create it?
>

My bad, I see you created a mep107 branch.  This should
work fine.

> Regards,
> Chris Felton
>
>
>
> ------------------------------------------------------------------------------
> This SF.net email is sponsored by Windows:
>
> Build for Windows Store.
>
> http://p.sf.net/sfu/windows-dev2dev
>

Re: [myhdl-list] MEP 107 Initial support

[Christopher F. <chr...@gm...>]

On 7/3/13 9:44 PM, Keerthan jai.c wrote:
> Hi,
>
> I've added inital support for conversion of attribute references. So
> far, it does not support inferring port names at the top level. However,
> it does support attribute referencing in lower levels of the hierarchy.
> I have not yet tested it extensively, but I did confirm it does not
> break any older tests.
>
> You can find it in the MEP107 branch here: https://bitbucket.org/jck2/myhdl
>
> --
> have a nice day
> -jck

Thanks for the contribution!  I am unavailable for the
next couple days (holiday in the states) but when I
return I will "pull request" my tests for MEP107 and
give the changes a look.

One logistical nit.  You made the changes to the default
branch.  We have been doing all our development on a branch
(so that bug fixes can be made on the default branch).  This
enhancement implementation should be on a 0.9-dev branch.
I don't know if anyone can create the branch or if Jan needs
to create it?

If we decide this implementation is desired, the current
bundle (commit, pull request, etc) could not be accepted
because it is on the default branch.

Regards,
Chris Felton

Re: [myhdl-list] MEP 107 Initial support

[Keerthan jai.c <jck...@gm...>]

I have also added support for inferring portnames from objects.
There is no depth restriction, You can safely use something like
instance.attr1.attr2.next = something.

Feel free to try it out and let me know if you experience any errors.


On Wed, Jul 3, 2013 at 10:44 PM, Keerthan jai.c <jck...@gm...>wrote:

> Hi,
>
> I've added inital support for conversion of attribute references. So far,
> it does not support inferring port names at the top level. However, it does
> support attribute referencing in lower levels of the hierarchy. I have not
> yet tested it extensively, but I did confirm it does not break any older
> tests.
>
> You can find it in the MEP107 branch here:
> https://bitbucket.org/jck2/myhdl
>
> --
> have a nice day
> -jck
>



-- 
have a nice day
-jck

[myhdl-list] MEP 107 Initial support

[Keerthan jai.c <jck...@gm...>]

Hi,

I've added inital support for conversion of attribute references. So far,
it does not support inferring port names at the top level. However, it does
support attribute referencing in lower levels of the hierarchy. I have not
yet tested it extensively, but I did confirm it does not break any older
tests.

You can find it in the MEP107 branch here: https://bitbucket.org/jck2/myhdl

-- 
have a nice day
-jck

Re: [myhdl-list] Slides of my presentation at PyConTW 2013

[Christopher F. <chr...@gm...>]

On 5/29/13 5:03 AM, Norbo wrote:
> I think myhdl is very good for verification because python is:

I couldn't really read the ASCII table you embedded,
and I couldn't resist ... some folks might despise
polls and data collection ... but I created a poll
with google docs.  If you like, feel free to voice
your opinion on the topics Norbo presented.

https://docs.google.com/forms/d/1bJHBeFYJGm9nkDBzn6G8h-wK04i3IcnVmuRbbmyi2Ls/viewform

Regards,
Chris

Re: [myhdl-list] Summary of "Initial Values Support" threads

[Norbo <Nor...@gm...>]

Am 27.06.2012, 06:26 Uhr, schrieb Christopher Felton  
<chr...@gm...>:

> On 6/15/12 4:12 AM, Jan Decaluwe wrote:
>> On 05/30/2012 06:47 AM, Christopher Felton wrote:
>>> We listed a summary a couple time but the initial value support (ivs)
>>> was embedded in a separate thread.  So, I thought it would be worth
>>> while to summarize in a new thread.
>>>
>>>
>>>      1.  Initial value support can be re-enabled.  The Verilog
>>>          support of initial values as verified with the latest
>>>          of Quartus.
>>>          Need to test with (list syn and sim tools)?
>>>            [x] Quartus latest
>>>            [ ] ISE (xst) latest
>>>            [ ] cver
>>>            [ ] icarus
>>
>> Ok, perhaps make a page on the site to keep track
>> of the status.
>>
>
> I created a wiki page and essentially copied the latest summary to the
> wiki page, it is a little rough right now.
>
> http://www.myhdl.org/doku.php/dev:initial_values
>
> Regards,
> Chris


I am now sure that the lattice diamond Synthesis Tool v2.1 works with  
memory initialisation infered from the code.
You may ask why?
Answer: The Initialisation of the memory didn't worked when the bitwidth  
of the memory exceeded 9 Bits. Everything that was above 9 bit was  
initialized to "0" on the fpga. The synthesis tool showed no error.
I had a long chat with the technical support. And know in v2.1 of the  
Latic Diamond Synthesis Tool they fixed this Glitch.
At the core they use Synplify pro for synthesis. But i think it was a  
mapping problem in there tool.

Hope that helps brings forward initial value support in Myhdl one Day.

Greetings
Norbo

Re: [myhdl-list] Slides of my presentation at PyConTW 2013

[Per K. <bas...@gm...>]

I'd certainly take the time to listen!
/Per

> Perhaps I should consider talks (even virtual ones :-) from a hardware or
HDL designers' perspective.



On Thu, May 30, 2013 at 7:40 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 05/29/2013 05:10 PM, Tom Dillon wrote:
> > Jan,
> >
> > That looks great. How was it received?
>
> I'm quite satisfied with the response.
>
> Now that I have published the slides on speakerdeck, I'm starting
> to think this may be a more powerful way to get a message across
> than through blogs or papers.
>
> > I wonder if you shouldn't post that as a quick intro on the MyHDL web
> site?
>
> I will certainly include the link. Of course, this was from a Python
> perspective. Perhaps I should consider talks (even virtual ones :-)
> from a hardware or HDL designers' perspective.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
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Re: [myhdl-list] Slides of my presentation at PyConTW 2013

[Jan D. <ja...@ja...>]

On 05/29/2013 05:10 PM, Tom Dillon wrote:
> Jan,
>
> That looks great. How was it received?

I'm quite satisfied with the response.

Now that I have published the slides on speakerdeck, I'm starting
to think this may be a more powerful way to get a message across
than through blogs or papers.

> I wonder if you shouldn't post that as a quick intro on the MyHDL web site?

I will certainly include the link. Of course, this was from a Python
perspective. Perhaps I should consider talks (even virtual ones :-)
from a hardware or HDL designers' perspective.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Slides of my presentation at PyConTW 2013

[Tom D. <TD...@Di...>]

Jan,

That looks great. How was it received?

I wonder if you shouldn't post that as a quick intro on the MyHDL web site?

Tom




On Tue, May 28, 2013 at 10:52 AM, Jan Decaluwe <ja...@ja...> wrote:

> Hi all:
>
> Here are the slides of my keynote presentation at PyConTW 2013
> in Taiwan. This was a Python conference, so the emphasis is on
> the design of MyHDL itself rather than hardware design with it.
>
>
> https://speakerdeck.com/jandecaluwe/myhdl-designing-digital-hardware-with-python-pycontw-2013
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Try New Relic Now & We'll Send You this Cool Shirt
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Re: [myhdl-list] Slides of my presentation at PyConTW 2013

[Norbo <Nor...@gm...>]

I think myhdl is very good for verification because python is.
Here the Reason why i think some other known Solutions arent that good for  
verfication.

I make my descision based on the following points i picked out:


Libraries....Easy to integrate libraries into the verification process
	 (etc.. opencv, ploting, 3d Visualisation, Unit-Testframeworks) all stuff
	that can help to verify your Design.

Kommunikation.....Effort (extracode) needed to interact with your Hardware  
Design from the highlevel libary

Learning effort....How long it takes to grab the basic konzept

Ease of Use.....When you have the konzept how easy is it to implement.

Vendor....Locked to a specific Vendor for verfication

Toolchain stability .... Glitches problems that might occour in the  
verfication (Simulation/cosimulation proccess)

Syntax Wiredness...How wired the Synthax looks and feels.



                 | Libraries | Kommunikation | Learning effort | Vendor   |  
Toolchain stability | Syntax Wiredness|
------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------SystemC          
|   OK      |     hard      |   pretty high   |   OK/Bad |  well (co-sim  
pain) |   high          |
------------------------------------------------------------------------------------------------------------------
SystemVeriolog  |    Bad    |     OK       |   pretty high    |  ?        
|    seems OK         | extra high(mixed)|
------------------------------------------------------------------------------------------------------------------Matlab           
|    Good   |     hard     |Low/high(integr.) |  Bad     |        
Good/OK       |    low          |
------------------------------------------------------------------------------------------------------------------
VHDL/Verilog    |    Bad    |     OK       |    moderate      |  OK       
|       OK            |    moderate     |
------------------------------------------------------------------------------------------------------------------
Myhdl           |    Best   |     Easy     |    moderate      | OK  
(VHDL)|      OK             |     low         |


Well this reflects my point of view.


Greetings
Norbo






> On Tue, May 28, 2013 at 5:52 PM, Jan Decaluwe <ja...@ja...>  
> wrote:
>> Hi all:
>>
>> Here are the slides of my keynote presentation at PyConTW 2013
>> in Taiwan. This was a Python conference, so the emphasis is on
>> the design of MyHDL itself rather than hardware design with it.
>>
>> https://speakerdeck.com/jandecaluwe/myhdl-designing-digital-hardware-with-python-pycontw-2013
>
> Thanks for sharing Jan,
>
> very nice presentation. It is a very good overview of what MyHDL is.
>
> You often highlight the fact that MyHDL is very good for verification.
> Is there a document or web page were you enter into that in more
> detail?
>
> Cheers,
>
> Angel
>
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Re: [myhdl-list] Slides of my presentation at PyConTW 2013

[Angel E. <ang...@gm...>]

On Tue, May 28, 2013 at 5:52 PM, Jan Decaluwe <ja...@ja...> wrote:
> Hi all:
>
> Here are the slides of my keynote presentation at PyConTW 2013
> in Taiwan. This was a Python conference, so the emphasis is on
> the design of MyHDL itself rather than hardware design with it.
>
> https://speakerdeck.com/jandecaluwe/myhdl-designing-digital-hardware-with-python-pycontw-2013

Thanks for sharing Jan,

very nice presentation. It is a very good overview of what MyHDL is.

You often highlight the fact that MyHDL is very good for verification.
Is there a document or web page were you enter into that in more
detail?

Cheers,

Angel

[myhdl-list] Slides of my presentation at PyConTW 2013

[Jan D. <ja...@ja...>]

Hi all:

Here are the slides of my keynote presentation at PyConTW 2013
in Taiwan. This was a Python conference, so the emphasis is on
the design of MyHDL itself rather than hardware design with it.

https://speakerdeck.com/jandecaluwe/myhdl-designing-digital-hardware-with-python-pycontw-2013

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Assignment to arbitrary bits of an intbv

[Alastair M. <amc...@go...>]

Hi Chris,

Thanks for your help. Very silly of me not to figure that one out!

Best regards,

Alastair


On 23 May 2013 13:20, Christopher Felton <chr...@gm...> wrote:

> On 5/23/2013 5:37 AM, Alastair McKinley wrote:
> > Hi all,
> >
> > I have just started looking in myHDL and am quite excited about it's
> > potential.
> >
> > I have a short question about assignment to intbv objects. I want to
> model
> > closely a reference VHDL implementation which has a 128 bit input from a
> > DMA engine.
> >
> <snip>
> >
> > The input signal to my module doesn't change in this case.
> >
> > What is the right way to do this in myHDL?
> >
> > Best regards,
> >
> > Alastair
> >
>
> Alastair,
>
> Your example is incomplete, you don't show how you
> define (instantiate) /inData/.  If inData is simply,
> (as you imply):
>
>      inData = Signal(intbv(0)[128:])
>
> Then you have a small syntax error:
>
>      inData[32:0].next = ...
>      inData[64:32].next = ...
>
> should be,
>
>      inData.next[32:0] = ...
>      inData.next[64:32] = ...
>
>
> The syntax /inData[].next/ and /inData.next[]/ is the
> difference between a list of signal item selection and
> the bit vector bit selection.
>
> Hope that helps,
> Chris
>
>
>
>
>
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Re: [myhdl-list] 0.8 released

[Christopher F. <chr...@gm...>]

On 5/23/2013 8:12 AM, Jan Decaluwe wrote:
> On 05/23/2013 02:29 PM, Christopher Felton wrote:
>> On 5/20/2013 1:04 PM, Jan Decaluwe wrote:
>>> All:
>>>
>>> I have just released 0.8.
>>>
>>> It is on SourceForge as usual, but of course
>>> you can also download from the tag on Bitbucket.
>>>
>>> The Bitbucket repo is the main repo from now
>>> on, I have update the development pages on
>>> myhdl.org accordingly.
>>>
>>
>> There appears to be some broken links in the updated
>> manual?
>
>
> Caching issues? (Shift-Refresh?)
>

Doh, sorry about that, ugh.

Yes, that fixes it.

Regards,
Chris

Re: [myhdl-list] 0.8 released

[Jan D. <ja...@ja...>]

On 05/23/2013 02:29 PM, Christopher Felton wrote:
> On 5/20/2013 1:04 PM, Jan Decaluwe wrote:
>> All:
>>
>> I have just released 0.8.
>>
>> It is on SourceForge as usual, but of course
>> you can also download from the tag on Bitbucket.
>>
>> The Bitbucket repo is the main repo from now
>> on, I have update the development pages on
>> myhdl.org accordingly.
>>
>
> There appears to be some broken links in the updated
> manual?


Caching issues? (Shift-Refresh?)

>
> On the manual landing page (http://www.myhdl.org/doc/current/)
> "Modeling techniques" points to:
>
> http://www.myhdl.org/doc/current/manual/modeling.html
>
> And I get a "Not Found" for this page.
>
> In addition the "What's new in MyHDL 0.8" is not available
> on the manuals landing page, (http://www.myhdl.org/doc/current/)
>
> The manual seems to be a mix of v0.7 and v0.8?
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Try New Relic Now & We'll Send You this Cool Shirt
> New Relic is the only SaaS-based application performance monitoring service
> that delivers powerful full stack analytics. Optimize and monitor your
> browser, app, & servers with just a few lines of code. Try New Relic
> and get this awesome Nerd Life shirt! http://p.sf.net/sfu/newrelic_d2d_may
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] 0.8 released

[Christopher F. <chr...@gm...>]

On 5/20/2013 1:04 PM, Jan Decaluwe wrote:
> All:
>
> I have just released 0.8.
>
> It is on SourceForge as usual, but of course
> you can also download from the tag on Bitbucket.
>
> The Bitbucket repo is the main repo from now
> on, I have update the development pages on
> myhdl.org accordingly.
>

There appears to be some broken links in the updated
manual?

On the manual landing page (http://www.myhdl.org/doc/current/)
"Modeling techniques" points to:

http://www.myhdl.org/doc/current/manual/modeling.html

And I get a "Not Found" for this page.

In addition the "What's new in MyHDL 0.8" is not available
on the manuals landing page, (http://www.myhdl.org/doc/current/)

The manual seems to be a mix of v0.7 and v0.8?

Regards,
Chris