myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] fixed-point thoughts : part two

[Benjamin B. <ben...@si...>]

Hello,

I think there are some serious issues with the behaviour that you are
suggest. The fact that two fixedbv added together should return an
integer (instead of a floating point value) alone opens a *huge* can of
worms.

Lets take your example:

On Mi, 2013-09-04 at 22:28 -0500, Christopher Felton wrote:
>      >>> x = fixbv(0,min=-8,max=8,res=1/16.)
>      >>> y = fixbv(0,min=-1,max=1,res=1/128.)
>      >>> x + y
>      AssertionError: Add: points not aligned
>             fixbv(0.00, format=(8,3,4), ) and fixbv(0.00, format=(8,0,7), )

A nice assertion error, but now, if I did:
      >>> x + x + y
Then the result:
 1. is not quite defined (either it is wrong, or results in really
surprising behaviour, see below)
 2. doesn't throw any error!

The same issue occurs when assigning the result of an operation to a new
fixedbv type. You do not get *any* error checking whether the point is
still at the same spot. The only way around this would be to either
return a fixedbv for any operation that happens[1], or a floating point
number.

Note that as a direct consequence the following code:
 >>> int(fixedbv(1.25,min=-8,max=8,res=1/16.)
would need to return 20. I personally would expect 1 to be returned.

The same turned, what about:
 >>> fixedbv(1.25,min=-8,max=8,res=1/16.) + 1
To be consistent with the suggestion, this would result in 1.3125. Not
something I would expect.

Benjamin

[1] I am actually very surprised that calculations with /intbv/s have an
integer result and not an intbv result with the min/max values kept up
to date.

Re: [myhdl-list] attribute enum_encoding: string;

[Jan D. <ja...@ja...>]

There are other similar case in the mean time due
to Python additions, such as 'bin'.

I propose to review all this when going to Python3,
seems a good time make larger changes iff required.

On 09/05/2013 01:20 PM, Angel Ezquerra wrote:
> My point was that perhaps calling MyHDL enums "enum" which is a
> builtin type in Python 3.4 (I believe!) may cause trouble long term,
> since it may require having to modify existing MyHDL files.
>
> Cheers,
>
> Angel
>
> On Thu, Sep 5, 2013 at 1:06 PM, Christopher Felton
> <chr...@gm...> wrote:
>> On 9/4/13 11:49 PM, Angel Ezquerra wrote:
>>> Chris,
>>>
>>> I have not followed this in much detail so please excuse me if this is
>>> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get
>>> a builtin enum class. I think we should make sure that we make it
>>> possible to use it if MyHDL is ever ported to Python 3.
>>>
>>> Cheers,
>>>
>>> Angel
>>>
>>>
>>
>> Yes, the "enum" is from the MyHDL package.  Something might
>> need to be done to be compatible with the latest version of
>> Python 3 when we get there :)
>>
>> Regards,
>> Chris
>>
>>
>>
>> ------------------------------------------------------------------------------
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] attribute enum_encoding: string;

[Jan D. <ja...@ja...>]

Mm, I suspect there will still be a bug iff an
enum type is used at the top-level.

If someone provides a failing test case, I'll
fix it :-)

On 09/09/2013 02:43 PM, David Holl wrote:
> ugh!  My asinine filesystem lockdowns had prevented any recent updates to myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012.  Updating to the latest 0.8 fixed the problem.
>
> The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package declared before any other statements such as "use work.pck_myhdl_08.all;"
>
>     package pck_pcie_drx is
>          type t_enum_t_state_1 is (
>          SM_RESET,
>     ...
>
> (but my design does not use any enum's in the ports)
>
> However in the vhdl from the latest 0.8, there is no top-level package, and the code opens with
>
>     library IEEE;
>     use IEEE.std_logic_1164.all;
>     use IEEE.numeric_std.all;
>     use std.textio.all;
>     use work.pck_myhdl_08.all;
>     entity pcie_drx is
>          port (
>              user_clk: in std_logic;
>     ...
>
>
> Thank you Chris and Jan for looking into this!
> - David
>
>
> On Mon, Sep 9, 2013 at 6:25 AM, Jan Decaluwe <ja...@ja... <mailto:ja...@ja...>> wrote:
>
>     Mm, the attribute is declared in pck_myhdl but probably this
>     is namespace issue. Iff a port uses an enum, then a top-level
>     package is needed and the declaration is not seen, unlike
>     when the enum type is declared in the architecture.
>
>     Jan
>
>     On 09/03/2013 09:48 PM, David Holl wrote:
>      > Hello, When using ghdl for syntax checks, I get the following error
>      > for any state machine where encoding="one_hot": pcie_drx.vhd:137:11:
>      > no declaration for "enum_encoding"
>      >
>      > I can resolve ghdl's complaints by adding attribute enum_encoding:
>      > string; to the generated .vhd file.
>      >
>      > Is there a way to have this line included automatically in .vhd
>      > output?  I could add it via a shell script, but I'm wondering if
>      > there is "better way" to do it.  (or is GHDL in error?)
>      >
>      >
>      > For example, here is an trimmed-down excerpt from the top of the .vhd
>      > file showing where I add the line:
>      >
>      > package pck_pcie_drx is attribute enum_encoding: string;  <--- I need
>      > to add this line.
>      >
>      > type t_enum_t_state_22 is (
>      >
>      > IDLE,
>      >
>      > THINK,
>      >
>      > SEND_CMD,
>      >
>      > ADVANCE
>      >
>      > );
>      >
>      > attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100
>      > 1000";
>      >
>      > type t_enum_t_state_23 is ( CMD, MWR_H0H1, MWR32_H2D0, MWR32_D1D2,
>      > MWR32_D3XX, MWR64_H2H3, MWR64_D0D1, DROP ); attribute enum_encoding
>      > of t_enum_t_state_23: type is "00000001 00000010 00000100 00001000
>      > 00010000 00100000 01000000 10000000"; end package pck_pcie_drx;
>      > library IEEE; etc...
>      >
>      >
>      >
>      >
>      > - David ps:  Thank you for the fantastic MyHDL.
>      >
>      >
>      >
>      > ------------------------------------------------------------------------------
>      >
>      >
>     Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
>      > Discover the easy way to master current and previous Microsoft
>      > technologies and advance your career. Get an incredible 1,500+ hours
>      > of step-by-step tutorial videos with LearnDevNow. Subscribe today and
>      > save!
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>      >
>      >
>      >
>      >
>      > _______________________________________________ myhdl-list mailing
>      > list myh...@li... <mailto:myh...@li...>
>      > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>      >
>
>
>     --
>     Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>           Python as a HDL: http://www.myhdl.org
>           VHDL development, the modern way: http://www.sigasi.com
>           World-class digital design: http://www.easics.com
>
>     ------------------------------------------------------------------------------
>     Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
>     Discover the easy way to master current and previous Microsoft technologies
>     and advance your career. Get an incredible 1,500+ hours of step-by-step
>     tutorial videos with LearnDevNow. Subscribe today and save!
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>
>
>
>
> ------------------------------------------------------------------------------
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> Discover the easy way to master current and previous Microsoft technologies
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>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] attribute enum_encoding: string;

[David H. <da...@ad...>]

ugh!  My asinine filesystem lockdowns had prevented any recent updates to
myhdl, and I had been stuck on an old 0.8dev from Nov 9, 2012.  Updating to
the latest 0.8 fixed the problem.

The vhdl output from the Nov 9th 0.8dev did indeed have a top-level package
declared before any other statements such as "use work.pck_myhdl_08.all;"

package pck_pcie_drx is

    type t_enum_t_state_1 is (
    SM_RESET,
...

(but my design does not use any enum's in the ports)

However in the vhdl from the latest 0.8, there is no top-level package, and
the code opens with

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_08.all;

entity pcie_drx is
    port (
        user_clk: in std_logic;
...


Thank you Chris and Jan for looking into this!
- David


On Mon, Sep 9, 2013 at 6:25 AM, Jan Decaluwe <ja...@ja...> wrote:

> Mm, the attribute is declared in pck_myhdl but probably this
> is namespace issue. Iff a port uses an enum, then a top-level
> package is needed and the declaration is not seen, unlike
> when the enum type is declared in the architecture.
>
> Jan
>
> On 09/03/2013 09:48 PM, David Holl wrote:
> > Hello, When using ghdl for syntax checks, I get the following error
> > for any state machine where encoding="one_hot": pcie_drx.vhd:137:11:
> > no declaration for "enum_encoding"
> >
> > I can resolve ghdl's complaints by adding attribute enum_encoding:
> > string; to the generated .vhd file.
> >
> > Is there a way to have this line included automatically in .vhd
> > output?  I could add it via a shell script, but I'm wondering if
> > there is "better way" to do it.  (or is GHDL in error?)
> >
> >
> > For example, here is an trimmed-down excerpt from the top of the .vhd
> > file showing where I add the line:
> >
> > package pck_pcie_drx is attribute enum_encoding: string;  <--- I need
> > to add this line.
> >
> > type t_enum_t_state_22 is (
> >
> > IDLE,
> >
> > THINK,
> >
> > SEND_CMD,
> >
> > ADVANCE
> >
> > );
> >
> > attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100
> > 1000";
> >
> > type t_enum_t_state_23 is ( CMD, MWR_H0H1, MWR32_H2D0, MWR32_D1D2,
> > MWR32_D3XX, MWR64_H2H3, MWR64_D0D1, DROP ); attribute enum_encoding
> > of t_enum_t_state_23: type is "00000001 00000010 00000100 00001000
> > 00010000 00100000 01000000 10000000"; end package pck_pcie_drx;
> > library IEEE; etc...
> >
> >
> >
> >
> > - David ps:  Thank you for the fantastic MyHDL.
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> >
> >
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> > Discover the easy way to master current and previous Microsoft
> > technologies and advance your career. Get an incredible 1,500+ hours
> > of step-by-step tutorial videos with LearnDevNow. Subscribe today and
> > save!
> >
> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
> >
> >
> >
> >
> > _______________________________________________ myhdl-list mailing
> > list myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] attribute enum_encoding: string;

[Jan D. <ja...@ja...>]

Mm, the attribute is declared in pck_myhdl but probably this
is namespace issue. Iff a port uses an enum, then a top-level
package is needed and the declaration is not seen, unlike
when the enum type is declared in the architecture.

Jan

On 09/03/2013 09:48 PM, David Holl wrote:
> Hello, When using ghdl for syntax checks, I get the following error
> for any state machine where encoding="one_hot": pcie_drx.vhd:137:11:
> no declaration for "enum_encoding"
>
> I can resolve ghdl's complaints by adding attribute enum_encoding:
> string; to the generated .vhd file.
>
> Is there a way to have this line included automatically in .vhd
> output?  I could add it via a shell script, but I'm wondering if
> there is "better way" to do it.  (or is GHDL in error?)
>
>
> For example, here is an trimmed-down excerpt from the top of the .vhd
> file showing where I add the line:
>
> package pck_pcie_drx is attribute enum_encoding: string;  <--- I need
> to add this line.
>
> type t_enum_t_state_22 is (
>
> IDLE,
>
> THINK,
>
> SEND_CMD,
>
> ADVANCE
>
> );
>
> attribute enum_encoding of t_enum_t_state_22: type is "0001 0010 0100
> 1000";
>
> type t_enum_t_state_23 is ( CMD, MWR_H0H1, MWR32_H2D0, MWR32_D1D2,
> MWR32_D3XX, MWR64_H2H3, MWR64_D0D1, DROP ); attribute enum_encoding
> of t_enum_t_state_23: type is "00000001 00000010 00000100 00001000
> 00010000 00100000 01000000 10000000"; end package pck_pcie_drx;
> library IEEE; etc...
>
>
>
>
> - David ps:  Thank you for the fantastic MyHDL.
>
>
>
> ------------------------------------------------------------------------------
>
>
Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft
> technologies and advance your career. Get an incredible 1,500+ hours
> of step-by-step tutorial videos with LearnDevNow. Subscribe today and
> save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
>
>
>
>
> _______________________________________________ myhdl-list mailing
> list myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] [PATCH 0 of 2 RFC] Add support for negative indexes

[Jan D. <ja...@ja...>]

On 10/13/2012 02:12 AM, Angel Ezquerra wrote:
> Python lists have a natural way to access list itemps from the end of
> the list, which is to use negative indexes. These patches add this
> functionality to MyHDL.
>
> The first patch adds negative index and slice limit support to the
> intbv class. I think this first patch is probably right and not very
> controversial

intbv's are dual in nature - bit sequence but also integer interpretation.

indexing is at the intersection of the two. An index corresponds
to a bit position, but also to the power of the bit when
expanding the integer in a sum of powers of 2. To match
the natural way of writing numbers, intbv slicing is already
totally different from any standard python sequence: the direction
is reversed.

Personally, I haven't seen much need to enhance intbv bit indexing
to match what you can do with sequences like lists. However, there
is a very good reason to stress the power of two interpretation:
when we add a fixbv type, it would be natural to use the same
interpretation. Negative indices would represent fractional bits.
It also seems natural that the intbv would like a subtype of
a general fixbv type.

Therefore, I propose to keep intbv indexing like it is.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] [PATCH 0 of 2 RFC] Add support for negative indexes

[Jan D. <ja...@ja...>]

On 10/13/2012 02:12 AM, Angel Ezquerra wrote:
> Python lists have a natural way to access list itemps from the end of
> the list, which is to use negative indexes. These patches add this
> functionality to MyHDL.
>
> The first patch adds negative index and slice limit support to the
> intbv class. I think this first patch is probably right and not very
> controversial

intbv's are dual in nature - bit sequence but also integer interpretation.

indexing is at the intersection of the two. An index corresponds
to a bit position, but also to the power of the bit when
expanding the integer in a sum of powers of 2. To match
the natural way of writing numbers, intbv slicing is already
totally different from any standard python sequence: the direction
is reversed.

Personally, I haven't seen much need to enhance intbv bit indexing
to match what you can do with sequences like lists. However, there
is a very good reason to stress the power of two interpretation:
when we add a fixbv type, it would be natural to use the same
interpretation. Negative indices would represent fractional bits.
It also seems natural that the intbv would like a subtype of
a general fixbv type.

Therefore, I propose to keep intbv indexing like it is.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] [PATCH 0 of 2 RFC] Add support for negative indexes

[Jan D. <ja...@ja...>]

On 10/13/2012 02:12 AM, Angel Ezquerra wrote:
> Python lists have a natural way to access list itemps from the end of
> the list, which is to use negative indexes. These patches add this
> functionality to MyHDL.
>
> The first patch adds negative index and slice limit support to the
> intbv class. I think this first patch is probably right and not very
> controversial

intbv's are dual in nature - bit sequence but also integer interpretation.

indexing is at the intersection of the two. An index corresponds
to a bit position, but also to the power of the bit when
expanding the integer in a sum of powers of 2. To match
the natural way of writing numbers, intbv slicing is already
totally different from any standard python sequence: the direction
is reversed.

Personally, I haven't seen much need to enhance intbv bit indexing
to match what you can do with sequences like lists. However, there
is a very good reason to stress the power of two interpretation:
when we add a fixbv type, it would be natural to use the same
interpretation. Negative indices would represent fractional bits.
It also seems natural that the intbv would like a subtype of
a general fixbv type.

Therefore, I propose to keep intbv indexing like it is.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] attribute enum_encoding: string;

[David H. <da...@ad...>]

> <snip>
> > But "ghdl -a ..." still complains unless I patch m_think.vhd to add "attribute enum_encoding: string;"
> 
> I don't recall all the VHDL rules here off the top
> of my head.  I can test with some synthesis tools
> as well and do some research.  It is a small change
> that can probably be added, but I have to do some
> inquiring before I create a pull-request.

If I could help with testing, I'd love to try any patch to
apply this small change in my branch.  (I had been using
0.8dev from hg before the 0.8 release, to get access to the
fabulous modbv...) I'm just not sure where the best place
is to add the attribute, since it only needs to be added
once and not for every state machine.

> Best I can tell adding
> 
>      attribute enum_encoding: string
> 
> should be harmless, just an additional attribute
> http://quartushelp.altera.com/11.1/mergedProjects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm
> 
> Regards,
> Chris

My motive for adding the attribute is that I found ghdl
will not complain of other potential syntax errors until
after I resolve this one.  In addition to behavioral test
bench code, I apply syntax checks from ghdl, cver,
iverilog, and verilator, because Xilinx's compiler is so
painfully slow...  :)

I've found that if my model passes all those compilers, my
behavioral tests, and Xilinx timing analysis, then my PCI
Express DMA engine has a great chance of working correctly
on the first try when I load it on a dev kit in Linux.  :)

Re: [myhdl-list] attribute enum_encoding: string;

[Christopher F. <chr...@gm...>]

<snip>
>
> But "ghdl -a ..." still complains unless I patch m_think.vhd to add "attribute enum_encoding: string;"
>
>      tensor(pts/0):~/m_think> diff -u m_think.vhd.orig m_think.vhd
>      --- m_think.vhd.orig    2013-09-05 08:31:50.002627130 -0400
>      +++ m_think.vhd 2013-09-05 08:37:51.481874280 -0400
>      @@ -6,6 +6,7 @@
>
>       package pck_m_think is
>
>      +attribute enum_encoding: string;
>           type t_enum_states_1 is (
>           IDLE,
>           THINK,
>

I don't recall all the VHDL rules here off the top
of my head.  I can test with some synthesis tools
as well and do some research.  It is a small change
that can probably be added, but I have to do some
inquiring before I create a pull-request.

Best I can tell adding

     attribute enum_encoding: string

should be harmless, just an additional attribute
http://quartushelp.altera.com/11.1/mergedProjects/hdl/vhdl/vhdl_file_dir_enum_encoding.htm

Regards,
Chris

Re: [myhdl-list] attribute enum_encoding: string;

[David H. <da...@ad...>]

On Thu, Sep 05, 2013 at 06:03:33AM -0500, Christopher Felton wrote:
> On 9/4/13 11:26 PM, David Holl wrote:
> > But it still triggers the "no declaration" error in ghdl when I specify encoding='one_hot' for states:
> > ...
> I have updated the example, for me I don't get the error, here is a snip of the converted code
> 
>      type t_enum_states_1 is (
>          IDLE,
>          THINK,
>          SEND_CMD,
>          ADVANCE
>      );
>      attribute enum_encoding of t_enum_states_1: type is "0001 0010 0100 1000";

hrm --- Yep, that's the code that I'm also generating.

>     >> ghdl -a pck_myhdl_09.vhd m_think.vhd
>     >> ghdl -e m_think
>     >> ghdl -r m_think

But "ghdl -a ..." still complains unless I patch m_think.vhd to add "attribute enum_encoding: string;"

    tensor(pts/0):~/m_think> diff -u m_think.vhd.orig m_think.vhd
    --- m_think.vhd.orig    2013-09-05 08:31:50.002627130 -0400
    +++ m_think.vhd 2013-09-05 08:37:51.481874280 -0400
    @@ -6,6 +6,7 @@
     
     package pck_m_think is
     
    +attribute enum_encoding: string;
         type t_enum_states_1 is (
         IDLE,
         THINK,

> The version of GHDL I am using:
>      ghdl -v
>      GHDL 0.29 (20100109) [Sokcho edition]
>       Compiled with GNAT Version: 4.4.0 20080314 (experimental)
>       mcode code generator
>      Written by Tristan Gingold

I'm using ghdl from Debian's package repository ("jessie" aka "testing").  It looks like a similar version to yours with differences in the GNAT version and code generator.

    tensor(pts/0):~/m_think> ghdl -v
    GHDL 0.29 (20100109) [Sokcho edition]
     Compiled with GNAT Version: 4.4.4
     GCC back-end code generator
    Written by Tristan Gingold.

Re: [myhdl-list] MyHDL : The Case for a Better HDL

[Christopher F. <chr...@gm...>]

On 8/26/2013 5:04 PM, Jonas wrote:
> Christopher Felton <chris.felton <at> gmail.com> writes:
>
>> For more information on the first topic, see Jan's "These Ints are Made
>> For Countin'" essay http://jandecaluwe.com/hdldesign/counting.html.
>
>> For me, the "RTL abstraction" section touched on some important points.
>>    How do you effectively teach complex digital systems architecture and
>> implementation (HDL) and the low-level digital circuits?  I see this as
>> a failure in the current education sytle.  We teach the digital systems
>> and HDL the same as the digital circuits, from the bottom-up.  Even
>> folks that are teaching themselves HDL appear to fall into folly.
>
> I was working with VHDL a while ago. I liked a lot the very flexible type
> system and the philosophy about code readability even if it results in more
> typing. All those good features comes from Ada, on which VHDL was greatly
> inspired. From all the languages I know, I see Ada as the best source of
> inpiration for an HDL, because you could have a very flexible language with
> high level constructs (for each loops, array slicing, attributes, ...), but
> with the possibility of specifying low level details.

I believe Jan D. has similar views, see the Ada
reference in the /modbv/ MEP:
http://myhdl.org/doku.php/meps:mep-106

<snip>
>
> A bigger reason of my bad experience with VHDL, was the persistant mentality
> among the community of VHDL to think low level only, even in situation when
> thinking high level makes a lot more sense.

Amen, your preaching to the choir!  Emphasis on
the *only*.  Need to navigate the trees and the
forest.

>That leaded to absurd and
> outdated coding standards like transforming everything to std_logic or
> std_logic_vector in the ports of entities (including unsigned/signed signals
> although they are represented exactly the same way as std_logic_vector)
> instead of keeping the higher level types, which makes it harder to read and
> more error prone. And those coding standards gets imposed upon you but
> nobody can tell you why. All you hear is something like "the VHDL experts
> told that it has to be done that way".
>

The infamous "experts" :)

> Even if it sounds weird to me to use python to do HDL, at least I like the
> idea of bringing modern ideas and a different mentality in the HDL community.
>

One thing you probably (I stand on limbs) don't find
absurd, is the use of a high-level language for modeling
and verification.  The use of Python for digital system
modeling and verification is very nice, very nice.  And
it is a bonus

Regards,
Chris

Re: [myhdl-list] attribute enum_encoding: string;

[Christopher F. <chr...@gm...>]

On 9/5/2013 6:20 AM, Angel Ezquerra wrote:
> My point was that perhaps calling MyHDL enums "enum" which is a
> builtin type in Python 3.4 (I believe!) may cause trouble long term,
> since it may require having to modify existing MyHDL files.
>
> Cheers,
>
> Angel
>

I am sure there are other projects that will have
to deal with the /enum/ collision(?).  I don't think
we would want to discourage the use of the myhdl.enum.

It shouldn't be an issue with existing or developing code,
it is assumed they are not using the py3.enum, the myhdl.enum
will be in the namespace.  The only issue would be if
someone wanted to update old code with py3.enum in the future,
I think is highly unlikely.

Regards,
Chris

> On Thu, Sep 5, 2013 at 1:06 PM, Christopher Felton
> <chr...@gm...> wrote:
>> On 9/4/13 11:49 PM, Angel Ezquerra wrote:
>>> Chris,
>>>
>>> I have not followed this in much detail so please excuse me if this is
>>> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get
>>> a builtin enum class. I think we should make sure that we make it
>>> possible to use it if MyHDL is ever ported to Python 3.
>>>
>>> Cheers,
>>>
>>> Angel
>>>
>>>
>>
>> Yes, the "enum" is from the MyHDL package.  Something might
>> need to be done to be compatible with the latest version of
>> Python 3 when we get there :)
>>
>> Regards,
>> Chris
>>
>>

Re: [myhdl-list] fixed-point thoughts : part two

[Christopher F. <chr...@gm...>]

On 9/5/13 12:05 AM, Angel Ezquerra wrote:
<snip>
>>
>> The proposed *resized* function will look like:
>>
>>       resize(val,format
>>               [,round_mode='convergent']
>>               [,overflow_mode='saturate'])
>>
>> Example:
>>
>>       z[:] = resize(x+y,z)
>
> Probably a basic question, but why do you need [:] here? Doesn't
> resize return a fixbv?
>

The *resize* function will return an /int/ the same
as the /intbv/ operations and the /fixbv/ operations.
The "[:]" is used because we really want to update the
value of /z/ and not have /z/ reference a different object.

This needs to be done: first, so it can be converted.  For
modeling only, we could be a little more flexible but then ...

Second, the bound checking would not be possible.

Typically, what you would see is:

     x = Signal(fixbv(0, min=-1, max=1, res=.125))
     y = Signal(fixbv(.25, min=-1, max=1, res=.125))
     z = Signal(fixbv(0, min=-1, max=1, res=.125))

     @always_seq(clock.posedge, reset=reset)
     def logic():
         z.next = resize(x+y,z)

As an object the /fixbv/ would work like the /intbv/.

> Also, I don't think there is a way for Python to pass the resize
> function z's size while using the assignment syntax. If there was
> resize() would not need the second parameter, which would be cool.
> Maybe the converter could know though... An alternative could be to
> add a "set" or "assign" method to the fixbv class. This method would
> be equivalent to a resize followed by an assignment? The result would
> be:
>
>      z.assign(x+y)
>
> Which would get rid of the need to use [:] (if there is any) and to
> use z both as a parameter to resize and as its output.
>

As mentioned, for /intbv/ and I would imagine with the /fixbv/
the bit assignment would not be used frequently, it commonly
would be handled by Signal assignments.

If you are using the /intbv/ and /fixbv/ for some modeling or
nonlocal variable, and a property/attribute is more Pythonic
than "[:]" we could propose a *val* public property that updates
/_val/ attribute and calls the check bounds.

     z.val = resize(x+y)

This would be consistent with the /Signal/.  If this change
was desired it would be made to the /intbv/ and the /fixbv/,
for now "[:]" will be used in the /fixbv/.

Regards,
Chris

Re: [myhdl-list] attribute enum_encoding: string;

[Angel E. <ang...@gm...>]

My point was that perhaps calling MyHDL enums "enum" which is a
builtin type in Python 3.4 (I believe!) may cause trouble long term,
since it may require having to modify existing MyHDL files.

Cheers,

Angel

On Thu, Sep 5, 2013 at 1:06 PM, Christopher Felton
<chr...@gm...> wrote:
> On 9/4/13 11:49 PM, Angel Ezquerra wrote:
>> Chris,
>>
>> I have not followed this in much detail so please excuse me if this is
>> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get
>> a builtin enum class. I think we should make sure that we make it
>> possible to use it if MyHDL is ever ported to Python 3.
>>
>> Cheers,
>>
>> Angel
>>
>>
>
> Yes, the "enum" is from the MyHDL package.  Something might
> need to be done to be compatible with the latest version of
> Python 3 when we get there :)
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
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> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
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Re: [myhdl-list] attribute enum_encoding: string;

[Christopher F. <chr...@gm...>]

On 9/4/13 11:49 PM, Angel Ezquerra wrote:
> Chris,
>
> I have not followed this in much detail so please excuse me if this is
> obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get
> a builtin enum class. I think we should make sure that we make it
> possible to use it if MyHDL is ever ported to Python 3.
>
> Cheers,
>
> Angel
>
>

Yes, the "enum" is from the MyHDL package.  Something might
need to be done to be compatible with the latest version of
Python 3 when we get there :)

Regards,
Chris

Re: [myhdl-list] attribute enum_encoding: string;

[Christopher F. <chr...@gm...>]

On 9/4/13 11:26 PM, David Holl wrote:
> Thank you for looking into it Chris. Â I confirm that the example code
> you sent works correctly with ghdl.
>
> But it still triggers the "no declaration" error in ghdl when I
> specify encoding='one_hot' for states:
>
> tensor(pts/0):~/m_think> diff old/m_think.py new/m_think.py
> 5c5
> < Â  Â  states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
> ---
>  > Â  Â  states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE',
> encoding='one_hot')
>

Sorry for the confusion, yes I forgot to add the "encoding='one_hot'".

I have updated the example, for me I don't get the error, here
is a snip of the converted code

     type t_enum_states_1 is (
         IDLE,
         THINK,
         SEND_CMD,
         ADVANCE
     );
     attribute enum_encoding of t_enum_states_1: type is "0001 0010 0100 
1000";

    >> ghdl -a pck_myhdl_09.vhd m_think.vhd
    >> ghdl -e m_think
    >> ghdl -r m_think

The version of GHDL I am using:
     ghdl -v
     GHDL 0.29 (20100109) [Sokcho edition]
      Compiled with GNAT Version: 4.4.0 20080314 (experimental)
      mcode code generator
     Written by Tristan Gingold

I update the exampe:
https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py

Regards,
Chris

>
> tensor(pts/0):~/m_think> python m_think.pyÂ
> ** ToVHDLWarning: Output port is read internally: sent
> tensor(pts/0):~/m_think> ghdl -a pck_myhdl_08.vhd m_think.vhd     Â
> Â  Â  Â  Â  Â  Â  Â  Â  Â
> m_think.vhd:15:11: no declaration for "enum_encoding"
> /usr/lib/ghdl/bin/ghdl: compilation error
> tensor(pts/0):~/m_think> echo $?
> 1
>
> I've attached the modify python code and generated vhdl.
>
> Thank you,
> David
>
>
> On Wed, Sep 4, 2013 at 10:57 PM, Christopher Felton
> <chr...@gm... <mailto:chr...@gm...>> wrote:
>
>     The following works without issue:
>
>     Â  Â  Â from myhdl import *
>
>     Â  Â  Â def m_think(clock,reset,thinking,sending,sent):
>
>     Â  Â  Â  Â  Â states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
>     Â  Â  Â  Â  Â state = Signal(states.IDLE)
>
>     Â  Â  Â  Â  Â @always_seq(clock.posedge, reset=reset)
>     Â  Â  Â  Â  Â def rtl():
>     Â  Â  Â  Â  Â  Â  Â thinking.next = False
>     Â  Â  Â  Â  Â  Â  Â sending.next = False
>     Â  Â  Â  Â  Â  Â  Â if state == states.IDLE:
>     Â  Â  Â  Â  Â  Â  Â  Â  Â state.next = states.THINK
>     Â  Â  Â  Â  Â  Â  Â elif state == states.THINK:
>     Â  Â  Â  Â  Â  Â  Â  Â  Â thinking.next = True
>     Â  Â  Â  Â  Â  Â  Â  Â  Â state.next = states.SEND_CMD
>     Â  Â  Â  Â  Â  Â  Â elif state == states.SEND_CMD:
>     Â  Â  Â  Â  Â  Â  Â  Â  Â sending.next = True
>     Â  Â  Â  Â  Â  Â  Â  Â  Â state.next = states.ADVANCE
>     Â  Â  Â  Â  Â  Â  Â elif state == states.ADVANCE:
>     Â  Â  Â  Â  Â  Â  Â  Â  Â sent.next = sent+1
>     Â  Â  Â  Â  Â  Â  Â  Â  Â state.next = states.IDLE
>     Â  Â  Â  Â  Â  Â  Â else:
>     Â  Â  Â  Â  Â  Â  Â  Â  Â assert False, "Invalid states %s"%(state)
>
>     Â  Â  Â  Â  Â return rtl
>
>     Â  Â  Â def convert():
>     Â  Â  Â  Â  Â clock = Signal(bool(0))
>     Â  Â  Â  Â  Â reset = ResetSignal(0,active=0,async=True)
>     Â  Â  Â  Â  Â thinking = Signal(bool(0))
>     Â  Â  Â  Â  Â sending = Signal(bool(0))
>     Â  Â  Â  Â  Â sent = Signal(intbv(0,min=0,max=10e12))
>
>     Â  Â  Â  Â  Â toVHDL(m_think,clock,reset,thinking,sending,sent)
>
>     Â  Â  Â if __name__ == '__main__':
>     Â  Â  Â  Â  Â convert()
>
>     Â  Â  >> ghdl -a pck_myhdl_09.vhd m_think.vhd
>     Â  Â  >> ghdl -e m_think
>
>     https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py?at=default
>
>     Note, I didn't test that the above example worked
>     functionally. Â I just put it together to demonstrate
>     the "enum" type in VHDL is working. Â In addition I am
>     using a development snapshot but there hasn't been any
>     changes in this area in the development, it is identical
>     to the 0.8.
>
>     Regards,
>     Chris
>
>     On 9/3/13 2:48 PM, David Holl wrote:
>      > Hello, When using ghdl for syntax checks, I get the following
>     error for
>      > any state machine where encoding="one_hot":
>      > pcie_drx.vhd:137:11: no declaration for "enum_encoding"
>      >
>      > I can resolve ghdl's complaints by adding
>      > Â  attribute enum_encoding: string;
>      > to the generated .vhd file.
>      >
>      > Is there a way to have this line included automatically in .vhd
>     output?
>      > Â I could add it via a shell script, but I'm wondering if there is
>      > "better way" to do it. Â (or is GHDL in error?)
>      >
>      >
>      > For example, here is an trimmed-down excerpt from the top of the .vhd
>      > file showing where I add the line:
>      >
>      > Â  Â  package pck_pcie_drx is
>      >     Â  Â  attribute enum_encoding: string; Â <--- I need
>     to add this line.
>      >
>      >     Â  Â  type t_enum_t_state_22 is (
>      >
>      >     Â  Â  IDLE,
>      >
>      >     Â  Â  THINK,
>      >
>      >     Â  Â  SEND_CMD,
>      >
>      >     Â  Â  ADVANCE
>      >
>      > Â  Â  );
>      >
>      > Â  Â  attribute enum_encoding of t_enum_t_state_22: type is "0001
>     0010
>      > Â  Â  0100 1000";
>      >
>      >     Â  Â  type t_enum_t_state_23 is (
>      >     Â  Â  CMD,
>      >     Â  Â  MWR_H0H1,
>      >     Â  Â  MWR32_H2D0,
>      >     Â  Â  MWR32_D1D2,
>      >     Â  Â  MWR32_D3XX,
>      >     Â  Â  MWR64_H2H3,
>      >     Â  Â  MWR64_D0D1,
>      >     Â  Â  DROP
>      > Â  Â  );
>      > Â  Â  attribute enum_encoding of t_enum_t_state_23: type is "00000001
>      > Â  Â  00000010 00000100 00001000 00010000 00100000 01000000
>     10000000";
>      > Â  Â  end package pck_pcie_drx;
>      > Â  Â  library IEEE;
>      > Â  Â  etc...
>      >
>      >
>      >
>      >
>      > - David
>      > Â  ps: Â Thank you for the fantastic MyHDL.
>      >
>      >
>      >
>      >
>     ------------------------------------------------------------------------------
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>      >
>
>
>
>     ------------------------------------------------------------------------------
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Re: [myhdl-list] fixed-point thoughts : part two

[Angel E. <ang...@gm...>]

Chris,

very nice wrap up. You have a very easy to follow writing style :-)
I have a couple of very smalll comments. See below:

On Thu, Sep 5, 2013 at 5:28 AM, Christopher Felton
<chr...@gm...> wrote:
>
> In part one I discussed fixed-point representation and introduced
> /fixbv/ construction.  Representation is only part of the fixed-point
> functionality.  In this conversation fixed-point operations and the
> proposed *resize* function will be discussed.
>
> First, lets review fixed-point mathematics, given two fixed-point
> variables, /x/ and /y/:
>
>      x = fixbv(0, min=-8, max=8, res=1/16)   # siii.ffff
>      y = fixbv(0, min=-1, max=1, rest=1/128) # s.fffffff
>
> Addition and subtraction require the operands to be aligned,
> they don't necessarily need to be the same word-length (wl) but
> the "point" needs to be aligned, using the above as operands:
>
>      siii.ffff000
>    + ssss.fffffff
>    --------------
>     siiii.fffffff
>
> once the operands are aligned normal 2's complement addition/
> subtraction can be performed.  The maximum result would be
> 2*max(x.max,y.max) (or max(len(x),len(y))+1).  If addition or
> subtraction is attempted and the values are not aligned an error
> will be thrown, example:
>
>      >>> x = fixbv(0,min=-8,max=8,res=1/16.)
>      >>> y = fixbv(0,min=-1,max=1,res=1/128.)
>      >>> x + y
>      AssertionError: Add: points not aligned
>             fixbv(0.00, format=(8,3,4), ) and fixbv(0.00, format=(8,0,7), )

Personally I'd say "decimal points", i.e.:

"AssertionError: Add: points not aligned"

Or even:

"AssertionError: Add: points not aligned in fixed point operation"

> It is assumed the /fixbv/ operations will actually return an
> /int/ same as /intbv/ operations
>
>      >>> x1 = fixbv(2.5,min=-8,max=8,res=1/16.)
>      >>> x2 = fixbv(1.25,min=-8,max=8,res=1/16.)
>      >>> x1 + x2
>      15
>
> When assigned to another /fixbv/ the value will fit in the
> format of the accepting object.
>
>      >>> x1 = fixbv(2.5,min=-8,max=8,res=1/16.)
>      >>> x2 = fixbv(1.25,min=-8,max=8,res=1/16.)
>      >>> z = fixbv(0,min=-16,max=16,res=1/16.)
>      >>> z[:] = x1 + x2
>      fixbv(3.75, format=(9,4,4))

It seems a bit easy to forget the [:], but I guess that is the same as
in the original intbv...

> For multiplication the operands do not need to be aligned before
> the operation but the "point" bookkeeping needs to be accounted
>
>            siii.ffff
>    *       s.fffffff
>    -----------------
>    ssiii.fffffffffff  (total 16 bits)
>
> An example using the example operands:
>
>      >>> x = fixbv(1.5,min=-8,max=8,res=1/16.)
>      >>> y = fixbv(0.25,min=-1,max=1,res=1/128.)
>      >>> myhdl.bin(x*y, 16)
>      '00000.01100000000'  # 3/2*1/4 = 3/8 = 1/4+1/8
>
> The basic mathematical operations have been reviewed, we will
> exclude division for now because we can achieve "division"
> by multiplying by the fractional parts.
>
> The next topic: rounding and overflow handling.  During operations
> it is common not to maintain the maximum word-length through out a
> chain of operations.  When reducing the word-length rounding and
> overflow come into play.
>
> Example, multiplying two numbers requires len(x)+len(y) bits or
> x.max*y.max range.  It is typical for the result to be *resized*
> after an operation.  In the previous multiply example, it may be
> desired to only preserve four fraction bits:
>
>      ssiii.ffff ffff fff
>                 ~~~~~~~~ <- these bits remove
>
> The remaining bits will be rounded based on the removed bits,
> there are different rounding methods that can be used.  This is
> a base feature of a fixed-point package.  Also, when resizing
> overflow (underflow) is also an issue.  If the value being
> resized does not fit, it needs to be saturated or wrapped.
>
> As eluded, the *resize* function is essential, the resize function
> will need to be a convertible function.  Logic will need to
> be created to handle the rounding and overflow.
>
> The proposed *resized* function will look like:
>
>      resize(val,format
>              [,round_mode='convergent']
>              [,overflow_mode='saturate'])
>
> Example:
>
>      z[:] = resize(x+y,z)

Probably a basic question, but why do you need [:] here? Doesn't
resize return a fixbv?

Also, I don't think there is a way for Python to pass the resize
function z's size while using the assignment syntax. If there was
resize() would not need the second parameter, which would be cool.
Maybe the converter could know though... An alternative could be to
add a "set" or "assign" method to the fixbv class. This method would
be equivalent to a resize followed by an assignment? The result would
be:

    z.assign(x+y)

Which would get rid of the need to use [:] (if there is any) and to
use z both as a parameter to resize and as its output.

Cheers,

Angel

Re: [myhdl-list] attribute enum_encoding: string;

[Angel E. <ang...@gm...>]

Chris,

I have not followed this in much detail so please excuse me if this is
obvious: Is this "enum" a MyHDL class? I ask because Python 3 will get
a builtin enum class. I think we should make sure that we make it
possible to use it if MyHDL is ever ported to Python 3.

Cheers,

Angel


On Thu, Sep 5, 2013 at 4:57 AM, Christopher Felton
<chr...@gm...> wrote:
> The following works without issue:
>
>      from myhdl import *
>
>      def m_think(clock,reset,thinking,sending,sent):
>
>          states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
>          state = Signal(states.IDLE)
>
>          @always_seq(clock.posedge, reset=reset)
>          def rtl():
>              thinking.next = False
>              sending.next = False
>              if state == states.IDLE:
>                  state.next = states.THINK
>              elif state == states.THINK:
>                  thinking.next = True
>                  state.next = states.SEND_CMD
>              elif state == states.SEND_CMD:
>                  sending.next = True
>                  state.next = states.ADVANCE
>              elif state == states.ADVANCE:
>                  sent.next = sent+1
>                  state.next = states.IDLE
>              else:
>                  assert False, "Invalid states %s"%(state)
>
>          return rtl
>
>      def convert():
>          clock = Signal(bool(0))
>          reset = ResetSignal(0,active=0,async=True)
>          thinking = Signal(bool(0))
>          sending = Signal(bool(0))
>          sent = Signal(intbv(0,min=0,max=10e12))
>
>          toVHDL(m_think,clock,reset,thinking,sending,sent)
>
>      if __name__ == '__main__':
>          convert()
>
>     >> ghdl -a pck_myhdl_09.vhd m_think.vhd
>     >> ghdl -e m_think
>
> https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py?at=default
>
> Note, I didn't test that the above example worked
> functionally.  I just put it together to demonstrate
> the "enum" type in VHDL is working.  In addition I am
> using a development snapshot but there hasn't been any
> changes in this area in the development, it is identical
> to the 0.8.
>
> Regards,
> Chris
>
> On 9/3/13 2:48 PM, David Holl wrote:
>> Hello, When using ghdl for syntax checks, I get the following error for
>> any state machine where encoding="one_hot":
>> pcie_drx.vhd:137:11: no declaration for "enum_encoding"
>>
>> I can resolve ghdl's complaints by adding
>> Â  attribute enum_encoding: string;
>> to the generated .vhd file.
>>
>> Is there a way to have this line included automatically in .vhd output?
>> Â I could add it via a shell script, but I'm wondering if there is
>> "better way" to do it. Â (or is GHDL in error?)
>>
>>
>> For example, here is an trimmed-down excerpt from the top of the .vhd
>> file showing where I add the line:
>>
>>     package pck_pcie_drx is
>>     Â  Â  attribute enum_encoding: string; Â <--- I need to add this line.
>>
>>     Â  Â  type t_enum_t_state_22 is (
>>
>>     Â  Â  IDLE,
>>
>>     Â  Â  THINK,
>>
>>     Â  Â  SEND_CMD,
>>
>>     Â  Â  ADVANCE
>>
>>     );
>>
>>     attribute enum_encoding of t_enum_t_state_22: type is "0001 0010
>>     0100 1000";
>>
>>     Â  Â  type t_enum_t_state_23 is (
>>     Â  Â  CMD,
>>     Â  Â  MWR_H0H1,
>>     Â  Â  MWR32_H2D0,
>>     Â  Â  MWR32_D1D2,
>>     Â  Â  MWR32_D3XX,
>>     Â  Â  MWR64_H2H3,
>>     Â  Â  MWR64_D0D1,
>>     Â  Â  DROP
>>     );
>>     attribute enum_encoding of t_enum_t_state_23: type is "00000001
>>     00000010 00000100 00001000 00010000 00100000 01000000 10000000";
>>     end package pck_pcie_drx;
>>     library IEEE;
>>     etc...
>>
>>
>>
>>
>> - David
>> Â  ps: Â Thank you for the fantastic MyHDL.
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
>> Discover the easy way to master current and previous Microsoft technologies
>> and advance your career. Get an incredible 1,500+ hours of step-by-step
>> tutorial videos with LearnDevNow. Subscribe today and save!
>> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] Keep hierarchy in VHDL conversion

[Keerthan jai.c <jck...@gm...>]

>This is definitely a plus but it is only a partial plus
>in MyHDL's case.  To do full regression-testing on any
>pull requests you would need a verilog and vhdl simulators.

We won't be able to use modelsim but we can certainly use icarus and ghdl
on travis.


On Wed, Sep 4, 2013 at 10:14 PM, Christopher Felton
<chr...@gm...>wrote:

> On 9/4/13 2:12 PM, Keerthan jai.c wrote:
> > Since I am not an expert on either git or hg, I won't comment on the
> > technical aspects. However I think that github is a better place to host
> > the main myhdl repo.
> >
> > Reasons why I think we should switch to github:
> > 1) Hosting myhdl on github will improve the visibility of the project,
> > and more people will contribute.
> > see
> >
> http://eli.thegreenplace.net/2013/06/09/switching-my-open-source-projects-from-bitbucket-to-github/
> >
>
> My personal experience is: this is not true.  I have
> projects on github and bitbucket.  Simply being on
> github, I don't see any evidence of increased visibility,
> etc.
>
> There are counter anecdotes with pypy, sphinx, etc on
> bitbucket - successful projects (high visibility).  I think
> there are other factors, not simply being hosted on X or Y.
>
> > 2) Github is arguably a better/more poular platform.
> > For example, travis-ci(continuous integration) supports github but not
> > bitbucket. While there are alternatives to travis-ci, none of the free
> > ones are as good.
> > You can check out the UI of travis-ci here:
> > https://travis-ci.org/kennethreitz/requests
> >
> > travis-ci is deeply integrated with github, this makes the process of
> > pull requests way simpler.
> > If travis is configured(a simple yml file in the repository root),
> > travis automatically runs tests on all commits and pull requests. From
> > the github pull requests page, you can see if tests passed/failed. And
> > additionally, get details about failed tests.
> > This is how it looks:
> > tests passed:
> > http://danlimerick.files.wordpress.com/2013/02/safetomergeprtravis.png
> > tests failed:
> > http://danlimerick.files.wordpress.com/2013/02/failedprtravis.png
> >
>
> This is definitely a plus but it is only a partial plus
> in MyHDL's case.  To do full regression-testing on any
> pull requests you would need a verilog and vhdl simulators.
>
> >
> > Thanks to this, users can submit quick bugfixes as pull requests and the
> > repo owner can accept pull requests without worrying too much(or without
> > pulling changes and running tests) if tests pass.
> > I imagine bugs like these: (
> >
> https://bitbucket.org/jandecaluwe/myhdl/issue/3/always_seq-decorator-error-message-string
> > ) would be handled much quicker.
> >
> > Additionally, github's UI makes it easy to see what other contributors
> > are up to, this makes it easier to co-ordinate and might make some
> > people more confident about contributing.
> > see:
> https://github.com/blog/39-say-hello-to-the-network-graph-visualizer
> >
> > 3) git and hg workflows aren't too different. hg users will not have too
> > much trouble contributing to git repos. Additionally, there are tools
> > like hg-git which allow you to use hg locally while contributing to a
> > git remote.
> > http://hg-git.github.io/
> >
>
> If hg-git works nice, there could be a mirror on github
> (note someone already created a mirror on github).  I have
> not been able to get hg-git to work.  I am moving some of my
> github projects to bitbucket because I don't see any benefit
> of having them on github (exception travis-ci).
>
> I think we have hashed through this topic, I don't know if the
> travis-ci is enough to overturn the inertia.
>
> Regards,
> Chris
>
>
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58041391&iu=/4140/ostg.clktrk
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

[myhdl-list] fixed-point thoughts : part two

[Christopher F. <chr...@gm...>]

In part one I discussed fixed-point representation and introduced
/fixbv/ construction.  Representation is only part of the fixed-point
functionality.  In this conversation fixed-point operations and the
proposed *resize* function will be discussed.

First, lets review fixed-point mathematics, given two fixed-point
variables, /x/ and /y/:

     x = fixbv(0, min=-8, max=8, res=1/16)   # siii.ffff
     y = fixbv(0, min=-1, max=1, rest=1/128) # s.fffffff

Addition and subtraction require the operands to be aligned,
they don't necessarily need to be the same word-length (wl) but
the "point" needs to be aligned, using the above as operands:

     siii.ffff000
   + ssss.fffffff
   --------------
    siiii.fffffff

once the operands are aligned normal 2's complement addition/
subtraction can be performed.  The maximum result would be
2*max(x.max,y.max) (or max(len(x),len(y))+1).  If addition or
subtraction is attempted and the values are not aligned an error
will be thrown, example:

     >>> x = fixbv(0,min=-8,max=8,res=1/16.)
     >>> y = fixbv(0,min=-1,max=1,res=1/128.)
     >>> x + y
     AssertionError: Add: points not aligned
            fixbv(0.00, format=(8,3,4), ) and fixbv(0.00, format=(8,0,7), )

It is assumed the /fixbv/ operations will actually return an
/int/ same as /intbv/ operations

     >>> x1 = fixbv(2.5,min=-8,max=8,res=1/16.)
     >>> x2 = fixbv(1.25,min=-8,max=8,res=1/16.)
     >>> x1 + x2
     15

When assigned to another /fixbv/ the value will fit in the
format of the accepting object.

     >>> x1 = fixbv(2.5,min=-8,max=8,res=1/16.)
     >>> x2 = fixbv(1.25,min=-8,max=8,res=1/16.)
     >>> z = fixbv(0,min=-16,max=16,res=1/16.)
     >>> z[:] = x1 + x2
     fixbv(3.75, format=(9,4,4))

For multiplication the operands do not need to be aligned before
the operation but the "point" bookkeeping needs to be accounted

           siii.ffff
   *       s.fffffff
   -----------------
   ssiii.fffffffffff  (total 16 bits)

An example using the example operands:

     >>> x = fixbv(1.5,min=-8,max=8,res=1/16.)
     >>> y = fixbv(0.25,min=-1,max=1,res=1/128.)
     >>> myhdl.bin(x*y, 16)
     '00000.01100000000'  # 3/2*1/4 = 3/8 = 1/4+1/8

The basic mathematical operations have been reviewed, we will
exclude division for now because we can achieve "division"
by multiplying by the fractional parts.

The next topic: rounding and overflow handling.  During operations
it is common not to maintain the maximum word-length through out a
chain of operations.  When reducing the word-length rounding and
overflow come into play.

Example, multiplying two numbers requires len(x)+len(y) bits or
x.max*y.max range.  It is typical for the result to be *resized*
after an operation.  In the previous multiply example, it may be
desired to only preserve four fraction bits:

     ssiii.ffff ffff fff
                ~~~~~~~~ <- these bits remove

The remaining bits will be rounded based on the removed bits,
there are different rounding methods that can be used.  This is
a base feature of a fixed-point package.  Also, when resizing
overflow (underflow) is also an issue.  If the value being
resized does not fit, it needs to be saturated or wrapped.

As eluded, the *resize* function is essential, the resize function
will need to be a convertible function.  Logic will need to
be created to handle the rounding and overflow.

The proposed *resized* function will look like:

     resize(val,format
             [,round_mode='convergent']
             [,overflow_mode='saturate'])

Example:

     z[:] = resize(x+y,z)

The above will resize the result of /x+y/ to the format of the
/z/ fixbv variable (note x and y need to be aligned or resized
before the operation).

This conversation reviewed fixed-point operations, how the
proposed /fixbv/ handles unalignment, and bounds.  Finally, the
*resize* function was introduced.  The next part will cover the
implementation details of the *resize* function and implications.

Regards,
Chris Felton

Re: [myhdl-list] attribute enum_encoding: string;

[Christopher F. <chr...@gm...>]

The following works without issue:

     from myhdl import *

     def m_think(clock,reset,thinking,sending,sent):

         states = enum('IDLE', 'THINK', 'SEND_CMD', 'ADVANCE')
         state = Signal(states.IDLE)

         @always_seq(clock.posedge, reset=reset)
         def rtl():
             thinking.next = False
             sending.next = False
             if state == states.IDLE:
                 state.next = states.THINK
             elif state == states.THINK:
                 thinking.next = True
                 state.next = states.SEND_CMD
             elif state == states.SEND_CMD:
                 sending.next = True
                 state.next = states.ADVANCE
             elif state == states.ADVANCE:
                 sent.next = sent+1
                 state.next = states.IDLE
             else:
                 assert False, "Invalid states %s"%(state)

         return rtl

     def convert():
         clock = Signal(bool(0))
         reset = ResetSignal(0,active=0,async=True)
         thinking = Signal(bool(0))
         sending = Signal(bool(0))
         sent = Signal(intbv(0,min=0,max=10e12))

         toVHDL(m_think,clock,reset,thinking,sending,sent)

     if __name__ == '__main__':
         convert()

    >> ghdl -a pck_myhdl_09.vhd m_think.vhd
    >> ghdl -e m_think

https://bitbucket.org/cfelton/examples/src/tip/state_machines/example1.py?at=default

Note, I didn't test that the above example worked
functionally.  I just put it together to demonstrate
the "enum" type in VHDL is working.  In addition I am
using a development snapshot but there hasn't been any
changes in this area in the development, it is identical
to the 0.8.

Regards,
Chris

On 9/3/13 2:48 PM, David Holl wrote:
> Hello, When using ghdl for syntax checks, I get the following error for
> any state machine where encoding="one_hot":
> pcie_drx.vhd:137:11: no declaration for "enum_encoding"
>
> I can resolve ghdl's complaints by adding
> Â  attribute enum_encoding: string;
> to the generated .vhd file.
>
> Is there a way to have this line included automatically in .vhd output?
> Â I could add it via a shell script, but I'm wondering if there is
> "better way" to do it. Â (or is GHDL in error?)
>
>
> For example, here is an trimmed-down excerpt from the top of the .vhd
> file showing where I add the line:
>
>     package pck_pcie_drx is
>     Â  Â  attribute enum_encoding: string; Â <--- I need to add this line.
>
>     Â  Â  type t_enum_t_state_22 is (
>
>     Â  Â  IDLE,
>
>     Â  Â  THINK,
>
>     Â  Â  SEND_CMD,
>
>     Â  Â  ADVANCE
>
>     );
>
>     attribute enum_encoding of t_enum_t_state_22: type is "0001 0010
>     0100 1000";
>
>     Â  Â  type t_enum_t_state_23 is (
>     Â  Â  CMD,
>     Â  Â  MWR_H0H1,
>     Â  Â  MWR32_H2D0,
>     Â  Â  MWR32_D1D2,
>     Â  Â  MWR32_D3XX,
>     Â  Â  MWR64_H2H3,
>     Â  Â  MWR64_D0D1,
>     Â  Â  DROP
>     );
>     attribute enum_encoding of t_enum_t_state_23: type is "00000001
>     00000010 00000100 00001000 00010000 00100000 01000000 10000000";
>     end package pck_pcie_drx;
>     library IEEE;
>     etc...
>
>
>
>
> - David
> Â  ps: Â Thank you for the fantastic MyHDL.
>
>
>
> ------------------------------------------------------------------------------
> Learn the latest--Visual Studio 2012, SharePoint 2013, SQL 2012, more!
> Discover the easy way to master current and previous Microsoft technologies
> and advance your career. Get an incredible 1,500+ hours of step-by-step
> tutorial videos with LearnDevNow. Subscribe today and save!
> http://pubads.g.doubleclick.net/gampad/clk?id=58040911&iu=/4140/ostg.clktrk
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Keep hierarchy in VHDL conversion

[Christopher F. <chr...@gm...>]

On 9/4/13 2:12 PM, Keerthan jai.c wrote:
> Since I am not an expert on either git or hg, I won't comment on the
> technical aspects. However I think that github is a better place to host
> the main myhdl repo.
>
> Reasons why I think we should switch to github:
> 1) Hosting myhdl on github will improve the visibility of the project,
> and more people will contribute.
> see
> http://eli.thegreenplace.net/2013/06/09/switching-my-open-source-projects-from-bitbucket-to-github/
>

My personal experience is: this is not true.  I have
projects on github and bitbucket.  Simply being on
github, I don't see any evidence of increased visibility,
etc.

There are counter anecdotes with pypy, sphinx, etc on
bitbucket - successful projects (high visibility).  I think
there are other factors, not simply being hosted on X or Y.

> 2) Github is arguably a better/more poular platform.
> For example, travis-ci(continuous integration) supports github but not
> bitbucket. While there are alternatives to travis-ci, none of the free
> ones are as good.
> You can check out the UI of travis-ci here:
> https://travis-ci.org/kennethreitz/requests
>
> travis-ci is deeply integrated with github, this makes the process of
> pull requests way simpler.
> If travis is configured(a simple yml file in the repository root),
> travis automatically runs tests on all commits and pull requests. From
> the github pull requests page, you can see if tests passed/failed. And
> additionally, get details about failed tests.
> This is how it looks:
> tests passed:
> http://danlimerick.files.wordpress.com/2013/02/safetomergeprtravis.png
> tests failed:
> http://danlimerick.files.wordpress.com/2013/02/failedprtravis.png
>

This is definitely a plus but it is only a partial plus
in MyHDL's case.  To do full regression-testing on any
pull requests you would need a verilog and vhdl simulators.

>
> Thanks to this, users can submit quick bugfixes as pull requests and the
> repo owner can accept pull requests without worrying too much(or without
> pulling changes and running tests) if tests pass.
> I imagine bugs like these: (
> https://bitbucket.org/jandecaluwe/myhdl/issue/3/always_seq-decorator-error-message-string
> ) would be handled much quicker.
>
> Additionally, github's UI makes it easy to see what other contributors
> are up to, this makes it easier to co-ordinate and might make some
> people more confident about contributing.
> see: https://github.com/blog/39-say-hello-to-the-network-graph-visualizer
>
> 3) git and hg workflows aren't too different. hg users will not have too
> much trouble contributing to git repos. Additionally, there are tools
> like hg-git which allow you to use hg locally while contributing to a
> git remote.
> http://hg-git.github.io/
>

If hg-git works nice, there could be a mirror on github
(note someone already created a mirror on github).  I have
not been able to get hg-git to work.  I am moving some of my
github projects to bitbucket because I don't see any benefit
of having them on github (exception travis-ci).

I think we have hashed through this topic, I don't know if the
travis-ci is enough to overturn the inertia.

Regards,
Chris

Re: [myhdl-list] Keep hierarchy in VHDL conversion

[Keerthan jai.c <jck...@gm...>]

Additionally, travis runs tests using multiple python versions. So we can
make it run tests with 2.6,2.7 and pypy. I beleive this will be very useful
during the python3 migration process.


On Wed, Sep 4, 2013 at 3:12 PM, Keerthan jai.c <jck...@gm...> wrote:

> Since I am not an expert on either git or hg, I won't comment on the
> technical aspects. However I think that github is a better place to host
> the main myhdl repo.
>
> Reasons why I think we should switch to github:
> 1) Hosting myhdl on github will improve the visibility of the project, and
> more people will contribute.
> see
> http://eli.thegreenplace.net/2013/06/09/switching-my-open-source-projects-from-bitbucket-to-github/
>
> 2) Github is arguably a better/more poular platform.
> For example, travis-ci(continuous integration) supports github but not
> bitbucket. While there are alternatives to travis-ci, none of the free ones
> are as good.
> You can check out the UI of travis-ci here:
> https://travis-ci.org/kennethreitz/requests
>
> travis-ci is deeply integrated with github, this makes the process of pull
> requests way simpler.
> If travis is configured(a simple yml file in the repository root), travis
> automatically runs tests on all commits and pull requests. From the github
> pull requests page, you can see if tests passed/failed. And additionally,
> get details about failed tests.
> This is how it looks:
> tests passed:
> http://danlimerick.files.wordpress.com/2013/02/safetomergeprtravis.png
> tests failed:
> http://danlimerick.files.wordpress.com/2013/02/failedprtravis.png
>
>
> Thanks to this, users can submit quick bugfixes as pull requests and the
> repo owner can accept pull requests without worrying too much(or without
> pulling changes and running tests) if tests pass.
> I imagine bugs like these: (
> https://bitbucket.org/jandecaluwe/myhdl/issue/3/always_seq-decorator-error-message-string) would be handled much quicker.
>
> Additionally, github's UI makes it easy to see what other contributors are
> up to, this makes it easier to co-ordinate and might make some people more
> confident about contributing.
> see: https://github.com/blog/39-say-hello-to-the-network-graph-visualizer
>
> 3) git and hg workflows aren't too different. hg users will not have too
> much trouble contributing to git repos. Additionally, there are tools like
> hg-git which allow you to use hg locally while contributing to a git remote.
> http://hg-git.github.io/
>
>
>
>
>
> On Fri, May 10, 2013 at 6:50 PM, Angel Ezquerra <ang...@gm...>wrote:
>
>> On Thu, May 9, 2013 at 4:04 PM, Jan Decaluwe <ja...@ja...> wrote:
>> > On 05/09/2013 02:09 PM, Angel Ezquerra wrote:
>> >> On Thu, May 9, 2013 at 12:14 PM, Jan Decaluwe <ja...@ja...>
>> wrote:
>> >
>> >> That is not true, and probably is the key difference. In mercurial no
>> >> mew commit is ever created when you do hg pull and it is not done when
>> >> you do hg merge either. You must explicitly do hg commit to "confirm"
>> >> your merge (once you do it).
>> >
>> > What I meant is that in both cases in the "default" workflow,
>> > a merge commit will eventually appear in the history, so that
>> > you can clearly see how and where the diverged branches converge
>> > (which was your original concern).
>>
>> OK, I understand what you meant now.
>>
>> > hg pull is more like git fetch; it is true that git pull tries
>> > to do many things at once which is not necessarily what you want
>> > on large projects. I prefer git fetch, no idea what most people
>> > do.
>>
>> I also think using git fetch is the sensible thing to do, but it is
>> not what I've seen people use most of the time, which I find quite
>> weird.
>>
>> > Note that for MyHDL there is basically a consensus to stick
>> > with mercurial - I have already put a repo on bitbucket that
>> > I intend to use as the main repo.
>>
>> Yes, I know that. I was just trying to answer Chris Felton's question
>> about why I prefer mercurial to git.
>>
>> Cheers,
>>
>> Angel
>>
>>
>> ------------------------------------------------------------------------------
>> Learn Graph Databases - Download FREE O'Reilly Book
>> "Graph Databases" is the definitive new guide to graph databases and
>> their applications. This 200-page book is written by three acclaimed
>> leaders in the field. The early access version is available now.
>> Download your free book today! http://p.sf.net/sfu/neotech_d2d_may
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> have a nice day
> -jck
>



-- 
have a nice day
-jck

Re: [myhdl-list] Keep hierarchy in VHDL conversion

[Keerthan jai.c <jck...@gm...>]

Since I am not an expert on either git or hg, I won't comment on the
technical aspects. However I think that github is a better place to host
the main myhdl repo.

Reasons why I think we should switch to github:
1) Hosting myhdl on github will improve the visibility of the project, and
more people will contribute.
see
http://eli.thegreenplace.net/2013/06/09/switching-my-open-source-projects-from-bitbucket-to-github/

2) Github is arguably a better/more poular platform.
For example, travis-ci(continuous integration) supports github but not
bitbucket. While there are alternatives to travis-ci, none of the free ones
are as good.
You can check out the UI of travis-ci here:
https://travis-ci.org/kennethreitz/requests

travis-ci is deeply integrated with github, this makes the process of pull
requests way simpler.
If travis is configured(a simple yml file in the repository root), travis
automatically runs tests on all commits and pull requests. From the github
pull requests page, you can see if tests passed/failed. And additionally,
get details about failed tests.
This is how it looks:
tests passed:
http://danlimerick.files.wordpress.com/2013/02/safetomergeprtravis.png
tests failed:
http://danlimerick.files.wordpress.com/2013/02/failedprtravis.png


Thanks to this, users can submit quick bugfixes as pull requests and the
repo owner can accept pull requests without worrying too much(or without
pulling changes and running tests) if tests pass.
I imagine bugs like these: (
https://bitbucket.org/jandecaluwe/myhdl/issue/3/always_seq-decorator-error-message-string)
would be handled much quicker.

Additionally, github's UI makes it easy to see what other contributors are
up to, this makes it easier to co-ordinate and might make some people more
confident about contributing.
see: https://github.com/blog/39-say-hello-to-the-network-graph-visualizer

3) git and hg workflows aren't too different. hg users will not have too
much trouble contributing to git repos. Additionally, there are tools like
hg-git which allow you to use hg locally while contributing to a git remote.
http://hg-git.github.io/





On Fri, May 10, 2013 at 6:50 PM, Angel Ezquerra <ang...@gm...>wrote:

> On Thu, May 9, 2013 at 4:04 PM, Jan Decaluwe <ja...@ja...> wrote:
> > On 05/09/2013 02:09 PM, Angel Ezquerra wrote:
> >> On Thu, May 9, 2013 at 12:14 PM, Jan Decaluwe <ja...@ja...>
> wrote:
> >
> >> That is not true, and probably is the key difference. In mercurial no
> >> mew commit is ever created when you do hg pull and it is not done when
> >> you do hg merge either. You must explicitly do hg commit to "confirm"
> >> your merge (once you do it).
> >
> > What I meant is that in both cases in the "default" workflow,
> > a merge commit will eventually appear in the history, so that
> > you can clearly see how and where the diverged branches converge
> > (which was your original concern).
>
> OK, I understand what you meant now.
>
> > hg pull is more like git fetch; it is true that git pull tries
> > to do many things at once which is not necessarily what you want
> > on large projects. I prefer git fetch, no idea what most people
> > do.
>
> I also think using git fetch is the sensible thing to do, but it is
> not what I've seen people use most of the time, which I find quite
> weird.
>
> > Note that for MyHDL there is basically a consensus to stick
> > with mercurial - I have already put a repo on bitbucket that
> > I intend to use as the main repo.
>
> Yes, I know that. I was just trying to answer Chris Felton's question
> about why I prefer mercurial to git.
>
> Cheers,
>
> Angel
>
>
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-- 
have a nice day
-jck