MyHDL 0.6 has been released.
MyHDL 0.5.1 was released today - a maintenance release for 0.5. See the bug tracker for fixed issues (group MyHDL 0.5).
MyHDL 0.5 has been released.
MyHDL is a Python package for using Python as a hardware description
and verification language. MyHDL 0.4.1 is now available at:
MyHDL 0.4.1 release notes:
* Maintenance release that solves most outstanding issues
and implements some feature requests.
See the SourceForge Bug and RFE Trackers for details.
More info can also be found on the mailing list.... read more
I am happy to announce the release of MyHDL 0.4. MyHDL is a Python
package for using Python as a hardware description & verification
MyHDL 0.4 supports the automatic conversion of a subset of MyHDL code
to synthesizable Verilog code. This feature provides a direct path
from Python to an FPGA or ASIC implementation.
For the details on the release, go here:
MyHDL starts using SourceForge services. A mailing list has been created, and the file download area has been moved over here.