myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Jan D. <ja...@ja...>]

On 05/15/2013 06:06 PM, Keerthan jai.c wrote:
>> That's a rhetorical question again.
> I'm not sure I understand the hostility here. I am not making feature
> requests, I like this project and would like to contribute. I have
> just started digging into the code base and I'm just thinking out
> loud. Is discussion of this sort not encouraged here?

It's really a matter of efficiency.

I have extremely bad experiences in the past with the
unethical behavior from people like Mr. Bourdeauducq and
Mr. Lozinski. Such people have there own hidden assumptions
and agendas (and frequently, misunderstandings).
They all claim they want to contribute, but in reality they
want to change the project in fundamental ways to their
liking.

That is such a waste of energy, and I have not the slightest
interest in repeating such discussions. I believe the fundamental
concepts behind MyHDL are very clear and open. Nobody is forced
to like them or agree, but if you don't, the ethical path
is to leave and start your own project.

I am *not* at all saying that is your case, but you have to
understand that I want to resolve these matters quickly.
Asking rhetorical questions that are impossible to answer
(by someone that obviously likes MyHDL) are not constructive
and make me wonder about your goals.

To remove doubts, you could perhaps tell a little more
about yourself, your experience, past projects, etc.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/15/2013 11:06 AM, Keerthan jai.c wrote:
>   > That's a rhetorical question again.
> I'm not sure I understand the hostility here. I am not making feature
> requests, I like this project and would like to contribute. I have just
> started digging into the code base and I'm just thinking out loud. Is
> discussion of this sort not encouraged here?

There is no hostility.  There is directness because
projects frequently get "ideas" by visitors.  It is
easiest to address the ideas by being as direct as
possible.  It saves time for everyone involved.

You need to be careful of generalities like "is the
AST the best path ..."  If it wasn't it would not be
used.

You will get a little more traction with specific
questions which requires some time commitment and grit
to dig into the existing code.

Maybe instead of asking if the AST is the best option
you could ask: "does anyone have suggestions on the best
path to get involved with conversion and the conversion
code?"

Regards,
Chris

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/15/2013 9:10 AM, Keerthan jai.c wrote:
> I did mention in the first post, that I've benifitted from MyHDL for
> testing. I was merely curious about how other users cope with the
> restrictions of conversion.
>
> On another note, do you think that using AST is the best approach for
> conversion? I think, in a language like python, where everything is an
> object, looking only at variable names feels a bit fragile.
>

This might help understand the MyHDL goals (or not)
from my perspective.  MyHDL is intended to be an HDL
and not a Verilog/VHDL code generator.

These three pages should give a good overview for the
project and philosophies:

    http://myhdl.org/doku.php/overview
    http://myhdl.org/doku.php/why
    http://myhdl.org/doku.php/whatitisnot

The MyHDL language design is important and should not
be under appreciated.  Look at the effort and thought
that went into the underlying Python language design.
Since, MyHDL lives in Python it has similar goals and
philosophies.  Jan has done a good job considering the
language design for an RTL level HDL.

 From this context it makes absolute sense to use the
Python front-end parsing tools and the AST representation,
otherwise you can end up with a very ugly HDL or spend
significant time re-implementing the same tools.  As Jan
mentioned more than simply the /name/ is available from the
AST tools, you have access to the objects.

This is from my perspective, Jan or others can correct
or chime in where necessary.

Regards,
Chris

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

 > That's a rhetorical question again.
I'm not sure I understand the hostility here. I am not making feature
requests, I like this project and would like to contribute. I have just
started digging into the code base and I'm just thinking out loud. Is
discussion of this sort not encouraged here?


>The fact that you ask a rethorical question like this
>suggests that you don't completely grasp what MyHDL is
>about.
In the earlier post, I specifically asked whether things like this were a
part of MyHDL's vision. Are you saying that conversion for synthesis is of
minor importance to the project?

>Of course I think using the AST is the best approach for
>my goal. What did you expect me to say?
After an initial examination of the source code, the conversion code felt
cumbersome to me. I asked this question because you mentioned "as
conversion is here and there already to tricky to my taste".

>> I think, in a language like python, where everything is
>> an object, looking only at variable names feels a bit fragile.
>I have no idea what you mean here. The convertor is looking
>at the details of every object behind a name.
I meant this with regards to how the converter needs that all the variables
are MyHDL primitives.



On Wed, May 15, 2013 at 11:21 AM, Christopher Felton <chr...@gm...
> wrote:

> On 5/15/2013 10:19 AM, Jan Decaluwe wrote:
> <snip>
> >
> >> I think, in a language like python, where everything is
> >> an object, looking only at variable names feels a bit fragile.
> >
> > I have no idea what you mean here. The convertor is looking
> > at the details of every object behind a name.
> >
>
> Agreed, not sure what was trying to be said here.
>
> Regards,
> Chris
>
>
>
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-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/15/2013 10:19 AM, Jan Decaluwe wrote:
<snip>
>
>> I think, in a language like python, where everything is
>> an object, looking only at variable names feels a bit fragile.
>
> I have no idea what you mean here. The convertor is looking
> at the details of every object behind a name.
>

Agreed, not sure what was trying to be said here.

Regards,
Chris

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Jan D. <ja...@ja...>]

On 05/15/2013 04:10 PM, Keerthan jai.c wrote:

> On another note, do you think that using AST is the best approach for
> conversion?

That's a rhetorical question again.

Of course I think using the AST is the best approach for
my goal. What did you expect me to say?

My goal is to convert behavior to behavior.

For a meaningful discussion, please specify your goal,
and, if it is the same, your alternative technique.

> I think, in a language like python, where everything is
> an object, looking only at variable names feels a bit fragile.

I have no idea what you mean here. The convertor is looking
at the details of every object behind a name.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

I did mention in the first post, that I've benifitted from MyHDL for
testing. I was merely curious about how other users cope with the
restrictions of conversion.

On another note, do you think that using AST is the best approach for
conversion? I think, in a language like python, where everything is an
object, looking only at variable names feels a bit fragile.



On Wed, May 15, 2013 at 8:10 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 05/13/2013 10:01 PM, Keerthan jai.c wrote:
> > Thanks, I will look at your examples.
> >
> > What about the two logic blocks mem_a and mem_b? They are essentially
> > the same logic, the only difference being their ports. Is there
> > anyway to make that more elegant? Is reducing the repetition of
> > information a part of myhdl's vision?
>
> The fact that you ask a rethorical question like this
> suggests that you don't completely grasp what MyHDL is
> about.
>
> It is not only about conversion and implementation, but
> also (perhaps even more so) about modeling and test benches.
>
> The modeling/test benches part is intended to be very generic.
> You should be able to use most Python features in the book
> to do it as you want.
>
> It's the conversion part that has the restrictions. This has
> all kinds of reasons, e.g. restrictions in Verilog/VHDL and
> the mere fact that such a conversion from a dynamic to
> static languages is not trivial.
>
> Please do make that distinction between modeling versus restrictions
> related to conversion.
>
> I understand that people expect all kinds of additional features
> from conversion. But you know - I think it's quite powerful
> as it is, *if you compare it with restrictions imposed by
> VHDL/Verilog synthesis itself*. Note that the main reason for
> conversion still is a path to synthesis.
>
> I don't see the occasional workaround as a problem. Moreover,
> as conversion is here and there already to tricky to my taste,
> I'm not looking for all kinds of new features except when they
> have an obvious significant additional value. I'd rather
> incorporate "boring" and "invisible" improvements that
> increase robustness.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Jan D. <ja...@ja...>]

On 05/13/2013 10:01 PM, Keerthan jai.c wrote:
> Thanks, I will look at your examples.
>
> What about the two logic blocks mem_a and mem_b? They are essentially
> the same logic, the only difference being their ports. Is there
> anyway to make that more elegant? Is reducing the repetition of
> information a part of myhdl's vision?

The fact that you ask a rethorical question like this
suggests that you don't completely grasp what MyHDL is
about.

It is not only about conversion and implementation, but
also (perhaps even more so) about modeling and test benches.

The modeling/test benches part is intended to be very generic.
You should be able to use most Python features in the book
to do it as you want.

It's the conversion part that has the restrictions. This has
all kinds of reasons, e.g. restrictions in Verilog/VHDL and
the mere fact that such a conversion from a dynamic to
static languages is not trivial.

Please do make that distinction between modeling versus restrictions
related to conversion.

I understand that people expect all kinds of additional features
from conversion. But you know - I think it's quite powerful
as it is, *if you compare it with restrictions imposed by
VHDL/Verilog synthesis itself*. Note that the main reason for
conversion still is a path to synthesis.

I don't see the occasional workaround as a problem. Moreover,
as conversion is here and there already to tricky to my taste,
I'm not looking for all kinds of new features except when they
have an obvious significant additional value. I'd rather
incorporate "boring" and "invisible" improvements that
increase robustness.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Proposal: New class, ClockDomain

[Jan D. <ja...@ja...>]

On 05/15/2013 03:47 AM, Christopher Lozinski wrote:
>   Clock domain is a great idea.
>
> There should be a rich and interesting library of Hardware modules
> available as a library in MyHDL.
>
> It makes life so much easier for the Newbies.
>
> Sure it is not that much code for the experienced guys to write one
> class, but it has to do with mindsets.  As an experienced object
> oriented developer
> new to MyHDL, I expect a rich and interesting class library to exist and
> be available for reuse.
>
> Here is one such suggested library.
>
> http://www.oohdl.com/HarwareModuleClassLibrary

BTW - I hate that classification - way too much level. Not
useful for real HDL work.

> Then I could make a blinking light out of a clock, and a counter.
> Just watch the 22nd bit on the counter, to see it blink at human speed.
>
> http://www.oohdl.com/Blinking_Light
>
> Much better than writing it from scratch.
>
> The fact that such a library  does not exist, that it is discouraged,
> that there is no culture of publishing and sharing class libraries in
> MyHDL gives me pause.
>
> Perhaps it is more efficient to write things from scratch, but for us
> newbies, it is way way easier to reuse existing class libraries.
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Proposal: New class, ClockDomain

[Jan D. <ja...@ja...>]

On 05/15/2013 03:47 AM, Christopher Lozinski wrote:
>   Clock domain is a great idea.
>
> There should be a rich and interesting library of Hardware modules
> available as a library in MyHDL.

Of course there should not.

Unlike Python, it is totally unclear how a "standard" library for
MyHDL should look like.

Guido himself recently explained how the concept of the Python
standard library is frequently misunderstood. The Python standard
library is like a minimum set of generally useful functionality,
on which there is basically a consensus.

However, being in the standard library is not a blessing. It takes
ages, and you have comply with all kinds of Python-release related
restrictions. I certainly would not want MyHDL to be in the
Python standard library. For innovation, you don't want a
standard library.

For the record, I am of course all of for "rich and interesting libraries
of MyHDL hardware modules" - plenty of them, including competing
ones. Just do not look at me or the MyHDL library itself for
that - I am doing my share and I have many other plans.

Nothing prevents you or anyone to make your hands dirty and
start with it today. Let's stop the high-level talk and get
to work.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Proposal: New class, ClockDomain

[Jan D. <ja...@ja...>]

On 05/15/2013 02:22 AM, Keerthan jai.c wrote:
> Do you think it is a good idea to have a new class ClockDoman,

Not in the myhdl library itself, and not enough value to
support for conversion.




which contains a clock and reset signal? Typically, we use the same clock and reset signals for most modules, having a clock domain object might simplify this.
>
> Example:
> def module(cd, ports...):
>      @always_seq(cd)
>      ....
>
> clk = Signal(bool(0))
> rst = ResetSignal(1, active=0, async=True)
> app_clk = ClockDomain(clk, rst)
>
> inst = module(app_clk, ports..
>
>
> --
> have a nice day
> -jck
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Proposal: New class, ClockDomain

[Christopher L. <loz...@fr...>]

 Clock domain is a great idea.

There should be a rich and interesting library of Hardware modules
available as a library in MyHDL.

It makes life so much easier for the Newbies.

Sure it is not that much code for the experienced guys to write one
class, but it has to do with mindsets.  As an experienced object
oriented developer
new to MyHDL, I expect a rich and interesting class library to exist and
be available for reuse.

Here is one such suggested library.

http://www.oohdl.com/HarwareModuleClassLibrary

Then I could make a blinking light out of a clock, and a counter. 
Just watch the 22nd bit on the counter, to see it blink at human speed.

http://www.oohdl.com/Blinking_Light

Much better than writing it from scratch.

The fact that such a library  does not exist, that it is discouraged,
that there is no culture of publishing and sharing class libraries in
MyHDL gives me pause.

Perhaps it is more efficient to write things from scratch, but for us
newbies, it is way way easier to reuse existing class libraries.

-- 
 I run 
http://Django.SpecialtyJobMarkets.com

Regards
Christopher Lozinski

The future of Zope 
http://ZOPACHE.COM

On Digital Design
http://OOHDL.COM

Re: [myhdl-list] Proposal: New class, ClockDomain

[Christopher F. <chr...@gm...>]

On 5/14/13 7:22 PM, Keerthan jai.c wrote:
> Do you think it is a good idea to have a new class ClockDoman, which
> contains a clock and reset signal? Typically, we use the same clock and
> reset signals for most modules, having a clock domain object might
> simplify this.
>
> Example:
> def module(cd, ports...):
>      @always_seq(cd)
>      ....
>
> clk = Signal(bool(0))
> rst = ResetSignal(1, active=0, async=True)
> app_clk = ClockDomain(clk, rst)
>
> inst = module(app_clk, ports..
>
>
> --
> have a nice day
> -jck
>
>

I think this is too application specific to be
included in the base myhdl pkg.  It is fairly
light to include:

     class SystemSignals:
         def __init__(def, frequency=1):
             self.clock = Signal(bool(0))
             self.reset = ResetSignal(0,active=0,async=False)

         def m_sync_reset(ext_reset, reset)
             ...

     def m_some_module(syssigs, *ports):
         clock = syssigs.clock
         reset = syssigs.reset
         ...

     def m_some_top(...):
         domain1 = SystemSignals(frequency=50e6)
         domain2 = SystemSignals(frequency=333e6)

         g_rst1 = domain1.m_sync_reset(ext_reset, domain1.reset)
         g_rst2 = domain2.m_sync_reset(ext_reset, domain2.reset)

         g1 = m_some_module(domain1, ...)
         g2 = m_some_module(domain2, ...)
         ...


in an project.  Sorry, I like to type out /clock/
and /reset/ :)


Regards,
Chris

[myhdl-list] Proposal: New class, ClockDomain

[Keerthan jai.c <jck...@gm...>]

Do you think it is a good idea to have a new class ClockDoman, which
contains a clock and reset signal? Typically, we use the same clock and
reset signals for most modules, having a clock domain object might simplify
this.

Example:
def module(cd, ports...):
    @always_seq(cd)
    ....

clk = Signal(bool(0))
rst = ResetSignal(1, active=0, async=True)
app_clk = ClockDomain(clk, rst)

inst = module(app_clk, ports..


-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

Thanks, that cleared my doubts about the current state of myhdl's
implementation.

Also, I took a look at MEP107 and myhdl's conversion code. I would like to
help in implementing MEP107. This is what I'm thinking so far(note: I have
never used ASTs before, so  I might be completely off):

1) Create a ast.NodeTransformer class to resolve references
2) Create visit_Attribute and visit_Subscript functions in it
3) Create lists of reserved attributes and subscripts. (So far it is only
.next I think)
4) Recursively resolve the references


On Tue, May 14, 2013 at 9:17 AM, Christopher Felton
<chr...@gm...>wrote:

> On 5/14/2013 8:04 AM, Christopher Felton wrote:
> > On 5/13/2013 5:33 PM, Keerthan jai.c wrote:
> >> But what about your example above?
> >>
> >
> > Here is a complete example, it is still an nonsensical
> > example and incomplete.  But it shows the different
> > methods we were discussing, simulates (nothing to verify
> > though, cause it doesn't do anything) and converts.
> >
> > https://gist.github.com/cfelton/5575659
> >
>
> I should note, only the first 30 lines are part of the
> example we have been discussing.  The reset is scaffolding
> to create an example, albeit nonsensical.  To create a
> top-level that is closer to a real-world example, which
> would be converted.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/14/2013 8:04 AM, Christopher Felton wrote:
> On 5/13/2013 5:33 PM, Keerthan jai.c wrote:
>> But what about your example above?
>>
>
> Here is a complete example, it is still an nonsensical
> example and incomplete.  But it shows the different
> methods we were discussing, simulates (nothing to verify
> though, cause it doesn't do anything) and converts.
>
> https://gist.github.com/cfelton/5575659
>

I should note, only the first 30 lines are part of the
example we have been discussing.  The reset is scaffolding
to create an example, albeit nonsensical.  To create a
top-level that is closer to a real-world example, which
would be converted.

Regards,
Chris

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/13/2013 5:33 PM, Keerthan jai.c wrote:
> But what about your example above?
>

Here is a complete example, it is still an nonsensical
example and incomplete.  But it shows the different
methods we were discussing, simulates (nothing to verify
though, cause it doesn't do anything) and converts.

https://gist.github.com/cfelton/5575659

Regards,
Chris

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

I wasn't expecting DPR to be used as a top-level,
i.e. directly converted but rather a submodule in
a design.  I can post a complete example later
tonight.

.chris


On Mon, May 13, 2013 at 5:33 PM, Keerthan jai.c <jck...@gm...>wrote:

> But what about your example above?
>
>
>      def DPR(clk pa, pb):
>          mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>          mem_ports = [None,None]
>          for inst,port in zip((mem_ports,(pa,pb)):
>              inst = mem_logic(clk, port.data, port.addr,
>                               port.we, port.q, mem
>          return mem_port
>
>
> On Mon, May 13, 2013 at 6:29 PM, Christopher Felton <
> chr...@gm...> wrote:
>
>> The class attributes ports can't be the top-level.
>>
>> Regards,
>> Chris
>>
>>
>> On Mon, May 13, 2013 at 5:16 PM, Keerthan jai.c <jck...@gm...>wrote:
>>
>>> It looks like using class attributes as signals don't work even if I
>>> create local variables inside the function and copy the class attributes
>>> into them.
>>>
>>> for example:
>>> def DPR(clk, a,b):
>>>     ...
>>>     data_a, addr_a, we_a, q_a = a.data, a.addr, a.we, a.q
>>>     ...
>>>
>>>     mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>>     ...
>>>     return mem_a,mem_b
>>>
>>> clk = Signal(bool(0))
>>> a = RamInt()
>>> b = RamInt()
>>> toVerilog(DPR, clk, a, b)
>>> -----------------------------------------------
>>> ** ToVerilogWarning: Signal is not driven: data_b
>>> ** ToVerilogWarning: Signal is not driven: data_a
>>> ** ToVerilogWarning: Signal is driven but not read: q_b
>>> ** ToVerilogWarning: Signal is driven but not read: q_a
>>> ** ToVerilogWarning: Signal is not driven: addr_b
>>> ** ToVerilogWarning: Signal is not driven: addr_a
>>> ** ToVerilogWarning: Signal is not driven: we_a
>>> ** ToVerilogWarning: Signal is not driven: we_b
>>>
>>> In the verilog code, data, q and we are wires and are assigned 0.
>>>
>>>
>>>
>>>
>>> On Mon, May 13, 2013 at 5:10 PM, Christopher Felton <
>>> chr...@gm...> wrote:
>>>
>>>> On 5/13/2013 3:54 PM, Keerthan jai.c wrote:
>>>> > I suppose I could have done this:
>>>> >
>>>> > def mem_logic(clk, data, addr, we, q, mem):
>>>> >      @always(clk.posedge)
>>>> >      def logic():
>>>> >          if we:
>>>> >              mem[int(addr)].next = data
>>>> >          else:
>>>> >              q.next = mem[int(addr)]
>>>> >      return logic
>>>> >
>>>> >
>>>> > def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
>>>> >                  we_a, we_b, q_a, q_b, depth=128):
>>>> >      """Ram model"""
>>>> >
>>>> >      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>>> >
>>>> >      mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>>> >      mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>>>> >
>>>> >      return mem_a, mem_b
>>>> >
>>>> >
>>>>
>>>> Also valid:
>>>>
>>>>      ...
>>>>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>>>      mem_ports = [None,None]
>>>>      mem_ports[0] = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>>>      mem_ports[1] = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>>>>
>>>>      return mem_ports
>>>>
>>>> In addition, I am fairly sure, in this case you could do
>>>> (would need to test first):
>>>>
>>>>      def DPR(clk pa, pb):
>>>>          mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>>>          mem_ports = [None,None]
>>>>          for inst,port in zip((mem_ports,(pa,pb)):
>>>>              inst = mem_logic(clk, port.data, port.addr,
>>>>                               port.we, port.q, mem
>>>>          return mem_port
>>>>
>>>> NOTE! I did not test the above, I did not even
>>>> check the syntax.
>>>>
>>>> Regards,
>>>> Chris
>>>>
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> AlienVault Unified Security Management (USM) platform delivers complete
>>>> security visibility with the essential security capabilities. Easily and
>>>> efficiently configure, manage, and operate all of your security controls
>>>> from a single console and one unified framework. Download a free trial.
>>>> http://p.sf.net/sfu/alienvault_d2d
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>
>>>
>>>
>>>
>>> --
>>> have a nice day
>>> -jck
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> AlienVault Unified Security Management (USM) platform delivers complete
>>> security visibility with the essential security capabilities. Easily and
>>> efficiently configure, manage, and operate all of your security controls
>>> from a single console and one unified framework. Download a free trial.
>>> http://p.sf.net/sfu/alienvault_d2d
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>>
>>
>>
>> ------------------------------------------------------------------------------
>> AlienVault Unified Security Management (USM) platform delivers complete
>> security visibility with the essential security capabilities. Easily and
>> efficiently configure, manage, and operate all of your security controls
>> from a single console and one unified framework. Download a free trial.
>> http://p.sf.net/sfu/alienvault_d2d
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> --
> have a nice day
> -jck
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

But what about your example above?

     def DPR(clk pa, pb):
         mem = [Signal(intbv(0)[8:]) for i in range(depth)]
         mem_ports = [None,None]
         for inst,port in zip((mem_ports,(pa,pb)):
             inst = mem_logic(clk, port.data, port.addr,
                              port.we, port.q, mem
         return mem_port


On Mon, May 13, 2013 at 6:29 PM, Christopher Felton
<chr...@gm...>wrote:

> The class attributes ports can't be the top-level.
>
> Regards,
> Chris
>
>
> On Mon, May 13, 2013 at 5:16 PM, Keerthan jai.c <jck...@gm...>wrote:
>
>> It looks like using class attributes as signals don't work even if I
>> create local variables inside the function and copy the class attributes
>> into them.
>>
>> for example:
>> def DPR(clk, a,b):
>>     ...
>>     data_a, addr_a, we_a, q_a = a.data, a.addr, a.we, a.q
>>     ...
>>
>>     mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>     ...
>>     return mem_a,mem_b
>>
>> clk = Signal(bool(0))
>> a = RamInt()
>> b = RamInt()
>> toVerilog(DPR, clk, a, b)
>> -----------------------------------------------
>> ** ToVerilogWarning: Signal is not driven: data_b
>> ** ToVerilogWarning: Signal is not driven: data_a
>> ** ToVerilogWarning: Signal is driven but not read: q_b
>> ** ToVerilogWarning: Signal is driven but not read: q_a
>> ** ToVerilogWarning: Signal is not driven: addr_b
>> ** ToVerilogWarning: Signal is not driven: addr_a
>> ** ToVerilogWarning: Signal is not driven: we_a
>> ** ToVerilogWarning: Signal is not driven: we_b
>>
>> In the verilog code, data, q and we are wires and are assigned 0.
>>
>>
>>
>>
>> On Mon, May 13, 2013 at 5:10 PM, Christopher Felton <
>> chr...@gm...> wrote:
>>
>>> On 5/13/2013 3:54 PM, Keerthan jai.c wrote:
>>> > I suppose I could have done this:
>>> >
>>> > def mem_logic(clk, data, addr, we, q, mem):
>>> >      @always(clk.posedge)
>>> >      def logic():
>>> >          if we:
>>> >              mem[int(addr)].next = data
>>> >          else:
>>> >              q.next = mem[int(addr)]
>>> >      return logic
>>> >
>>> >
>>> > def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
>>> >                  we_a, we_b, q_a, q_b, depth=128):
>>> >      """Ram model"""
>>> >
>>> >      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>> >
>>> >      mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>> >      mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>>> >
>>> >      return mem_a, mem_b
>>> >
>>> >
>>>
>>> Also valid:
>>>
>>>      ...
>>>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>>      mem_ports = [None,None]
>>>      mem_ports[0] = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>>      mem_ports[1] = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>>>
>>>      return mem_ports
>>>
>>> In addition, I am fairly sure, in this case you could do
>>> (would need to test first):
>>>
>>>      def DPR(clk pa, pb):
>>>          mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>>          mem_ports = [None,None]
>>>          for inst,port in zip((mem_ports,(pa,pb)):
>>>              inst = mem_logic(clk, port.data, port.addr,
>>>                               port.we, port.q, mem
>>>          return mem_port
>>>
>>> NOTE! I did not test the above, I did not even
>>> check the syntax.
>>>
>>> Regards,
>>> Chris
>>>
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> AlienVault Unified Security Management (USM) platform delivers complete
>>> security visibility with the essential security capabilities. Easily and
>>> efficiently configure, manage, and operate all of your security controls
>>> from a single console and one unified framework. Download a free trial.
>>> http://p.sf.net/sfu/alienvault_d2d
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>
>>
>>
>> --
>> have a nice day
>> -jck
>>
>>
>> ------------------------------------------------------------------------------
>> AlienVault Unified Security Management (USM) platform delivers complete
>> security visibility with the essential security capabilities. Easily and
>> efficiently configure, manage, and operate all of your security controls
>> from a single console and one unified framework. Download a free trial.
>> http://p.sf.net/sfu/alienvault_d2d
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

The class attributes ports can't be the top-level.

Regards,
Chris


On Mon, May 13, 2013 at 5:16 PM, Keerthan jai.c <jck...@gm...>wrote:

> It looks like using class attributes as signals don't work even if I
> create local variables inside the function and copy the class attributes
> into them.
>
> for example:
> def DPR(clk, a,b):
>     ...
>     data_a, addr_a, we_a, q_a = a.data, a.addr, a.we, a.q
>     ...
>
>     mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>     ...
>     return mem_a,mem_b
>
> clk = Signal(bool(0))
> a = RamInt()
> b = RamInt()
> toVerilog(DPR, clk, a, b)
> -----------------------------------------------
> ** ToVerilogWarning: Signal is not driven: data_b
> ** ToVerilogWarning: Signal is not driven: data_a
> ** ToVerilogWarning: Signal is driven but not read: q_b
> ** ToVerilogWarning: Signal is driven but not read: q_a
> ** ToVerilogWarning: Signal is not driven: addr_b
> ** ToVerilogWarning: Signal is not driven: addr_a
> ** ToVerilogWarning: Signal is not driven: we_a
> ** ToVerilogWarning: Signal is not driven: we_b
>
> In the verilog code, data, q and we are wires and are assigned 0.
>
>
>
>
> On Mon, May 13, 2013 at 5:10 PM, Christopher Felton <
> chr...@gm...> wrote:
>
>> On 5/13/2013 3:54 PM, Keerthan jai.c wrote:
>> > I suppose I could have done this:
>> >
>> > def mem_logic(clk, data, addr, we, q, mem):
>> >      @always(clk.posedge)
>> >      def logic():
>> >          if we:
>> >              mem[int(addr)].next = data
>> >          else:
>> >              q.next = mem[int(addr)]
>> >      return logic
>> >
>> >
>> > def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
>> >                  we_a, we_b, q_a, q_b, depth=128):
>> >      """Ram model"""
>> >
>> >      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>> >
>> >      mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>> >      mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>> >
>> >      return mem_a, mem_b
>> >
>> >
>>
>> Also valid:
>>
>>      ...
>>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>      mem_ports = [None,None]
>>      mem_ports[0] = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>>      mem_ports[1] = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>>
>>      return mem_ports
>>
>> In addition, I am fairly sure, in this case you could do
>> (would need to test first):
>>
>>      def DPR(clk pa, pb):
>>          mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>>          mem_ports = [None,None]
>>          for inst,port in zip((mem_ports,(pa,pb)):
>>              inst = mem_logic(clk, port.data, port.addr,
>>                               port.we, port.q, mem
>>          return mem_port
>>
>> NOTE! I did not test the above, I did not even
>> check the syntax.
>>
>> Regards,
>> Chris
>>
>>
>>
>> ------------------------------------------------------------------------------
>> AlienVault Unified Security Management (USM) platform delivers complete
>> security visibility with the essential security capabilities. Easily and
>> efficiently configure, manage, and operate all of your security controls
>> from a single console and one unified framework. Download a free trial.
>> http://p.sf.net/sfu/alienvault_d2d
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> have a nice day
> -jck
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

It looks like using class attributes as signals don't work even if I create
local variables inside the function and copy the class attributes into them.

for example:
def DPR(clk, a,b):
    ...
    data_a, addr_a, we_a, q_a = a.data, a.addr, a.we, a.q
    ...
    mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
    ...
    return mem_a,mem_b

clk = Signal(bool(0))
a = RamInt()
b = RamInt()
toVerilog(DPR, clk, a, b)
-----------------------------------------------
** ToVerilogWarning: Signal is not driven: data_b
** ToVerilogWarning: Signal is not driven: data_a
** ToVerilogWarning: Signal is driven but not read: q_b
** ToVerilogWarning: Signal is driven but not read: q_a
** ToVerilogWarning: Signal is not driven: addr_b
** ToVerilogWarning: Signal is not driven: addr_a
** ToVerilogWarning: Signal is not driven: we_a
** ToVerilogWarning: Signal is not driven: we_b

In the verilog code, data, q and we are wires and are assigned 0.




On Mon, May 13, 2013 at 5:10 PM, Christopher Felton
<chr...@gm...>wrote:

> On 5/13/2013 3:54 PM, Keerthan jai.c wrote:
> > I suppose I could have done this:
> >
> > def mem_logic(clk, data, addr, we, q, mem):
> >      @always(clk.posedge)
> >      def logic():
> >          if we:
> >              mem[int(addr)].next = data
> >          else:
> >              q.next = mem[int(addr)]
> >      return logic
> >
> >
> > def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
> >                  we_a, we_b, q_a, q_b, depth=128):
> >      """Ram model"""
> >
> >      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
> >
> >      mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
> >      mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
> >
> >      return mem_a, mem_b
> >
> >
>
> Also valid:
>
>      ...
>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>      mem_ports = [None,None]
>      mem_ports[0] = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>      mem_ports[1] = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>
>      return mem_ports
>
> In addition, I am fairly sure, in this case you could do
> (would need to test first):
>
>      def DPR(clk pa, pb):
>          mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>          mem_ports = [None,None]
>          for inst,port in zip((mem_ports,(pa,pb)):
>              inst = mem_logic(clk, port.data, port.addr,
>                               port.we, port.q, mem
>          return mem_port
>
> NOTE! I did not test the above, I did not even
> check the syntax.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/13/2013 3:54 PM, Keerthan jai.c wrote:
> I suppose I could have done this:
>
> def mem_logic(clk, data, addr, we, q, mem):
>      @always(clk.posedge)
>      def logic():
>          if we:
>              mem[int(addr)].next = data
>          else:
>              q.next = mem[int(addr)]
>      return logic
>
>
> def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
>                  we_a, we_b, q_a, q_b, depth=128):
>      """Ram model"""
>
>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>
>      mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
>      mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)
>
>      return mem_a, mem_b
>
>

Also valid:

     ...
     mem = [Signal(intbv(0)[8:]) for i in range(depth)]
     mem_ports = [None,None]
     mem_ports[0] = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
     mem_ports[1] = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)

     return mem_ports

In addition, I am fairly sure, in this case you could do
(would need to test first):

     def DPR(clk pa, pb):
         mem = [Signal(intbv(0)[8:]) for i in range(depth)]
         mem_ports = [None,None]
         for inst,port in zip((mem_ports,(pa,pb)):
             inst = mem_logic(clk, port.data, port.addr,
                              port.we, port.q, mem
         return mem_port

NOTE! I did not test the above, I did not even
check the syntax.

Regards,
Chris

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

I suppose I could have done this:

def mem_logic(clk, data, addr, we, q, mem):
    @always(clk.posedge)
    def logic():
        if we:
            mem[int(addr)].next = data
        else:
            q.next = mem[int(addr)]
    return logic


def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
                we_a, we_b, q_a, q_b, depth=128):
    """Ram model"""

    mem = [Signal(intbv(0)[8:]) for i in range(depth)]

    mem_a = mem_logic(clk, data_a, addr_a, we_a, q_a, mem)
    mem_b = mem_logic(clk, data_b, addr_b, we_b, q_b, mem)

    return mem_a, mem_b


On Mon, May 13, 2013 at 4:18 PM, Norbo <Nor...@gm...> wrote:

>  From a RTL point of view the following code has the same functionallity.
> But be aware some synthesis tools need this specific way of writting the
> vhdl/verilog code inorder to
> succesfully infere a dual ported ram. But i think most of the newer tools
> will recognize.
>
>
> def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
>                  we_a, we_b, q_a, q_b, depth=128):
>      """Ram model"""
>
>      mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>
>      @always(clk.posedge)
>      def mem_both():
>          if we_b:
>              mem[int(addr_b)].next = data_b
>          else:
>              q_b.next = mem[int(addr_b)]
>
>         if we_a:
>              mem[int(addr_a)].next = data_a
>          else:
>              q_a.next = mem[int(addr_a)]
>
>      return mem_both
>
>
> best greets
> Norbo
>
>
> > Thanks, I will look at your examples.
> >
> > What about the two logic blocks mem_a and mem_b? They are essentially the
> > same logic, the only difference being their ports. Is there anyway to
> > make
> > that more elegant?
> > Is reducing the repetition of information a part of myhdl's vision?
> >
> >
> > On Mon, May 13, 2013 at 3:52 PM, Christopher Felton
> > <chr...@gm...>wrote:
> >
> >> On 5/13/2013 2:15 PM, Keerthan jai.c wrote:
> >> > Hi,
> >> >
> >> > I have been using myhdl for some time now, and while writing tests
> >> using
> >> > myhdl are clearly simpler and more powerful than using verilog/vhdl, I
> >> feel
> >> > like I am not able to exploit python for writing synthesizable code.
> >> >
> >> > For example, here is a description of a Dual ported ram:
> >> > https://gist.github.com/jck/00e016e0ff6baa0e7fbf
> >> >
> >> > As you can see, there seems to be a lot of repeated code. And
> >> additionally,
> >> > it feels like the way of handling variables(such as data_a, data_b
> >> rather
> >> > than a list of two elements) is unelegent/unpythonic.
> >>
> >> You mean repeated code in the port list (function
> >> arguments) and signals used?
> >>
> >> If this is mainly what you are talking about, not
> >> being able to have higher data structures, there are
> >> some options.  But some of this is limited by having
> >> to convert to V*, where they don't support similar
> >> constructs, so the conversion has to do a lot more
> >> work.  But with that said, we do have a MEP for
> >> interfaces (MEP-107) which I hope to address in 0.9-dev.
> >>
> >> In anticipation for MEP-107 implementation you can use
> >> attributes that are signals but you need to locally reference
> >> the signals, example:
> >>
> >>      def DualPortRam(clock, dpram_a, dpram_b):
> >>
> >>          (data_a,addr_a,
> >>           we_a,q_a,) = dpram_a.get_signals()
> >>          (data_b,addr_b,
> >>           we_b,q_b,) = dpram_b.get_signals()
> >>
> >>          ...
> >>
> >> Here is an example of a project where I used this technique:
> >> https://github.com/cfelton/minnesota
> >> https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
> >>
> >> In the future if we implement the interfaces you will be
> >> able to use /dpram_a.data/ directly.
> >>
> >> > Are there any python/myhdl techniques I could use to make this code
> >> more
> >> > elegant? Additionally, I would like to see your code examples where
> >> you
> >> > feel like the myhdl description is more elegant than conventional
> >> hdls,
> >> > either in single modules, or a systems of interconnected modules.
> >>
> >> For me I see the biggest gain when I am writing very
> >> parameterizable modules and more complicated modules,
> >> where it is hard to envision how these might even look
> >> in V*.  It typically includes a fair amount of computation
> >> code in the elaboration phase, a small example from
> >> DesignWest:
> >>
> >>
> >>
> https://bitbucket.org/cfelton/dw2013_examples/src/tip/iir_filter/iir_type1.py
> >>
> >>
> >> Regards,
> >> Chris
> >>
> >>
> >>
> >>
> ------------------------------------------------------------------------------
> >> AlienVault Unified Security Management (USM) platform delivers complete
> >> security visibility with the essential security capabilities. Easily and
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Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Norbo <Nor...@gm...>]

 From a RTL point of view the following code has the same functionallity.
But be aware some synthesis tools need this specific way of writting the  
vhdl/verilog code inorder to
succesfully infere a dual ported ram. But i think most of the newer tools  
will recognize.


def DualPortRAM(clk, data_a, data_b, addr_a, addr_b,
                 we_a, we_b, q_a, q_b, depth=128):
     """Ram model"""

     mem = [Signal(intbv(0)[8:]) for i in range(depth)]

     @always(clk.posedge)
     def mem_both():
         if we_b:
             mem[int(addr_b)].next = data_b
         else:
             q_b.next = mem[int(addr_b)]

	if we_a:
             mem[int(addr_a)].next = data_a
         else:
             q_a.next = mem[int(addr_a)]

     return mem_both


best greets
Norbo


> Thanks, I will look at your examples.
>
> What about the two logic blocks mem_a and mem_b? They are essentially the
> same logic, the only difference being their ports. Is there anyway to  
> make
> that more elegant?
> Is reducing the repetition of information a part of myhdl's vision?
>
>
> On Mon, May 13, 2013 at 3:52 PM, Christopher Felton
> <chr...@gm...>wrote:
>
>> On 5/13/2013 2:15 PM, Keerthan jai.c wrote:
>> > Hi,
>> >
>> > I have been using myhdl for some time now, and while writing tests  
>> using
>> > myhdl are clearly simpler and more powerful than using verilog/vhdl, I
>> feel
>> > like I am not able to exploit python for writing synthesizable code.
>> >
>> > For example, here is a description of a Dual ported ram:
>> > https://gist.github.com/jck/00e016e0ff6baa0e7fbf
>> >
>> > As you can see, there seems to be a lot of repeated code. And
>> additionally,
>> > it feels like the way of handling variables(such as data_a, data_b  
>> rather
>> > than a list of two elements) is unelegent/unpythonic.
>>
>> You mean repeated code in the port list (function
>> arguments) and signals used?
>>
>> If this is mainly what you are talking about, not
>> being able to have higher data structures, there are
>> some options.  But some of this is limited by having
>> to convert to V*, where they don't support similar
>> constructs, so the conversion has to do a lot more
>> work.  But with that said, we do have a MEP for
>> interfaces (MEP-107) which I hope to address in 0.9-dev.
>>
>> In anticipation for MEP-107 implementation you can use
>> attributes that are signals but you need to locally reference
>> the signals, example:
>>
>>      def DualPortRam(clock, dpram_a, dpram_b):
>>
>>          (data_a,addr_a,
>>           we_a,q_a,) = dpram_a.get_signals()
>>          (data_b,addr_b,
>>           we_b,q_b,) = dpram_b.get_signals()
>>
>>          ...
>>
>> Here is an example of a project where I used this technique:
>> https://github.com/cfelton/minnesota
>> https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
>>
>> In the future if we implement the interfaces you will be
>> able to use /dpram_a.data/ directly.
>>
>> > Are there any python/myhdl techniques I could use to make this code  
>> more
>> > elegant? Additionally, I would like to see your code examples where  
>> you
>> > feel like the myhdl description is more elegant than conventional  
>> hdls,
>> > either in single modules, or a systems of interconnected modules.
>>
>> For me I see the biggest gain when I am writing very
>> parameterizable modules and more complicated modules,
>> where it is hard to envision how these might even look
>> in V*.  It typically includes a fair amount of computation
>> code in the elaboration phase, a small example from
>> DesignWest:
>>
>>
>> https://bitbucket.org/cfelton/dw2013_examples/src/tip/iir_filter/iir_type1.py
>>
>>
>> Regards,
>> Chris
>>
>>
>>
>> ------------------------------------------------------------------------------
>> AlienVault Unified Security Management (USM) platform delivers complete
>> security visibility with the essential security capabilities. Easily and
>> efficiently configure, manage, and operate all of your security controls
>> from a single console and one unified framework. Download a free trial.
>> http://p.sf.net/sfu/alienvault_d2d
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>


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Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

Thanks, I will look at your examples.

What about the two logic blocks mem_a and mem_b? They are essentially the
same logic, the only difference being their ports. Is there anyway to make
that more elegant?
Is reducing the repetition of information a part of myhdl's vision?


On Mon, May 13, 2013 at 3:52 PM, Christopher Felton
<chr...@gm...>wrote:

> On 5/13/2013 2:15 PM, Keerthan jai.c wrote:
> > Hi,
> >
> > I have been using myhdl for some time now, and while writing tests using
> > myhdl are clearly simpler and more powerful than using verilog/vhdl, I
> feel
> > like I am not able to exploit python for writing synthesizable code.
> >
> > For example, here is a description of a Dual ported ram:
> > https://gist.github.com/jck/00e016e0ff6baa0e7fbf
> >
> > As you can see, there seems to be a lot of repeated code. And
> additionally,
> > it feels like the way of handling variables(such as data_a, data_b rather
> > than a list of two elements) is unelegent/unpythonic.
>
> You mean repeated code in the port list (function
> arguments) and signals used?
>
> If this is mainly what you are talking about, not
> being able to have higher data structures, there are
> some options.  But some of this is limited by having
> to convert to V*, where they don't support similar
> constructs, so the conversion has to do a lot more
> work.  But with that said, we do have a MEP for
> interfaces (MEP-107) which I hope to address in 0.9-dev.
>
> In anticipation for MEP-107 implementation you can use
> attributes that are signals but you need to locally reference
> the signals, example:
>
>      def DualPortRam(clock, dpram_a, dpram_b):
>
>          (data_a,addr_a,
>           we_a,q_a,) = dpram_a.get_signals()
>          (data_b,addr_b,
>           we_b,q_b,) = dpram_b.get_signals()
>
>          ...
>
> Here is an example of a project where I used this technique:
> https://github.com/cfelton/minnesota
> https://groups.google.com/forum/#!topic/fpgalink-users/P8q7texZqIQ
>
> In the future if we implement the interfaces you will be
> able to use /dpram_a.data/ directly.
>
> > Are there any python/myhdl techniques I could use to make this code more
> > elegant? Additionally, I would like to see your code examples where you
> > feel like the myhdl description is more elegant than conventional hdls,
> > either in single modules, or a systems of interconnected modules.
>
> For me I see the biggest gain when I am writing very
> parameterizable modules and more complicated modules,
> where it is hard to envision how these might even look
> in V*.  It typically includes a fair amount of computation
> code in the elaboration phase, a small example from
> DesignWest:
>
>
> https://bitbucket.org/cfelton/dw2013_examples/src/tip/iir_filter/iir_type1.py
>
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck