myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Assignment to arbitrary bits of an intbv

[Christopher F. <chr...@gm...>]

On 5/23/2013 5:37 AM, Alastair McKinley wrote:
> Hi all,
>
> I have just started looking in myHDL and am quite excited about it's
> potential.
>
> I have a short question about assignment to intbv objects. I want to model
> closely a reference VHDL implementation which has a 128 bit input from a
> DMA engine.
>
<snip>
>
> The input signal to my module doesn't change in this case.
>
> What is the right way to do this in myHDL?
>
> Best regards,
>
> Alastair
>

Alastair,

Your example is incomplete, you don't show how you
define (instantiate) /inData/.  If inData is simply,
(as you imply):

     inData = Signal(intbv(0)[128:])

Then you have a small syntax error:

     inData[32:0].next = ...
     inData[64:32].next = ...

should be,

     inData.next[32:0] = ...
     inData.next[64:32] = ...


The syntax /inData[].next/ and /inData.next[]/ is the
difference between a list of signal item selection and
the bit vector bit selection.

Hope that helps,
Chris

[myhdl-list] Assignment to arbitrary bits of an intbv

[Alastair M. <amc...@go...>]

Hi all,

I have just started looking in myHDL and am quite excited about it's
potential.

I have a short question about assignment to intbv objects. I want to model
closely a reference VHDL implementation which has a 128 bit input from a
DMA engine.

4*32 bit words are input on the 128 bit interface.  I can't seem to figure
out how to achieve this is myHDL.

I've illustrated this in the following testbench.

def TestBench(clk,reset,inData):

        tb_dut = module(clk, reset,inData)
        data = [i for i in range(0,12)]

        @always(delay(1))
        def tb_clkgen():
                clk.next = not clk

        @instance
        def tb_stim():
                reset.next = True
                yield delay(2)
                reset.next = False

                yield clk.posedge

                for i in range(0,3):
                        inData[32:0].next = data[4*i]
                        inData[64:32].next = data[4*i+1]
                        inData[96:64].next = data[4*i+2]
                        inData[128:96].next = data[4*i+3]
                        yield clk.posedge

                raise StopSimulation

        return tb_dut, tb_clkgen, tb_stim

The input signal to my module doesn't change in this case.

What is the right way to do this in myHDL?

Best regards,

Alastair

Re: [myhdl-list] myhdl_cores

[Christopher F. <chr...@gm...>]

<snip>
>>
>> This is something I think could benefit from some lively
>> conversation and experimentation.  I have gone down this
>> path a bunch of time and posted examples.  I have implemented
>> various control buses (i.e. mem-map buses) for different
>> projects.  In my mind we should be able to come up with a
>> very elegant control bus interface which includes a flexible
>> method to define the register file for each component on the
>> control bus.
>
> I guess some of us were working on the same issues on our projects;
> that's another motivation for the index and group develop.
>
> I proposed my bus library initially as a "test" for this procedure,
> but I also want it to be a useful library. In fact, I have a lot of
> clean-up and re-factor to do, so I'd be glad to hear feedback about
> it.
>
> By the way I forgot the link in the previous email:
>
> https://bitbucket.org/dargor0/myhdl_buslib
>

Here is an example I tried to put together, never quite
finished.  I was hoping this would be an example for the
interface efforts we have been discussing.

https://bitbucket.org/cfelton/examples/src/tip/simple

It will be a couple days before I can review your code and
contrast it the above example.

Regards,
Chris

Re: [myhdl-list] myhdl_cores

[Oscar D. D. <osc...@gm...>]

El Wed, 22 May 2013 09:12:43 -0500
Christopher Felton <chr...@gm...> escribió:

> <snip>
> >> But it is easy to talk about this stuff and throw some ideas
> >> around but it is some work to actually put it all together.  I
> >> would be supportive and could move a bunch of my stuff to the
> >> repo, if one was put together and it looked promising.
> >
> > Fair enough. Right now I'm working on a library for wishbone and
> > AXI4 bus support (I'm still working on the test and documentation),
> > and of course I'll use bitbucket. What I propose is:
> >
> > * Start with a bitbucket repo
> > * Comply with guidelines (for example, require documentation and
> > test suites)
> > * Add an entry to the index wiki
> > * If someone wants to contribute with that particular module, use
> >    bitbucket groups.
> >
> > I'm planing to write a guideline draft and an index template. But
> > let me check Sphinx first.
> >
> > Best regards,
> >
> 
> This is something I think could benefit from some lively
> conversation and experimentation.  I have gone down this
> path a bunch of time and posted examples.  I have implemented
> various control buses (i.e. mem-map buses) for different
> projects.  In my mind we should be able to come up with a
> very elegant control bus interface which includes a flexible
> method to define the register file for each component on the
> control bus.

I guess some of us were working on the same issues on our projects;
that's another motivation for the index and group develop.

I proposed my bus library initially as a "test" for this procedure,
but I also want it to be a useful library. In fact, I have a lot of
clean-up and re-factor to do, so I'd be glad to hear feedback about
it.

By the way I forgot the link in the previous email:

https://bitbucket.org/dargor0/myhdl_buslib

> 
> Regards,
> Chris
> 
> 
> 
> 
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Best regards,

-- 
Oscar Díaz
Key Fingerprint = 904B 306C C3C2 7487 650B  BFAC EDA2 B702 90E9 9964
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[myhdl-list] myhdl_cores

[Christopher F. <chr...@gm...>]

On 5/20/2013 6:30 PM, Oscar Daniel Diaz wrote:
> El Fri, 17 May 2013 13:07:30 -0500
> Christopher Felton <chr...@gm...> escribió:
>
>>> I was thinking on making a module index on the wiki; with module
>>> descriptions and some search keywords. The current mechanism is the
>>> user's pages and its own descriptions of their projects.
>>
>> There is a little bit of this in the user-space, but to have
>> a dedicated page with a module link and short description
>> and, maybe, a few checkboxes like open-cores (model,
>> convertible, ect) would be an straightforward way to get
>> going.  There have been a few useful modules posted to
>> the mailing-list (I think only exist on the mailing list).
>>
>>>
>>> Also, I think we should define some coding guidelines for the
>>> modules to be included on the index, so we have basic quality
>>> standard.
>>
>> There has been past discussions if it would be possible
>> to create an open-cores like site with a bunch of myhdl
>> modules.  If you have a site with this goal you can have
>> guidelines etc (I would like to see complete tests more
>> than syntax guidelines as a requirement).  But you would
>> need someone fairly dedicated to build the site.
>
> Fair enough, but I think we can all contribute to build this "page" in
> a wiki way, at least at beginning.
>

I agree the wiki page is an easy way to get going.

<snip>
>> But it is easy to talk about this stuff and throw some ideas
>> around but it is some work to actually put it all together.  I
>> would be supportive and could move a bunch of my stuff to the
>> repo, if one was put together and it looked promising.
>
> Fair enough. Right now I'm working on a library for wishbone and AXI4
> bus support (I'm still working on the test and documentation), and of
> course I'll use bitbucket. What I propose is:
>
> * Start with a bitbucket repo
> * Comply with guidelines (for example, require documentation and test
>    suites)
> * Add an entry to the index wiki
> * If someone wants to contribute with that particular module, use
>    bitbucket groups.
>
> I'm planing to write a guideline draft and an index template. But let
> me check Sphinx first.
>
> Best regards,
>

This is something I think could benefit from some lively
conversation and experimentation.  I have gone down this
path a bunch of time and posted examples.  I have implemented
various control buses (i.e. mem-map buses) for different
projects.  In my mind we should be able to come up with a
very elegant control bus interface which includes a flexible
method to define the register file for each component on the
control bus.

Regards,
Chris

Re: [myhdl-list] Proposal: New class, ClockDomain

[Oscar D. D. <osc...@gm...>]

El Fri, 17 May 2013 13:07:30 -0500
Christopher Felton <chr...@gm...> escribió:

> > I was thinking on making a module index on the wiki; with module
> > descriptions and some search keywords. The current mechanism is the
> > user's pages and its own descriptions of their projects.
> 
> There is a little bit of this in the user-space, but to have
> a dedicated page with a module link and short description
> and, maybe, a few checkboxes like open-cores (model,
> convertible, ect) would be an straightforward way to get
> going.  There have been a few useful modules posted to
> the mailing-list (I think only exist on the mailing list).
> 
> >
> > Also, I think we should define some coding guidelines for the
> > modules to be included on the index, so we have basic quality
> > standard.
> 
> There has been past discussions if it would be possible
> to create an open-cores like site with a bunch of myhdl
> modules.  If you have a site with this goal you can have
> guidelines etc (I would like to see complete tests more
> than syntax guidelines as a requirement).  But you would
> need someone fairly dedicated to build the site.

Fair enough, but I think we can all contribute to build this "page" in
a wiki way, at least at beginning.

> > Another option is to use bitbucket features for group develop, I'm
> > checking what bitbucket offers for multi-users.
> 
> You can look at other projects like pypy hosted on bitbucket,
> bitbucket does have "groups", I think this is a simple way
> to control permissions/access.  Example, you could create
> a group, /myhdl_cores/ (or whatever) and have myhdl_cores_public
> repository that you give permissions to a large group.

I checked bitbucket groups: that's a very nice way for group
development. 

> The documentation for the cores can be in sphinx and you can
> post/host it on "readthedocs".  It would be useful/interesting
> to have nightly builds where the cores are checked for changes
> and if so the tests are run against the cores.  You can have a
> real-time status of which cores are stable (ish).
> 
> But it is easy to talk about this stuff and throw some ideas
> around but it is some work to actually put it all together.  I
> would be supportive and could move a bunch of my stuff to the
> repo, if one was put together and it looked promising.

Fair enough. Right now I'm working on a library for wishbone and AXI4
bus support (I'm still working on the test and documentation), and of
course I'll use bitbucket. What I propose is:

* Start with a bitbucket repo
* Comply with guidelines (for example, require documentation and test
  suites) 
* Add an entry to the index wiki
* If someone wants to contribute with that particular module, use
  bitbucket groups.

I'm planing to write a guideline draft and an index template. But let
me check Sphinx first.

Best regards,

-- 
Oscar Díaz
Key Fingerprint = 904B 306C C3C2 7487 650B  BFAC EDA2 B702 90E9 9964
gpg --keyserver subkeys.pgp.net --recv-keys 90E99964

I recommend using OpenDocument Format
for daily use and exchange of documents.

http://www.fsf.org/campaigns/opendocument

[myhdl-list] 0.8 released

[Jan D. <ja...@ja...>]

All:

I have just released 0.8.

It is on SourceForge as usual, but of course
you can also download from the tag on Bitbucket.

The Bitbucket repo is the main repo from now
on, I have update the development pages on
myhdl.org accordingly.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl ebuild for gentoo user

[Jan D. <ja...@ja...>]

Thoma:

such installation files should use the latest download
url on SourceForge, not a mercurial repo.

BTW, the repo on myhdl.org may disappear. There is a
mirror on SourceForge, and the main one is on Bitbucket
in the mean time.

With the release of 0.8 today, I have update the docs
about that on myhdl.org accordingly.

Also, please just send me the file - I have no idea
how it should be called but probably the filename
matters.


On 05/20/2013 05:18 PM, Thoma HAUC wrote:
> Hello Jan,
>
> If you put the file provided through pastebin, Gentoo GNU/Linux user will be
> able to install quickly myhdl on their system.
>
> So, if it is possible for you to put this file on the "Installation
> instructions" of the myhdl website, it will probably help Gentoo GNU/Linux
> user.
>
> Regards,
>
> Thoma
>
>
> Jan Decaluwe wrote:
>
>> What is it exactly that you want me to do with it?
>>
>> On 05/20/2013 11:13 AM, Thoma HAUC wrote:
>>> Hello Jan,
>>>
>>> Here is a little contribution. This gentoo ebuild use the default
>>> mecurial repository of your myhdl project.
>>>
>>> http://pastebin.com/rkM0WKCM
>>>
>>> Could you made that available for the myhdl and gentoo user of the
>>> website?
>>>
>>> Thanks in advance.
>>>
>>> Thoma
>>>
>>>
>>>
> ------------------------------------------------------------------------------
>>> AlienVault Unified Security Management (USM) platform delivers complete
>>> security visibility with the essential security capabilities. Easily and
>>> efficiently configure, manage, and operate all of your security controls
>>> from a single console and one unified framework. Download a free trial.
>>> http://p.sf.net/sfu/alienvault_d2d
>>>
>>
>>
>
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] myhdl ebuild for gentoo user

[Thoma H. <tho...@gm...>]

Hello Jan,

If you put the file provided through pastebin, Gentoo GNU/Linux user will be 
able to install quickly myhdl on their system.

So, if it is possible for you to put this file on the "Installation 
instructions" of the myhdl website, it will probably help Gentoo GNU/Linux 
user.

Regards,

Thoma


Jan Decaluwe wrote:

> What is it exactly that you want me to do with it?
> 
> On 05/20/2013 11:13 AM, Thoma HAUC wrote:
>> Hello Jan,
>>
>> Here is a little contribution. This gentoo ebuild use the default
>> mecurial repository of your myhdl project.
>>
>> http://pastebin.com/rkM0WKCM
>>
>> Could you made that available for the myhdl and gentoo user of the
>> website?
>>
>> Thanks in advance.
>>
>> Thoma
>>
>>
>> 
------------------------------------------------------------------------------
>> AlienVault Unified Security Management (USM) platform delivers complete
>> security visibility with the essential security capabilities. Easily and
>> efficiently configure, manage, and operate all of your security controls
>> from a single console and one unified framework. Download a free trial.
>> http://p.sf.net/sfu/alienvault_d2d
>>
> 
> 

Re: [myhdl-list] MyHDL and Python 3.x

[Thoma H. <tho...@gm...>]

Hello Jan,

Many thanks for your quick answer.

Regards,

Thoma

Jan Decaluwe wrote:

> No, and that will take some time.
> 
> In the next development cycle (0.9-dev), I plan
> to start preparing the code base by making
> it as Python 3 compatible as possible.
> 
> On 05/19/2013 12:25 PM, Thoma HAUC wrote:
>> Hello,
>>
>> Is MyHDL compatible with Python 3?
>> I tried to install MyHDL 0.7 with Python 3.2 but without success
>> (setup.py uses the pre-Python 3.x syntax)
>>
>> Thank you in advance.
>>
>> Thoma
>>
>>
>> 
------------------------------------------------------------------------------
>> AlienVault Unified Security Management (USM) platform delivers complete
>> security visibility with the essential security capabilities. Easily and
>> efficiently configure, manage, and operate all of your security controls
>> from a single console and one unified framework. Download a free trial.
>> http://p.sf.net/sfu/alienvault_d2d
>>
> 
> 

Re: [myhdl-list] myhdl ebuild for gentoo user

[Jan D. <ja...@ja...>]

What is it exactly that you want me to do with it?

On 05/20/2013 11:13 AM, Thoma HAUC wrote:
> Hello Jan,
>
> Here is a little contribution. This gentoo ebuild use the default mecurial
> repository of your myhdl project.
>
> http://pastebin.com/rkM0WKCM
>
> Could you made that available for the myhdl and gentoo user of the website?
>
> Thanks in advance.
>
> Thoma
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Development status 0.8

[Jan D. <ja...@ja...>]

Thanks!

On 05/20/2013 05:03 AM, Christopher Felton wrote:
> On 5/13/13 11:14 AM, Jan Decaluwe wrote:
>> I have merged 0.8-dev in the default branch
>> and changed the version number to 0.8. The 0.8 release
>> will be tagged and maintained from the default branch.
>>
>> I'll give it a few more days to make sure some recent
>> changes don't break existing designs (all tests pass
>> of course, as well as my own design) and to review the docs.
>> Thanks to Chris for helping with the documentation.
>>
>> The main repo is now on bitbucket.
>>
>> I will also update the development process docs
>> on the wiki accordingly.
>>
>> https://bitbucket.org/jandecaluwe/myhdl
>>
>> Jan
>>
>
> I used the 0.8 trunk and ran it against a bunch
> of projects and didn't uncover any issues.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL and Python 3.x

[Jan D. <ja...@ja...>]

No, and that will take some time.

In the next development cycle (0.9-dev), I plan
to start preparing the code base by making
it as Python 3 compatible as possible.

On 05/19/2013 12:25 PM, Thoma HAUC wrote:
> Hello,
>
> Is MyHDL compatible with Python 3?
> I tried to install MyHDL 0.7 with Python 3.2 but without success (setup.py
> uses the pre-Python 3.x syntax)
>
> Thank you in advance.
>
> Thoma
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] myhdl ebuild for gentoo user

[Thoma H. <tho...@gm...>]

Hello Jan,

Here is a little contribution. This gentoo ebuild use the default mecurial 
repository of your myhdl project.

http://pastebin.com/rkM0WKCM

Could you made that available for the myhdl and gentoo user of the website?

Thanks in advance.

Thoma

Re: [myhdl-list] Development status 0.8

[Christopher F. <chr...@gm...>]

On 5/13/13 11:14 AM, Jan Decaluwe wrote:
> I have merged 0.8-dev in the default branch
> and changed the version number to 0.8. The 0.8 release
> will be tagged and maintained from the default branch.
>
> I'll give it a few more days to make sure some recent
> changes don't break existing designs (all tests pass
> of course, as well as my own design) and to review the docs.
> Thanks to Chris for helping with the documentation.
>
> The main repo is now on bitbucket.
>
> I will also update the development process docs
> on the wiki accordingly.
>
> https://bitbucket.org/jandecaluwe/myhdl
>
> Jan
>

I used the 0.8 trunk and ran it against a bunch
of projects and didn't uncover any issues.

Regards,
Chris

[myhdl-list] MyHDL and Python 3.x

[Thoma H. <tho...@gm...>]

Hello,

Is MyHDL compatible with Python 3?
I tried to install MyHDL 0.7 with Python 3.2 but without success (setup.py 
uses the pre-Python 3.x syntax)

Thank you in advance.

Thoma

Re: [myhdl-list] Proposal: New class, ClockDomain

[Christopher L. <loz...@fr...>]

On 5/17/13 12:23 PM, Oscar Daniel Diaz wrote:
> I was thinking on making a module index on the wiki; with module
> descriptions and some search keywords. The current mechanism is the
> user's pages and its own descriptions of their projects.
That is a great idea.

There are probably more classes available than any one of us know
about.  And they are all over the place, git, mercurial, tarballs.

It just needs a brief high level description, and a link to the source
code for more information.   A pypi link if they are using that
distribution method. Or a link to the home page for the product, or
article.

Of course the ability to rate modules would be great.  Dependencies
would be great.  But at least a listing of hardware modules would be a
start.

You can start with a brief description of the classes you wrote, and a
link to their location, and to the article you wrote.

-- 
 I run
http://Django.SpecialtyJobMarkets.com

Regards
Christopher Lozinski

The future of Zope
http://ZOPACHE.COM

On Digital Design
http://OOHDL.COM

Re: [myhdl-list] Proposal: New class, ClockDomain

[Christopher F. <chr...@gm...>]

On 5/17/13 12:23 PM, Oscar Daniel Diaz wrote:
> El Wed, 15 May 2013 09:29:15 +0200
> Jan Decaluwe <ja...@ja...> escribió:
>
>> On 05/15/2013 03:47 AM, Christopher Lozinski wrote:
>>>    Clock domain is a great idea.
>>>
>>> There should be a rich and interesting library of Hardware modules
>>> available as a library in MyHDL.
>>
>> Of course there should not.
>>
>> Unlike Python, it is totally unclear how a "standard" library for
>> MyHDL should look like.
>>
>> Guido himself recently explained how the concept of the Python
>> standard library is frequently misunderstood. The Python standard
>> library is like a minimum set of generally useful functionality,
>> on which there is basically a consensus.
>>
>> However, being in the standard library is not a blessing. It takes
>> ages, and you have comply with all kinds of Python-release related
>> restrictions. I certainly would not want MyHDL to be in the
>> Python standard library. For innovation, you don't want a
>> standard library.
>>
>> For the record, I am of course all of for "rich and interesting
>> libraries of MyHDL hardware modules" - plenty of them, including
>> competing ones. Just do not look at me or the MyHDL library itself for
>> that - I am doing my share and I have many other plans.
>
> Totally agree. Lately I though about how to gather different
> contributions into one (or several) modules.
>
> I was thinking on making a module index on the wiki; with module
> descriptions and some search keywords. The current mechanism is the
> user's pages and its own descriptions of their projects.

There is a little bit of this in the user-space, but to have
a dedicated page with a module link and short description
and, maybe, a few checkboxes like open-cores (model,
convertible, ect) would be an straightforward way to get
going.  There have been a few useful modules posted to
the mailing-list (I think only exist on the mailing list).

>
> Also, I think we should define some coding guidelines for the modules
> to be included on the index, so we have basic quality standard.

There has been past discussions if it would be possible
to create an open-cores like site with a bunch of myhdl
modules.  If you have a site with this goal you can have
guidelines etc (I would like to see complete tests more
than syntax guidelines as a requirement).  But you would
need someone fairly dedicated to build the site.

>
> Another option is to use bitbucket features for group develop, I'm
> checking what bitbucket offers for multi-users.

You can look at other projects like pypy hosted on bitbucket,
bitbucket does have "groups", I think this is a simple way
to control permissions/access.  Example, you could create
a group, /myhdl_cores/ (or whatever) and have myhdl_cores_public
repository that you give permissions to a large group.

The documentation for the cores can be in sphinx and you can
post/host it on "readthedocs".  It would be useful/interesting
to have nightly builds where the cores are checked for changes
and if so the tests are run against the cores.  You can have a
real-time status of which cores are stable (ish).

But it is easy to talk about this stuff and throw some ideas
around but it is some work to actually put it all together.  I
would be supportive and could move a bunch of my stuff to the
repo, if one was put together and it looked promising.

Regards,
Chris

Re: [myhdl-list] Proposal: New class, ClockDomain

[Oscar D. D. <osc...@gm...>]

El Wed, 15 May 2013 09:29:15 +0200
Jan Decaluwe <ja...@ja...> escribió:

> On 05/15/2013 03:47 AM, Christopher Lozinski wrote:
> >   Clock domain is a great idea.
> >
> > There should be a rich and interesting library of Hardware modules
> > available as a library in MyHDL.
> 
> Of course there should not.
> 
> Unlike Python, it is totally unclear how a "standard" library for
> MyHDL should look like.
> 
> Guido himself recently explained how the concept of the Python
> standard library is frequently misunderstood. The Python standard
> library is like a minimum set of generally useful functionality,
> on which there is basically a consensus.
> 
> However, being in the standard library is not a blessing. It takes
> ages, and you have comply with all kinds of Python-release related
> restrictions. I certainly would not want MyHDL to be in the
> Python standard library. For innovation, you don't want a
> standard library.
> 
> For the record, I am of course all of for "rich and interesting
> libraries of MyHDL hardware modules" - plenty of them, including
> competing ones. Just do not look at me or the MyHDL library itself for
> that - I am doing my share and I have many other plans.

Totally agree. Lately I though about how to gather different
contributions into one (or several) modules.

I was thinking on making a module index on the wiki; with module
descriptions and some search keywords. The current mechanism is the
user's pages and its own descriptions of their projects. 

Also, I think we should define some coding guidelines for the modules
to be included on the index, so we have basic quality standard.

Another option is to use bitbucket features for group develop, I'm
checking what bitbucket offers for multi-users.

> 
> Nothing prevents you or anyone to make your hands dirty and
> start with it today. Let's stop the high-level talk and get
> to work.
> 

Best regards, 

-- 
Oscar Díaz
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Re: [myhdl-list] VHDL_Analyzer tool

[Oscar D. D. <osc...@gm...>]

El Mon, 13 May 2013 13:11:29 -0500
Christopher Felton <chr...@gm...> escribió:

> On Mon, May 13, 2013 at 12:55 PM, Angel Ezquerra
> <ang...@gm...>wrote:
> 
> > On Mon, May 13, 2013 at 7:06 PM, Christopher Felton
> > <chr...@gm...> wrote:
> > > On 5/13/2013 11:47 AM, Angel Ezquerra wrote:
> > >>>
> > >>> Why did you decide to use pydot over networkx?
> > >>
> > >> The only reason is that I had used pydot in the past and it had
> > >> worked reasonably well, so it was easy for me to use that. I had
> > >> heard of networkx but I had never used it before.
> > >
> > > As good as reasons as any.
> > >
> > >>
> > >> I've quicky skimmed the netwokx docs and it seems quite similar
> > >> to pydot. Does it also need graphviz? Are there any advantages
> > >> to using networkx over pydot, other than the fact that is being
> > >> more actively maintained?
> > >>
> > >> Also, did you get a chance to actually test the tool? Any
> > >> thoughts on
> > it?

I've been using networkx from couple years on my project [1], I
recommend it, not only is a great tool for graph management and
calculus, but also it has several graphic frontends (including
graphviz). Perhaps the only issue with networkx is that graph
visualization is a bit more complex than pydot.

> > >>
> > >
> > > No, I don't have a project that I could/would use
> > > it on right now.  I was more curious if it could
> > > be useful as a MyHDL tool :)  If I could leverage
> > > the work you did for creating graphs etc and use
> > > it to generate similar analysis for MyHDL projects,
> > > simply to create visuals for a design.
> >
> > You could start by running the tool on the VHDL that MyHDL
> > generates :-D
> >
> > I don't recall whether MyHDL issues case statements? The tool looks
> > for state machines by looking for case statements within processes,
> > so if that is not the case it would not work :-/
> >
> 
> It does, unfortunately not my interest right now to analyze
> some VHDL code.  Also, tools like Aldec and even the synthesis
> RTL viewers do a good job of extracting state-machines and providing
> state diagrams.  But what I do like about the dot language, if I
> export the dot description I can import into other tools and edit it
> for final documentation.
> 
> 
> >
> > Also, since the MyHDL converter (parser?) already generates an AST
> > tree (I think!) from the MyHDL code, a similar approach to what I
> > did could be used, but it would probably be much easier and more
> 
> accurate...
> >
> 
> My thought without digging into it would be to ignore the
> front-end parsing portion and only use the backend parts.
> Yes, with myhdl and the python parsing, you could simply
> use the myhdl "enums" to identify a state-machine and
> produce the nice little state-diagrams.
> 
> Regards,
> Chris


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Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Christopher F. <chr...@gm...>]

On 5/15/2013 3:08 PM, Keerthan jai.c wrote:
>> This is a typical difficulty: with limited RTL experience it
>> is often difficult to make the distinction between limitations
>> imposed by synthesis, and MyHDL itself.
>
> This is true, I ended up doing proof of concept work in verilog and
> migrated to myhdl to use python for algorithmic data generation. MyHDL
> certainly facilitates fine grained control for distributing data across
> memories.
>
>
>> I'm sure people will be interested in reviewing your code and
>> giving feedback.
> It is a funded project, so I will have to look into the terms. I will try
> to share the code with the community ASAP!
>
>> But there's the point already. Those arbitrary data structures are
>> not there as such in Verilog/VHDL. So there is the nontrivial difficulty
>> on how to map them into those target languages, and how generic
>> this should be.
> It is implied that references to these data structures should point to
> MyHDL primitives.
> For example, MemorySubsystem['a'].tag_memory[2].dout, which is a MyHDL
> Signal object. (Overly complex example to show the possibilities). I will
> search the mailing list and codify my ideas sometime next month.
>

Here are some links and short description:

This was the first proposal to the mailing-list:
http://thread.gmane.org/gmane.comp.python.myhdl/2191/focus=2515

The MEP was first posted to the mailingl=list some discussion
and then was created on the wiki.  Here is Jan's first assessment
of the MEP after the first wiki write-up (I think that is the
correct order of things).
http://thread.gmane.org/gmane.comp.python.myhdl/2659

Second assessment after some changes and conversations:
http://thread.gmane.org/gmane.comp.python.myhdl/2690

A follow-up by me based on what is currently supported:
http://thread.gmane.org/gmane.comp.python.myhdl/2698

An inquiry about MEP-107 status:
http://thread.gmane.org/gmane.comp.python.myhdl/2794/focus=2797

A recap
http://permalink.gmane.org/gmane.comp.python.myhdl/2959

I think that is most of them,
Chris Felton

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

>This is a typical difficulty: with limited RTL experience it
>is often difficult to make the distinction between limitations
>imposed by synthesis, and MyHDL itself.

This is true, I ended up doing proof of concept work in verilog and
migrated to myhdl to use python for algorithmic data generation. MyHDL
certainly facilitates fine grained control for distributing data across
memories.


>I'm sure people will be interested in reviewing your code and
>giving feedback.
It is a funded project, so I will have to look into the terms. I will try
to share the code with the community ASAP!

>But there's the point already. Those arbitrary data structures are
>not there as such in Verilog/VHDL. So there is the nontrivial difficulty
>on how to map them into those target languages, and how generic
>this should be.
It is implied that references to these data structures should point to
MyHDL primitives.
For example, MemorySubsystem['a'].tag_memory[2].dout, which is a MyHDL
Signal object. (Overly complex example to show the possibilities). I will
search the mailing list and codify my ideas sometime next month.





On Wed, May 15, 2013 at 3:35 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 05/15/2013 09:08 PM, Keerthan jai.c wrote:
>
> >> To remove doubts, you could perhaps tell a little more about
> >> yourself, your experience, past projects, etc.
>
> > I'm a computer engineering graduate student and my academic focus is
> > on computer architectures and acclerating algorithms using FPGAs. I
> > am an inexperienced RTL Developer. Currently my past projects and
> > experience in RTL are limited to minor academic and personal
> > projects.
>
> This is a typical difficulty: with limited RTL experience it
> is often difficult to make the distinction between limitations
> imposed by synthesis, and MyHDL itself.
>
> Unfortunately, the reason is that RTL is not very well documented
> for beginners. Also unfortunately, it implies that MyHDL is not
> necessarily a good way for beginners to learn HDL design.
> I wish it were different, but that's the way it is.
>
> >  However, I will be open-sourcing a slightly complex
> > application early next month(A lot of it is written with MyHDL!). I'm
> > currently in the process of cleaning up its code before documenting
> > it and packaging it.
>
> Excellent. You are an active user. We're listening.
>
> I'm sure people will be interested in reviewing your code and
> giving feedback.
>
> >> Secondly, the convertor is not a synthesis tool - it maintains the
> >> abstraction level. Therefore, there has to be some way to map
> >> supported MyHDL code to Verilog/VHDL in a reasonably direct way.
> >> Hence the supported primitives are defined by those that exist in
> >> the target languages.
>
> > I understand this. I do not mean that the converter should work with
> > arbitrary python code. It should however be able to handle arbitrary
> > data structures (MEP 107).
>
> But there's the point already. Those arbitrary data structures are
> not there as such in Verilog/VHDL. So there is the nontrivial difficulty
> on how to map them into those target languages, and how generic
> this should be.
>
> As for your investigation, it may be a good idea to start by
> reviewing all the past communications on the issue.
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
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> _______________________________________________
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Jan D. <ja...@ja...>]

On 05/15/2013 09:08 PM, Keerthan jai.c wrote:

>> To remove doubts, you could perhaps tell a little more about
>> yourself, your experience, past projects, etc.

> I'm a computer engineering graduate student and my academic focus is
> on computer architectures and acclerating algorithms using FPGAs. I
> am an inexperienced RTL Developer. Currently my past projects and
> experience in RTL are limited to minor academic and personal
> projects.

This is a typical difficulty: with limited RTL experience it
is often difficult to make the distinction between limitations
imposed by synthesis, and MyHDL itself.

Unfortunately, the reason is that RTL is not very well documented
for beginners. Also unfortunately, it implies that MyHDL is not
necessarily a good way for beginners to learn HDL design.
I wish it were different, but that's the way it is.

>  However, I will be open-sourcing a slightly complex
> application early next month(A lot of it is written with MyHDL!). I'm
> currently in the process of cleaning up its code before documenting
> it and packaging it.

Excellent. You are an active user. We're listening.

I'm sure people will be interested in reviewing your code and
giving feedback.

>> Secondly, the convertor is not a synthesis tool - it maintains the
>> abstraction level. Therefore, there has to be some way to map
>> supported MyHDL code to Verilog/VHDL in a reasonably direct way.
>> Hence the supported primitives are defined by those that exist in
>> the target languages.

> I understand this. I do not mean that the converter should work with
> arbitrary python code. It should however be able to handle arbitrary
> data structures (MEP 107).

But there's the point already. Those arbitrary data structures are
not there as such in Verilog/VHDL. So there is the nontrivial difficulty
on how to map them into those target languages, and how generic
this should be.

As for your investigation, it may be a good idea to start by
reviewing all the past communications on the issue.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Keerthan jai.c <jck...@gm...>]

>There is no hostility.  There is directness because
>It's really a matter of efficiency.
I understand, I apologize for jumping to conclusions.

>You need to be careful of generalities
Thanks, I'll keep that in mind henceforth

>To remove doubts, you could perhaps tell a little more
>about yourself, your experience, past projects, etc.
I'm a computer engineering graduate student and my academic focus is on
computer architectures and acclerating algorithms using FPGAs. I am an
inexperienced RTL Developer. Currently my past projects and experience in
RTL are limited to minor academic and personal projects. However, I will be
open-sourcing a slightly complex application early next month(A lot of it
is written with MyHDL!). I'm currently in the process of cleaning up its
code before documenting it and packaging it.

My programming skills are adequate and I've written non trivial
applications such as a compiler. I'm very passionate about the open source
movement and I want to start contributing.


>Secondly, the convertor is not a synthesis tool - it maintains
>the abstraction level. Therefore, there has to be some way to
>map supported MyHDL code to Verilog/VHDL in a reasonably direct
>way. Hence the supported primitives are defined by those that
>exist in the target languages.
I understand this. I do not mean that the converter should work with
arbitrary python code. It should however be able to handle arbitrary data
structures (MEP 107). I have some ideas which are not well formed about how
this might be acheived without complicating the AST parser. I have free
time next month, so i'll dig deeper and let you guys know.




On Wed, May 15, 2013 at 1:13 PM, Jan Decaluwe <ja...@ja...> wrote:

> On 05/15/2013 06:06 PM, Keerthan jai.c wrote:
>
> > In the earlier post, I specifically asked whether things like this
> > were a part of MyHDL's vision. Are you saying that conversion for
> > synthesis is of minor importance to the project?
>
> Of course not. I am simply saying there is more to MyHDL than
> conversion, and reducing MyHDL to restrictions imposed
> byconversion misses the point.
>
> I am stressing this because this mistake is being make continuously.
>
> >> Of course I think using the AST is the best approach for my goal.
> >> What did you expect me to say?
> > After an initial examination of the source code, the conversion code
> > felt cumbersome to me. I asked this question because you mentioned
> > "as conversion is here and there already to tricky to my taste".
>
> Yes I have said it is tricky in some places - but why
> would that contradict the fact that it may be the best approach for
> the goal? (converting behavior to behavior)
>
> >>> I think, in a language like python, where everything is an
> >>> object, looking only at variable names feels a bit fragile.
> >> I have no idea what you mean here. The convertor is looking at the
> >> details of every object behind a name.
> > I meant this with regards to how the converter needs that all the
> > variables are MyHDL primitives.
>
> First, it uses Python concepts such as lists and tuples as
> much as possible.
>
> Secondly, the convertor is not a synthesis tool - it maintains
> the abstraction level. Therefore, there has to be some way to
> map supported MyHDL code to Verilog/VHDL in a reasonably direct
> way. Hence the supported primitives are defined by those that
> exist in the target languages.
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> AlienVault Unified Security Management (USM) platform delivers complete
> security visibility with the essential security capabilities. Easily and
> efficiently configure, manage, and operate all of your security controls
> from a single console and one unified framework. Download a free trial.
> http://p.sf.net/sfu/alienvault_d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] What techniques can I use to avoid repeating myself in myhdl code?

[Jan D. <ja...@ja...>]

On 05/15/2013 06:06 PM, Keerthan jai.c wrote:

> In the earlier post, I specifically asked whether things like this
> were a part of MyHDL's vision. Are you saying that conversion for
> synthesis is of minor importance to the project?

Of course not. I am simply saying there is more to MyHDL than
conversion, and reducing MyHDL to restrictions imposed
byconversion misses the point.

I am stressing this because this mistake is being make continuously.

>> Of course I think using the AST is the best approach for my goal.
>> What did you expect me to say?
> After an initial examination of the source code, the conversion code
> felt cumbersome to me. I asked this question because you mentioned
> "as conversion is here and there already to tricky to my taste".

Yes I have said it is tricky in some places - but why
would that contradict the fact that it may be the best approach for
the goal? (converting behavior to behavior)

>>> I think, in a language like python, where everything is an
>>> object, looking only at variable names feels a bit fragile.
>> I have no idea what you mean here. The convertor is looking at the
>> details of every object behind a name.
> I meant this with regards to how the converter needs that all the
> variables are MyHDL primitives.

First, it uses Python concepts such as lists and tuples as
much as possible.

Secondly, the convertor is not a synthesis tool - it maintains
the abstraction level. Therefore, there has to be some way to
map supported MyHDL code to Verilog/VHDL in a reasonably direct
way. Hence the supported primitives are defined by those that
exist in the target languages.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com