myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm...> wrote:

> So, I can't use the same signal as a signal and a variable. Just like VHDL
> :)
>

Not sure what you mean?  You can mix the signal assignment
and variable assignment in VHDL?  If you declare a signal you
need to use "<=" if a variable ":=".

MyHDL only has one assignment operator, "=".  But the types
need to match.  You need to determine if you really want a signal
or a variable:
http://www.jandecaluwe.com/hdldesign/signal-assignments.html


>
> What is the difference between assigning a value with [:] and without it?
> All the intbv values need a [:] ?
>

In Python everything is a reference

    x = intbv(0, min=-4, max=4)
    y = intbv(0, min=-8, max=8)
    # ...
    x = 2
    y[:] = 4
    assert isinstance(x, intbv)   # will fail
    assert isinstance(y, intbv)   # will pass

The [:] indicates you are updating the value of the intbv type
(updating all the bits).  If you didn't do this you would loose the
intbv information, because the reference would be assigned to
another type.  But in our HDL we need to know the types we are
dealing with (we remove some of the dynamicism :)

Yes, all "variable" intbv need "[:] = <new value>".

I made changes to your original and it converts, but I did not
check if it still passes the testbench:
http://www.edaplayground.com/x/eW

Note: conversion to Verilog will fail to compile with a Verilog
compiler because some of the signal/variable names are reserved
words (e.g. "real").  It has been on our todo list to check for
reserved words in conversion.

Regards,
Chris

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

So, I can't use the same signal as a signal and a variable. Just like VHDL
:)

What is the difference between assigning a value with [:] and without it?
All the intbv values need a [:] ?

Thank you Christopher, Will get back to if you if I get more errors hehe






On Fri, Jul 4, 2014 at 8:28 AM, Christopher Felton <chr...@gm...>
wrote:

> <snip>
>>
>>
>> KeyError: 'real_reg' and a long traceback list error
>>
>> The module is not 100% functional yet, It's the first time I am doing and
>> I confess I am struggling with this different paradigm, It's not VHDL and
>> it's not Matlab, it's somewhere in the middle hah.
>>
>>
> One issue, "real_reg" is being used as a variable (real_reg[:]) and as
> a signal (real_reg.next).  If you resolve this inconsistency it might
> fix the error.
>
> The testbench must not exercise those branches, otherwise you
> should of had an attribute error.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
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>
>


-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

>
> <snip>
>
> KeyError: 'real_reg' and a long traceback list error
>
> The module is not 100% functional yet, It's the first time I am doing and
> I confess I am struggling with this different paradigm, It's not VHDL and
> it's not Matlab, it's somewhere in the middle hah.
>
>
One issue, "real_reg" is being used as a variable (real_reg[:]) and as
a signal (real_reg.next).  If you resolve this inconsistency it might
fix the error.

The testbench must not exercise those branches, otherwise you
should of had an attribute error.

Regards,
Chris

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

When you are using the "tuple of ints" they cannot be used
directly in an expression - you can do the following:

               c_gain = gains[int(num_iteracao)]
               tmp_mul_gain_imag[:] = (c_gain * imag_reg) << 16
               tmp_mul_gain_real[:] = (c_gain * tmp_real) << 16

You will have to do something similar with the angles as
well.

This will get you past the first set of errors, I didn't verify that
the testbench still worked with the changes.

This is an example of a simple FIR (sum of products) where
the coefficients (h) tuple of ints needs to be separately referenced:
https://github.com/cfelton/alt.hdl/blob/master/examples/ex4_mathsop/myhdl/sop1.py


Regards,
Chris


On Thu, Jul 3, 2014 at 4:58 PM, André Prado <and...@gm...> wrote:

> Hello everyone,
>
> I am trying to start with MyHDL! I have FPGA design experience with VHDL
> in the old school style.
>
> I am trying to implement my Cordic module which works in VHDL (Converts
> from REAL/IMAG to MAG/ANG)
>
> However I am getting this error when I try to convert to VHDL:
>
> KeyError: 'real_reg' and a long traceback list error
>
> The module is not 100% functional yet, It's the first time I am doing and
> I confess I am struggling with this different paradigm, It's not VHDL and
> it's not Matlab, it's somewhere in the middle hah.
>
>
> This is my testbench: http://pastebin.com/zqRQxbGL
>
> This is my Cordic module at the moment: http://pastebin.com/tRU85uwe
>
> The testbench seems to be OK but I can't generate the VHDL,
>
> Thank you very much;
>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

[myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Hello everyone,

I am trying to start with MyHDL! I have FPGA design experience with VHDL in
the old school style.

I am trying to implement my Cordic module which works in VHDL (Converts
from REAL/IMAG to MAG/ANG)

However I am getting this error when I try to convert to VHDL:

KeyError: 'real_reg' and a long traceback list error

The module is not 100% functional yet, It's the first time I am doing and I
confess I am struggling with this different paradigm, It's not VHDL and
it's not Matlab, it's somewhere in the middle hah.


This is my testbench: http://pastebin.com/zqRQxbGL

This is my Cordic module at the moment: http://pastebin.com/tRU85uwe

The testbench seems to be OK but I can't generate the VHDL,

Thank you very much;




-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Broken mailing list link on http://www.myhdl.org/support/community.html

[Christopher F. <chr...@gm...>]

On 7/1/14 7:41 PM, Colin Beighley wrote:
> Hello,
>
> The link http://sourceforge.net/mail?group_id=91207 posted on
> http://www.myhdl.org/support/community.html appears to be broken. I'd like to
> sign up for the mailing list, any chance someone can fix this?
>

Thanks for the heads up, you can find the info you need
here http://dir.gmane.org/gmane.comp.python.myhdl
which is the link at the bottom of the community page
http://www.myhdl.org/support/community.html

Regards,
Chris

Re: [myhdl-list] Synchronous Set

[Christopher F. <chr...@gm...>]

On 7/2/14 4:18 PM, Colin Beighley wrote:
> Hello,
>
> I'm wondering what the best way of doing a synchronous set in MyHDL is.
> Since there doesn't seem to be a built-in equivalent of
> @always_seq(clk.posedge, rst) for synchronous sets, is the following
> best practice? Let me know if it's bad practice to embed html.
>
> def  qff_w_set(clk,  set,  q0,  q,  d):
>
>    @always_seq(clk.posedge)
>    def  logic():
>      if  set:
>        q.next=  q0
>      else:
>        q.next=  d
>
>    return  logic
>
> Thanks,
> Colin
>
>

Yes, that is a reasonable approach.

Regards,
Chris

[myhdl-list] Synchronous Set

[Colin B. <col...@gm...>]

Hello,

I'm wondering what the best way of doing a synchronous set in MyHDL is.
Since there doesn't seem to be a built-in equivalent of
@always_seq(clk.posedge, rst) for synchronous sets, is the following best
practice? Let me know if it's bad practice to embed html.

def qff_w_set(clk, set, q0, q, d):

  @always_seq(clk.posedge)
  def logic():
    if set:
      q.next = q0
    else:
      q.next = d

  return logic

Thanks,
Colin

[myhdl-list] Broken mailing list link on http://www.myhdl.org/support/community.html

[Colin B. <col...@gm...>]

Hello,

The link http://sourceforge.net/mail?group_id=91207 posted on 
http://www.myhdl.org/support/community.html appears to be broken. I'd like to 
sign up for the mailing list, any chance someone can fix this?

Colin

[myhdl-list] New essay

[Jan D. <ja...@ja...>]

I have just published an edited version of an essay that
was published earlier on APP and then disappeared with it.

Using a concrete example, it explains some of the ideas about
HDL design that I feel quite strong about.

http://www.jandecaluwe.com/hdldesign/thinking-software-rtl.html

I have also published it on reddit, it is possible that it
triggers an interesting discussion over there.

http://www.reddit.com/r/programming/comments/27skdh/thinking_software_at_the_rtl_level/


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] cosimulated verilog as an instance?

[Henry G. <he...@ca...>]

On 26/05/14 16:36, Christopher Felton wrote:
>> >
>> >Yeah, I'm aware of this problem and I haven't quite worked out the
>> >solution. I'm hoping there is an adequate simulation model for the
>> >blocks I need that aren't encrypted (simple things like the DSP48) until
>> >I can justify an expensive license for modelsim or something.
>> >
>>> >>ps. If it is specifically a question of Xilinx IP, then you could
>>> >>implement co-simulation for isim (which Xilinx provides for free). I
>>> >>don't know how much work that would be, it depends on whether isim
>>> >>supports VPI.
>> >
>> >As far as I can tell, VPI is not supported. I shall report back if I
>> >find out something interesting!
>> >
> I concur, I don't believe isim supports any foreign language
> interfaces, no PLI/VPI/DPI, etc.

Something interesting actually occurred to me today - considering a 
device like a Xilinx Zynq with an on-die ARM Cortex A9, one could 
actually run a Python test bench on the device itself. This is something 
that lends itself to Python as it's already running on such a platform.

It would be lovely to run the same Python test bench on the device as is 
being used for development - at least on the system level.

Cheers,

Henry

Re: [myhdl-list] cosimulated verilog as an instance?

[Christopher F. <chr...@gm...>]

>
> Yeah, I'm aware of this problem and I haven't quite worked out the
> solution. I'm hoping there is an adequate simulation model for the
> blocks I need that aren't encrypted (simple things like the DSP48) until
> I can justify an expensive license for modelsim or something.
>
>> ps. If it is specifically a question of Xilinx IP, then you could
>> implement co-simulation for isim (which Xilinx provides for free). I
>> don't know how much work that would be, it depends on whether isim
>> supports VPI.
>
> As far as I can tell, VPI is not supported. I shall report back if I
> find out something interesting!
>

I concur, I don't believe isim supports any foreign language
interfaces, no PLI/VPI/DPI, etc.

Regards
Chris

Re: [myhdl-list] cosimulated verilog as an instance?

[Martin S. <ha...@se...>]

Hi there,

> 
> Yeah, I'm aware of this problem and I haven't quite worked out the 
> solution. I'm hoping there is an adequate simulation model for the 
> blocks I need that aren't encrypted (simple things like the DSP48) until 
> I can justify an expensive license for modelsim or something.
> 

Actually, I got pretty far on the VHDL side using some cosimulation
tricks using GHDL (like debugging virtual CPU designs using the standard
GNU debugger). But I haven't seen this on the iverilog side yet. Might
require quite some coding..
The Xilinx IP is mostly obfuscated, not really encrypted. As long as it
doesn't severely violate the VHDL standards, it mostly works.

Cheers,

- Martin

Re: [myhdl-list] cosimulated verilog as an instance?

[Henry G. <he...@ca...>]

On 24/05/14 23:38, Per Karlsson wrote:
> Usually simulation models for commercial IP:s come as encrypted RTL, 
> and so far as I'm aware you cannot simulate encrypted RTL in any 
> currently available tool based on open source. You'll simply have to 
> fork up the cash for a commercial, closed source, simulation tool.
> But if you do, there is nothing preventing you from instanciating the 
> IP in a MyHDL module using user defined code and then driving it with 
> a MyHDL testbench using co-simulation.
>
> The greater question is of course whether an open source tool could in 
> theory simulate encrypted RTL, but I leave that for people better 
> versed in cryptography than myself.
> It is also not a question with which MyHDL needs to bother itself, 
> because it has nothing to do with the language. It concerns only the 
> simulator.
>

Yeah, I'm aware of this problem and I haven't quite worked out the 
solution. I'm hoping there is an adequate simulation model for the 
blocks I need that aren't encrypted (simple things like the DSP48) until 
I can justify an expensive license for modelsim or something.

> ps. If it is specifically a question of Xilinx IP, then you could 
> implement co-simulation for isim (which Xilinx provides for free). I 
> don't know how much work that would be, it depends on whether isim 
> supports VPI.

As far as I can tell, VPI is not supported. I shall report back if I 
find out something interesting!

Cheers,

Henry

Re: [myhdl-list] cosimulated verilog as an instance?

[Per K. <bas...@gm...>]

Usually simulation models for commercial IP:s come as encrypted RTL, and so
far as I'm aware you cannot simulate encrypted RTL in any currently
available tool based on open source. You'll simply have to fork up the cash
for a commercial, closed source, simulation tool.
But if you do, there is nothing preventing you from instanciating the IP in
a MyHDL module using user defined code and then driving it with a MyHDL
testbench using co-simulation.

The greater question is of course whether an open source tool could in
theory simulate encrypted RTL, but I leave that for people better versed in
cryptography than myself.
It is also not a question with which MyHDL needs to bother itself, because
it has nothing to do with the language. It concerns only the simulator.

Cheers!
Per

ps. If it is specifically a question of Xilinx IP, then you could implement
co-simulation for isim (which Xilinx provides for free). I don't know how
much work that would be, it depends on whether isim supports VPI.



On Sat, May 24, 2014 at 3:59 PM, Christopher Felton
<chr...@gm...>wrote:

> On 5/24/14 5:32 AM, Henry Gomersall wrote:
> > Consider the use case in which one wishes to use a piece of
> > off-the-shelf IP, which comes with a suitable simulation library (let's
> > say some Xilinx IP with a unisim library).
> >
> > I have a notion that I want to be able to generate an instance of the
> > simulated model for incorporation into a MyHDL design, so when run, it
> > executes in the cosimulation environment. This would remove the
> > requirement to reimplement the logic of an IP block in MyHDL.
> >
> > In conjunction with user defined code, this would allow a neat way to
> > incorporate commercial blocks into the design.
> >
> > Is all this sensible? Is there a better way to do it?
>
>
> I don't think this would be a small addition/change and I am
> not certain if it is possible, it would take some experimentation
> etc.
>
> The solution that I am aware of is to use a module to emulate
> the IP but this can take some work to get the timing of the
> interfaces and the behavior correct.   When creating the module
> to emulate the IP you can use the /v*_code/ or /v*_instance/
> to generate the V* to instantiate the IP.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> "Accelerate Dev Cycles with Automated Cross-Browser Testing - For FREE
> Instantly run your Selenium tests across 300+ browser/OS combos.
> Get unparalleled scalability from the best Selenium testing platform
> available
> Simple to use. Nothing to install. Get started now for free."
> http://p.sf.net/sfu/SauceLabs
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] cosimulated verilog as an instance?

[Christopher F. <chr...@gm...>]

On 5/24/14 5:32 AM, Henry Gomersall wrote:
> Consider the use case in which one wishes to use a piece of
> off-the-shelf IP, which comes with a suitable simulation library (let's
> say some Xilinx IP with a unisim library).
>
> I have a notion that I want to be able to generate an instance of the
> simulated model for incorporation into a MyHDL design, so when run, it
> executes in the cosimulation environment. This would remove the
> requirement to reimplement the logic of an IP block in MyHDL.
>
> In conjunction with user defined code, this would allow a neat way to
> incorporate commercial blocks into the design.
>
> Is all this sensible? Is there a better way to do it?


I don't think this would be a small addition/change and I am
not certain if it is possible, it would take some experimentation
etc.

The solution that I am aware of is to use a module to emulate
the IP but this can take some work to get the timing of the
interfaces and the behavior correct.   When creating the module
to emulate the IP you can use the /v*_code/ or /v*_instance/
to generate the V* to instantiate the IP.

Regards,
Chris

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

Henry,

I recreated the doctest repo to make sure there
were not lingering effects on previous branches.

Hopefully you haven't clone it yet and no harm,
otherwise if you did clone, could you reclone

https://cf...@bi.../cfelton/myhdl_09dev_doctest

And make the changes in the new repo (with the
same name :)

Regards,
Chris

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

On 5/24/14 4:56 AM, Jan Decaluwe wrote:
> 0.8 is in maintenance mode. Bug fixes yes, but
> new development should be based on 0.9. Otherwize
> things are going to be messy.

Of course, but I had made the changes on the 0.8
branch when we were doing 0.8 dev.  I attempted
to leverage mercurial to merge and prune.  The
only reason I mentioned it was as a heads up
and/or a reminder for me

I guess to be safe I will manually create a new
clone and copy the files over because I am not
100% sure what happened on 0.8.

Regards,
Chris

[myhdl-list] cosimulated verilog as an instance?

[Henry G. <he...@ca...>]

Consider the use case in which one wishes to use a piece of 
off-the-shelf IP, which comes with a suitable simulation library (let's 
say some Xilinx IP with a unisim library).

I have a notion that I want to be able to generate an instance of the 
simulated model for incorporation into a MyHDL design, so when run, it 
executes in the cosimulation environment. This would remove the 
requirement to reimplement the logic of an IP block in MyHDL.

In conjunction with user defined code, this would allow a neat way to 
incorporate commercial blocks into the design.

Is all this sensible? Is there a better way to do it?

Cheers,

Henry

Re: [myhdl-list] Another typo in docs

[Jan D. <ja...@ja...>]

0.8 is in maintenance mode. Bug fixes yes, but
new development should be based on 0.9. Otherwize
things are going to be messy.

I have recently merged in or handled all outstanding
PRs I believe.

Jan


On 05/24/2014 02:52 AM, Christopher Felton wrote:
> On 5/23/14 4:47 PM, Henry Gomersall wrote:
>> On 23/05/14 21:55, Christopher Felton wrote:
>>> On 5/23/2014 3:04 PM, Henry Gomersall wrote:
>>>>> On 23/05/14 20:57, Christopher Felton wrote:
>>>>>>>>>>> Would it make sense to convert the code snippets in the Sphinx
>>>>>>>>>>> documentation to doctests so this can be picked up automatically? I can
>>>>>>>>>>> have a bash at this if desired (certainly, the FSM one above would be
>>>>>>>>>>> useful as a doctest).
>>>>>>> Yes, I think this is a great idea, I actually have a
>>>>>>> start on this.  I have a couple sections completed with
>>>>>>> doctest.  If others agree I can create a PR with my
>>>>>>> changes and then you can add to if you like:)
>>>>>>>
>>>>> Can you do a sibling pull request (I mean, is it possible)? It makes
>>>>> sense to not replicate one another's work! Otherwise can you point me at
>>>>> the relevant repository and I'll fork that?
>>>>>
>>> Yes, I can point you to a repo (it will be a little while).
>>> I did this awhile ago, the work was originally done on the
>>> 0.8dev branch.  It will need to be merged to 0.9.
>>
>> Great, just let me know when you have it.
>>
>> Cheers,
>>
>> Henry
>
>
> Here are the merged changes - I don't know if this is
> the final version/format desired but it is a starting
> point, I merged it to the 0.9dev branch:
>
> https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview
>
> One note of caution, I had made these changes a while
> back on 0.8 branch.  I used mercurial to merge but which
> all went well.  But when I pushed it back to the repo above
> it indicated it had to create a new head.  Not 100% positive
> if we want the closed/dead/hanging head pushed back to the
> main repo.
>
> If you fork/clone this make sure you update to the 0.9dev
> branch
>
>       >> hg up -C 0.9-dev
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> "Accelerate Dev Cycles with Automated Cross-Browser Testing - For FREE
> Instantly run your Selenium tests across 300+ browser/OS combos.
> Get unparalleled scalability from the best Selenium testing platform available
> Simple to use. Nothing to install. Get started now for free."
> http://p.sf.net/sfu/SauceLabs
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Another typo in docs

[Jan D. <ja...@ja...>]

0.8 is in maintenance mode. Bug fixes yes, but
new development should be based on 0.9. Otherwize
things are going to be messy.

I have recently merged in or handled all outstanding
PRs I believe.

Jan


On 05/24/2014 02:52 AM, Christopher Felton wrote:
> On 5/23/14 4:47 PM, Henry Gomersall wrote:
>> On 23/05/14 21:55, Christopher Felton wrote:
>>> On 5/23/2014 3:04 PM, Henry Gomersall wrote:
>>>>> On 23/05/14 20:57, Christopher Felton wrote:
>>>>>>>>>>> Would it make sense to convert the code snippets in the Sphinx
>>>>>>>>>>> documentation to doctests so this can be picked up automatically? I can
>>>>>>>>>>> have a bash at this if desired (certainly, the FSM one above would be
>>>>>>>>>>> useful as a doctest).
>>>>>>> Yes, I think this is a great idea, I actually have a
>>>>>>> start on this.  I have a couple sections completed with
>>>>>>> doctest.  If others agree I can create a PR with my
>>>>>>> changes and then you can add to if you like:)
>>>>>>>
>>>>> Can you do a sibling pull request (I mean, is it possible)? It makes
>>>>> sense to not replicate one another's work! Otherwise can you point me at
>>>>> the relevant repository and I'll fork that?
>>>>>
>>> Yes, I can point you to a repo (it will be a little while).
>>> I did this awhile ago, the work was originally done on the
>>> 0.8dev branch.  It will need to be merged to 0.9.
>>
>> Great, just let me know when you have it.
>>
>> Cheers,
>>
>> Henry
>
>
> Here are the merged changes - I don't know if this is
> the final version/format desired but it is a starting
> point, I merged it to the 0.9dev branch:
>
> https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview
>
> One note of caution, I had made these changes a while
> back on 0.8 branch.  I used mercurial to merge but which
> all went well.  But when I pushed it back to the repo above
> it indicated it had to create a new head.  Not 100% positive
> if we want the closed/dead/hanging head pushed back to the
> main repo.
>
> If you fork/clone this make sure you update to the 0.9dev
> branch
>
>       >> hg up -C 0.9-dev
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> "Accelerate Dev Cycles with Automated Cross-Browser Testing - For FREE
> Instantly run your Selenium tests across 300+ browser/OS combos.
> Get unparalleled scalability from the best Selenium testing platform available
> Simple to use. Nothing to install. Get started now for free."
> http://p.sf.net/sfu/SauceLabs
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

On 5/23/14 4:47 PM, Henry Gomersall wrote:
> On 23/05/14 21:55, Christopher Felton wrote:
>> On 5/23/2014 3:04 PM, Henry Gomersall wrote:
>>>> On 23/05/14 20:57, Christopher Felton wrote:
>>>>>>>>>> Would it make sense to convert the code snippets in the Sphinx
>>>>>>>>>> documentation to doctests so this can be picked up automatically? I can
>>>>>>>>>> have a bash at this if desired (certainly, the FSM one above would be
>>>>>>>>>> useful as a doctest).
>>>>>> Yes, I think this is a great idea, I actually have a
>>>>>> start on this.  I have a couple sections completed with
>>>>>> doctest.  If others agree I can create a PR with my
>>>>>> changes and then you can add to if you like:)
>>>>>>
>>>> Can you do a sibling pull request (I mean, is it possible)? It makes
>>>> sense to not replicate one another's work! Otherwise can you point me at
>>>> the relevant repository and I'll fork that?
>>>>
>> Yes, I can point you to a repo (it will be a little while).
>> I did this awhile ago, the work was originally done on the
>> 0.8dev branch.  It will need to be merged to 0.9.
>
> Great, just let me know when you have it.
>
> Cheers,
>
> Henry


Here are the merged changes - I don't know if this is
the final version/format desired but it is a starting
point, I merged it to the 0.9dev branch:

https://bitbucket.org/cfelton/myhdl_09dev_doctest/overview

One note of caution, I had made these changes a while
back on 0.8 branch.  I used mercurial to merge but which
all went well.  But when I pushed it back to the repo above
it indicated it had to create a new head.  Not 100% positive
if we want the closed/dead/hanging head pushed back to the
main repo.

If you fork/clone this make sure you update to the 0.9dev
branch

     >> hg up -C 0.9-dev

Regards,
Chris

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 23/05/14 21:55, Christopher Felton wrote:
> On 5/23/2014 3:04 PM, Henry Gomersall wrote:
>> >On 23/05/14 20:57, Christopher Felton wrote:
>>>>> >>>>Would it make sense to convert the code snippets in the Sphinx
>>>>> >>>>documentation to doctests so this can be picked up automatically? I can
>>>>> >>>>have a bash at this if desired (certainly, the FSM one above would be
>>>>> >>>>useful as a doctest).
>>> >>Yes, I think this is a great idea, I actually have a
>>> >>start on this.  I have a couple sections completed with
>>> >>doctest.  If others agree I can create a PR with my
>>> >>changes and then you can add to if you like:)
>>> >>
>> >Can you do a sibling pull request (I mean, is it possible)? It makes
>> >sense to not replicate one another's work! Otherwise can you point me at
>> >the relevant repository and I'll fork that?
>> >
> Yes, I can point you to a repo (it will be a little while).
> I did this awhile ago, the work was originally done on the
> 0.8dev branch.  It will need to be merged to 0.9.

Great, just let me know when you have it.

Cheers,

Henry

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

On 5/23/2014 3:04 PM, Henry Gomersall wrote:
> On 23/05/14 20:57, Christopher Felton wrote:
>>>> Would it make sense to convert the code snippets in the Sphinx
>>>> documentation to doctests so this can be picked up automatically? I can
>>>> have a bash at this if desired (certainly, the FSM one above would be
>>>> useful as a doctest).
>> Yes, I think this is a great idea, I actually have a
>> start on this.  I have a couple sections completed with
>> doctest.  If others agree I can create a PR with my
>> changes and then you can add to if you like:)
>>
> Can you do a sibling pull request (I mean, is it possible)? It makes
> sense to not replicate one another's work! Otherwise can you point me at
> the relevant repository and I'll fork that?
>

Yes, I can point you to a repo (it will be a little while).
I did this awhile ago, the work was originally done on the
0.8dev branch.  It will need to be merged to 0.9.

Regards,
Chris

Re: [myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

On 23/05/14 20:57, Christopher Felton wrote:
>> >Would it make sense to convert the code snippets in the Sphinx
>> >documentation to doctests so this can be picked up automatically? I can
>> >have a bash at this if desired (certainly, the FSM one above would be
>> >useful as a doctest).
> Yes, I think this is a great idea, I actually have a
> start on this.  I have a couple sections completed with
> doctest.  If others agree I can create a PR with my
> changes and then you can add to if you like:)
>
Can you do a sibling pull request (I mean, is it possible)? It makes 
sense to not replicate one another's work! Otherwise can you point me at 
the relevant repository and I'll fork that?

Cheers,

Henry