myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Just to give a feedback. It was working, just that it is faster than my old
module and that was causing me trouble.
Cheers
Em 09/07/2014 07:35, "Jan Coombs" <jen...@mu...>
escreveu:

> On 04/07/14 13:33, Christopher Felton wrote:
> >    . . .
> >
> >
> >     What is the difference between assigning a value with [:] and
> >     without it? All the intbv values need a [:] ?
> >
> >
> > In Python everything is a reference
> >
> >     x = intbv(0, min=-4, max=4)
> >     y = intbv(0, min=-8, max=8)
> >     # ...
> >     x = 2
> >     y[:] = 4
> >     assert isinstance(x, intbv)   # will fail
> >     assert isinstance(y, intbv)   # will pass
> >
> > The [:] indicates you are updating the value of the intbv type
> > (updating all the bits).  If you didn't do this you would loose
> > the to
> > intbv information, because the reference would be assigned to
> > will start
> > another type.  But in our HDL we need to know the types we are
> > dealing with (we remove some of the dynamicism :)
> >
> > Yes, all "variable" intbv need "[:] = <new value>".
>
> Thanks, I'd completely missed this point, even though I've paid
> close attention to discussions about the use of signals and variables.
>
> If I had known this three years ago I might well have finished my
> novel processor project by now, and would not be living in a house
> in which all the walls are decorated with skull impressions.
>
> Jan Coombs.
>
>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Problem converting list of intbv

[Pedro P. <ped...@gm...>]

It worked. Thank you.

ızznɹpǝԀ oɹpǝԀ


On Tue, Jul 8, 2014 at 8:55 AM, Christopher Felton <chr...@gm...>
wrote:

> On 7/8/14 5:07 AM, Pedro Pedruzzi wrote:
> > Guy, thanks for your response.
> >
> > Unfortunately I can't use tuples because I acually write to the "array"
> > as well. So allow me to modify my example. Now I have 4 counters and the
> > one selected with signal s will get incremented and tranfered to the
> output.
> >
> > Shouldn't list of intbvs be supported?
>
> Yes, a tuple of intbv, and int is supported from ROM,
> if you want to RAM you need a list-of-signals,
> change your u32 function to:
>
>      def u32(val = 0):
>          return Signal(uint(32, val))
>
> In addition, move your RAM definition (I know if this
> case it won't be synthesized using a BRAM because it is
> small but it act as RAM) to the elaboration phase:
>
> def mux(s, o):
>      i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb),
>            u32(0xcccccccc), u32(0xdddddddd) ]
>      @always_comb
>      def logic():
>          o.next = i[s]
>      return logi
>
>
> Also see,
>
> http://docs.myhdl.org/en/latest/manual/conversion_examples.html#ram-inference
>
> Personally I don't like the use of functions in this
> case.  You remove modularity from you module and I
> don't think it adds to readability,  I would simplify
> to something like:
>
>      def mux(s, o, width=32):
>          i = [ Signal(intbv(val)[width:])
>                for val in (0xaaaaaaaa, 0xbbbbbbbb,
>                            0xcccccccc, 0xdddddddd,) ]
>          @always_comb
>          def logic():
>              o.next = i[s]
>      return logic
>
>
> Regards,
> Chris
>
> >
> > from myhdl import Signal, always_comb, intbv, toVerilog
> >
> > def uint(width, val = 0):
> >      return intbv(val, 0, 2 ** width)
> >
> > def u32(val = 0):
> >      return uint(32, val)
> >
> > def counters(s, o):
> >      m = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
> > u32(0xdddddddd) ]
> >      @always_comb
> >      def logic():
> >          m[s] += 1
> >          o.next = m[s]
> >      return logic
> >
> > s = Signal(intbv(0)[2:])
> > o = Signal(intbv(0)[32:])
> >
> > toVerilog(counters, s, o)
> >
> > ızznɹpǝԀ oɹpǝԀ
> >
> >
> > On Tue, Jul 8, 2014 at 5:46 AM, Guy Eschemann <gu...@no...
> > <mailto:gu...@no...>> wrote:
> >
> >     Hello Pedro,
> >
> >     here's how I would do it:
> >
> >     def mux(s, o):
> >          i = (0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd)
> >
> >
> >     @always_comb
> >     def logic():
> >              o.next = i[s]
> >     return logic
> >
> >     Regards,
> >     Guy.
> >
> >     On Jul 8, 2014, at 1:16 AM, Pedro Pedruzzi wrote:
> >
> >>     Hello,
> >>
> >>     I am new to this list.
> >>
> >>     I am getting the following exception while trying to convert a
> >>     simple mux to Verilog.
> >>
> >>     myhdl.ConversionError: in file list-of-intbv.py, line 12: Not
> >>     supported: list
> >>
> >>     I know I could use tuple of int (since I am using constants), but
> >>     I want to use lists to implement array of registers and the docs
> >>     says it is possible.
> >>
> >>     Here is the design:
> >>
> >>     from myhdl import Signal, always_comb, intbv, toVerilog
> >>
> >>     def uint(width, val = 0):
> >>         return intbv(val, 0, 2 ** width)
> >>
> >>     def u32(val = 0):
> >>         return uint(32, val)
> >>
> >>     def mux(s, o):
> >>         @always_comb
> >>         def logic():
> >>             i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
> >>     u32(0xdddddddd) ]
> >>             o.next = i[s]
> >>         return logic
> >>
> >>     s = Signal(intbv(0)[2:])
> >>     o = Signal(intbv(0)[32:])
> >>
> >>     toVerilog(mux, s, o)
> >>
> >>
> >>     Any help is appreciated. Thanks.
> >>
> >>     ızznɹpǝԀ oɹpǝԀ
> >>
> ------------------------------------------------------------------------------
> >>     Open source business process management suite built on Java and
> >>     Eclipse
> >>     Turn processes into business applications with Bonita BPM
> >>     Community Edition
> >>     Quickly connect people, data, and systems into organized workflows
> >>     Winner of BOSSIE, CODIE, OW2 and Gartner awards
> >>
> http://p.sf.net/sfu/Bonitasoft_______________________________________________
> >>     myhdl-list mailing list
> >>     myh...@li...
> >>     <mailto:myh...@li...>
> >>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
> >
> >
> ------------------------------------------------------------------------------
> >     Open source business process management suite built on Java and
> Eclipse
> >     Turn processes into business applications with Bonita BPM Community
> >     Edition
> >     Quickly connect people, data, and systems into organized workflows
> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
> >     http://p.sf.net/sfu/Bonitasoft
> >     _______________________________________________
> >     myhdl-list mailing list
> >     myh...@li...
> >     <mailto:myh...@li...>
> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> > Open source business process management suite built on Java and Eclipse
> > Turn processes into business applications with Bonita BPM Community
> Edition
> > Quickly connect people, data, and systems into organized workflows
> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
> > http://p.sf.net/sfu/Bonitasoft
> >
> >
> >
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan C. <jen...@mu...>]

On 04/07/14 13:33, Christopher Felton wrote:
>    . . .
>
>
>     What is the difference between assigning a value with [:] and
>     without it? All the intbv values need a [:] ?
>
>
> In Python everything is a reference
>
>     x = intbv(0, min=-4, max=4)
>     y = intbv(0, min=-8, max=8)
>     # ...
>     x = 2
>     y[:] = 4
>     assert isinstance(x, intbv)   # will fail
>     assert isinstance(y, intbv)   # will pass
>
> The [:] indicates you are updating the value of the intbv type
> (updating all the bits).  If you didn't do this you would loose 
> the to
> intbv information, because the reference would be assigned to 
> will start
> another type.  But in our HDL we need to know the types we are
> dealing with (we remove some of the dynamicism :)
>
> Yes, all "variable" intbv need "[:] = <new value>".

Thanks, I'd completely missed this point, even though I've paid 
close attention to discussions about the use of signals and variables.

If I had known this three years ago I might well have finished my 
novel processor project by now, and would not be living in a house 
in which all the walls are decorated with skull impressions.

Jan Coombs.

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Thanks Jan, I will take a look at that, however, it seems that I was using
extra bits in my old design just to fit in 32 bits, which is not needed
anymore. I will make sure of that thought with the logic analyser (signal
tap) though.
BTW, did you recieve my e-mail about an interview for Embarcados ?:)

Cheers


On Wed, Jul 9, 2014 at 4:38 AM, Jan Decaluwe <ja...@ja...> wrote:

> 1) if the generated VHDL looks OK and simulates fine, it's not a MyHDL
> issue
> 2) reset strategy seems ok
> 3) synthesis bug is highly unlikely
>     - although we can consider it further if you use Xilinx Vivado
>     - if there is one, almost certainly not related to variables
> 4) my first guess would be an interpretation/acquisition issue
>
> I notice that the interface widths between original and generated
> are different. This means that you have to do something different
> to get values to/from the board. Perhaps there is an issue there.
>
>
> On 07/08/2014 07:52 PM, André Prado wrote:
> > So, here I am. Finally had some time to finish it;
> >
> > It's working perfectly! Here is my Py cordic code:
> http://pastebin.com/NzphEmrY and here is my testbench in Py:
> http://pastebin.com/PtqKWJN6
> > I do have a problem with the angle validation, The py function returns
> from -pi to pi and I have to do the same with my cordic, but I won't worry
> about that now.
> >
> > So, I've generated the VHDL and compiled in my project, here is the
> VHDL: http://pastebin.com/5j5muvGq
> >
> > Compared to my OLD VHDL ( http://pastebin.com/v9FJVUXr ), I do prefer
> the generated one, it uses less logic, the ports are smaller and it's also
> 1 uS faster (and I have python functions, yay). This OLD VHDL is really
> old, there are a few errors with it like mixing numeric_std and
> signed_artih, but...
> >
> > the MyHDL VHDL isn't working in my product! :(
> >
> > I know that's a lot of work, but I've been scratching my head and I
> can't find why the MyHDL VHDL isn't working. I am getting some random
> values from my acquisition board instead of the right mag/ang pair.
> >
> > I've made a test bench with both VHDLs running in paralalel and I get
> the same result from both.
> >
> > I don't know if it's a problem with the Variable usage or these cases
> returning a constant to a variable, or even the state machine being half
> if/else half case. Everything seems OK, I took a look at the RTL Viewer and
> didn't see anything strange.
> >
> >
> > Cheers
> >
> >
> >
> >
> > On Fri, Jul 4, 2014 at 1:10 PM, André Prado <and...@gm...
> <mailto:and...@gm...>> wrote:
> >
> >     Thanks again.
> >
> >     Well, even if the synthesis result is the same, I really need to use
> the CASE statement for state machines. If I don't do it the product leader
> won't let me use MyHDL, lol :-)
> >     Also, we use this here:
> >
> >     attribute SYN_ENCODING of READ_PARAMETER_ST_TYPE : type is "safe";
> >
> >     As far as I understood, I can send this line directly to the VHDL
> with the special MyHDL command vhdl_code, right?
> >
> >
> >
> >     Cheers
> >
> >
> >     On Fri, Jul 4, 2014 at 11:59 AM, Christopher Felton <
> chr...@gm... <mailto:chr...@gm...>> wrote:
> >
> >         On Fri, Jul 4, 2014 at 9:43 AM, André Prado <
> and...@gm... <mailto:and...@gm...>> wrote:
> >
> >             Humm, my state machine was translated to an IF else if
> fashiong instead of switch case.
> >
> >
> >         Thats fine, compare synthesis results if there is concern.
> >
> >         Regards,
> >         Chris
> >
> >
> ------------------------------------------------------------------------------
> >         Open source business process management suite built on Java and
> Eclipse
> >         Turn processes into business applications with Bonita BPM
> Community Edition
> >         Quickly connect people, data, and systems into organized
> workflows
> >         Winner of BOSSIE, CODIE, OW2 and Gartner awards
> >         http://p.sf.net/sfu/Bonitasoft
> >         _______________________________________________
> >         myhdl-list mailing list
> >         myh...@li... <mailto:
> myh...@li...>
> >         https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
> >
> >
> >
> >     --
> >     Atenciosamente/Regards
> >     André Castelan Prado
> >
> >
> >
> >
> > --
> > Atenciosamente/Regards
> > André Castelan Prado
> >
> >
> >
> ------------------------------------------------------------------------------
> > Open source business process management suite built on Java and Eclipse
> > Turn processes into business applications with Bonita BPM Community
> Edition
> > Quickly connect people, data, and systems into organized workflows
> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
> > http://p.sf.net/sfu/Bonitasoft
> >
> >
> >
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      Analog design automation: http://www.mephisto-da.com
>      World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan D. <ja...@ja...>]

1) if the generated VHDL looks OK and simulates fine, it's not a MyHDL issue
2) reset strategy seems ok
3) synthesis bug is highly unlikely
    - although we can consider it further if you use Xilinx Vivado
    - if there is one, almost certainly not related to variables
4) my first guess would be an interpretation/acquisition issue

I notice that the interface widths between original and generated
are different. This means that you have to do something different
to get values to/from the board. Perhaps there is an issue there.


On 07/08/2014 07:52 PM, André Prado wrote:
> So, here I am. Finally had some time to finish it;
>
> It's working perfectly! Here is my Py cordic code: http://pastebin.com/NzphEmrY and here is my testbench in Py: http://pastebin.com/PtqKWJN6
> I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.
>
> So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvGq
>
> Compared to my OLD VHDL ( http://pastebin.com/v9FJVUXr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...
>
> the MyHDL VHDL isn't working in my product! :(
>
> I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.
>
> I've made a test bench with both VHDLs running in paralalel and I get the same result from both.
>
> I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.
>
>
> Cheers
>
>
>
>
> On Fri, Jul 4, 2014 at 1:10 PM, André Prado <and...@gm... <mailto:and...@gm...>> wrote:
>
>     Thanks again.
>
>     Well, even if the synthesis result is the same, I really need to use the CASE statement for state machines. If I don't do it the product leader won't let me use MyHDL, lol :-)
>     Also, we use this here:
>
>     attribute SYN_ENCODING of READ_PARAMETER_ST_TYPE : type is "safe";
>
>     As far as I understood, I can send this line directly to the VHDL with the special MyHDL command vhdl_code, right?
>
>
>
>     Cheers
>
>
>     On Fri, Jul 4, 2014 at 11:59 AM, Christopher Felton <chr...@gm... <mailto:chr...@gm...>> wrote:
>
>         On Fri, Jul 4, 2014 at 9:43 AM, André Prado <and...@gm... <mailto:and...@gm...>> wrote:
>
>             Humm, my state machine was translated to an IF else if fashiong instead of switch case.
>
>
>         Thats fine, compare synthesis results if there is concern.
>
>         Regards,
>         Chris
>
>         ------------------------------------------------------------------------------
>         Open source business process management suite built on Java and Eclipse
>         Turn processes into business applications with Bonita BPM Community Edition
>         Quickly connect people, data, and systems into organized workflows
>         Winner of BOSSIE, CODIE, OW2 and Gartner awards
>         http://p.sf.net/sfu/Bonitasoft
>         _______________________________________________
>         myhdl-list mailing list
>         myh...@li... <mailto:myh...@li...>
>         https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
>     --
>     Atenciosamente/Regards
>     André Castelan Prado
>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan D. <ja...@ja...>]

1) if the generated VHDL looks OK and simulates fine, it's not a MyHDL issue
2) reset strategy seems ok
3) synthesis bug is highly unlikely
    - although we can consider it further if you use Xilinx Vivado
    - if there is one, almost certainly not related to variables
4) my first guess would be an interpretation/acquisition issue

I notice that the interface widths between original and generated
are different. This means that you have to do something different
to get values to/from the board. Perhaps there is an issue there.


On 07/08/2014 07:52 PM, André Prado wrote:
> So, here I am. Finally had some time to finish it;
>
> It's working perfectly! Here is my Py cordic code: http://pastebin.com/NzphEmrY and here is my testbench in Py: http://pastebin.com/PtqKWJN6
> I do have a problem with the angle validation, The py function returns from -pi to pi and I have to do the same with my cordic, but I won't worry about that now.
>
> So, I've generated the VHDL and compiled in my project, here is the VHDL: http://pastebin.com/5j5muvGq
>
> Compared to my OLD VHDL ( http://pastebin.com/v9FJVUXr ), I do prefer the generated one, it uses less logic, the ports are smaller and it's also 1 uS faster (and I have python functions, yay). This OLD VHDL is really old, there are a few errors with it like mixing numeric_std and signed_artih, but...
>
> the MyHDL VHDL isn't working in my product! :(
>
> I know that's a lot of work, but I've been scratching my head and I can't find why the MyHDL VHDL isn't working. I am getting some random values from my acquisition board instead of the right mag/ang pair.
>
> I've made a test bench with both VHDLs running in paralalel and I get the same result from both.
>
> I don't know if it's a problem with the Variable usage or these cases returning a constant to a variable, or even the state machine being half if/else half case. Everything seems OK, I took a look at the RTL Viewer and didn't see anything strange.
>
>
> Cheers
>
>
>
>
> On Fri, Jul 4, 2014 at 1:10 PM, André Prado <and...@gm... <mailto:and...@gm...>> wrote:
>
>     Thanks again.
>
>     Well, even if the synthesis result is the same, I really need to use the CASE statement for state machines. If I don't do it the product leader won't let me use MyHDL, lol :-)
>     Also, we use this here:
>
>     attribute SYN_ENCODING of READ_PARAMETER_ST_TYPE : type is "safe";
>
>     As far as I understood, I can send this line directly to the VHDL with the special MyHDL command vhdl_code, right?
>
>
>
>     Cheers
>
>
>     On Fri, Jul 4, 2014 at 11:59 AM, Christopher Felton <chr...@gm... <mailto:chr...@gm...>> wrote:
>
>         On Fri, Jul 4, 2014 at 9:43 AM, André Prado <and...@gm... <mailto:and...@gm...>> wrote:
>
>             Humm, my state machine was translated to an IF else if fashiong instead of switch case.
>
>
>         Thats fine, compare synthesis results if there is concern.
>
>         Regards,
>         Chris
>
>         ------------------------------------------------------------------------------
>         Open source business process management suite built on Java and Eclipse
>         Turn processes into business applications with Bonita BPM Community Edition
>         Quickly connect people, data, and systems into organized workflows
>         Winner of BOSSIE, CODIE, OW2 and Gartner awards
>         http://p.sf.net/sfu/Bonitasoft
>         _______________________________________________
>         myhdl-list mailing list
>         myh...@li... <mailto:myh...@li...>
>         https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
>     --
>     Atenciosamente/Regards
>     André Castelan Prado
>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

So, here I am. Finally had some time to finish it;

It's working perfectly! Here is my Py cordic code:
http://pastebin.com/NzphEmrY and here is my testbench in Py:
http://pastebin.com/PtqKWJN6
I do have a problem with the angle validation, The py function returns from
-pi to pi and I have to do the same with my cordic, but I won't worry about
that now.

So, I've generated the VHDL and compiled in my project, here is the VHDL:
http://pastebin.com/5j5muvGq

Compared to my OLD VHDL ( http://pastebin.com/v9FJVUXr ), I do prefer the
generated one, it uses less logic, the ports are smaller and it's also 1 uS
faster (and I have python functions, yay). This OLD VHDL is really old,
there are a few errors with it like mixing numeric_std and signed_artih,
but...

the MyHDL VHDL isn't working in my product! :(

I know that's a lot of work, but I've been scratching my head and I can't
find why the MyHDL VHDL isn't working. I am getting some random values from
my acquisition board instead of the right mag/ang pair.

I've made a test bench with both VHDLs running in paralalel and I get the
same result from both.

I don't know if it's a problem with the Variable usage or these cases
returning a constant to a variable, or even the state machine being half
if/else half case. Everything seems OK, I took a look at the RTL Viewer and
didn't see anything strange.


Cheers




On Fri, Jul 4, 2014 at 1:10 PM, André Prado <and...@gm...> wrote:

> Thanks again.
>
> Well, even if the synthesis result is the same, I really need to use the
> CASE statement for state machines. If I don't do it the product leader
> won't let me use MyHDL, lol :-)
> Also, we use this here:
>
> attribute SYN_ENCODING of READ_PARAMETER_ST_TYPE : type is "safe";
>
> As far as I understood, I can send this line directly to the VHDL with the
> special MyHDL command vhdl_code, right?
>
>
>
> Cheers
>
>
> On Fri, Jul 4, 2014 at 11:59 AM, Christopher Felton <
> chr...@gm...> wrote:
>
>> On Fri, Jul 4, 2014 at 9:43 AM, André Prado <and...@gm...>
>> wrote:
>>
>>> Humm, my state machine was translated to an IF else if fashiong instead
>>> of switch case.
>>>
>>
>> Thats fine, compare synthesis results if there is concern.
>>
>> Regards,
>> Chris
>>
>>
>> ------------------------------------------------------------------------------
>> Open source business process management suite built on Java and Eclipse
>> Turn processes into business applications with Bonita BPM Community
>> Edition
>> Quickly connect people, data, and systems into organized workflows
>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>> http://p.sf.net/sfu/Bonitasoft
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>



-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Problem converting list of intbv

[Christopher F. <chr...@gm...>]

On 7/8/14 5:07 AM, Pedro Pedruzzi wrote:
> Guy, thanks for your response.
>
> Unfortunately I can't use tuples because I acually write to the "array"
> as well. So allow me to modify my example. Now I have 4 counters and the
> one selected with signal s will get incremented and tranfered to the output.
>
> Shouldn't list of intbvs be supported?

Yes, a tuple of intbv, and int is supported from ROM,
if you want to RAM you need a list-of-signals,
change your u32 function to:

     def u32(val = 0):
         return Signal(uint(32, val))

In addition, move your RAM definition (I know if this
case it won't be synthesized using a BRAM because it is
small but it act as RAM) to the elaboration phase:

def mux(s, o):
     i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb),
           u32(0xcccccccc), u32(0xdddddddd) ]
     @always_comb
     def logic():
         o.next = i[s]
     return logi


Also see,
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#ram-inference

Personally I don't like the use of functions in this
case.  You remove modularity from you module and I
don't think it adds to readability,  I would simplify
to something like:

     def mux(s, o, width=32):
         i = [ Signal(intbv(val)[width:])
               for val in (0xaaaaaaaa, 0xbbbbbbbb,
                           0xcccccccc, 0xdddddddd,) ]
         @always_comb
         def logic():
             o.next = i[s]
     return logic


Regards,
Chris

>
> from myhdl import Signal, always_comb, intbv, toVerilog
>
> def uint(width, val = 0):
>      return intbv(val, 0, 2 ** width)
>
> def u32(val = 0):
>      return uint(32, val)
>
> def counters(s, o):
>      m = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
> u32(0xdddddddd) ]
>      @always_comb
>      def logic():
>          m[s] += 1
>          o.next = m[s]
>      return logic
>
> s = Signal(intbv(0)[2:])
> o = Signal(intbv(0)[32:])
>
> toVerilog(counters, s, o)
>
> ızznɹpǝԀ oɹpǝԀ
>
>
> On Tue, Jul 8, 2014 at 5:46 AM, Guy Eschemann <gu...@no...
> <mailto:gu...@no...>> wrote:
>
>     Hello Pedro,
>
>     here's how I would do it:
>
>     def mux(s, o):
>          i = (0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd)
>
>
>     @always_comb
>     def logic():
>              o.next = i[s]
>     return logic
>
>     Regards,
>     Guy.
>
>     On Jul 8, 2014, at 1:16 AM, Pedro Pedruzzi wrote:
>
>>     Hello,
>>
>>     I am new to this list.
>>
>>     I am getting the following exception while trying to convert a
>>     simple mux to Verilog.
>>
>>     myhdl.ConversionError: in file list-of-intbv.py, line 12: Not
>>     supported: list
>>
>>     I know I could use tuple of int (since I am using constants), but
>>     I want to use lists to implement array of registers and the docs
>>     says it is possible.
>>
>>     Here is the design:
>>
>>     from myhdl import Signal, always_comb, intbv, toVerilog
>>
>>     def uint(width, val = 0):
>>         return intbv(val, 0, 2 ** width)
>>
>>     def u32(val = 0):
>>         return uint(32, val)
>>
>>     def mux(s, o):
>>         @always_comb
>>         def logic():
>>             i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
>>     u32(0xdddddddd) ]
>>             o.next = i[s]
>>         return logic
>>
>>     s = Signal(intbv(0)[2:])
>>     o = Signal(intbv(0)[32:])
>>
>>     toVerilog(mux, s, o)
>>
>>
>>     Any help is appreciated. Thanks.
>>
>>     ızznɹpǝԀ oɹpǝԀ
>>     ------------------------------------------------------------------------------
>>     Open source business process management suite built on Java and
>>     Eclipse
>>     Turn processes into business applications with Bonita BPM
>>     Community Edition
>>     Quickly connect people, data, and systems into organized workflows
>>     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>     http://p.sf.net/sfu/Bonitasoft_______________________________________________
>>     myhdl-list mailing list
>>     myh...@li...
>>     <mailto:myh...@li...>
>>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>     ------------------------------------------------------------------------------
>     Open source business process management suite built on Java and Eclipse
>     Turn processes into business applications with Bonita BPM Community
>     Edition
>     Quickly connect people, data, and systems into organized workflows
>     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>     http://p.sf.net/sfu/Bonitasoft
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li...
>     <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Verilog RAM

[Christopher F. <chr...@gm...>]

On 7/7/14 4:55 PM, Edward Vidal wrote:
> Hello,
> I am new to myhdl and python.  I have been able to create ram_l and
> ram_r. I have been able to also create a testbench that is sort of
> working.  I also have a ram_odd where the result of
>      @always(clk.posedge)
>      def hdl():
>
>          pix.din_odd.next = (pix.dout_l + pix.dout_r)*ca1
>
>      return hdl
> When n = 1 I would like to use pix.dout_odd -1and pix.dout_odd +1
> instead of what I have now.

What is "n" (haven't looked at the attached code yet,
probably won't have time to work through it).

You can always conditionally created the myhdl-generators

     if n == 1
	@always(clk.posedge)
	def hdl():
	    pix.din_odd.next = (pix.dout_l - pix.dout_r) * cal
     else:
        @always(clk.posedge)
	def hdl():
	    pix.din_odd.next = (pix.dout_l + pix.dout_r) * cal

Or you can include the condition in generator.

Regards,
Chris

Re: [myhdl-list] Problem converting list of intbv

[Pedro P. <ped...@gm...>]

Guy, thanks for your response.

Unfortunately I can't use tuples because I acually write to the "array" as
well. So allow me to modify my example. Now I have 4 counters and the one
selected with signal s will get incremented and tranfered to the output.

Shouldn't list of intbvs be supported?

from myhdl import Signal, always_comb, intbv, toVerilog

def uint(width, val = 0):
    return intbv(val, 0, 2 ** width)

def u32(val = 0):
    return uint(32, val)

def counters(s, o):
    m = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
u32(0xdddddddd) ]
    @always_comb
    def logic():
        m[s] += 1
        o.next = m[s]
    return logic

s = Signal(intbv(0)[2:])
o = Signal(intbv(0)[32:])

toVerilog(counters, s, o)

ızznɹpǝԀ oɹpǝԀ


On Tue, Jul 8, 2014 at 5:46 AM, Guy Eschemann <gu...@no...> wrote:

> Hello Pedro,
>
> here's how I would do it:
>
> def mux(s, o):
>     i = (0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd)
>
>
>     @always_comb
>     def logic():
>         o.next = i[s]
>     return logic
>
> Regards,
> Guy.
>
> On Jul 8, 2014, at 1:16 AM, Pedro Pedruzzi wrote:
>
> Hello,
>
> I am new to this list.
>
> I am getting the following exception while trying to convert a simple mux
> to Verilog.
>
> myhdl.ConversionError: in file list-of-intbv.py, line 12: Not supported:
> list
>
> I know I could use tuple of int (since I am using constants), but I want
> to use lists to implement array of registers and the docs says it is
> possible.
>
> Here is the design:
>
> from myhdl import Signal, always_comb, intbv, toVerilog
>
> def uint(width, val = 0):
>     return intbv(val, 0, 2 ** width)
>
> def u32(val = 0):
>     return uint(32, val)
>
> def mux(s, o):
>     @always_comb
>     def logic():
>         i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
> u32(0xdddddddd) ]
>         o.next = i[s]
>     return logic
>
> s = Signal(intbv(0)[2:])
> o = Signal(intbv(0)[32:])
>
> toVerilog(mux, s, o)
>
>
> Any help is appreciated. Thanks.
>
> ızznɹpǝԀ oɹpǝԀ
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>
> http://p.sf.net/sfu/Bonitasoft_______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] Problem converting list of intbv

[Guy E. <gu...@no...>]

Hello Pedro,

here's how I would do it:

def mux(s, o):
    i = (0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd)
    
    @always_comb
    def logic():
        o.next = i[s]
    return logic

Regards,
Guy.

On Jul 8, 2014, at 1:16 AM, Pedro Pedruzzi wrote:

> Hello,
> 
> I am new to this list.
> 
> I am getting the following exception while trying to convert a simple mux to Verilog.
> 
> myhdl.ConversionError: in file list-of-intbv.py, line 12: Not supported: list
> 
> I know I could use tuple of int (since I am using constants), but I want to use lists to implement array of registers and the docs says it is possible.
> 
> Here is the design:
> 
> from myhdl import Signal, always_comb, intbv, toVerilog
> 
> def uint(width, val = 0):
>     return intbv(val, 0, 2 ** width)
> 
> def u32(val = 0):
>     return uint(32, val)
> 
> def mux(s, o):
>     @always_comb
>     def logic():
>         i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc), u32(0xdddddddd) ]
>         o.next = i[s]
>     return logic
> 
> s = Signal(intbv(0)[2:])
> o = Signal(intbv(0)[32:])
> 
> toVerilog(mux, s, o)
> 
> 
> Any help is appreciated. Thanks.
> 
> ızznɹpǝԀ oɹpǝԀ
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft_______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

[myhdl-list] Problem converting list of intbv

[Pedro P. <ped...@gm...>]

Hello,

I am new to this list.

I am getting the following exception while trying to convert a simple mux
to Verilog.

myhdl.ConversionError: in file list-of-intbv.py, line 12: Not supported:
list

I know I could use tuple of int (since I am using constants), but I want to
use lists to implement array of registers and the docs says it is possible.

Here is the design:

from myhdl import Signal, always_comb, intbv, toVerilog

def uint(width, val = 0):
    return intbv(val, 0, 2 ** width)

def u32(val = 0):
    return uint(32, val)

def mux(s, o):
    @always_comb
    def logic():
        i = [ u32(0xaaaaaaaa), u32(0xbbbbbbbb), u32(0xcccccccc),
u32(0xdddddddd) ]
        o.next = i[s]
    return logic

s = Signal(intbv(0)[2:])
o = Signal(intbv(0)[32:])

toVerilog(mux, s, o)


Any help is appreciated. Thanks.

ızznɹpǝԀ oɹpǝԀ

[myhdl-list] message without attachment

[Edward V. <dev...@sb...>]

 
Hello,
I am new to myhdl and python.  I have been able to create ram_l and 
ram_r. I have been able to also create a testbench that is sort of 
working.  I also have a ram_odd where the result of 

    @always(clk.posedge)
    def hdl():
                 
        pix.din_odd.next = (pix.dout_l + pix.dout_r)*ca1
     
    return hdl
When n = 1 I would like to use pix.dout_odd -1and pix.dout_odd +1 instead of what I have now.  

In the object pix of have methods to set the addr and we lines but don't know how to do the same with the above @always. to not use the ram_l & ram_r. 

    def setSig_we_odd(self,val):   
        self.we_odd.next = Signal(bool(val))
        
    def setSig_we_even(self,val):   
        self.we_even.next = Signal(bool(val))
    
     def setSig_we_l(self,val):   
       
 self.we_l.next = Signal(bool(val))
    
     def setSig_we_r(self,val):   
        self.we_r.next = Signal(bool(val))
    
     def setSig_addr_odd(self,val):   
        self.addr_odd.next = Signal(intbv(val))

     def setSig_addr_even(self,val):   
        self.addr_even.next = Signal(intbv(val))

    def setSig_addr_l(self,val):   
        self.addr_l.next = Signal(intbv(val))

    def
 setSig_addr_r(self,val):   
        self.addr_r.next = Signal(intbv(val))

    def setSig_din_odd(self,val):   
        ww = (26,18)
        self.din_odd.next = Signal(fixbv(val)[ww])        

    def setSig_din_l(self,val):   
        ww = (26,18)
        self.din_l.next = Signal(fixbv(val)[ww])

    def setSig_din_r(self,val):
        ww = (26,18)
        self.din_r.next =
 Signal(fixbv(val)[ww])
 The file attached is what I am using.
I would also like to use the methods in a python model instead of just in the testbench?
Any help will be appreciated.
Thanks
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

[myhdl-list] Verilog RAM

[Edward V. <dev...@sb...>]

Hello,
I am new to myhdl and python.  I have been able to create ram_l and ram_r. I have been able to also create a testbench that is sort of working.  I also have a ram_odd where the result of 

    @always(clk.posedge)
    def hdl():
                 
        pix.din_odd.next = (pix.dout_l + pix.dout_r)*ca1
     
    return hdl
When n = 1 I would like to use pix.dout_odd -1and pix.dout_odd +1 instead of what I have now.  

In the object pix of have methods to set the addr and we lines but don't know how to do the same with the above @always. to not use the ram_l & ram_r. 

    def setSig_we_odd(self,val):   
        self.we_odd.next = Signal(bool(val))
        
    def setSig_we_even(self,val):   
        self.we_even.next = Signal(bool(val))
    
     def setSig_we_l(self,val):   
        self.we_l.next = Signal(bool(val))
    
     def setSig_we_r(self,val):   
        self.we_r.next = Signal(bool(val))
    
     def setSig_addr_odd(self,val):   
        self.addr_odd.next = Signal(intbv(val))

     def setSig_addr_even(self,val):   
        self.addr_even.next = Signal(intbv(val))

    def setSig_addr_l(self,val):   
        self.addr_l.next = Signal(intbv(val))

    def setSig_addr_r(self,val):   
        self.addr_r.next = Signal(intbv(val))

    def setSig_din_odd(self,val):   
        ww = (26,18)
        self.din_odd.next = Signal(fixbv(val)[ww])        

    def setSig_din_l(self,val):   
        ww = (26,18)
        self.din_l.next = Signal(fixbv(val)[ww])

    def setSig_din_r(self,val):
        ww = (26,18)
        self.din_r.next = Signal(fixbv(val)[ww])

 The file attached is what I am using.
I would also like to use the methods in a python model instead of just in the testbench?
Any help will be appreciated.
Thanks
 

Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Thanks again.

Well, even if the synthesis result is the same, I really need to use the
CASE statement for state machines. If I don't do it the product leader
won't let me use MyHDL, lol :-)
Also, we use this here:

attribute SYN_ENCODING of READ_PARAMETER_ST_TYPE : type is "safe";

As far as I understood, I can send this line directly to the VHDL with the
special MyHDL command vhdl_code, right?



Cheers


On Fri, Jul 4, 2014 at 11:59 AM, Christopher Felton <chr...@gm...>
wrote:

> On Fri, Jul 4, 2014 at 9:43 AM, André Prado <and...@gm...>
> wrote:
>
>> Humm, my state machine was translated to an IF else if fashiong instead
>> of switch case.
>>
>
> Thats fine, compare synthesis results if there is concern.
>
> Regards,
> Chris
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

On Fri, Jul 4, 2014 at 9:43 AM, André Prado <and...@gm...> wrote:

> Humm, my state machine was translated to an IF else if fashiong instead of
> switch case.
>

Thats fine, compare synthesis results if there is concern.

Regards,
Chris

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

On Fri, Jul 4, 2014 at 9:21 AM, André Prado <and...@gm...> wrote:

> Now it says
>
> Can't infer variable type: real_reg and the line goes to the declaration
> real_reg = Signal(intbv(....))
> (This is the code with this modification : http://pastebin.com/UFV4Pp84)
>

You have to move the declaration (instantiation) outside of the
@always.


>
> I saw your EDAplayground code, the problem is, I do need to register the
> inputs, looks reasonable to use real_reg as a reg, right?
>
> How MyHDL deals with this? At least, as far as I know, in FPGA designs you
> should register the inputs/outputs of your module for a better throughput
> and fitter possibilities, like Logic Lock from Altera.
>

Using a Signal will add the register - take care it adds it where you
want, you will have considerable logic in front of the reg (selecting
what to load in the real_reg).


Regards,
Chris

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Humm, my state machine was translated to an IF else if fashiong instead of
switch case.

My code regarding to the State machine looks identical to the SineCompute
example. (http://pastebin.com/GYs2N3jD)

Cheers




On Fri, Jul 4, 2014 at 11:28 AM, André Prado <and...@gm...> wrote:

> Sorry I forgot to put outside the generator, it works now!!! Thank you so
> much.
>
>
> On Fri, Jul 4, 2014 at 11:22 AM, André Prado <and...@gm...>
> wrote:
>
>> Better FMAX, wrong word. :)
>>
>>
>> On Fri, Jul 4, 2014 at 11:21 AM, André Prado <and...@gm...>
>> wrote:
>>
>>> Now it says
>>>
>>> Can't infer variable type: real_reg and the line goes to the declaration
>>> real_reg = Signal(intbv(....))
>>> (This is the code with this modification : http://pastebin.com/UFV4Pp84)
>>>
>>> I saw your EDAplayground code, the problem is, I do need to register the
>>> inputs, looks reasonable to use real_reg as a reg, right?
>>>
>>> How MyHDL deals with this? At least, as far as I know, in FPGA designs
>>> you should register the inputs/outputs of your module for a better
>>> throughput and fitter possibilities, like Logic Lock from Altera.
>>>
>>> Christopher, thank you very much for taking your time to help me with
>>> this issue.
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> On Fri, Jul 4, 2014 at 10:31 AM, Christopher Felton <
>>> chr...@gm...> wrote:
>>>
>>>> If you convert everything to:
>>>>
>>>>     real_reg.next = ....
>>>>
>>>> then you need to define real_reg as:
>>>>
>>>>     real_reg = Signal(...)
>>>>
>>>> outside the generator, if you leave real_reg as a variable
>>>> (that is declared inside the generator as real_reg = intbv(...))
>>>> then you need to use [:] everywhere.
>>>>
>>>> you should be able to access the EDAplayground version now.
>>>>
>>>> Hope that helps,
>>>> Chris
>>>>
>>>>
>>>> On Fri, Jul 4, 2014 at 8:24 AM, André Prado <and...@gm...>
>>>> wrote:
>>>>
>>>>> Thanks Jan, I understand it now.
>>>>>
>>>>> Christopher, I made the alterations with your suggestions, however the
>>>>> same error when I try to convert still happens.
>>>>>
>>>>> http://pastebin.com/E2JGAJ50
>>>>>
>>>>>
>>>>> KeyError: 'real_reg' and a long traceback list error
>>>>>
>>>>> Any ideas?
>>>>>
>>>>> Also, I cannot access this link:
>>>>> http://www.edaplayground.com/x/eW
>>>>>
>>>>> Says I don't have the permission required.
>>>>>
>>>>> Cheers
>>>>>
>>>>>
>>>>> On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...>
>>>>> wrote:
>>>>>
>>>>>> On 07/04/2014 02:38 PM, André Prado wrote:
>>>>>> > I meant that you can't do this in VHDL but I thought that in MyHDL
>>>>>> you could do that.
>>>>>>
>>>>>> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl
>>>>>>
>>>>>> >
>>>>>> > Thanks for the Explanation, I look forward to translate the code of
>>>>>> my product from VHDL to MyHDL :), still in the learning process but the
>>>>>> power of Python makes VHDL looks out dated hehe.
>>>>>> >
>>>>>> > Cheers
>>>>>> >
>>>>>> >
>>>>>> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <
>>>>>> chr...@gm... <mailto:chr...@gm...>> wrote:
>>>>>> >
>>>>>> >     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <
>>>>>> and...@gm... <mailto:and...@gm...>> wrote:
>>>>>> >
>>>>>> >         So, I can't use the same signal as a signal and a variable.
>>>>>> Just like VHDL :)
>>>>>> >
>>>>>> >
>>>>>> >     Not sure what you mean?  You can mix the signal assignment
>>>>>> >     and variable assignment in VHDL?  If you declare a signal you
>>>>>> >     need to use "<=" if a variable ":=".
>>>>>> >
>>>>>> >     MyHDL only has one assignment operator, "=".  But the types
>>>>>> >     need to match.  You need to determine if you really want a
>>>>>> signal
>>>>>> >     or a variable:
>>>>>> >     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>>>>>> >
>>>>>> >
>>>>>> >         What is the difference between assigning a value with [:]
>>>>>> and without it? All the intbv values need a [:] ?
>>>>>> >
>>>>>> >
>>>>>> >     In Python everything is a reference
>>>>>> >
>>>>>> >          x = intbv(0, min=-4, max=4)
>>>>>> >          y = intbv(0, min=-8, max=8)
>>>>>> >          # ...
>>>>>> >          x = 2
>>>>>> >          y[:] = 4
>>>>>> >          assert isinstance(x, intbv)   # will fail
>>>>>> >          assert isinstance(y, intbv)   # will pass
>>>>>> >
>>>>>> >     The [:] indicates you are updating the value of the intbv type
>>>>>> >     (updating all the bits).  If you didn't do this you would loose
>>>>>> the
>>>>>> >     intbv information, because the reference would be assigned to
>>>>>> >     another type.  But in our HDL we need to know the types we are
>>>>>> >     dealing with (we remove some of the dynamicism :)
>>>>>> >
>>>>>> >     Yes, all "variable" intbv need "[:] = <new value>".
>>>>>> >
>>>>>> >     I made changes to your original and it converts, but I did not
>>>>>> >     check if it still passes the testbench:
>>>>>> >     http://www.edaplayground.com/x/eW
>>>>>> >
>>>>>> >     Note: conversion to Verilog will fail to compile with a Verilog
>>>>>> >     compiler because some of the signal/variable names are reserved
>>>>>> >     words (e.g. "real").  It has been on our todo list to check for
>>>>>> >     reserved words in conversion.
>>>>>> >
>>>>>> >     Regards,
>>>>>> >     Chris
>>>>>> >
>>>>>> >
>>>>>> ------------------------------------------------------------------------------
>>>>>> >     Open source business process management suite built on Java and
>>>>>> Eclipse
>>>>>> >     Turn processes into business applications with Bonita BPM
>>>>>> Community Edition
>>>>>> >     Quickly connect people, data, and systems into organized
>>>>>> workflows
>>>>>> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>>> >     http://p.sf.net/sfu/Bonitasoft
>>>>>> >     _______________________________________________
>>>>>> >     myhdl-list mailing list
>>>>>> >     myh...@li... <mailto:
>>>>>> myh...@li...>
>>>>>> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>>> >
>>>>>> >
>>>>>> >
>>>>>> >
>>>>>> > --
>>>>>> > Atenciosamente/Regards
>>>>>> > André Castelan Prado
>>>>>> >
>>>>>> >
>>>>>> >
>>>>>> ------------------------------------------------------------------------------
>>>>>> > Open source business process management suite built on Java and
>>>>>> Eclipse
>>>>>> > Turn processes into business applications with Bonita BPM Community
>>>>>> Edition
>>>>>> > Quickly connect people, data, and systems into organized workflows
>>>>>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>>> > http://p.sf.net/sfu/Bonitasoft
>>>>>> >
>>>>>> >
>>>>>> >
>>>>>> > _______________________________________________
>>>>>> > myhdl-list mailing list
>>>>>> > myh...@li...
>>>>>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>>> >
>>>>>>
>>>>>>
>>>>>> --
>>>>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>>>>      Python as a HDL: http://www.myhdl.org
>>>>>>      VHDL development, the modern way: http://www.sigasi.com
>>>>>>      World-class digital design: http://www.easics.com
>>>>>>
>>>>>>
>>>>>> ------------------------------------------------------------------------------
>>>>>> Open source business process management suite built on Java and
>>>>>> Eclipse
>>>>>> Turn processes into business applications with Bonita BPM Community
>>>>>> Edition
>>>>>> Quickly connect people, data, and systems into organized workflows
>>>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>>> http://p.sf.net/sfu/Bonitasoft
>>>>>> _______________________________________________
>>>>>> myhdl-list mailing list
>>>>>> myh...@li...
>>>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Atenciosamente/Regards
>>>>> André Castelan Prado
>>>>>
>>>>>
>>>>> ------------------------------------------------------------------------------
>>>>> Open source business process management suite built on Java and Eclipse
>>>>> Turn processes into business applications with Bonita BPM Community
>>>>> Edition
>>>>> Quickly connect people, data, and systems into organized workflows
>>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>> http://p.sf.net/sfu/Bonitasoft
>>>>> _______________________________________________
>>>>> myhdl-list mailing list
>>>>> myh...@li...
>>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>>
>>>>>
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Open source business process management suite built on Java and Eclipse
>>>> Turn processes into business applications with Bonita BPM Community
>>>> Edition
>>>> Quickly connect people, data, and systems into organized workflows
>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>> http://p.sf.net/sfu/Bonitasoft
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>
>>>>
>>>
>>>
>>> --
>>> Atenciosamente/Regards
>>> André Castelan Prado
>>>
>>
>>
>>
>> --
>> Atenciosamente/Regards
>> André Castelan Prado
>>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>



-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Sorry I forgot to put outside the generator, it works now!!! Thank you so
much.


On Fri, Jul 4, 2014 at 11:22 AM, André Prado <and...@gm...> wrote:

> Better FMAX, wrong word. :)
>
>
> On Fri, Jul 4, 2014 at 11:21 AM, André Prado <and...@gm...>
> wrote:
>
>> Now it says
>>
>> Can't infer variable type: real_reg and the line goes to the declaration
>> real_reg = Signal(intbv(....))
>> (This is the code with this modification : http://pastebin.com/UFV4Pp84)
>>
>> I saw your EDAplayground code, the problem is, I do need to register the
>> inputs, looks reasonable to use real_reg as a reg, right?
>>
>> How MyHDL deals with this? At least, as far as I know, in FPGA designs
>> you should register the inputs/outputs of your module for a better
>> throughput and fitter possibilities, like Logic Lock from Altera.
>>
>> Christopher, thank you very much for taking your time to help me with
>> this issue.
>>
>>
>>
>>
>>
>>
>>
>>
>> On Fri, Jul 4, 2014 at 10:31 AM, Christopher Felton <
>> chr...@gm...> wrote:
>>
>>> If you convert everything to:
>>>
>>>     real_reg.next = ....
>>>
>>> then you need to define real_reg as:
>>>
>>>     real_reg = Signal(...)
>>>
>>> outside the generator, if you leave real_reg as a variable
>>> (that is declared inside the generator as real_reg = intbv(...))
>>> then you need to use [:] everywhere.
>>>
>>> you should be able to access the EDAplayground version now.
>>>
>>> Hope that helps,
>>> Chris
>>>
>>>
>>> On Fri, Jul 4, 2014 at 8:24 AM, André Prado <and...@gm...>
>>> wrote:
>>>
>>>> Thanks Jan, I understand it now.
>>>>
>>>> Christopher, I made the alterations with your suggestions, however the
>>>> same error when I try to convert still happens.
>>>>
>>>> http://pastebin.com/E2JGAJ50
>>>>
>>>>
>>>> KeyError: 'real_reg' and a long traceback list error
>>>>
>>>> Any ideas?
>>>>
>>>> Also, I cannot access this link:
>>>> http://www.edaplayground.com/x/eW
>>>>
>>>> Says I don't have the permission required.
>>>>
>>>> Cheers
>>>>
>>>>
>>>> On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...>
>>>> wrote:
>>>>
>>>>> On 07/04/2014 02:38 PM, André Prado wrote:
>>>>> > I meant that you can't do this in VHDL but I thought that in MyHDL
>>>>> you could do that.
>>>>>
>>>>> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl
>>>>>
>>>>> >
>>>>> > Thanks for the Explanation, I look forward to translate the code of
>>>>> my product from VHDL to MyHDL :), still in the learning process but the
>>>>> power of Python makes VHDL looks out dated hehe.
>>>>> >
>>>>> > Cheers
>>>>> >
>>>>> >
>>>>> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <
>>>>> chr...@gm... <mailto:chr...@gm...>> wrote:
>>>>> >
>>>>> >     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <
>>>>> and...@gm... <mailto:and...@gm...>> wrote:
>>>>> >
>>>>> >         So, I can't use the same signal as a signal and a variable.
>>>>> Just like VHDL :)
>>>>> >
>>>>> >
>>>>> >     Not sure what you mean?  You can mix the signal assignment
>>>>> >     and variable assignment in VHDL?  If you declare a signal you
>>>>> >     need to use "<=" if a variable ":=".
>>>>> >
>>>>> >     MyHDL only has one assignment operator, "=".  But the types
>>>>> >     need to match.  You need to determine if you really want a signal
>>>>> >     or a variable:
>>>>> >     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>>>>> >
>>>>> >
>>>>> >         What is the difference between assigning a value with [:]
>>>>> and without it? All the intbv values need a [:] ?
>>>>> >
>>>>> >
>>>>> >     In Python everything is a reference
>>>>> >
>>>>> >          x = intbv(0, min=-4, max=4)
>>>>> >          y = intbv(0, min=-8, max=8)
>>>>> >          # ...
>>>>> >          x = 2
>>>>> >          y[:] = 4
>>>>> >          assert isinstance(x, intbv)   # will fail
>>>>> >          assert isinstance(y, intbv)   # will pass
>>>>> >
>>>>> >     The [:] indicates you are updating the value of the intbv type
>>>>> >     (updating all the bits).  If you didn't do this you would loose
>>>>> the
>>>>> >     intbv information, because the reference would be assigned to
>>>>> >     another type.  But in our HDL we need to know the types we are
>>>>> >     dealing with (we remove some of the dynamicism :)
>>>>> >
>>>>> >     Yes, all "variable" intbv need "[:] = <new value>".
>>>>> >
>>>>> >     I made changes to your original and it converts, but I did not
>>>>> >     check if it still passes the testbench:
>>>>> >     http://www.edaplayground.com/x/eW
>>>>> >
>>>>> >     Note: conversion to Verilog will fail to compile with a Verilog
>>>>> >     compiler because some of the signal/variable names are reserved
>>>>> >     words (e.g. "real").  It has been on our todo list to check for
>>>>> >     reserved words in conversion.
>>>>> >
>>>>> >     Regards,
>>>>> >     Chris
>>>>> >
>>>>> >
>>>>> ------------------------------------------------------------------------------
>>>>> >     Open source business process management suite built on Java and
>>>>> Eclipse
>>>>> >     Turn processes into business applications with Bonita BPM
>>>>> Community Edition
>>>>> >     Quickly connect people, data, and systems into organized
>>>>> workflows
>>>>> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>> >     http://p.sf.net/sfu/Bonitasoft
>>>>> >     _______________________________________________
>>>>> >     myhdl-list mailing list
>>>>> >     myh...@li... <mailto:
>>>>> myh...@li...>
>>>>> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>> >
>>>>> >
>>>>> >
>>>>> >
>>>>> > --
>>>>> > Atenciosamente/Regards
>>>>> > André Castelan Prado
>>>>> >
>>>>> >
>>>>> >
>>>>> ------------------------------------------------------------------------------
>>>>> > Open source business process management suite built on Java and
>>>>> Eclipse
>>>>> > Turn processes into business applications with Bonita BPM Community
>>>>> Edition
>>>>> > Quickly connect people, data, and systems into organized workflows
>>>>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>> > http://p.sf.net/sfu/Bonitasoft
>>>>> >
>>>>> >
>>>>> >
>>>>> > _______________________________________________
>>>>> > myhdl-list mailing list
>>>>> > myh...@li...
>>>>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>> >
>>>>>
>>>>>
>>>>> --
>>>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>>>      Python as a HDL: http://www.myhdl.org
>>>>>      VHDL development, the modern way: http://www.sigasi.com
>>>>>      World-class digital design: http://www.easics.com
>>>>>
>>>>>
>>>>> ------------------------------------------------------------------------------
>>>>> Open source business process management suite built on Java and Eclipse
>>>>> Turn processes into business applications with Bonita BPM Community
>>>>> Edition
>>>>> Quickly connect people, data, and systems into organized workflows
>>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>>> http://p.sf.net/sfu/Bonitasoft
>>>>> _______________________________________________
>>>>> myhdl-list mailing list
>>>>> myh...@li...
>>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Atenciosamente/Regards
>>>> André Castelan Prado
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Open source business process management suite built on Java and Eclipse
>>>> Turn processes into business applications with Bonita BPM Community
>>>> Edition
>>>> Quickly connect people, data, and systems into organized workflows
>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>> http://p.sf.net/sfu/Bonitasoft
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>
>>>>
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Open source business process management suite built on Java and Eclipse
>>> Turn processes into business applications with Bonita BPM Community
>>> Edition
>>> Quickly connect people, data, and systems into organized workflows
>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>> http://p.sf.net/sfu/Bonitasoft
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>>
>>
>>
>> --
>> Atenciosamente/Regards
>> André Castelan Prado
>>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>



-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Better FMAX, wrong word. :)


On Fri, Jul 4, 2014 at 11:21 AM, André Prado <and...@gm...> wrote:

> Now it says
>
> Can't infer variable type: real_reg and the line goes to the declaration
> real_reg = Signal(intbv(....))
> (This is the code with this modification : http://pastebin.com/UFV4Pp84)
>
> I saw your EDAplayground code, the problem is, I do need to register the
> inputs, looks reasonable to use real_reg as a reg, right?
>
> How MyHDL deals with this? At least, as far as I know, in FPGA designs you
> should register the inputs/outputs of your module for a better throughput
> and fitter possibilities, like Logic Lock from Altera.
>
> Christopher, thank you very much for taking your time to help me with this
> issue.
>
>
>
>
>
>
>
>
> On Fri, Jul 4, 2014 at 10:31 AM, Christopher Felton <
> chr...@gm...> wrote:
>
>> If you convert everything to:
>>
>>     real_reg.next = ....
>>
>> then you need to define real_reg as:
>>
>>     real_reg = Signal(...)
>>
>> outside the generator, if you leave real_reg as a variable
>> (that is declared inside the generator as real_reg = intbv(...))
>> then you need to use [:] everywhere.
>>
>> you should be able to access the EDAplayground version now.
>>
>> Hope that helps,
>> Chris
>>
>>
>> On Fri, Jul 4, 2014 at 8:24 AM, André Prado <and...@gm...>
>> wrote:
>>
>>> Thanks Jan, I understand it now.
>>>
>>> Christopher, I made the alterations with your suggestions, however the
>>> same error when I try to convert still happens.
>>>
>>> http://pastebin.com/E2JGAJ50
>>>
>>>
>>> KeyError: 'real_reg' and a long traceback list error
>>>
>>> Any ideas?
>>>
>>> Also, I cannot access this link:
>>> http://www.edaplayground.com/x/eW
>>>
>>> Says I don't have the permission required.
>>>
>>> Cheers
>>>
>>>
>>> On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...>
>>> wrote:
>>>
>>>> On 07/04/2014 02:38 PM, André Prado wrote:
>>>> > I meant that you can't do this in VHDL but I thought that in MyHDL
>>>> you could do that.
>>>>
>>>> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl
>>>>
>>>> >
>>>> > Thanks for the Explanation, I look forward to translate the code of
>>>> my product from VHDL to MyHDL :), still in the learning process but the
>>>> power of Python makes VHDL looks out dated hehe.
>>>> >
>>>> > Cheers
>>>> >
>>>> >
>>>> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <
>>>> chr...@gm... <mailto:chr...@gm...>> wrote:
>>>> >
>>>> >     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <
>>>> and...@gm... <mailto:and...@gm...>> wrote:
>>>> >
>>>> >         So, I can't use the same signal as a signal and a variable.
>>>> Just like VHDL :)
>>>> >
>>>> >
>>>> >     Not sure what you mean?  You can mix the signal assignment
>>>> >     and variable assignment in VHDL?  If you declare a signal you
>>>> >     need to use "<=" if a variable ":=".
>>>> >
>>>> >     MyHDL only has one assignment operator, "=".  But the types
>>>> >     need to match.  You need to determine if you really want a signal
>>>> >     or a variable:
>>>> >     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>>>> >
>>>> >
>>>> >         What is the difference between assigning a value with [:] and
>>>> without it? All the intbv values need a [:] ?
>>>> >
>>>> >
>>>> >     In Python everything is a reference
>>>> >
>>>> >          x = intbv(0, min=-4, max=4)
>>>> >          y = intbv(0, min=-8, max=8)
>>>> >          # ...
>>>> >          x = 2
>>>> >          y[:] = 4
>>>> >          assert isinstance(x, intbv)   # will fail
>>>> >          assert isinstance(y, intbv)   # will pass
>>>> >
>>>> >     The [:] indicates you are updating the value of the intbv type
>>>> >     (updating all the bits).  If you didn't do this you would loose
>>>> the
>>>> >     intbv information, because the reference would be assigned to
>>>> >     another type.  But in our HDL we need to know the types we are
>>>> >     dealing with (we remove some of the dynamicism :)
>>>> >
>>>> >     Yes, all "variable" intbv need "[:] = <new value>".
>>>> >
>>>> >     I made changes to your original and it converts, but I did not
>>>> >     check if it still passes the testbench:
>>>> >     http://www.edaplayground.com/x/eW
>>>> >
>>>> >     Note: conversion to Verilog will fail to compile with a Verilog
>>>> >     compiler because some of the signal/variable names are reserved
>>>> >     words (e.g. "real").  It has been on our todo list to check for
>>>> >     reserved words in conversion.
>>>> >
>>>> >     Regards,
>>>> >     Chris
>>>> >
>>>> >
>>>> ------------------------------------------------------------------------------
>>>> >     Open source business process management suite built on Java and
>>>> Eclipse
>>>> >     Turn processes into business applications with Bonita BPM
>>>> Community Edition
>>>> >     Quickly connect people, data, and systems into organized workflows
>>>> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>> >     http://p.sf.net/sfu/Bonitasoft
>>>> >     _______________________________________________
>>>> >     myhdl-list mailing list
>>>> >     myh...@li... <mailto:
>>>> myh...@li...>
>>>> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>> >
>>>> >
>>>> >
>>>> >
>>>> > --
>>>> > Atenciosamente/Regards
>>>> > André Castelan Prado
>>>> >
>>>> >
>>>> >
>>>> ------------------------------------------------------------------------------
>>>> > Open source business process management suite built on Java and
>>>> Eclipse
>>>> > Turn processes into business applications with Bonita BPM Community
>>>> Edition
>>>> > Quickly connect people, data, and systems into organized workflows
>>>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>> > http://p.sf.net/sfu/Bonitasoft
>>>> >
>>>> >
>>>> >
>>>> > _______________________________________________
>>>> > myhdl-list mailing list
>>>> > myh...@li...
>>>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>> >
>>>>
>>>>
>>>> --
>>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>>      Python as a HDL: http://www.myhdl.org
>>>>      VHDL development, the modern way: http://www.sigasi.com
>>>>      World-class digital design: http://www.easics.com
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Open source business process management suite built on Java and Eclipse
>>>> Turn processes into business applications with Bonita BPM Community
>>>> Edition
>>>> Quickly connect people, data, and systems into organized workflows
>>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>>> http://p.sf.net/sfu/Bonitasoft
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>
>>>
>>>
>>>
>>> --
>>> Atenciosamente/Regards
>>> André Castelan Prado
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Open source business process management suite built on Java and Eclipse
>>> Turn processes into business applications with Bonita BPM Community
>>> Edition
>>> Quickly connect people, data, and systems into organized workflows
>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>> http://p.sf.net/sfu/Bonitasoft
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>>
>>
>>
>> ------------------------------------------------------------------------------
>> Open source business process management suite built on Java and Eclipse
>> Turn processes into business applications with Bonita BPM Community
>> Edition
>> Quickly connect people, data, and systems into organized workflows
>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>> http://p.sf.net/sfu/Bonitasoft
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>



-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Now it says

Can't infer variable type: real_reg and the line goes to the declaration
real_reg = Signal(intbv(....))
(This is the code with this modification : http://pastebin.com/UFV4Pp84)

I saw your EDAplayground code, the problem is, I do need to register the
inputs, looks reasonable to use real_reg as a reg, right?

How MyHDL deals with this? At least, as far as I know, in FPGA designs you
should register the inputs/outputs of your module for a better throughput
and fitter possibilities, like Logic Lock from Altera.

Christopher, thank you very much for taking your time to help me with this
issue.








On Fri, Jul 4, 2014 at 10:31 AM, Christopher Felton <chr...@gm...>
wrote:

> If you convert everything to:
>
>     real_reg.next = ....
>
> then you need to define real_reg as:
>
>     real_reg = Signal(...)
>
> outside the generator, if you leave real_reg as a variable
> (that is declared inside the generator as real_reg = intbv(...))
> then you need to use [:] everywhere.
>
> you should be able to access the EDAplayground version now.
>
> Hope that helps,
> Chris
>
>
> On Fri, Jul 4, 2014 at 8:24 AM, André Prado <and...@gm...>
> wrote:
>
>> Thanks Jan, I understand it now.
>>
>> Christopher, I made the alterations with your suggestions, however the
>> same error when I try to convert still happens.
>>
>> http://pastebin.com/E2JGAJ50
>>
>>
>> KeyError: 'real_reg' and a long traceback list error
>>
>> Any ideas?
>>
>> Also, I cannot access this link:
>> http://www.edaplayground.com/x/eW
>>
>> Says I don't have the permission required.
>>
>> Cheers
>>
>>
>> On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...> wrote:
>>
>>> On 07/04/2014 02:38 PM, André Prado wrote:
>>> > I meant that you can't do this in VHDL but I thought that in MyHDL you
>>> could do that.
>>>
>>> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl
>>>
>>> >
>>> > Thanks for the Explanation, I look forward to translate the code of my
>>> product from VHDL to MyHDL :), still in the learning process but the power
>>> of Python makes VHDL looks out dated hehe.
>>> >
>>> > Cheers
>>> >
>>> >
>>> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <
>>> chr...@gm... <mailto:chr...@gm...>> wrote:
>>> >
>>> >     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <
>>> and...@gm... <mailto:and...@gm...>> wrote:
>>> >
>>> >         So, I can't use the same signal as a signal and a variable.
>>> Just like VHDL :)
>>> >
>>> >
>>> >     Not sure what you mean?  You can mix the signal assignment
>>> >     and variable assignment in VHDL?  If you declare a signal you
>>> >     need to use "<=" if a variable ":=".
>>> >
>>> >     MyHDL only has one assignment operator, "=".  But the types
>>> >     need to match.  You need to determine if you really want a signal
>>> >     or a variable:
>>> >     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>>> >
>>> >
>>> >         What is the difference between assigning a value with [:] and
>>> without it? All the intbv values need a [:] ?
>>> >
>>> >
>>> >     In Python everything is a reference
>>> >
>>> >          x = intbv(0, min=-4, max=4)
>>> >          y = intbv(0, min=-8, max=8)
>>> >          # ...
>>> >          x = 2
>>> >          y[:] = 4
>>> >          assert isinstance(x, intbv)   # will fail
>>> >          assert isinstance(y, intbv)   # will pass
>>> >
>>> >     The [:] indicates you are updating the value of the intbv type
>>> >     (updating all the bits).  If you didn't do this you would loose the
>>> >     intbv information, because the reference would be assigned to
>>> >     another type.  But in our HDL we need to know the types we are
>>> >     dealing with (we remove some of the dynamicism :)
>>> >
>>> >     Yes, all "variable" intbv need "[:] = <new value>".
>>> >
>>> >     I made changes to your original and it converts, but I did not
>>> >     check if it still passes the testbench:
>>> >     http://www.edaplayground.com/x/eW
>>> >
>>> >     Note: conversion to Verilog will fail to compile with a Verilog
>>> >     compiler because some of the signal/variable names are reserved
>>> >     words (e.g. "real").  It has been on our todo list to check for
>>> >     reserved words in conversion.
>>> >
>>> >     Regards,
>>> >     Chris
>>> >
>>> >
>>> ------------------------------------------------------------------------------
>>> >     Open source business process management suite built on Java and
>>> Eclipse
>>> >     Turn processes into business applications with Bonita BPM
>>> Community Edition
>>> >     Quickly connect people, data, and systems into organized workflows
>>> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>> >     http://p.sf.net/sfu/Bonitasoft
>>> >     _______________________________________________
>>> >     myhdl-list mailing list
>>> >     myh...@li... <mailto:
>>> myh...@li...>
>>> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>> >
>>> >
>>> >
>>> >
>>> > --
>>> > Atenciosamente/Regards
>>> > André Castelan Prado
>>> >
>>> >
>>> >
>>> ------------------------------------------------------------------------------
>>> > Open source business process management suite built on Java and Eclipse
>>> > Turn processes into business applications with Bonita BPM Community
>>> Edition
>>> > Quickly connect people, data, and systems into organized workflows
>>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>> > http://p.sf.net/sfu/Bonitasoft
>>> >
>>> >
>>> >
>>> > _______________________________________________
>>> > myhdl-list mailing list
>>> > myh...@li...
>>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>> >
>>>
>>>
>>> --
>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>      Python as a HDL: http://www.myhdl.org
>>>      VHDL development, the modern way: http://www.sigasi.com
>>>      World-class digital design: http://www.easics.com
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Open source business process management suite built on Java and Eclipse
>>> Turn processes into business applications with Bonita BPM Community
>>> Edition
>>> Quickly connect people, data, and systems into organized workflows
>>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>>> http://p.sf.net/sfu/Bonitasoft
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>
>>
>>
>> --
>> Atenciosamente/Regards
>> André Castelan Prado
>>
>>
>> ------------------------------------------------------------------------------
>> Open source business process management suite built on Java and Eclipse
>> Turn processes into business applications with Bonita BPM Community
>> Edition
>> Quickly connect people, data, and systems into organized workflows
>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>> http://p.sf.net/sfu/Bonitasoft
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Christopher F. <chr...@gm...>]

If you convert everything to:

    real_reg.next = ....

then you need to define real_reg as:

    real_reg = Signal(...)

outside the generator, if you leave real_reg as a variable
(that is declared inside the generator as real_reg = intbv(...))
then you need to use [:] everywhere.

you should be able to access the EDAplayground version now.

Hope that helps,
Chris


On Fri, Jul 4, 2014 at 8:24 AM, André Prado <and...@gm...> wrote:

> Thanks Jan, I understand it now.
>
> Christopher, I made the alterations with your suggestions, however the
> same error when I try to convert still happens.
>
> http://pastebin.com/E2JGAJ50
>
>
> KeyError: 'real_reg' and a long traceback list error
>
> Any ideas?
>
> Also, I cannot access this link:
> http://www.edaplayground.com/x/eW
>
> Says I don't have the permission required.
>
> Cheers
>
>
> On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...> wrote:
>
>> On 07/04/2014 02:38 PM, André Prado wrote:
>> > I meant that you can't do this in VHDL but I thought that in MyHDL you
>> could do that.
>>
>> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl
>>
>> >
>> > Thanks for the Explanation, I look forward to translate the code of my
>> product from VHDL to MyHDL :), still in the learning process but the power
>> of Python makes VHDL looks out dated hehe.
>> >
>> > Cheers
>> >
>> >
>> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <
>> chr...@gm... <mailto:chr...@gm...>> wrote:
>> >
>> >     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm...
>> <mailto:and...@gm...>> wrote:
>> >
>> >         So, I can't use the same signal as a signal and a variable.
>> Just like VHDL :)
>> >
>> >
>> >     Not sure what you mean?  You can mix the signal assignment
>> >     and variable assignment in VHDL?  If you declare a signal you
>> >     need to use "<=" if a variable ":=".
>> >
>> >     MyHDL only has one assignment operator, "=".  But the types
>> >     need to match.  You need to determine if you really want a signal
>> >     or a variable:
>> >     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>> >
>> >
>> >         What is the difference between assigning a value with [:] and
>> without it? All the intbv values need a [:] ?
>> >
>> >
>> >     In Python everything is a reference
>> >
>> >          x = intbv(0, min=-4, max=4)
>> >          y = intbv(0, min=-8, max=8)
>> >          # ...
>> >          x = 2
>> >          y[:] = 4
>> >          assert isinstance(x, intbv)   # will fail
>> >          assert isinstance(y, intbv)   # will pass
>> >
>> >     The [:] indicates you are updating the value of the intbv type
>> >     (updating all the bits).  If you didn't do this you would loose the
>> >     intbv information, because the reference would be assigned to
>> >     another type.  But in our HDL we need to know the types we are
>> >     dealing with (we remove some of the dynamicism :)
>> >
>> >     Yes, all "variable" intbv need "[:] = <new value>".
>> >
>> >     I made changes to your original and it converts, but I did not
>> >     check if it still passes the testbench:
>> >     http://www.edaplayground.com/x/eW
>> >
>> >     Note: conversion to Verilog will fail to compile with a Verilog
>> >     compiler because some of the signal/variable names are reserved
>> >     words (e.g. "real").  It has been on our todo list to check for
>> >     reserved words in conversion.
>> >
>> >     Regards,
>> >     Chris
>> >
>> >
>> ------------------------------------------------------------------------------
>> >     Open source business process management suite built on Java and
>> Eclipse
>> >     Turn processes into business applications with Bonita BPM Community
>> Edition
>> >     Quickly connect people, data, and systems into organized workflows
>> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>> >     http://p.sf.net/sfu/Bonitasoft
>> >     _______________________________________________
>> >     myhdl-list mailing list
>> >     myh...@li... <mailto:
>> myh...@li...>
>> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>> >
>> >
>> >
>> >
>> > --
>> > Atenciosamente/Regards
>> > André Castelan Prado
>> >
>> >
>> >
>> ------------------------------------------------------------------------------
>> > Open source business process management suite built on Java and Eclipse
>> > Turn processes into business applications with Bonita BPM Community
>> Edition
>> > Quickly connect people, data, and systems into organized workflows
>> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
>> > http://p.sf.net/sfu/Bonitasoft
>> >
>> >
>> >
>> > _______________________________________________
>> > myhdl-list mailing list
>> > myh...@li...
>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>> >
>>
>>
>> --
>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>      Python as a HDL: http://www.myhdl.org
>>      VHDL development, the modern way: http://www.sigasi.com
>>      World-class digital design: http://www.easics.com
>>
>>
>> ------------------------------------------------------------------------------
>> Open source business process management suite built on Java and Eclipse
>> Turn processes into business applications with Bonita BPM Community
>> Edition
>> Quickly connect people, data, and systems into organized workflows
>> Winner of BOSSIE, CODIE, OW2 and Gartner awards
>> http://p.sf.net/sfu/Bonitasoft
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

Thanks Jan, I understand it now.

Christopher, I made the alterations with your suggestions, however the same
error when I try to convert still happens.

http://pastebin.com/E2JGAJ50

KeyError: 'real_reg' and a long traceback list error

Any ideas?

Also, I cannot access this link:
http://www.edaplayground.com/x/eW

Says I don't have the permission required.

Cheers


On Fri, Jul 4, 2014 at 9:44 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 07/04/2014 02:38 PM, André Prado wrote:
> > I meant that you can't do this in VHDL but I thought that in MyHDL you
> could do that.
>
> http://myhdl.org/start/why.html#signals-and-variables-like-vhdl
>
> >
> > Thanks for the Explanation, I look forward to translate the code of my
> product from VHDL to MyHDL :), still in the learning process but the power
> of Python makes VHDL looks out dated hehe.
> >
> > Cheers
> >
> >
> > On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <
> chr...@gm... <mailto:chr...@gm...>> wrote:
> >
> >     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm...
> <mailto:and...@gm...>> wrote:
> >
> >         So, I can't use the same signal as a signal and a variable. Just
> like VHDL :)
> >
> >
> >     Not sure what you mean?  You can mix the signal assignment
> >     and variable assignment in VHDL?  If you declare a signal you
> >     need to use "<=" if a variable ":=".
> >
> >     MyHDL only has one assignment operator, "=".  But the types
> >     need to match.  You need to determine if you really want a signal
> >     or a variable:
> >     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
> >
> >
> >         What is the difference between assigning a value with [:] and
> without it? All the intbv values need a [:] ?
> >
> >
> >     In Python everything is a reference
> >
> >          x = intbv(0, min=-4, max=4)
> >          y = intbv(0, min=-8, max=8)
> >          # ...
> >          x = 2
> >          y[:] = 4
> >          assert isinstance(x, intbv)   # will fail
> >          assert isinstance(y, intbv)   # will pass
> >
> >     The [:] indicates you are updating the value of the intbv type
> >     (updating all the bits).  If you didn't do this you would loose the
> >     intbv information, because the reference would be assigned to
> >     another type.  But in our HDL we need to know the types we are
> >     dealing with (we remove some of the dynamicism :)
> >
> >     Yes, all "variable" intbv need "[:] = <new value>".
> >
> >     I made changes to your original and it converts, but I did not
> >     check if it still passes the testbench:
> >     http://www.edaplayground.com/x/eW
> >
> >     Note: conversion to Verilog will fail to compile with a Verilog
> >     compiler because some of the signal/variable names are reserved
> >     words (e.g. "real").  It has been on our todo list to check for
> >     reserved words in conversion.
> >
> >     Regards,
> >     Chris
> >
> >
> ------------------------------------------------------------------------------
> >     Open source business process management suite built on Java and
> Eclipse
> >     Turn processes into business applications with Bonita BPM Community
> Edition
> >     Quickly connect people, data, and systems into organized workflows
> >     Winner of BOSSIE, CODIE, OW2 and Gartner awards
> >     http://p.sf.net/sfu/Bonitasoft
> >     _______________________________________________
> >     myhdl-list mailing list
> >     myh...@li... <mailto:
> myh...@li...>
> >     https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
> >
> >
> >
> > --
> > Atenciosamente/Regards
> > André Castelan Prado
> >
> >
> >
> ------------------------------------------------------------------------------
> > Open source business process management suite built on Java and Eclipse
> > Turn processes into business applications with Bonita BPM Community
> Edition
> > Quickly connect people, data, and systems into organized workflows
> > Winner of BOSSIE, CODIE, OW2 and Gartner awards
> > http://p.sf.net/sfu/Bonitasoft
> >
> >
> >
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan D. <ja...@ja...>]

On 07/04/2014 02:38 PM, André Prado wrote:
> I meant that you can't do this in VHDL but I thought that in MyHDL you could do that.

http://myhdl.org/start/why.html#signals-and-variables-like-vhdl

>
> Thanks for the Explanation, I look forward to translate the code of my product from VHDL to MyHDL :), still in the learning process but the power of Python makes VHDL looks out dated hehe.
>
> Cheers
>
>
> On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <chr...@gm... <mailto:chr...@gm...>> wrote:
>
>     On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm... <mailto:and...@gm...>> wrote:
>
>         So, I can't use the same signal as a signal and a variable. Just like VHDL :)
>
>
>     Not sure what you mean?  You can mix the signal assignment
>     and variable assignment in VHDL?  If you declare a signal you
>     need to use "<=" if a variable ":=".
>
>     MyHDL only has one assignment operator, "=".  But the types
>     need to match.  You need to determine if you really want a signal
>     or a variable:
>     http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>
>
>         What is the difference between assigning a value with [:] and without it? All the intbv values need a [:] ?
>
>
>     In Python everything is a reference
>
>          x = intbv(0, min=-4, max=4)
>          y = intbv(0, min=-8, max=8)
>          # ...
>          x = 2
>          y[:] = 4
>          assert isinstance(x, intbv)   # will fail
>          assert isinstance(y, intbv)   # will pass
>
>     The [:] indicates you are updating the value of the intbv type
>     (updating all the bits).  If you didn't do this you would loose the
>     intbv information, because the reference would be assigned to
>     another type.  But in our HDL we need to know the types we are
>     dealing with (we remove some of the dynamicism :)
>
>     Yes, all "variable" intbv need "[:] = <new value>".
>
>     I made changes to your original and it converts, but I did not
>     check if it still passes the testbench:
>     http://www.edaplayground.com/x/eW
>
>     Note: conversion to Verilog will fail to compile with a Verilog
>     compiler because some of the signal/variable names are reserved
>     words (e.g. "real").  It has been on our todo list to check for
>     reserved words in conversion.
>
>     Regards,
>     Chris
>
>     ------------------------------------------------------------------------------
>     Open source business process management suite built on Java and Eclipse
>     Turn processes into business applications with Bonita BPM Community Edition
>     Quickly connect people, data, and systems into organized workflows
>     Winner of BOSSIE, CODIE, OW2 and Gartner awards
>     http://p.sf.net/sfu/Bonitasoft
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li... <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Open source business process management suite built on Java and Eclipse
> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
> Winner of BOSSIE, CODIE, OW2 and Gartner awards
> http://p.sf.net/sfu/Bonitasoft
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[André P. <and...@gm...>]

I meant that you can't do this in VHDL but I thought that in MyHDL you
could do that.

Thanks for the Explanation, I look forward to translate the code of my
product from VHDL to MyHDL :), still in the learning process but the power
of Python makes VHDL looks out dated hehe.

Cheers


On Fri, Jul 4, 2014 at 9:33 AM, Christopher Felton <chr...@gm...>
wrote:

> On Fri, Jul 4, 2014 at 6:50 AM, André Prado <and...@gm...>
> wrote:
>
>> So, I can't use the same signal as a signal and a variable. Just like
>> VHDL :)
>>
>
> Not sure what you mean?  You can mix the signal assignment
> and variable assignment in VHDL?  If you declare a signal you
> need to use "<=" if a variable ":=".
>
> MyHDL only has one assignment operator, "=".  But the types
> need to match.  You need to determine if you really want a signal
> or a variable:
> http://www.jandecaluwe.com/hdldesign/signal-assignments.html
>
>
>>
>> What is the difference between assigning a value with [:] and without it?
>> All the intbv values need a [:] ?
>>
>
> In Python everything is a reference
>
>     x = intbv(0, min=-4, max=4)
>     y = intbv(0, min=-8, max=8)
>     # ...
>     x = 2
>     y[:] = 4
>     assert isinstance(x, intbv)   # will fail
>     assert isinstance(y, intbv)   # will pass
>
> The [:] indicates you are updating the value of the intbv type
> (updating all the bits).  If you didn't do this you would loose the
> intbv information, because the reference would be assigned to
> another type.  But in our HDL we need to know the types we are
> dealing with (we remove some of the dynamicism :)
>
> Yes, all "variable" intbv need "[:] = <new value>".
>
> I made changes to your original and it converts, but I did not
> check if it still passes the testbench:
> http://www.edaplayground.com/x/eW
>
> Note: conversion to Verilog will fail to compile with a Verilog
> compiler because some of the signal/variable names are reserved
> words (e.g. "real").  It has been on our todo list to check for
> reserved words in conversion.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
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> Turn processes into business applications with Bonita BPM Community Edition
> Quickly connect people, data, and systems into organized workflows
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> http://p.sf.net/sfu/Bonitasoft
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-- 
Atenciosamente/Regards
André Castelan Prado