myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] Can't compare Signal(enum)

[Thomas H. <th...@ct...>]

I cannot compare signals containing enum instances; this looks like a 
bug to me:

c:\Users\thomas\ip>py -2.7-32
Python 2.7.7 (default, Jun  1 2014, 14:17:13) [MSC v.1500 32 bit 
(Intel)] on win32
Type "help", "copyright", "credits" or "license" for more information.
 >>> import myhdl
 >>>
 >>> state = myhdl.enum("foo", "bar")
 >>>
 >>> a = myhdl.Signal(state.foo)
 >>> b = myhdl.Signal(state.bar)
 >>>
 >>> print a == b
Traceback (most recent call last):
   File "<stdin>", line 1, in <module>
   File "C:\Python27\lib\site-packages\myhdl\_Signal.py", line 479, in 
__cmp__
     return cmp(self._val, other)
   File "C:\Python27\lib\site-packages\myhdl\_enum.py", line 109, in 
_notImplementedCompare
     raise NotImplementedError
NotImplementedError
 >>>


Thomas

Re: [myhdl-list] Pre-Init RAM

[Jan C. <jen...@mu...>]

On 24/07/14 08:53, Martin Strubel wrote:
> There is so much case dependency, that it might be very hard to satisfy
> everyone. I'd rather see if we can collect a few use cases and tricks
> from the community and document them.
I have a user defined code solution for the Lattice (ex Silicon 
Blue) tiny low power iCE40 FPGA parts.

Custom tools write a RAM image file containing the initialisation 
data.   This file contains a sixteen item list of 256b intbv, which 
is close to the format required in Verilog or VHDL instantiations 
of the block RAM primitive.  Inside a python comment there is also 
a simple hex dump so that I can read the content, because the bit 
ordering of the initialisation data is unsuitable for me to read.

The design imports this file and the RAM definition, which is 
instantiated with the initialisation data.  The initialised RAM 
works in simulation, and incorporates user-defined Verilog or VHDL 
code suitable to pass the initialisation data to the synthesis 
tools as Verilog defparam statements, or a VHDL generic map( statement.

If anyone else wants to use this I will try to complete testing and 
documenting soon.  Otherwise it will be much later.

Jan Coombs.
-- 

Re: [myhdl-list] Pre-Init RAM

[Martin S. <ha...@se...>]

Hi all,

> 
> Code exists to enable initial values but the difficult
> part has been making sure support is consistent across
> synthesis vendors (mainly FPGA).  Since we have not had
> someone willing to test all the vendors and verify the
> generic approach we have not been able to turn it on.
> 

This can be painful and cause support issues, so I wouldn't even start
thinking about adding it to MyHDL. I've taken an approach for the VHDL
side using generics as initialization value which works ok, but has some
minor quirks with various tools (some don't like an initialization of an
array with undefined size).

Example:

        constant BOOTROM_DATA_A_INIT : dram_bank_t := (
#include "dram_a_init.tmp"
        );

In the instanced memory block, the memory init data is passed on like

l1_ram_a : entity work.soc_memory_dma
        generic map (
     		...
                DRAM_INIT  => BOOTROM_DATA_A_INIT
        )


As you can guess, there is some abuse of the cpp involved, also, there
are switches to satisfy the tools.
Another tool generates the actual memory data content. It gets much more
complicated when using non standard bit widths (like 18 bit CPU
instructions).

There is so much case dependency, that it might be very hard to satisfy
everyone. I'd rather see if we can collect a few use cases and tricks
from the community and document them.

Greetings,

- Martin

Re: [myhdl-list] myHDL and BFM

[Chris T. <te...@gm...>]

Its not too hard to roll your own BFM.

Here's a simple one I wrote for APB3
https://github.com/testaco/whitebox/blob/feature/rx/hdl/apb3_utils.py


On Thu, Jul 24, 2014 at 8:02 AM, Matthias Dübon <
mat...@in...> wrote:

> Hello everyone
>
> I didn't use myHDL up to now but I am quite convinced this approach
> makes absolutely sense. But the problem I see is, how to integrate bus
> functional models. I am working quite often with AXI interfaces and I
> have great use of the AXI BFM. With myHDL I would need something
> similarly but as far as i googled there isn't a BFM for myHDL. Am I
> right?
>
> best
> Matthias
>
> ᐧ
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] myHDL and BFM

[Matthias D. <mat...@in...>]

Hello everyone

I didn't use myHDL up to now but I am quite convinced this approach
makes absolutely sense. But the problem I see is, how to integrate bus
functional models. I am working quite often with AXI interfaces and I
have great use of the AXI BFM. With myHDL I would need something
similarly but as far as i googled there isn't a BFM for myHDL. Am I
right?

best
Matthias

ᐧ

Re: [myhdl-list] Pre-Init RAM

[Daryl W. <dw...@ou...>]

If it is desired by more people to have an option to turn on/off signal initializations and list of signal initializations, I might be willing to work on writing tests and code for it and submit a patch. I'd like to hear more feedback first though on whether other people might find this useful. It'll be a little work as I'm a little rusty in Verilog (although this seems like it should be pretty straightforward). My current strategy is working very well for me right now. So, if no one else thinks it will be useful for them, then probably not worth the effort.
The page linked by the page you sent says that there is no need that the synthesis tools do anything meaningful with the initialization code and that it is primarily to make the pre- and post-conversion simulations match. Doesn't that mean that having an option to turn it on/off should be available regardless of synthesis results? I would envision a way to activate an individual signal or signal list. Possibly, this could be accomplished by way of an attribute called "._initialize" that defaults to False, but can be set to True in the constructor using a keyword argument. This would allow everyone to carry on like normal, but it would also enable the initializations for those who want to use them. 
-Daryl 		 	   		  

Re: [myhdl-list] Pre-Init RAM

[Christopher F. <chr...@gm...>]

On 7/21/2014 6:56 PM, Daryl Wasden wrote:
> Chris,
> Thanks for the reply. At first, I thought user-defined code would be just the thing, but I couldn't figure out a way to suppress the signal instantiation in the MyHDL-generated output, and then provide my own to replace it. So, I gave up and tried this. I'll read up on the initial values support link you provided and see what I can see.
> -Daryl
>

One thing to note, the page I linked is a summary of the
mailing-list conversation - it can be a little confusing
out of context, it should be updated.

And I misspoke, the pre-init RAM code does not exist (well
it existed in someones sandbox at some point).  The initial
value support that exists is just for signals, not list of
signals.  Will need to see if we can dig up the past code
(Norbo?) or if your version can be merged and used.

Regards,
Chris

Re: [myhdl-list] Pre-Init RAM

[Daryl W. <dw...@ou...>]

Chris, 
Thanks for the reply. At first, I thought user-defined code would be just the thing, but I couldn't figure out a way to suppress the signal instantiation in the MyHDL-generated output, and then provide my own to replace it. So, I gave up and tried this. I'll read up on the initial values support link you provided and see what I can see.
-Daryl

> To: myh...@li...
> From: chr...@gm...
> Date: Mon, 21 Jul 2014 18:21:04 -0500
> Subject: Re: [myhdl-list] Pre-Init RAM
> 
> On 7/21/14 4:50 PM, Daryl Wasden wrote:
> 
> >
> > http://article.gmane.org/gmane.comp.python.myhdl/2235
> >
> > Its a long thread with lots of discussion. The use-case for converting
> > initial values that I find most interesting is the pre-init RAM for
> > FPGAs. I have used this extensively with xst and VHDL. I often use an
> > array of signed numbers for storing filter coefficients, twiddle factors
> > for FFTs, and other quantities. Sometimes, I want these things to be
> > modifiable at run-time (which prevents me from using the case
> > structure/tuple of ints method). I prefer to write it into my RTL,
> > because it allows the synthesis tool to choose between block RAM,
> > distributed RAM, etc. for me. Unless I have a compelling reason to worry
> > about these low level details, I'd rather not.
> 
> Code exists to enable initial values but the difficult
> part has been making sure support is consistent across
> synthesis vendors (mainly FPGA).  Since we have not had
> someone willing to test all the vendors and verify the
> generic approach we have not been able to turn it on.
> 
> The latest information on the initial value support can be
> found here (this is probably a little outdated):
> http://dev.myhdl.org/ideas/initial-values.html
> 
> The previous does not require a separate function call but
> will use the initial value in the declaration (instantiation)
> as the init value.
> 
> Maybe we need a hook to provide people with there own approach.
> One such hook is using the "user defined" modules.  This way
> you can write whatever VHDL you need to generate the initial
> values.  This might be the best option until we know the
> generic method is supported by "most" tools.
> 
> Regards,
> Chris
> 
> 
> 
> 
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
 		 	   		  

Re: [myhdl-list] Pre-Init RAM

[Christopher F. <chr...@gm...>]

On 7/21/14 4:50 PM, Daryl Wasden wrote:

>
> http://article.gmane.org/gmane.comp.python.myhdl/2235
>
> Its a long thread with lots of discussion. The use-case for converting
> initial values that I find most interesting is the pre-init RAM for
> FPGAs. I have used this extensively with xst and VHDL. I often use an
> array of signed numbers for storing filter coefficients, twiddle factors
> for FFTs, and other quantities. Sometimes, I want these things to be
> modifiable at run-time (which prevents me from using the case
> structure/tuple of ints method). I prefer to write it into my RTL,
> because it allows the synthesis tool to choose between block RAM,
> distributed RAM, etc. for me. Unless I have a compelling reason to worry
> about these low level details, I'd rather not.

Code exists to enable initial values but the difficult
part has been making sure support is consistent across
synthesis vendors (mainly FPGA).  Since we have not had
someone willing to test all the vendors and verify the
generic approach we have not been able to turn it on.

The latest information on the initial value support can be
found here (this is probably a little outdated):
http://dev.myhdl.org/ideas/initial-values.html

The previous does not require a separate function call but
will use the initial value in the declaration (instantiation)
as the init value.

Maybe we need a hook to provide people with there own approach.
One such hook is using the "user defined" modules.  This way
you can write whatever VHDL you need to generate the initial
values.  This might be the best option until we know the
generic method is supported by "most" tools.

Regards,
Chris

[myhdl-list] Pre-Init RAM

[Daryl W. <dw...@ou...>]

Hello everyone,
I do a lot of signal processing blocks for prototyping in FPGAs. I love MyHDL and prefer to use it whenever possible. That said, I was looking for a solution to a problem I am having. There is a thread dating back to 2012 where there was a discussion regarding the conversion of initial values to VHDL and Verilog. See the link below for more information:
http://article.gmane.org/gmane.comp.python.myhdl/2235

Its a long thread with lots of discussion. The use-case for converting initial values that I find most interesting is the pre-init RAM for FPGAs. I have used this extensively with xst and VHDL. I often use an array of signed numbers for storing filter coefficients, twiddle factors for FFTs, and other quantities. Sometimes, I want these things to be modifiable at run-time (which prevents me from using the case structure/tuple of ints method). I prefer to write it into my RTL, because it allows the synthesis tool to choose between block RAM, distributed RAM, etc. for me. Unless I have a compelling reason to worry about these low level details, I'd rather not. 
I have created a contrived test module and something I wrote quickly to demonstrate one approach to solving this issue on my own. This example is highly contrived, but it illustrates how to initialize signals, and I think it probably wouldn't be too hard to convert it to support Verilog.
You can download the example here: 
https://bitbucket.org/dwasden/myhdl_util
Line 226-234 demonstrate the interface for a new function, initVHDL() that has the same arguments as toVHDL(). I ran the code with the 0.9dev branch installed. 
To summarize the approach: A call is made to the toVHDL() function on the test module to produce testmod.vhd (provided in the repository so you don't need to run the code). Then, a call is made to the initVHDL() function. The call to initVHDL() extracts the hierarchy, then generates the signal and memory lists using the same internal functionality as toVHDL(). Then it proceeds line by line through the VHDL file and tries to find lines that match Signal declaration syntax. If a line doesn't match, it repeats it. If a line matches, it searches for the signals in the signal and memory lists. If the signals are found, it writes a signal declaration with an initial value equal to the value of the signal in the signal list. It may be a good idea to do this more selectively in the future if I continue to need it (for example, only for signal names that are explicitly passed to the function). 
I don't like this approach primarily because I am using the converter's internal functionality to find the signal names and initial values. This functionality is not part of the public API and may change in future releases, but I also don't see a better way to achieve the results that I want (automated signal initialization to match the VHDL output and the MyHDL output). I haven't yet found anything in the documentation, and the closest thing I found was that thread. 
So, this leaves me wondering... Is there already support for this in MyHDL? If not, does anyone else think that this feature would benefit them? Is it something that the community would be supportive of?
Thanks,Daryl
Warning: the code in the repository has been lightly validated. It is for illustration of the method only. If I were to provide something for the general public to use, then I would test it much more thoroughly (and provide test code for anyone else to run so they could modify it for their own uses). 		 	   		  

Re: [myhdl-list] Best way to think in test driven development using MyHDL coming from VHDL?

[Christopher F. <chr...@gm...>]

On 7/15/2014 9:51 AM, André Prado wrote:
<snip>
>
> Is this the best way to do it?
>
> I am evaluation it by running:
>
> py.test tb_cordic.py -v
>
> It does work but I don't know if it's the best way to do it,

I don't know if there is a "best", many like to
use py.test, less scaffolding other prefer the
Python included unittest.

The great thing, MyHDL is Python - we can use
the Python references to investigate [1][2].

I haven't reviewed you code fully but I tend to
use a similar approach (that is use py.test),
I use this template

     def testbench(args):
         # all dut port instantiations
         clock = Signal(bool(0))
         reset = ResetSignal(0, active=0, async=True)
	# ...

         def _test():
             tbdut = # ...

             return tbdut, tbstim, ...

         Simulation(traceSignals(_test)).run()

I use the inner function because I often want to
view my testbench signals in the waveform and it
also allows multiple tests to be defined using
the same port definitions and arguments.

Typically, I use argparse to fill the test arguments,
this might be things like number of loop iterations
etc.

>
> I also have two functions doing almost the same thing, (random_bench and
> fft_bench), this violates the DRY mantra, but I could'nt find a way to do
> it generic enough.
>
> Taking all the DRY stuff (that also appears on my tests) that I messed up
> while testing, any good tips? Am I in the right path?

You could use the inner function to define your
"stimulus" and have the generic generators in the
outer function.  This will allow you to reuse
definitions and generic generators:

     def testbench():
         # signal instantiations

         @always(delay(3))
         def tbclk():
             clock.next = not clock

         @instance
         def tbmon():  #monitor
             # ...

         def _test_fft():
             tbdut =  # dut needs to be in the func to be traced
             # ...
             @instance
             def tbstim()
                 # ...
             return tbclk, tbmon, tbdut, tbstim, ....

        def _test_rand():
             tbdut = ...
             @instance
             def tbstim():
             # ...
             return tbclk, tbmon, tbdut, tbstim, ...


     if args.run == 'fft':
          tb = traceSignals(_test_fft)
     else:
          tb = traceSignals(_test_rand)
     Simulation(tb).run()


Regards,
Chris


[1] http://docs.python-guide.org/en/latest/writing/tests/
[2] http://www.ibm.com/developerworks/aix/library/au-python_test/

Re: [myhdl-list] First steps

[Colin B. <col...@gm...>]

If using Linux you can set your MAC address to any you want temporarily
while using the software, if you're worried about this:
http://www.aboutlinux.info/2005/09/how-to-change-mac-address-of-your.html.


On Tue, Jul 15, 2014 at 10:55 AM, André Prado <and...@gm...>
wrote:

> If you are using a Lattice FPGA you do have to use Lattice's tools to
> generate the fpga configuration file.
>
>
> On Tue, Jul 15, 2014 at 2:54 PM, wally <wa...@vo...> wrote:
>
>>
>> Thank You!
>> but its not really free, they require a lot of privacy data including
>> physical MAC address.
>> Now i have a problem i fear.
>>
>>
>>
>>
>> On 07/15/2014 07:26 PM, Colin Beighley wrote:
>>
>> Looks like you can get a free version of Lattice Diamond here:
>> http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx -
>> under the "Licensing" tab, "Click Here to Get your Free License".
>>
>>
>> On Tue, Jul 15, 2014 at 10:17 AM, wally <wa...@vo...> wrote:
>>
>>>
>>> Thank you, but no Lattice Software available.
>>> At least not Lattice Diamond.
>>> Alternatives ?
>>>
>>>
>>>
>>>
>>> On 07/15/2014 07:12 PM, André Prado wrote:
>>>
>>>  http://www.fpgarelated.com/showarticle/25.php
>>>
>>>  You can use any text editor that you wish, I use VIM.
>>> You can follow this tutorial, when you have your VHDL generated, create
>>> a new project in Lattice software, set the pins and compile.
>>>
>>>
>>>
>>>
>>> On Tue, Jul 15, 2014 at 1:28 PM, wally <wa...@vo...> wrote:
>>>
>>>> Hello,
>>>>
>>>> i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
>>>> Now i want to start learning how to program this devices on
>>>> a linux machine (OpenSuse13.1).
>>>> What are good first steps for beginner and what devel software
>>>> do you recommend ?
>>>> Is there a devel tool ide or Gui or only command line and emacs ?
>>>> ( i do not want to use Lattice diamond )
>>>>
>>>> thank you
>>>> wally
>>>>
>>>>
>>>>
>>>> ------------------------------------------------------------------------------
>>>> Want fast and easy access to all the code in your enterprise? Index and
>>>> search up to 200,000 lines of code with a free copy of Black Duck
>>>> Code Sight - the same software that powers the world's largest code
>>>> search on Ohloh, the Black Duck Open Hub! Try it now.
>>>> http://p.sf.net/sfu/bds
>>>> _______________________________________________
>>>> myhdl-list mailing list
>>>> myh...@li...
>>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>>
>>>
>>>
>>>
>>> --
>>>   Atenciosamente/Regards
>>> André Castelan Prado
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Want fast and easy access to all the code in your enterprise? Index and
>>> search up to 200,000 lines of code with a free copy of Black Duck
>>> Code Sight - the same software that powers the world's largest code
>>> search on Ohloh, the Black Duck Open Hub! Try it now.http://p.sf.net/sfu/bds
>>>
>>>
>>>
>>> _______________________________________________
>>> myhdl-list mailing lis...@li...https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>>
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Want fast and easy access to all the code in your enterprise? Index and
>>> search up to 200,000 lines of code with a free copy of Black Duck
>>> Code Sight - the same software that powers the world's largest code
>>> search on Ohloh, the Black Duck Open Hub! Try it now.
>>> http://p.sf.net/sfu/bds
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>>
>>
>>
>> ------------------------------------------------------------------------------
>> Want fast and easy access to all the code in your enterprise? Index and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.http://p.sf.net/sfu/bds
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing lis...@li...https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Want fast and easy access to all the code in your enterprise? Index and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] First steps

[André P. <and...@gm...>]

If you are using a Lattice FPGA you do have to use Lattice's tools to
generate the fpga configuration file.


On Tue, Jul 15, 2014 at 2:54 PM, wally <wa...@vo...> wrote:

>
> Thank You!
> but its not really free, they require a lot of privacy data including
> physical MAC address.
> Now i have a problem i fear.
>
>
>
>
> On 07/15/2014 07:26 PM, Colin Beighley wrote:
>
> Looks like you can get a free version of Lattice Diamond here:
> http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx -
> under the "Licensing" tab, "Click Here to Get your Free License".
>
>
> On Tue, Jul 15, 2014 at 10:17 AM, wally <wa...@vo...> wrote:
>
>>
>> Thank you, but no Lattice Software available.
>> At least not Lattice Diamond.
>> Alternatives ?
>>
>>
>>
>>
>> On 07/15/2014 07:12 PM, André Prado wrote:
>>
>>  http://www.fpgarelated.com/showarticle/25.php
>>
>>  You can use any text editor that you wish, I use VIM.
>> You can follow this tutorial, when you have your VHDL generated, create a
>> new project in Lattice software, set the pins and compile.
>>
>>
>>
>>
>> On Tue, Jul 15, 2014 at 1:28 PM, wally <wa...@vo...> wrote:
>>
>>> Hello,
>>>
>>> i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
>>> Now i want to start learning how to program this devices on
>>> a linux machine (OpenSuse13.1).
>>> What are good first steps for beginner and what devel software
>>> do you recommend ?
>>> Is there a devel tool ide or Gui or only command line and emacs ?
>>> ( i do not want to use Lattice diamond )
>>>
>>> thank you
>>> wally
>>>
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> Want fast and easy access to all the code in your enterprise? Index and
>>> search up to 200,000 lines of code with a free copy of Black Duck
>>> Code Sight - the same software that powers the world's largest code
>>> search on Ohloh, the Black Duck Open Hub! Try it now.
>>> http://p.sf.net/sfu/bds
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>
>>
>>
>> --
>>   Atenciosamente/Regards
>> André Castelan Prado
>>
>>
>> ------------------------------------------------------------------------------
>> Want fast and easy access to all the code in your enterprise? Index and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.http://p.sf.net/sfu/bds
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing lis...@li...https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Want fast and easy access to all the code in your enterprise? Index and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.http://p.sf.net/sfu/bds
>
>
>
> _______________________________________________
> myhdl-list mailing lis...@li...https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] First steps

[wally <wa...@vo...>]

Thank You!
but its not really free, they require a lot of privacy data including
physical MAC address.
Now i have a problem i fear.



On 07/15/2014 07:26 PM, Colin Beighley wrote:
> Looks like you can get a free version of Lattice Diamond here: 
> http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx - 
> under the "Licensing" tab, "Click Here to Get your Free License".
>
>
> On Tue, Jul 15, 2014 at 10:17 AM, wally <wa...@vo... 
> <mailto:wa...@vo...>> wrote:
>
>
>     Thank you, but no Lattice Software available.
>     At least not Lattice Diamond.
>     Alternatives ?
>
>
>
>
>     On 07/15/2014 07:12 PM, André Prado wrote:
>>     http://www.fpgarelated.com/showarticle/25.php
>>
>>     You can use any text editor that you wish, I use VIM.
>>     You can follow this tutorial, when you have your VHDL generated,
>>     create a new project in Lattice software, set the pins and compile.
>>
>>
>>
>>
>>     On Tue, Jul 15, 2014 at 1:28 PM, wally <wa...@vo...
>>     <mailto:wa...@vo...>> wrote:
>>
>>         Hello,
>>
>>         i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
>>         Now i want to start learning how to program this devices on
>>         a linux machine (OpenSuse13.1).
>>         What are good first steps for beginner and what devel software
>>         do you recommend ?
>>         Is there a devel tool ide or Gui or only command line and emacs ?
>>         ( i do not want to use Lattice diamond )
>>
>>         thank you
>>         wally
>>
>>
>>         ------------------------------------------------------------------------------
>>         Want fast and easy access to all the code in your enterprise?
>>         Index and
>>         search up to 200,000 lines of code with a free copy of Black Duck
>>         Code Sight - the same software that powers the world's
>>         largest code
>>         search on Ohloh, the Black Duck Open Hub! Try it now.
>>         http://p.sf.net/sfu/bds
>>         _______________________________________________
>>         myhdl-list mailing list
>>         myh...@li...
>>         <mailto:myh...@li...>
>>         https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>>
>>
>>     -- 
>>     Atenciosamente/Regards
>>     André Castelan Prado
>>
>>
>>     ------------------------------------------------------------------------------
>>     Want fast and easy access to all the code in your enterprise? Index and
>>     search up to 200,000 lines of code with a free copy of Black Duck
>>     Code Sight - the same software that powers the world's largest code
>>     search on Ohloh, the Black Duck Open Hub! Try it now.
>>     http://p.sf.net/sfu/bds
>>
>>
>>     _______________________________________________
>>     myhdl-list mailing list
>>     myh...@li...  <mailto:myh...@li...>
>>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>     ------------------------------------------------------------------------------
>     Want fast and easy access to all the code in your enterprise?
>     Index and
>     search up to 200,000 lines of code with a free copy of Black Duck
>     Code Sight - the same software that powers the world's largest code
>     search on Ohloh, the Black Duck Open Hub! Try it now.
>     http://p.sf.net/sfu/bds
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li...
>     <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] First steps

[Christopher F. <chr...@gm...>]

On 7/15/2014 12:17 PM, wally wrote:
>
> Thank you, but no Lattice Software available.
> At least not Lattice Diamond.
> Alternatives ?

To synthesize, place-n-route (Par), and generate the
bitstream you will need the Lattice software - no
way around it.  Fairly sure you can download a free
version for linux [1].

For all your design work -assuming you are using myhdl-
you can use any Python IDE to develop and then use a
waveform viewer like gtkwave to help debug simulations,
if needed.

Regards,
Chris

[1] the latest diamond download for linux, will need
to login to download:
http://www.latticesemi.com/view_document?document_id=50605

Re: [myhdl-list] First steps

[Colin B. <col...@gm...>]

Looks like you can get a free version of Lattice Diamond here:
http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/FPGAandLDS/LatticeDiamond.aspx
-
under the "Licensing" tab, "Click Here to Get your Free License".


On Tue, Jul 15, 2014 at 10:17 AM, wally <wa...@vo...> wrote:

>
> Thank you, but no Lattice Software available.
> At least not Lattice Diamond.
> Alternatives ?
>
>
>
>
> On 07/15/2014 07:12 PM, André Prado wrote:
>
>  http://www.fpgarelated.com/showarticle/25.php
>
>  You can use any text editor that you wish, I use VIM.
> You can follow this tutorial, when you have your VHDL generated, create a
> new project in Lattice software, set the pins and compile.
>
>
>
>
> On Tue, Jul 15, 2014 at 1:28 PM, wally <wa...@vo...> wrote:
>
>> Hello,
>>
>> i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
>> Now i want to start learning how to program this devices on
>> a linux machine (OpenSuse13.1).
>> What are good first steps for beginner and what devel software
>> do you recommend ?
>> Is there a devel tool ide or Gui or only command line and emacs ?
>> ( i do not want to use Lattice diamond )
>>
>> thank you
>> wally
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Want fast and easy access to all the code in your enterprise? Index and
>> search up to 200,000 lines of code with a free copy of Black Duck
>> Code Sight - the same software that powers the world's largest code
>> search on Ohloh, the Black Duck Open Hub! Try it now.
>> http://p.sf.net/sfu/bds
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
>   Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.http://p.sf.net/sfu/bds
>
>
>
> _______________________________________________
> myhdl-list mailing lis...@li...https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] First steps

[wally <wa...@vo...>]

Thank you, but no Lattice Software available.
At least not Lattice Diamond.
Alternatives ?



On 07/15/2014 07:12 PM, André Prado wrote:
> http://www.fpgarelated.com/showarticle/25.php
>
> You can use any text editor that you wish, I use VIM.
> You can follow this tutorial, when you have your VHDL generated, 
> create a new project in Lattice software, set the pins and compile.
>
>
>
>
> On Tue, Jul 15, 2014 at 1:28 PM, wally <wa...@vo... 
> <mailto:wa...@vo...>> wrote:
>
>     Hello,
>
>     i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
>     Now i want to start learning how to program this devices on
>     a linux machine (OpenSuse13.1).
>     What are good first steps for beginner and what devel software
>     do you recommend ?
>     Is there a devel tool ide or Gui or only command line and emacs ?
>     ( i do not want to use Lattice diamond )
>
>     thank you
>     wally
>
>
>     ------------------------------------------------------------------------------
>     Want fast and easy access to all the code in your enterprise?
>     Index and
>     search up to 200,000 lines of code with a free copy of Black Duck
>     Code Sight - the same software that powers the world's largest code
>     search on Ohloh, the Black Duck Open Hub! Try it now.
>     http://p.sf.net/sfu/bds
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li...
>     <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> -- 
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] First steps

[André P. <and...@gm...>]

http://www.fpgarelated.com/showarticle/25.php

You can use any text editor that you wish, I use VIM.
You can follow this tutorial, when you have your VHDL generated, create a
new project in Lattice software, set the pins and compile.




On Tue, Jul 15, 2014 at 1:28 PM, wally <wa...@vo...> wrote:

> Hello,
>
> i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
> Now i want to start learning how to program this devices on
> a linux machine (OpenSuse13.1).
> What are good first steps for beginner and what devel software
> do you recommend ?
> Is there a devel tool ide or Gui or only command line and emacs ?
> ( i do not want to use Lattice diamond )
>
> thank you
> wally
>
>
>
> ------------------------------------------------------------------------------
> Want fast and easy access to all the code in your enterprise? Index and
> search up to 200,000 lines of code with a free copy of Black Duck
> Code Sight - the same software that powers the world's largest code
> search on Ohloh, the Black Duck Open Hub! Try it now.
> http://p.sf.net/sfu/bds
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Atenciosamente/Regards
André Castelan Prado

[myhdl-list] First steps

[wally <wa...@vo...>]

Hello,

i bought a  Pif-7000 (XO2-7000HC) and a TIF-4000 (XO2-4000).
Now i want to start learning how to program this devices on
a linux machine (OpenSuse13.1).
What are good first steps for beginner and what devel software
do you recommend ?
Is there a devel tool ide or Gui or only command line and emacs ?
( i do not want to use Lattice diamond )

thank you
wally

[myhdl-list] Best way to think in test driven development using MyHDL coming from VHDL?

[André P. <and...@gm...>]

So, I am having really fun with MyHDL but I think I am testing things in
the wrong way.

I am toying around with my Cordic module (that I got working thanks to your
help) and I am trying to evolute my test bench

http://pastebin.com/Hbd9eRui

Is this the best way to do it?

I am evaluation it by running:

py.test tb_cordic.py -v

It does work but I don't know if it's the best way to do it,

I also have two functions doing almost the same thing, (random_bench and
fft_bench), this violates the DRY mantra, but I could'nt find a way to do
it generic enough.

Taking all the DRY stuff (that also appears on my tests) that I messed up
while testing, any good tips? Am I in the right path?

I would like py.test to print what it is doing, like, when it runs
test_max_clock it should print the clk periods that he is going throught,
print statement do not work in py.test, only when an assert fails

I would also be glad if someone could point me to a good book in this
subject (doesn't need to be myhdl or python related)

Cheers and thanks for the great work! It's so much better than looking at
waveforms...





-- 
Atenciosamente/Regards
André Castelan Prado

[myhdl-list] Python bool type used as constant

[Josy B. <jo...@c-...>]

Hi all,

The following code:
def ramreader( Clk, Reset , ... , WRAP_AROUND ): # WRAP_AROUND is a Python 
bool constant
...
   @always_...
   def f():
      ...
      if not  WRAP_AROUND :

gets converted to:
      if (not '1') then

which is invalid VHDL ...

A work-around is to bring the constant to the highest level and 
conditionally generate the two cases:

def ramreader( Clk, Reset , ... , WRAP_AROUND ): # WRAP_AROUND is a Python 
bool constant
...
   if not  WRAP_AROUND :
      @always_...
      def f():
         ...
   else:
      @always_...
      def f():
         ...

Now we have duplicated the code and the maintenance

Regards,

Josy 

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan C. <jen...@mu...>]

On 12/07/14 09:58, Jan Decaluwe wrote:
> On 07/11/2014 11:12 AM, Jan Coombs wrote:
>
>> Yesterday I found that the need for [:] in variable assignments is
>> demonstrated in two of the 'learning by example' code samples, so
>> hopefully no-one else will get to see my pain.
> The primary reference should be the manual.
> These issues are explained in depth:
>
> http://docs.myhdl.org/en/latest/manual/conversion.html#assignment-issues
>
Not complaining, but 10/12 the way through the manual, in  a 
section about conversion


I'm very happy now, because I just re-wrote this code with a 
variable and it now works:

   @always_seq(clk.posedge, reset=rst)
   def irLogic():
     ''' load ir '''
     nextIR = intbv(0)[GSW*2:]
     nextIR[:] = ir
     if   (irState==IRstate.IrA):
       nextIR[GSW*2:GSW] = db01Data
       nextIR[GSW:0] = 0
     elif (irState==IRstate.IrB):
       nextIR[GSW:0] = db01Data
     ir.next = nextIR


I can probably now guess why the old code silently failed, but it 
was frustrating, and sapped my interest:

   @always_seq(clk.posedge, reset=rst)
   def irLogic():
     ''' load ir '''
     if   (irState==IRstate.IrA):
       ir[GSW*2:GSW].next = db01Data  #WHYNOT?
       ir[GSW:0].next = 0             #WHYNOT?
       #ir.next = db01Data<<GSW
     elif (irState==IRstate.IrB):
       ir[GSW:0].next = db01Data      #WHYNOT?
       #ir.next = ir|db01Data


Thanks for your help, I'll hijack this thread no further, Jan Coombs
-- 

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan C. <jen...@mu...>]

On 12/07/14 09:58, Jan Decaluwe wrote:
> The primary reference should be the manual.
> These issues are explained in depth:
>
> http://docs.myhdl.org/en/latest/manual/conversion.html#assignment-issues
Thanks, must have rushed, skipped, or simply didn't grasp this part.

Jan Coombs.

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan D. <ja...@ja...>]

On 07/11/2014 11:12 AM, Jan Coombs wrote:

> Yesterday I found that the need for [:] in variable assignments is
> demonstrated in two of the 'learning by example' code samples, so
> hopefully no-one else will get to see my pain.

The primary reference should be the manual.
These issues are explained in depth:

http://docs.myhdl.org/en/latest/manual/conversion.html#assignment-issues

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Starting with MyHDL and trying to do my Cordic Module

[Jan C. <jen...@mu...>]

On 10/07/14 23:06, André Prado wrote:
>
> Just to give a feedback. It was working, just that it is faster 
> than my old module and that was causing me trouble.
> Cheers
>
Thanks André, and congratulations on finding, using, and succeeding 
with this powerful tool.  MyHDL has provided me with similar 
benefits, and I certainly do not wish to return to modelling in VHDL.

I fell through a small hole in the otherwise excellent MyHDL 
support, and will soon be up and running again.

Yesterday I found that the need for [:] in variable assignments is 
demonstrated in two of the 'learning by example' code samples, so 
hopefully no-one else will get to see my pain.

Jan Coombs
--