myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Another typo in docs

[Christopher F. <chr...@gm...>]

>
> Would it make sense to convert the code snippets in the Sphinx
> documentation to doctests so this can be picked up automatically? I can
> have a bash at this if desired (certainly, the FSM one above would be
> useful as a doctest).

Yes, I think this is a great idea, I actually have a
start on this.  I have a couple sections completed with
doctest.  If others agree I can create a PR with my
changes and then you can add to if you like :)

> Also (and separately), is there a reason why the API docs aren't
> autogenerated with Sphinx autodoc (with the content in the Python
> docstrings)?
>

Don't know if there is a reason for this?

Regards,
Chris

[myhdl-list] Another typo in docs

[Henry G. <he...@ca...>]

Please don't think I'm trying to be annoying with this - I'm having a 
great time expanding my horizon whilst reading every line of 
documentation in great detail.

Referring to the code in 
http://docs.myhdl.org/en/latest/manual/rtl.html#finite-state-machine-modeling

The reset signal in the testBench() should be initialised to 1 to yield 
the output expected in gtkwave shown below it.

I've pushed the change to my MyHDL fork on bitbucket - as before, PR on 
demand.

Would it make sense to convert the code snippets in the Sphinx 
documentation to doctests so this can be picked up automatically? I can 
have a bash at this if desired (certainly, the FSM one above would be 
useful as a doctest).

Also (and separately), is there a reason why the API docs aren't 
autogenerated with Sphinx autodoc (with the content in the Python 
docstrings)?

Cheers,

Henry

[myhdl-list] Typo in docs

[Henry G. <he...@ca...>]

There is a typo in the docs for ResetSignal 
http://docs.myhdl.org/en/latest/manual/reference.html#myhdl.ResetSignal

As it reads, both True and False async args lead to an asynchronous reset.

I've pushed this (minor) change to my fork and can raise a PR if desired.

Cheers,

Henry

[myhdl-list] Broken list link on the website

[Henry G. <he...@ca...>]

The link on the MyHDL community page 
(http://www.myhdl.org/support/community.html) to the MyHDL mailing list 
appears to be broken - under Firefox I get a redirecting error for 
http://sourceforge.net/mail?group_id=91207 .

I found my way to subscribe through the Gmane page.

Cheers,

Henry

Re: [myhdl-list] missing cast in toVHDL conversion

[Josy B. <jo...@c-...>]

Thanks Chris,
Being too busy at the moment I will file enhancement request later. I can 
live with a work-around as I only need to expose a single module to the 
Qsys project

Regards,

Josy

Re: [myhdl-list] missing cast in toVHDL conversion

[Christopher F. <chr...@gm...>]

On 5/19/14 5:06 PM, Christopher Felton wrote:
> On 5/19/14 3:47 PM, Josy Boelen wrote:
>> Josy Boelen <josy <at> c-cam.be> writes:
>>
>>>
>>> When setting toVHDL.numeric_ports = False
>>> the following construct:
>>>       simx.next = DVectors - DObj
>>>
>>> gets converted into:
>>>       ed_ed_edc_0_simx <= signed(resize(DVectors(18-1 downto 0), 19) -
>> unsigned
>>> (DObj));
>>>
>>> where it should be:
>>> either
>>>        ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors)(18-1 downto 0),
>> 19)
>>> - unsigned(DObj));
>>> (or  ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors(18-1 downto 0)),
>> 19)
>>> - unsigned(DObj));)
>>>
>>> Both DObj and DVectors are ports
>>> For now I can live with the workaround of not setting
>> toVHDL.numeric_ports to
>>> False, but at some point in the future I will have to expose
>>> std_logic_vectors in stead of unsigned ports (as this is what Altera's
>> Qsys
>>> allows for VHDL-based components)
>>>
>>> Best regards,
>>>
>>> Josy
>>>
>>>
>> ----------------------------------------------------------------------------
>> No takers?
>> Do I have to move it to the bug report list?
>>
>> Regards,
>>
>> Josy
>>
>
> That might be the best bet, I haven't read the details
> yet and some of these features I have not used (I will
> not be of much use in the near future :)
>
> You can log it as an issue here:
> https://bitbucket.org/jandecaluwe/myhdl/issues?status=new&status=open
>

Note, if you add it to the issue tracker it probably is
a feature request.  As noted by another user .numeric_port
is not an advertised feature.  I don't know if it is complete
or not.  You might want to add an issue as "enhancement" and
for the completion of the feature.

Regards,
Chris

Re: [myhdl-list] missing cast in toVHDL conversion

[Christopher F. <chr...@gm...>]

On 5/19/14 3:47 PM, Josy Boelen wrote:
> Josy Boelen <josy <at> c-cam.be> writes:
>
>>
>> When setting toVHDL.numeric_ports = False
>> the following construct:
>>      simx.next = DVectors - DObj
>>
>> gets converted into:
>>      ed_ed_edc_0_simx <= signed(resize(DVectors(18-1 downto 0), 19) -
> unsigned
>> (DObj));
>>
>> where it should be:
>> either
>>       ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors)(18-1 downto 0),
> 19)
>> - unsigned(DObj));
>> (or  ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors(18-1 downto 0)),
> 19)
>> - unsigned(DObj));)
>>
>> Both DObj and DVectors are ports
>> For now I can live with the workaround of not setting
> toVHDL.numeric_ports to
>> False, but at some point in the future I will have to expose
>> std_logic_vectors in stead of unsigned ports (as this is what Altera's
> Qsys
>> allows for VHDL-based components)
>>
>> Best regards,
>>
>> Josy
>>
>>
> ----------------------------------------------------------------------------
> No takers?
> Do I have to move it to the bug report list?
>
> Regards,
>
> Josy
>

That might be the best bet, I haven't read the details
yet and some of these features I have not used (I will
not be of much use in the near future :)

You can log it as an issue here:
https://bitbucket.org/jandecaluwe/myhdl/issues?status=new&status=open

Regards,
Chris

Re: [myhdl-list] missing cast in toVHDL conversion

[Josy B. <jo...@c-...>]

Josy Boelen <josy <at> c-cam.be> writes:

> 
> When setting toVHDL.numeric_ports = False
> the following construct:
>     simx.next = DVectors - DObj
> 
> gets converted into:
>     ed_ed_edc_0_simx <= signed(resize(DVectors(18-1 downto 0), 19) - 
unsigned
> (DObj));
> 
> where it should be:
> either
>      ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors)(18-1 downto 0), 
19) 
> - unsigned(DObj));
> (or  ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors(18-1 downto 0)), 
19) 
> - unsigned(DObj));)
> 
> Both DObj and DVectors are ports
> For now I can live with the workaround of not setting 
toVHDL.numeric_ports to 
> False, but at some point in the future I will have to expose 
> std_logic_vectors in stead of unsigned ports (as this is what Altera's 
Qsys 
> allows for VHDL-based components)
> 
> Best regards,
> 
> Josy
> 
> 
----------------------------------------------------------------------------
No takers?
Do I have to move it to the bug report list?

Regards,

Josy

[myhdl-list] toVHDL.numeric_ports

[Guy E. <gu...@no...>]

Hello,

I've noticed that the "toVHDL.numeric_ports" atttribute is not described 
in the manual. Is that an omission or is the use of this attribute not 
recommended/deprecated?

Thanks,
Guy.

-- 
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noasic e.K.
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[myhdl-list] missing cast in toVHDL conversion

[Josy B. <jo...@c-...>]

When setting toVHDL.numeric_ports = False
the following construct:
    simx.next = DVectors - DObj

gets converted into:
    ed_ed_edc_0_simx <= signed(resize(DVectors(18-1 downto 0), 19) - unsigned
(DObj));

where it should be:
either
     ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors)(18-1 downto 0), 19) 
- unsigned(DObj));
(or  ed_ed_edc_0_simx <= signed(resize(unsigned(DVectors(18-1 downto 0)), 19) 
- unsigned(DObj));)

Both DObj and DVectors are ports
For now I can live with the workaround of not setting toVHDL.numeric_ports to 
False, but at some point in the future I will have to expose 
std_logic_vectors in stead of unsigned ports (as this is what Altera's Qsys 
allows for VHDL-based components)

Best regards,

Josy

Re: [myhdl-list] Delay Models in MyHDL

[Christopher F. <chr...@gm...>]

On 5/7/2014 2:54 PM, Guy Eschemann wrote:
> Hello,
>
> I was wondering whether MyHDL has anything similar to VHDL's inertial or
> transport delay models. Not that I would need them, it's just out of
> curiosity.
>
> Thanks,
> Guy.
>


The /Signal/ has a delay argument:

     Signal(val=None, delay=None)

A simple example:

     def m_add(a, b, c):
         @always_comb
         def rtl():
             c.next = a and b
         return rtl

     def test():
         a = Signal(bool(0), delay=10)
         b = Signal(bool(0), delay=1)
         c = Signal(bool(0))
         ...

https://gist.github.com/cfelton/a0dbd2c12070a649bb56
http://www.edaplayground.com/x/3Gw
(waveform attached, signal order is funny though)

The delay is in simulation steps, if you want to relate sim
steps back to a physical meaning you have to manage it
yourself, e.g. we could arbitrarily say 1 sim step is 1ps
and a 1ns delay would be delay=1000 (make sure you set the
traceSignals and Cosimulation timescales if needed).

Regards,
Chris

[myhdl-list] Delay Models in MyHDL

[Guy E. <gu...@no...>]

Hello,

I was wondering whether MyHDL has anything similar to VHDL's inertial or 
transport delay models. Not that I would need them, it's just out of 
curiosity.

Thanks,
Guy.

Re: [myhdl-list] to_VHDL: last 'elif .. :' translates to 'when others =>'

[Josy B. <jo...@c-...>]

Josy Boelen <josy <at> c-cam.be> writes:

> 
> When converting a state machine MyHDL translates the last 'elif ... :' 
>
>...
>
> As a side effect it 'repaired' a case where toVHDL 
> lumped together several states into a single 'when others =>' block and 
> generated 'if then else' constructs to elaborate those lumped-in states.
> 
> Regards,
> 
> Josy

I must edit the last sentence: apparently the 'tangled state machine case' 
is in another module ... I'll post a follow up thread on this later

Regards,

Josy

Re: [myhdl-list] User-defined code in submodules

[Guy E. <gu...@no...>]

Am 05.05.2014 15:23, schrieb Christopher Felton:
>
>
> Yes, the generators (see [1] for intro on generators)
> cannot have the user-defined code attribute only a
> module (a function).
>
> Typically, in MyHDL we call a (myhdl) module a Python
> function that returns MyHDL generators (yes this overlaps
> with the Python definition of a module, context specific
> (i.e. a file)).
>
> As Josy, replied, if you modify the code to (sorry changed
> some of the signal names, see below)
>
> Regards,
> Chris
>

I didn't realize that user-defined code cannot be applied to generators. 
This is something that a (future?) MyHDL linter may want to check.

Thanks,
Guy.

[myhdl-list] to_VHDL: last 'elif .. :' translates to 'when others =>'

[Josy B. <jo...@c-...>]

When converting a state machine MyHDL translates the last 'elif ... :' into 
a 'when others =>'statement.
I felt this is rather impure so I looked in the _toVHDL.py source and 
changed the following around line 1146:
#07-05-2014 jb: do not use default clause for last test
#         for i, (test, suite) in enumerate(node.tests):
        for _, (test, suite) in enumerate(node.tests):
            self.writeline()
            item = test.case[1]
            if isinstance(item, EnumItemType):
                itemRepr = item._toVHDL()
            else:
                itemRepr = self.BitRepr(item, obj)
            comment = ""
#             # potentially use default clause for last test
#             if (i == len(node.tests)-1) and not node.else_:
#                 self.write("when others")
#                 comment = " -- %s" % itemRepr
#             else:
#                 self.write("when ")
#                 self.write(itemRepr)
            self.write("when ")
            self.write(itemRepr)
#07-05-2014 end
That did the trick. As a side effect it 'repaired' a case where toVHDL 
lumped together several states into a single 'when others =>' block and 
generated 'if then else' constructs to elaborate those lumped-in states.

Regards,

Josy

[myhdl-list] to_VHDL adds a signed(resize()( , ) when comparing intbv to a 'constant value'

[Josy B. <jo...@c-...>]

The following code:
def module(...  , D, ... ,  Q, ...):
     L_WIDTH_D = len(D)
     L_WIDTH_Q = len(Q)
     L_N = L_WIDTH_D / L_WIDTH_Q

     counter = Signal(intbv(0 , min = 0, max = L_N))
...
          if counter == L_N - 1:

gets translated into VHDL as :
signal counter: unsigned(1 downto 0);
...
          if (signed(resize(counter, 3)) = (L_N - 1)) then

In VHDL I would have simply written the test as:
          if ( counter = (L_N - 1) ) then
and I don't see why MyHDL should do different. Perhaps, as Python doesn't 
know 'constants' it interprets 'L_N - 1' as a possibly signed value?

Regards,

Josy

Re: [myhdl-list] MyHDL docs search

[Christopher F. <chr...@gm...>]

On 5/2/14 3:55 AM, Guy Eschemann wrote:
> Hello,
>
> it looks like searching the docs for "User-defined code" does not give
> any results. This is unfortunate, because there actually is a section in
> the manual about user-defined code
> (http://docs.myhdl.org/en/latest/manual/conversion.html#user-defined-code).
>
>
>
> Regards,
> Guy.
>
>

What's weird, is it gives you a result in the menu
area (left column) - odd.

Regards,
Chris

Re: [myhdl-list] User-defined code in submodules

[Christopher F. <chr...@gm...>]

On 5/3/2014 3:14 AM, Josy Boelen wrote:
> Guy Eschemann <guy <at> noasic.com> writes:
>
> I experimented a bit with your code and got the intended result when
> replacing 'inc_comb.vhdl_code' with 'top.vhdl_code'. Now you wrapped
> 'inc_comb' inside a 'top' module which is the one you convert, so this may
> make sense?
>
> Regards,
>
> Josy
>


Yes, the generators (see [1] for intro on generators)
cannot have the user-defined code attribute only a
module (a function).

Typically, in MyHDL we call a (myhdl) module a Python
function that returns MyHDL generators (yes this overlaps
with the Python definition of a module, context specific
(i.e. a file)).

As Josy, replied, if you modify the code to (sorry changed
some of the signal names, see below)

Regards,
Chris

[1] 
http://docs.myhdl.org/en/latest/manual/background.html#a-small-tutorial-on-generators

#---------------------------------------------------------------
def m_top(clock, reset, x, y):

     incx = Signal(y.val)
     g = m_next_count(x, incx, 8)

     @always_seq(clock.posedge, reset=reset)
     def rtl():
         y.next = incx

     return g, rtl

def m_next_count(x, y, n):
     @always(x)
     def logic():
         pass
     y.driven = "wire"
     return logic
m_next_count.vhdl_code = \
"""
$y <= ($x + 1) mod $n
"""

clock = Signal(bool(0))
reset = ResetSignal(0, active=0, async=True)
x,y = [Signal(intbv(0, min=-256, max=256)) for _ in range(2)]
toVHDL(m_top, clock, reset, x, y)


---------------------------------------------------------------
-- File: m_top.vhd
-- Generated by MyHDL 0.9dev
-- Date: Mon May  5 08:17:25 2014

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_09.all;

entity m_top is
     port (
         clock: in std_logic;
         reset: in std_logic;
         x: in signed (8 downto 0);
         y: out signed (8 downto 0)
     );
end entity m_top;

architecture MyHDL of m_top is

signal incx: signed (8 downto 0);

begin

incx <= (x + 1) mod 8

M_TOP_RTL: process (clock, reset) is
begin
     if (reset = '0') then
         y <= to_signed(0, 9);
     elsif rising_edge(clock) then
         y <= incx;
     end if;
end process M_TOP_RTL;

end architecture MyHDL;

Re: [myhdl-list] User-defined code in submodules

[Josy B. <jo...@c-...>]

Guy Eschemann <guy <at> noasic.com> writes:

I experimented a bit with your code and got the intended result when 
replacing 'inc_comb.vhdl_code' with 'top.vhdl_code'. Now you wrapped 
'inc_comb' inside a 'top' module which is the one you convert, so this may 
make sense?

Regards,

Josy

[myhdl-list] User-defined code in submodules

[Guy E. <gu...@no...>]

Hello,

is there anything wrong with the following code? What I'm seeing is that 
the generated VHDL code does not include the specified user-defined code.

    from myhdl import *

    def top(nextCount, count, n):

         def inc_comb(nextCount, count, n):
             @always(count)
             def logic():
                 # do nothing here
                 pass

             nextCount.driven = "wire"
             return logic

         inc_comb.vhdl_code =\
         """
         $nextCount <= ($count + 1) mod $n;
         """

         inst_inc_comb = inc_comb(nextCount, count, n)

         return instances()

    if __name__ == '__main__':
         nextCount = Signal(intbv(0)[8:])
         count = Signal(intbv(0)[8:])
         n = 8
         inst_top = toVHDL(top, nextCount, count, n

Regards,
Guy.

[myhdl-list] MyHDL docs search

[Guy E. <gu...@no...>]

Hello,

it looks like searching the docs for "User-defined code" does not give 
any results. This is unfortunate, because there actually is a section in 
the manual about user-defined code 
(http://docs.myhdl.org/en/latest/manual/conversion.html#user-defined-code).



Regards,
Guy.

[myhdl-list] MyHDL: library use clauses in user-defined code

[Guy E. <gu...@no...>]

Hello,

I've posted a new MyHDL-related question to Stackoverflow: 
http://stackoverflow.com/questions/23423971

Regards,
Guy.

Re: [myhdl-list] modbv vs. intbv

[Christopher F. <chr...@gm...>]

On 4/29/2014 9:05 AM, Josy Boelen wrote:
> Guy Eschemann <guy <at> noasic.com> writes:
>
>>
>>
>>      Hello,
>>      I've been wondering about this:>>> from myhdl import *
>>        >>> a = modbv(0, min = 0, max = 16)
>>        >>> a
>>        intbv(0)
>>
>>      Why does the last command print "intbv(0)" instead of "modbv(0)"?
>>      Regards,
>>      Guy.
>
> modbv is derived from intbv and hasn't got it's own __repr__ function
> (yet?) so it uses the one from the intbv class.
>
> Regards,
>
> Josy


Thanks for pointing this out, this should be modified
as suggested.

Regards,
Chris

Re: [myhdl-list] simulation coding vs conversion coding

[Christopher F. <chr...@gm...>]

On 4/30/2014 11:35 AM, Keerthan jai.c wrote:
> Awesome, should I submit a bug report/pull request?
>

My opinion yes, but it is not clear if this is a
bug against the trunk or a feature/fix for 0.9.
I would create a PR towards 0.9.  It will provide
the opportunity for more testing.

Regards,
Chris

Re: [myhdl-list] simulation coding vs conversion coding

[Keerthan jai.c <jck...@gm...>]

Awesome, should I submit a bug report/pull request?


On Mon, Apr 28, 2014 at 5:29 PM, Lars <L...@rs...> wrote:

> >
> >  <at> Keerthan:
> > Thanks. I will try and post the result.
> >
>
> yes, works with _toVHDL.
>
> thx,
> Lars
>
>
>
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-- 
have a nice day
-jck