myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

I don't have a clear idea for the architecture yet, but I suspect it is not
that simple (or maybe it is)...

This is what I understand you are referring to:

def myADC(value):
  @always(clk.posedge)
  def logic():
    value.next = do_things()

And then in do_things() control the spice simulator. In this case, the
spice simulator runs "behind" the digital simulation, this is, when myhdl
gets to t=ti, stop and sun spice until t=ti.

The problem is that I might need to stop for different signals, and having
them all call do_things() makes having a centralized control of the
mixed-signal simulation environment very complicated. On top of this, how
can I know them "time" at which the signal toggle inside the "logic()"
function"? I would need that to determine for how long to run the analog
simulation.

Even worse, what if "clk" came from the analog simulation... I would have
to wait for each analog run complete to know when to toggle it, and then
manually toggle it. Here, the myhdl simulation would run "behind".

For short, I don't think I can implement the control of the whole system
from a single "do_things()" function. What do you think?

Thanks,

JP



On Sun, Apr 5, 2015 at 5:43 PM, Henry Gomersall <he...@ca...> wrote:

> On 05/04/15 21:06, Juan Pablo Caram wrote:
> > I would like to be able to simulate until signal X toggles or changes,
> > get the time, run spice until this time is reached, update signals in
> > myhdl and spice, resume myhdl simulation, etc.
> >
>
> You can always have your own MyHDL generator instance that does
> programmatic control. In each call, it just checks some IO and does
> something suitable. Remember, you have the full power of Python
> available to the running code.
>
> So, you just run the simulator forever, handling state changes from
> whatever external source you want inside the running code, and then when
> you want to stop, raise StopSimulation. It could even be a real physical
> source if you wanted :)
>
> If anything, programmatic control is much easier, since that's what
> programming languages are for!
>
> cheers,
> Henry
>
>
> ------------------------------------------------------------------------------
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> by Intel and developed in partnership with Slashdot Media, is your hub for
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> things parallel software development, from weekly thought leadership blogs
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Re: [myhdl-list] Simulation control

[Henry G. <he...@ca...>]

On 05/04/15 21:06, Juan Pablo Caram wrote:
> I would like to be able to simulate until signal X toggles or changes, 
> get the time, run spice until this time is reached, update signals in 
> myhdl and spice, resume myhdl simulation, etc.
>

You can always have your own MyHDL generator instance that does 
programmatic control. In each call, it just checks some IO and does 
something suitable. Remember, you have the full power of Python 
available to the running code.

So, you just run the simulator forever, handling state changes from 
whatever external source you want inside the running code, and then when 
you want to stop, raise StopSimulation. It could even be a real physical 
source if you wanted :)

If anything, programmatic control is much easier, since that's what 
programming languages are for!

cheers,
Henry

Re: [myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

I apologize for the confusion. I'm hoping to do do this with code, not a
debugger. I'm trying to create a mixed signal simulator exchanging data
between ngspice and myhdl.

I would like to be able to simulate until signal X toggles or changes, get
the time, run spice until this time is reached, update signals in myhdl and
spice, resume myhdl simulation, etc.

Sometimes the clock comes from spice, I detect the change in output from a
comparator, stop the simulation, and must toggle the corresponding signal
in the digital side and resume the digital.

I couldn't find any fine controls for the simulation in MyHDL. SimPy, that
looks quite similar in terms of using generators, seem to have "simulate
until" kind of controls. I wonder if this is already possible or if someone
had tried to implement such functionality.

Thanks,

JP

On Sun, Apr 5, 2015 at 2:28 PM, Euripedes Rocha Filho <
roc...@gm...> wrote:

> I had some debug of simulation(also cosimulation) using pudb without any
> problems so far.
>
> 2015-04-05 3:12 GMT-03:00 Jose M. Gomez Cama <ch...@gm...>:
>
>> I use eclipse with PyDev or Aptana which is the out-of-the-box version,
>> and it works quite well.
>>
>> Best,
>>
>> Jose M.
>>
>> > El 05/04/2015, a las 04:33, Christopher Felton <chr...@gm...>
>> escribió:
>> >
>> >> On 4/4/15 9:08 PM, Christopher Felton wrote:
>>
>> >>> On 4/4/15 6:39 PM, Juan Pablo Caram wrote:
>> >>> Hi,
>> >>>
>> >>> I was wondering if there was a way to 1) pause a simulation by setting
>> >>> breakpoints (toggle on signal X, or similar), 2) changing the state of
>> >>> signals manually during pause and 3) resuming?
>> >>
>> >> You should be able to use any Python debugger
>> >> (pdb) to do this.  I personally have not tried
>> >> it, so I don't know if there are any issues.
>> >
>> > I just tried PyCharm and it is fairly straightforward
>> > to set breakpoints in a simulation, step, inspect,
>> > etc.  I am sure there are many different Python
>> > debug interfaces (command line pdb probably works
>> > fine as well).
>> >
>> > Regards,
>> > Chris
>> >
>> >
>> >
>> >
>> ------------------------------------------------------------------------------
>> > Dive into the World of Parallel Programming The Go Parallel Website,
>> sponsored
>> > by Intel and developed in partnership with Slashdot Media, is your hub
>> for all
>> > things parallel software development, from weekly thought leadership
>> blogs to
>> > news, videos, case studies, tutorials and more. Take a look and join the
>> > conversation now. http://goparallel.sourceforge.net/
>> > _______________________________________________
>> > myhdl-list mailing list
>> > myh...@li...
>> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>> ------------------------------------------------------------------------------
>> Dive into the World of Parallel Programming The Go Parallel Website,
>> sponsored
>> by Intel and developed in partnership with Slashdot Media, is your hub
>> for all
>> things parallel software development, from weekly thought leadership
>> blogs to
>> news, videos, case studies, tutorials and more. Take a look and join the
>> conversation now. http://goparallel.sourceforge.net/
>> _______________________________________________
>> myhdl-list mailing list
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>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
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> sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for
> all
> things parallel software development, from weekly thought leadership blogs
> to
> news, videos, case studies, tutorials and more. Take a look and join the
> conversation now. http://goparallel.sourceforge.net/
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>
>

Re: [myhdl-list] Simulation control

[Euripedes R. F. <roc...@gm...>]

I had some debug of simulation(also cosimulation) using pudb without any
problems so far.

2015-04-05 3:12 GMT-03:00 Jose M. Gomez Cama <ch...@gm...>:

> I use eclipse with PyDev or Aptana which is the out-of-the-box version,
> and it works quite well.
>
> Best,
>
> Jose M.
>
> > El 05/04/2015, a las 04:33, Christopher Felton <chr...@gm...>
> escribió:
> >
> >> On 4/4/15 9:08 PM, Christopher Felton wrote:
> >>> On 4/4/15 6:39 PM, Juan Pablo Caram wrote:
> >>> Hi,
> >>>
> >>> I was wondering if there was a way to 1) pause a simulation by setting
> >>> breakpoints (toggle on signal X, or similar), 2) changing the state of
> >>> signals manually during pause and 3) resuming?
> >>
> >> You should be able to use any Python debugger
> >> (pdb) to do this.  I personally have not tried
> >> it, so I don't know if there are any issues.
> >
> > I just tried PyCharm and it is fairly straightforward
> > to set breakpoints in a simulation, step, inspect,
> > etc.  I am sure there are many different Python
> > debug interfaces (command line pdb probably works
> > fine as well).
> >
> > Regards,
> > Chris
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> > Dive into the World of Parallel Programming The Go Parallel Website,
> sponsored
> > by Intel and developed in partnership with Slashdot Media, is your hub
> for all
> > things parallel software development, from weekly thought leadership
> blogs to
> > news, videos, case studies, tutorials and more. Take a look and join the
> > conversation now. http://goparallel.sourceforge.net/
> > _______________________________________________
> > myhdl-list mailing list
> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website,
> sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for
> all
> things parallel software development, from weekly thought leadership blogs
> to
> news, videos, case studies, tutorials and more. Take a look and join the
> conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 05/04/15 04:38, Christopher Felton wrote:
>>> I'm getting an error likely due to to a std_logic_vector being
>>> >>much monger than myHDL was intended to handle.
>>> >>
>>> >>addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
> On 4/3/15 3:43 AM, Henry Gomersall wrote:
>> >The first is concat as you highlighted, not seeming to like values that
>> >are too long. I suspect this is a problem only in the analyser and can
>> >be rectified relatively easily? I worked around this by assigning to
>> >sub-vectors independently.
> The issues is: you are trying to concat an `intbv`
> and a `long`.  A `long` doesn't have a length so the
> concat doesn't work.  You end up with a `long` when
> you do the decrement `addr-1`.  This operation
> results in a `long` not a type with a length.

My bad, I didn't note that.

The rest of my points still stand though.

Henry

Re: [myhdl-list] Simulation control

[Jose M. G. C. <ch...@gm...>]

I use eclipse with PyDev or Aptana which is the out-of-the-box version, and it works quite well.

Best,

Jose M.

> El 05/04/2015, a las 04:33, Christopher Felton <chr...@gm...> escribió:
> 
>> On 4/4/15 9:08 PM, Christopher Felton wrote:
>>> On 4/4/15 6:39 PM, Juan Pablo Caram wrote:
>>> Hi,
>>> 
>>> I was wondering if there was a way to 1) pause a simulation by setting
>>> breakpoints (toggle on signal X, or similar), 2) changing the state of
>>> signals manually during pause and 3) resuming?
>> 
>> You should be able to use any Python debugger
>> (pdb) to do this.  I personally have not tried
>> it, so I don't know if there are any issues.
> 
> I just tried PyCharm and it is fairly straightforward
> to set breakpoints in a simulation, step, inspect,
> etc.  I am sure there are many different Python
> debug interfaces (command line pdb probably works
> fine as well).
> 
> Regards,
> Chris
> 
> 
> 
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website, sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for all
> things parallel software development, from weekly thought leadership blogs to
> news, videos, case studies, tutorials and more. Take a look and join the 
> conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

On 4/4/15 3:10 PM, Tony Stark wrote:
> 1. How do I receive replies to my questions through email without also
> receiving emails for any other question posted to the mailing list?

BOMK there isn't a method, you can setup email
filters and/or use a mailing-list reader like
the one available in Thunderbird.

Regards,
Chris

Re: [myhdl-list] Conversion to VHDL

[Christopher F. <chr...@gm...>]

On 4/2/15 10:22 AM, Edward Vidal wrote:
> Hello All,
>
> <snip>
> Where W0 = 9
> x = Signal(intbv(0, min=-(2**(W0)), max=(2**(W0))))
> z = Signal(intbv(0)[W0:])
>
> <snip>
> z.next = x[W0:]
> yield clk.posedge
> matrix_sa[ma_row][ma_col].next = z
>
> Should the above convert to VHDL as

No it would not convert because MyHDL currently
does not support 2D list-of-signals (what I assume
matrix_sa is).

Regards,
Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

>> I'm getting an error likely due to to a std_logic_vector being
>> much monger than myHDL was intended to handle.
>>
>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)

On 4/3/15 3:43 AM, Henry Gomersall wrote:
> The first is concat as you highlighted, not seeming to like values that
> are too long. I suspect this is a problem only in the analyser and can
> be rectified relatively easily? I worked around this by assigning to
> sub-vectors independently.

The issues is: you are trying to concat an `intbv`
and a `long`.  A `long` doesn't have a length so the
concat doesn't work.  You end up with a `long` when
you do the decrement `addr-1`.  This operation
results in a `long` not a type with a length.

I created a minimal example to demonstrate the `concat`
works with the large bitvectors:

https://gist.github.com/cfelton/36a2ee340ecea58cdff0

Regards,
Chris

Re: [myhdl-list] The definition of an interface?

[Christopher F. <chr...@gm...>]

On 4/2/15 9:02 AM, Henry Gomersall wrote:
> On 02/04/15 14:54, Henry Gomersall wrote:
>> How are signals referenced in an interface? Do they need to exist in the
>> __dict__, or is there another way to look them up?
>
> By this, I mean, should Signals that are returned from, say, a property,
> be considered part of the interface?
>

I would have to double check what the actual
conversion code does but it uses the compiler
to walk the objects.  Yes, I believe they would
have to exist in the __dict__.

Creating a small example with a property it does
not convert.  So no, a property used to access a
signal would not be supported.  I can't think of
a use-case where you would.  In a MyHDL generator
you need access to the signal.

https://gist.github.com/cfelton/bb4e0850c5245a1ef960

Interface properties would be useful in elaboration
code but not in the generators/processes.

Regards,
Chris

Re: [myhdl-list] Simulation control

[Christopher F. <chr...@gm...>]

On 4/4/15 9:08 PM, Christopher Felton wrote:
> On 4/4/15 6:39 PM, Juan Pablo Caram wrote:
>> Hi,
>>
>> I was wondering if there was a way to 1) pause a simulation by setting
>> breakpoints (toggle on signal X, or similar), 2) changing the state of
>> signals manually during pause and 3) resuming?
>>
>
> You should be able to use any Python debugger
> (pdb) to do this.  I personally have not tried
> it, so I don't know if there are any issues.

I just tried PyCharm and it is fairly straightforward
to set breakpoints in a simulation, step, inspect,
etc.  I am sure there are many different Python
debug interfaces (command line pdb probably works
fine as well).

Regards,
Chris

Re: [myhdl-list] Simulation control

[Christopher F. <chr...@gm...>]

On 4/4/15 6:39 PM, Juan Pablo Caram wrote:
> Hi,
>
> I was wondering if there was a way to 1) pause a simulation by setting
> breakpoints (toggle on signal X, or similar), 2) changing the state of
> signals manually during pause and 3) resuming?
>

You should be able to use any Python debugger
(pdb) to do this.  I personally have not tried
it, so I don't know if there are any issues.

I don't know which Python IDE works well with
the Python debugger (maybe others have
suggestions?).  I have heard PyCharm mentioned
before?

Regards,
Chris

[myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

Hi,

I was wondering if there was a way to 1) pause a simulation by setting
breakpoints (toggle on signal X, or similar), 2) changing the state of
signals manually during pause and 3) resuming?

Thank you,

JP

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

>	Well, the problem there is a python problem. You're trying to import
>	from a module that doesn't exist, or at least not in your path. Again, I
>	suggest that your problems so far are predominantly a lack of
>	understanding of the way Python works, rather than MyHDL.
>	
>	Beyond that, I don't understand what you're trying to achieve.
>	
>	Cheers,
>	
>	Henry

Alright, I've made a little progress on this but still nothing useful
yet. The VHDL code I've written below is what I want to have MyHDL
generate. The Python code following that is my attempt at it. It
generates code without error but it's not nearly useful yet.

***************************** VHDL *****************************************
library ieee;
use ieee.std_logic_1164.all;

entity top_level_tb is
end top_level_tb;

architecture tb of top_level_tb is
	signal s_sw                   				: std_logic_vector(9 downto 0) 	:=
(others => '0');
	signal s_clk                     			: std_logic                   			:= '0';
	signal s_btn                    		 	: std_logic_vector(2 downto 0)
	:= (others => '1');
	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:=
(others => '0');
	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:=
(others => '0');
	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:=
(others => '0');
	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:=
(others => '0');
	signal s_done                    			: std_logic                    			:= '0';
begin
	UUT : entity work.top_level port map(
			i_sw                  				=> s_sw,
			i_clk                   				=> s_clk,
			i_btn                   				=> s_btn,
			o_seven_segment_display_1 	=> s_seven_segment_display_1,
			o_seven_segment_display_0 	=> s_seven_segment_display_0,
			o_seven_segment_display_3 	=> s_seven_segment_display_3,
			o_seven_segment_display_2 	=> s_seven_segment_display_2
		);

	s_clk <= not s_clk and not s_done after 10 ns;

	process
	begin
		wait for 10 ns;
		s_btn(2) <= '0';                 -- reset on
		wait for 20 ns;
		s_btn(2) <= '1';                 -- reset off

		-- <tests to be added here>
		
		--	s_done <= '1';
		-- wait;
	end process;

end tb;

***************************** MyHDL ******************************************

from myhdl import *

# fake entity & fake process created in an attempt to get MyHDL to
stop complaining about not knowing what top_level() was
def top_level(
        i_sw,
        i_clk,
        i_btn,
        o_seven_segment_display_1,
        o_seven_segment_display_0,
        o_seven_segment_display_3,
        o_seven_segment_display_2
):
    s_rst = ResetSignal(0, active=0, async=True)

    @always_seq(i_clk.posedge, reset=s_rst)
    def main_process():
        o_seven_segment_display_1 = 0

    return main_process

# actual entity of interest
def top_level_tb():
    s_sw = intbv(0)[10]
    s_clk = Signal(bool(0))
    s_btn = intbv(0)[3]
    s_seven_segment_display_1 = intbv(0)[7]
    s_seven_segment_display_0 = intbv(0)[7]
    s_seven_segment_display_3 = intbv(0)[7]
    s_seven_segment_display_2 = intbv(0)[7]

    top_level_instance = top_level(s_sw, s_clk, s_btn,
s_seven_segment_display_1, s_seven_segment_display_0,
s_seven_segment_display_3, s_seven_segment_display_2)

    @always(delay(10))
    def clkGenerator():
        s_clk.next = not s_clk

    @always(s_clk.posedge)
    def stimulus():
		
		# <more tests to be added here>
		
        s_btn[2].next = 0

    return top_level_instance, clkGenerator, stimulus

toVHDL(top_level_tb)


On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:

> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much monger
> than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>
> I actually converted VHDL code to pyhton and want to continue development
> of this fifo-like-buffer entity using python, but I need to get around this
> error first..
> The reason the array is so large is because I want to go through it in one
> clock cycle if needed. It represents 20, 23-bit addresses.
>
> The code is attached. please advise.
>
> Thanks,
> David
>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 04/04/15 21:10, Tony Stark wrote:
> 1. How do I receive replies to my questions through email without also 
> receiving emails for any other question posted to the mailing list?

Pay for a support contract? I'm sure several people, likely including 
BDFL Jan, would be willing to offer you the service for a suitable fee.

Otherwise a suitable regex based filter?

>
> 2. I'm unclear on variables. I see how they are declared now but how 
> would I make them retain their value each clock cycle like they do in 
> VHDL instead of reset to zero as you implied? I want to be able to use 
> them for instances where I need the value to change immediately 
> instead of on the next clock cycle, just like they do in VHDL.
>

Like I demonstrated in the example. You're writing valid python, so if 
you assign the variable outside the closure, python scoping rules mean 
it cannot be reassigned inside the closure (an exception will be raised 
if you try), so state is maintained unless explicitly updated. This is 
possible because the type is mutable and so its contents can be modified 
with the [:] slicing operator.

>The second is you're using interim variables like signals (with .next
>and so on). If you want to use interim variables, do so something like:
>
>def foo(signal, clock, reset):
>     my_interim = intbv(0)[10:]
>
>     @always_seq(clock.posedge, reset)
>     def foo_entity():
>         signal.next = my_interim
>         my_interim[:] = my_interim + 1
>
>     return foo_entity


> 3. I'm not sure this code does what was originally intended:
>     addr_array[436:0].next = addr_array[436:0]
>     addr_array[:436].next = most_recent_addr_req_to_sdram - 1
>
>     For a simpler example, lets say cached_addresses is a 
> std_logic_vector representing three, 4-bit addresses put together and 
> has these contents: 0000_0101_1111, and a signal called new_adddress 
> is 4 bits wide, I wanted to shift cached_addresses left 4 bits and 
> make cached_addresses = "0101_1111" & new_adddress. We are basically 
> pushing everything down one spot and adding the new address to the 
> newly opened space. I'm not sure the code above does that..

Crumbs, I might have got the subtleties wrong, but surely you can work 
out how to tweak the example.

How about:
addr_array[436:].next = most_recent_addr_req_to_sdram - 1

Might I suggest learning something about the fundamentals of python - 
slicing and what not.

>
> 4. Is there an example of MyHDL code that generates a VHDL testbench. 
> To clarify, I want to write a testbench in MyHDL for a VHDL entity 
> that MyHDL doesn't know about, and have it immediately generate the 
> VHDL testbench as opposed to MyHDL trying to run it's own simulation 
> of it. So it should be the same process as getting MyHDL to generate a 
> VHDL file for a normal entity excpet it needs to know that this is a 
> testbench so that it doesn't complain about there being no ports 
> declared in the entity being tested. I tried something like this but 
> MyHDL doesn't like it..
>
> from design import *
>
> def top_level_tb():
>     s_sw = Signal(bool(0))
>     s_clk = Signal(bool(0))
>     s_btn = Signal(bool(0))
>     s_seven_segment_display_1 = intbv(0)[7]
>     s_seven_segment_display_0 = intbv(0)[7]
>     s_seven_segment_display_3 = intbv(0)[7]
>     s_seven_segment_display_2 = intbv(0)[7]
>
>     top_level_instance = top_level(top_level, s_sw, s_clk, s_btn, 
> s_seven_segment_display_1, s_seven_segment_display_0, 
> s_seven_segment_display_3, s_seven_segment_display_2)
>
>     @always(delay(10))
>     def clkGenerator():
>         s_clk.next = not s_clk
>
>     @always(clk.posedge)
>     def stimulus():
>         s_btn[2].next = 0
>
>     return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> which threw:
> "ImportError: No module named design"

Well, the problem there is a python problem. You're trying to import 
from a module that doesn't exist, or at least not in your path. Again, I 
suggest that your problems so far are predominantly a lack of 
understanding of the way Python works, rather than MyHDL.

Beyond that, I don't understand what you're trying to achieve.

Cheers,

Henry

Re: [myhdl-list] A VHDL question about signal assignments and delta cycles?

[Henry G. <he...@ca...>]

On 04/04/15 15:41, Christopher Felton wrote:
> <snip>
>> >
>> >Is this a delta cycle thing? Is it simulation specific? I'm not too
>> >concerned about it, but I'd like to understand the reason behind it.
> I have not reviewed your inquiry in detail but
> this might help answer your question:
>
> http://www.sigasi.com/content/vhdls-crown-jewel

Yes, thanks. It was actually that that suggested to me it might be delta 
cycles :)

Henry

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

I have a few questions now:

1. How do I receive replies to my questions through email without also
receiving emails for any other question posted to the mailing list?

2. I'm unclear on variables. I see how they are declared now but how would
I make them retain their value each clock cycle like they do in VHDL
instead of reset to zero as you implied? I want to be able to use them for
instances where I need the value to change immediately instead of on the
next clock cycle, just like they do in VHDL.

3. I'm not sure this code does what was originally intended:
    addr_array[436:0].next = addr_array[436:0]
    addr_array[:436].next = most_recent_addr_req_to_sdram - 1

    For a simpler example, lets say cached_addresses is a std_logic_vector
representing three, 4-bit addresses put together and has these contents:
0000_0101_1111, and a signal called new_adddress is 4 bits wide, I wanted
to shift cached_addresses left 4 bits and make cached_addresses =
"0101_1111" & new_adddress. We are basically pushing everything down one
spot and adding the new address to the newly opened space. I'm not sure the
code above does that..

4. Is there an example of MyHDL code that generates a VHDL testbench. To
clarify, I want to write a testbench in MyHDL for a VHDL entity that MyHDL
doesn't know about, and have it immediately generate the VHDL testbench as
opposed to MyHDL trying to run it's own simulation of it. So it should be
the same process as getting MyHDL to generate a VHDL file for a normal
entity excpet it needs to know that this is a testbench so that it doesn't
complain about there being no ports declared in the entity being tested. I
tried something like this but MyHDL doesn't like it..

from design import *

def top_level_tb():
    s_sw = Signal(bool(0))
    s_clk = Signal(bool(0))
    s_btn = Signal(bool(0))
    s_seven_segment_display_1 = intbv(0)[7]
    s_seven_segment_display_0 = intbv(0)[7]
    s_seven_segment_display_3 = intbv(0)[7]
    s_seven_segment_display_2 = intbv(0)[7]

    top_level_instance = top_level(top_level, s_sw, s_clk, s_btn,
s_seven_segment_display_1, s_seven_segment_display_0,
s_seven_segment_display_3, s_seven_segment_display_2)

    @always(delay(10))
    def clkGenerator():
        s_clk.next = not s_clk

    @always(clk.posedge)
    def stimulus():
        s_btn[2].next = 0

    return top_level_instance, clkGenerator, stimulus

toVHDL(top_level_tb)

which threw:
"ImportError: No module named design"



>On 03/04/15 00:31, Tony Stark wrote:
>> Hi,
>>
>> I'm getting an error likely due to to a std_logic_vector being much
>> monger than myHDL was intended to handle.
>>
>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram -1)
>> I actually converted VHDL code to pyhton and want to continue
>> development of this fifo-like-buffer entity using python, but I need
>> to get around this error first..
>> The reason the array is so large is because I want to go through it in
>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>
>>
>
>I've created a gist that I think works based on your code...>https://gist.github.com/hgomersall/fc43e4cda49fc2494510 <https://gist.github.com/hgomersall/fc43e4cda49fc2494510>
>
>There seemed to be 2 obvious problems with your code.
>
>The first is concat as you highlighted, not seeming to like values that
>are too long. I suspect this is a problem only in the analyser and can
>be rectified relatively easily? I worked around this by assigning to
>sub-vectors independently.
>
>The second is you're using interim variables like signals (with .next
>and so on). If you want to use interim variables, do so something like:
>
>def foo(signal, clock, reset):
>     my_interim = intbv(0)[10:]
>
>     @always_seq(clock.posedge, reset)
>     def foo_entity():
>         signal.next = my_interim
>         my_interim[:] = my_interim + 1
>
>     return foo_entity
>
>There are two things to pick up on from this: (1) the way in which the
>intbv is updated with the `:` slicing and (2) that my_interim is created
>outside the instance. You can create it inside, but then every time
>foo_entity is run, it will be re initialized to zero (which is not what
>you want?).
>
>The version I've posted goes the other way and turns all your intbv
>interims into signals. This means the timings are all the same (writing
>to an intbv happens now, doing signal.next, nothing changes until next
>time). Effectively a few interim registers are created.
>
>I hope that all makes sense.
>
>Cheers,
>
>Henry


On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:

> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much monger
> than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>
> I actually converted VHDL code to pyhton and want to continue development
> of this fifo-like-buffer entity using python, but I need to get around this
> error first..
> The reason the array is so large is because I want to go through it in one
> clock cycle if needed. It represents 20, 23-bit addresses.
>
> The code is attached. please advise.
>
> Thanks,
> David
>

Re: [myhdl-list] A VHDL question about signal assignments and delta cycles?

[Christopher F. <chr...@gm...>]

<snip>
>
> Is this a delta cycle thing? Is it simulation specific? I'm not too
> concerned about it, but I'd like to understand the reason behind it.

I have not reviewed your inquiry in detail but
this might help answer your question:

http://www.sigasi.com/content/vhdls-crown-jewel

Regards,
Chris

[myhdl-list] A VHDL question about signal assignments and delta cycles?

[Henry G. <he...@ca...>]

In the process of writing my verification utilities code, I've 
encountered an interesting situation.

The following gist contains an example VHDL result that I'm querying:
https://gist.github.com/hgomersall/1d02129f02dd209e07cd

It's not a short gist, but it isn't very complicated, and the all the 
question relates to a small section of the code.

In the code the clock is not called clock, but "each_sub_signal" due to 
the way it was generated.

There is a recording block at line 165 onwards that writes to a line to 
a file on every clock edge (i.e. every edge of "each_sub_signal").

As written, this recording block also writes a signal called 
"copied_signal", which is assigned on line 161 just above it, and is 
assigned to be simply "each_sub_signal". That is, according to my 
understanding, it should be the same value as the clock.

Now, when this is run in Vivado, the resultant written file contains the 
values at each edge, and "each_sub_signal" (the clock) is always "1", as 
expected (since we're concerned with the rising edge), and 
"copied_signal" is always "0", implying it hasn't yet been updated.

Is this a delta cycle thing? Is it simulation specific? I'm not too 
concerned about it, but I'd like to understand the reason behind it.

Cheers,

Henry

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 03/04/15 00:31, Tony Stark wrote:
> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much 
> monger than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram -1)
> I actually converted VHDL code to pyhton and want to continue 
> development of this fifo-like-buffer entity using python, but I need 
> to get around this error first..
> The reason the array is so large is because I want to go through it in 
> one clock cycle if needed. It represents 20, 23-bit addresses.
>
>

I've created a gist that I think works based on your code...
https://gist.github.com/hgomersall/fc43e4cda49fc2494510

There seemed to be 2 obvious problems with your code.

The first is concat as you highlighted, not seeming to like values that 
are too long. I suspect this is a problem only in the analyser and can 
be rectified relatively easily? I worked around this by assigning to 
sub-vectors independently.

The second is you're using interim variables like signals (with .next 
and so on). If you want to use interim variables, do so something like:

def foo(signal, clock, reset):
     my_interim = intbv(0)[10:]

     @always_seq(clock.posedge, reset)
     def foo_entity():
         signal.next = my_interim
         my_interim[:] = my_interim + 1

     return foo_entity

There are two things to pick up on from this: (1) the way in which the 
intbv is updated with the `:` slicing and (2) that my_interim is created 
outside the instance. You can create it inside, but then every time 
foo_entity is run, it will be re initialized to zero (which is not what 
you want?).

The version I've posted goes the other way and turns all your intbv 
interims into signals. This means the timings are all the same (writing 
to an intbv happens now, doing signal.next, nothing changes until next 
time). Effectively a few interim registers are created.

I hope that all makes sense.

Cheers,

Henry

[myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

from myhdl import *

CACHE_SIZE = 20
NUM_OF_ADDRESSES = 25

# entity creation:
def vga_fifo(
  # ports:
  clk,
  rst,
  # VGA: Avalon Memory Mapped Slave
  read_request_from_vga ,
  addr_req_by_vga,
  data_out_to_vga,

  # EXPORT
  vga_cache_miss,
  oldest_stored_addr,
  newest_stored_addr,

  # SDRAM: Avalon Memory Mapped Master
  read_req_to_sdram,
  valid_from_sdram,
  wait_req_from_sdram,
  addr_req_to_sdram ,
  data_in_from_sdram
):
    # Entity instantiation:
    # entity_name = entity_name(ports, in, order)

    # procedural process:
    @always_seq(clk.posedge, reset=rst)
    def main_process():

        most_recent_addr_req_to_sdram = intbv(0)[23:] # modbv loops back to zero when incremented
        addr_array = intbv(0)[459:0]
        data_array = intbv(0)[319:0]
        cas_delay_counter = modbv(0)[2:]

        #############################
        #  addr_array & data_array  #
        #############################
        if valid_from_sdram:
            if most_recent_addr_req_to_sdram + 1 > 0:
                addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
            else:
                addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
            oldest_stored_addr.next = addr_array[459:437]
            newest_stored_addr.next = addr_array[22:0]
            data_array.next = concat(data_array[303:0], data_in_from_sdram)

        #######################
        #  addr_req_to_sdram  #
        #######################
        if not wait_req_from_sdram:
            if addr_array[22:0] + 1 < NUM_OF_ADDRESSES:
                addr_req_to_sdram.next = addr_array[22:0] + 1
                most_recent_addr_req_to_sdram.next = addr_array[22:0] + 1
            else:
                addr_req_to_sdram.next = 0
                most_recent_addr_req_to_sdram.next = 0

        #######################
        #  read_req_to_sdram  #
        #######################
        if not wait_req_from_sdram and addr_req_by_vga != addr_array[459:437]:
            read_req_to_sdram.next = 1
        else:
            read_req_to_sdram.next = 0


        #####################
        #  data_out_to_vga  #
        #####################
        if read_request_from_vga:
            vga_cache_miss.next = 0
            if addr_array[459:437] == addr_req_by_vga: # oldest
                data_out_to_vga.next = data_array[319:304]
            elif addr_array[436:414] == addr_req_by_vga:
                data_out_to_vga.next = data_array[303:288]
            elif addr_array[413:391] == addr_req_by_vga:
                data_out_to_vga.next = data_array[287:272]
            elif addr_array[390:368] == addr_req_by_vga:
                data_out_to_vga.next = data_array[271:256]
            elif addr_array[367:345] == addr_req_by_vga:
                data_out_to_vga.next = data_array[255:240]
            elif addr_array[344:322] == addr_req_by_vga:
                data_out_to_vga.next = data_array[239:224]
            elif addr_array[321:299] == addr_req_by_vga:
                data_out_to_vga.next = data_array[223:208]
            elif addr_array[298:276] == addr_req_by_vga:
                data_out_to_vga.next = data_array[207:192]
            elif addr_array[275:253] == addr_req_by_vga:
                data_out_to_vga.next = data_array[191:176]
            elif addr_array[252:230] == addr_req_by_vga:
                data_out_to_vga.next = data_array[175:160]
            elif addr_array[229:207] == addr_req_by_vga:
                data_out_to_vga.next = data_array[159:144]
            elif addr_array[206:184] == addr_req_by_vga:
                data_out_to_vga.next = data_array[143:128]
            elif addr_array[183:161] == addr_req_by_vga:
                data_out_to_vga.next = data_array[127:112]
            elif addr_array[160:138] == addr_req_by_vga:
                data_out_to_vga.next = data_array[111:96]
            elif addr_array[137:115] == addr_req_by_vga:
                data_out_to_vga.next = data_array[95:80]
            elif addr_array[114:92] == addr_req_by_vga:
                data_out_to_vga.next = data_array[79:64]
            elif addr_array[91:69] == addr_req_by_vga:
                data_out_to_vga.next = data_array[63:48]
            elif addr_array[68:46] == addr_req_by_vga:
                data_out_to_vga.next = data_array[47:32]
            elif addr_array[45:23] == addr_req_by_vga:
                data_out_to_vga.next = data_array[31:16]
            elif addr_array[22:0] == addr_req_by_vga: # newest
                data_out_to_vga.next = data_array[15:0]
            else:
                vga_cache_miss.next = 1

    return main_process


clk = Signal(bool())
rst = ResetSignal(0, active=0, async=True)
# VGA: Avalon Memory Mapped Slave
read_request_from_vga = Signal(bool())
addr_req_by_vga = Signal(modbv(0)[23:])
data_out_to_vga = Signal(modbv(0)[16:])
# EXPORT
vga_cache_miss  = Signal(bool())
addr_of_data_to_vga = Signal(modbv(0)[23:])
oldest_stored_addr = Signal(modbv(0)[23:])
newest_stored_addr = Signal(modbv(0)[23:])
# SDRAM: Avalon Memory Mapped Master
read_req_to_sdram = Signal(bool())
valid_from_sdram = Signal(bool())
wait_req_from_sdram = Signal(bool())
addr_req_to_sdram = Signal(modbv(0)[23:])
data_in_from_sdram = Signal(modbv(0)[16:])

# convert to VHDL toVHDL(entity_name, port1, port2, port3...)
toVHDL(vga_fifo,
       clk,
       rst,
       read_request_from_vga ,
       addr_req_by_vga,
       data_out_to_vga,
       vga_cache_miss,
       oldest_stored_addr,
       newest_stored_addr,
       read_req_to_sdram,
       valid_from_sdram,
       wait_req_from_sdram,
       addr_req_to_sdram,
       data_in_from_sdram)

Re: [myhdl-list] Problem with slicing of a slice signal when using a user defined verilog code

[Christopher F. <chr...@gm...>]

Yes, I will fix my typo and investigate.

Regard,
Chris

On Thursday, April 2, 2015, cad master <pro...@gm...> wrote:

> Hi Chris,
>
> First of all thank you for your comments.
>
> 1. The myhdl version I'm using is 482b832bda4c.
> 2. Line 14, and 15 in your snippet should be:
> part_of_in1_part = in1_part(5,2)
> part_of_in2_part = in2_part(5,2)
>
> and not
>
> part_of_in1_part = in1(5,2)
> part_of_in2_part = in2(5,2)
>
> And this is exactly my problem, a slice of a slice.
>
> Thanks,
> Alon
>
>

-- 
Sent from Gmail Mobile

Re: [myhdl-list] Conversion to VHDL

[Henry G. <he...@ca...>]

On 02/04/15 16:22, Edward Vidal wrote:
> Should the above convert to VHDL as

Seriously, you really need to think how you're presenting your code. 
Your snippets are very difficult to read.

Can I suggest using a github gist, or, at the very least, using a 
monospaced font and proper python syntax.

Cheers,

Henry

Re: [myhdl-list] Problem with slicing of a slice signal when using a user defined verilog code

[cad m. <pro...@gm...>]

Hi Chris,

First of all thank you for your comments.

1. The myhdl version I'm using is 482b832bda4c.
2. Line 14, and 15 in your snippet should be:
part_of_in1_part = in1_part(5,2)
part_of_in2_part = in2_part(5,2)

and not

part_of_in1_part = in1(5,2)
part_of_in2_part = in2(5,2)

And this is exactly my problem, a slice of a slice.

Thanks,
Alon

[myhdl-list] Conversion to VHDL

[Edward V. <dev...@sb...>]

Hello All,

<snip>
Where W0 = 9
x = Signal(intbv(0, min=-(2**(W0)), max=(2**(W0))))
z = Signal(intbv(0)[W0:])

<snip>
z.next = x[W0:]
yield clk.posedge
matrix_sa[ma_row][ma_col].next = z

Should the above convert to VHDL as
z: out unsigned(8 downto 0);
(the above is what I am getting)
or z: inout unsigned(8 downto 0);?

The one with inout is what I need to do
when I instantiate in another VHDL file.
Thanks
 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613