myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Hello World

[Christopher F. <chr...@gm...>]

On 4/25/15 1:12 PM, Günther Stangassinger wrote:
> Hello,
> i am quite new to Myhdl and playing around with the de0-nano Board.
> I was trying to access the  ADXL345 over the SPI 3 wire bus. (just
> trying to read the DEVID)
> The small code example is working in simulation mode as far as i can judge.
> But on the real board i get 0x0 for the DEVID which should be 0xE5

Is this the latest DE0 with the cyclone-IV?

If you are intending to communicate over I2C are
you keeping the CSn signal high to the ADXL345?
(I have dug through the code yet).  If you are
not

Do you have this in a public repo, like github
or bitbucket?

Regards,
Chris

Re: [myhdl-list] IP core library

[Christopher F. <chr...@gm...>]

On 4/25/15 1:54 PM, Euripedes Rocha Filho wrote:
> Hi,
> I'm starting a small (actually no IP so far) library and wondering if
> someone has some suggestion on how to structure it.Â

This is great, more IP (cores) development the
better.  Using common Python package structure
is a good place to start.

There are various projects out there,
here are a couple that you can look at:

This is my small collection of "cores", I slowly
add to it as I have time ...
https://github.com/cfelton/minnesota

FPGA digital radio (SDR) using MyHDL:
https://github.com/testaco/whitebox

Keerthan's HDL toolbox:
https://github.com/jck/uhdl

>
> The repository (just started the package using cookiecutter)
> Â https://github.com/euripedesrocha/instar
>
> My idea is to use MyHDL as both simulation and hdl decription language,
> using verilog conversion to put the design under the regular FPGA work
> flow ( also I'll use Chistopher's myhdl_tools package in the build flow ).
>

Note, I have moved the FPGA flow from myhdl_tools
to gizflo (couple reasons why and I can explain
if interested)
https://github.com/cfelton/gizflo

> What I have in mind now is:
>
> There's any advantage in use a class packing the interface signals and a
> method with the hardware description, or use another structure?

This depends, in my opinion you don't want to go
class/object crazy :)  Creating clean interfaces
will help the code a ton.  I tend to keep my main
modules not part of a class but for models I include
many myhdl generators in a class.

>
> Any thoughts?

One of the things you should do early is how you
want to structure the tests.  I would suggest using
py.test and following some of their suggestions:
https://pytest.org/latest/goodpractises.html

Following a TDD flow would be an good idea but takes
some discipline.

Regards,
Chris

[myhdl-list] IP core library

[Euripedes R. F. <roc...@gm...>]

Hi,
I'm starting a small (actually no IP so far) library and wondering if
someone has some suggestion on how to structure it.

The repository (just started the package using cookiecutter)
 https://github.com/euripedesrocha/instar

My idea is to use MyHDL as both simulation and hdl decription language,
using verilog conversion to put the design under the regular FPGA work flow
( also I'll use Chistopher's myhdl_tools package in the build flow ).

What I have in mind now is:

There's any advantage in use a class packing the interface signals and a
method with the hardware description, or use another structure?

Any thoughts?

[myhdl-list] Hello World

[Günther S. <gue...@gm...>]

Hello,
i am quite new to Myhdl and playing around with the de0-nano Board.
I was trying to access the  ADXL345 over the SPI 3 wire bus. (just 
trying to read the DEVID)
The small code example is working in simulation mode as far as i can judge.
But on the real board i get 0x0 for the DEVID which should be 0xE5



 >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
import os
import random
from random import randrange
from copy import copy

## python compile.py  de0nano;  cp altera/ise/stroby_de0nano/de0nano.qsf 
/home/tux/altera_proj/DE0_NANO_default
## python convert.py ; cp top.vhd pck_myhdl_081.vhd 
/home/tux/altera_proj/DE0_NANO_default
## python convert.py ; cp top.v tb_top.v 
/home/tux/altera_proj/DE0_NANO_default
## cp top.v top.v_orig; cp tb_top.v tb_top.v_orig; python convert.py ; 
cp top.v tb_top.v /home/tux/altera_proj/DE0_NANO_default; meld top.v 
top.v_orig; meld tb_top.v tb_top.v_orig;
## python gw.py; gtkwave  test_dff.vcd
## pip install --upgrade git+https://github.com/jandecaluwe/myhdl



from myhdl import *

def clk_gen(CLOCK_50, tick, tick2):
     #CLK_FREQ = 48e6  # clock frequency
     #LED_RATE = 0.001 # strobe change rate
     CLK_FREQ = 10   # simulation only !!!!
     LED_RATE = 1 # simulation mode
     CNT_MAX = int(CLK_FREQ * LED_RATE)
     diff_rate = 0.45
     CNT_DIFF = int(CLK_FREQ * diff_rate)
     clk_cnt        = Signal(intbv(0, min=0, max=CNT_MAX+2))

     @always(CLOCK_50.posedge)
     def logic():
         clk_cnt.next = clk_cnt + 1
         if clk_cnt == CNT_MAX-CNT_MAX/2:
             tick.next = 1

         if clk_cnt == CNT_MAX-CNT_MAX/2+CNT_DIFF:
             tick2.next = 1


         if clk_cnt == CNT_MAX:
             clk_cnt.next = 0
             tick.next = 0
             tick2.next = 0




     return logic



def readData(tick, tick2, G_SENSOR_CS_N,I2C_SDAT,LED , I2C_SCLK, count, 
START, PAUSE):

     w_adr_1  = Signal(intbv(0x8c)[8:0])#31-->31
     w_data1  = Signal(intbv(0x02)[8:0])#40-->40
     w_adr_2  = Signal(intbv(0x01)[8:0])#00-->80
     r_data2  = Signal(intbv(0)[8:0])   # should be DEVID (0xE5)

     io = I2C_SDAT.driver()



     @always(tick.negedge)
     def readData_gen():


         if count > 37+PAUSE:
             count.next = count -1


         elif (count >=29+PAUSE) and (count <= 37+PAUSE) :
             count.next = count - 1

             if (count >= 29+PAUSE) and (count <= 36+PAUSE):
                 io.next = w_adr_1[36+PAUSE - count]

         elif (count >= 21+PAUSE) and (count < 29+PAUSE):
             count.next= count - 1
             io.next = w_data1[28+PAUSE - count]

         elif (count >= 20) and (count < 21+PAUSE):
             count.next= count - 1


         elif (count >= 11) and (count < 20):
             count.next = count - 1
             if (count > 11) and (count <= 18):
                 io.next = w_adr_2[18 - count]

         elif (count > 0) and (count < 11):
             count.next = count - 1
             io.next = None


         else:
             count.next = START


     @always(tick2.posedge)
     def c_select():
         if count == (45 + PAUSE):
             G_SENSOR_CS_N.next = 0

         if count == (43 + PAUSE):
             G_SENSOR_CS_N.next = 1


         if count == (36 + PAUSE):
             G_SENSOR_CS_N.next = 0

         if count == (20 + PAUSE):
             G_SENSOR_CS_N.next = 1

         if count == 18 :
             G_SENSOR_CS_N.next = 0

         if count == 2 :
             G_SENSOR_CS_N.next = 1


         if (count > 2) and (count < 11):
             if (I2C_SDAT == True):
                 r_data2.next[10-count] = 1
             else:
                 r_data2.next[10-count] = 0




     collector = Signal(intbv(0)[8:0])
     @always_comb
     def check_sclk2():

         if I2C_SDAT == 1:
             collector.next[0] = 1
         else:
             collector.next[0] = 0


         if I2C_SCLK == 1:
             collector.next[1] = 1
         else:
             collector.next[1] = 0

         if G_SENSOR_CS_N == 1:
             collector.next[2] = 0
         else:
             collector.next[2] = 1

#################################
         if count == 36+PAUSE:
             collector.next[7] = 1
         else:
             collector.next[7] = 0


         if count == 28+PAUSE:
             collector.next[6] = 1
         else:
             collector.next[6] = 0

         if count == 18:
             collector.next[5] = 1
         else:
             collector.next[5] = 0


         if count <=9 and count >=2:
             collector.next[4] = 1
         else:
             collector.next[4] = 0



     @always_comb
     def collector_comb():
         LED.next = r_data2
         #LED.next = collector




     return instances()


def drive_spi(tick, tick2, G_SENSOR_CS_N,G_SENSOR_INT,I2C_SCLK,I2C_SDAT, 
LED, count, START, PAUSE):

     read_Adr_inst = readData( tick, tick2, G_SENSOR_CS_N,I2C_SDAT,LED , 
I2C_SCLK,count, START, PAUSE)


     @always_comb
     def al_c1():
         I2C_SCLK.next = tick


     return instances()



def top( CLOCK_50, LED,G_SENSOR_CS_N,G_SENSOR_INT,I2C_SCLK,I2C_SDAT):
     tick  = Signal(False)
     tick2  = Signal(False)
     START = 40
     PAUSE = 4
     count = Signal(intbv(START, min=-1, max=10000))
     clk_gen_inst = clk_gen(CLOCK_50, tick, tick2)
     drive_spi_inst = drive_spi(tick, tick2, 
G_SENSOR_CS_N,G_SENSOR_INT,I2C_SCLK,I2C_SDAT, LED, count, START, PAUSE)


     return instances()





def test_dff():
     G_SENSOR_CS_N = Signal(bool(1))
     G_SENSOR_INT  = Signal(bool(0))
     I2C_SCLK      = Signal(bool(1))
     I2C_SDAT      = TristateSignal(False)
     LED =   Signal(intbv(0)[8:])

     clk = Signal(bool(0))
     dff_inst = top( clk, LED,G_SENSOR_CS_N,G_SENSOR_INT,I2C_SCLK,I2C_SDAT)

     @always(delay(1))
     def clkgen():
         clk.next = not clk

     return dff_inst, clkgen

def simulate(timesteps):
     tb = traceSignals(test_dff)
     sim = Simulation(tb)
     sim.run(timesteps)

simulate(4000)



########################################################
main.py:
from myhdl import *
from gw import top


def convert():
     G_SENSOR_CS_N = Signal(bool(1))
     G_SENSOR_INT  = Signal(bool(0))
     I2C_SCLK      = Signal(bool(1))
     I2C_SDAT = TristateSignal(False)
     CLOCK_50 =   Signal(bool(0))
     LED =   Signal(intbv(0)[8:])


  ##   toVerilog(top,clock,reset,LED)
  ##   toVHDL(top,CLOCK_50, 
LED,G_SENSOR_CS_N,G_SENSOR_INT,I2C_SCLK,I2C_SDAT )
     toVerilog(top,CLOCK_50, 
LED,G_SENSOR_CS_N,G_SENSOR_INT,I2C_SCLK,I2C_SDAT )

if __name__ == '__main__':
     convert()

 >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>


I could not see any errors whan i look on the gtkwave signal.
Mybe somebody has the same eval board and is somewhat familiar with the SPI.
My guess is, that i am doing something wrong with the tristate signal 
I2C_SDAT !
Could this be the reason that a still have 0x0 instead of 0xE5 when i 
read this port?
I would very much appreciate if someone could help me out because i
really like myhdl a lot even i have not seen al lot of this tooling.
Thank you very much.



-- 
Mit freundlichen Grüßen
Günther Stangassinger

Re: [myhdl-list] Module uses globals

[Henry G. <he...@ca...>]

On 19/04/15 16:36, Christopher Felton wrote:
> On 4/16/15 3:11 AM, Henry Gomersall wrote:
>> >On 15/04/15 21:29, Christopher Felton wrote:
>>> >><snip>
>>>>>>>>> >>>>>>>>
>>>>>>>>> >>>>>>>>This totally defeats the beauty of object orientation in Python. For
>>>>>>>>> >>>>>>>>example you cannot have two instances of a Simulation() at the same time.
>>>>>>> >>>>>>
>>>>>>> >>>>>>What is the rationale for more than one simulation
>>>>>>> >>>>>>running at a time?  Why have two simulators running?
>>>>>>> >>>>>>
>>>>> >>>>
>>>>> >>>>What is great about having a HDL simulation within a full blown language
>>>>> >>>>like Python is the possibility of doing unconventional things. Some that I
>>>>> >>>>can think of are, first, running a same model in delayed and asynchronous
>>>>> >>>>versions, with a controlled, time varying delay and comparing states.
>>> >>Sure, folks have experiment with aysnc simulations before
>>> >>but did not require two simulation instances.
>>> >>
>> >
>> >One thing that is quite hard to do is making blocking calls without
>> >pausing the simulator. It is always possible to run the blocking code in
>> >its own thread with polling on every tick, but there is plausibly a neat
>> >model with separate simulations representing entities that are not
>> >synchronous to one another.
> In my opinion, you would not want to make "blocking"
> calls because you are mixing the thread scheduling and
> the simulator scheduling - bad idea.

Sometimes (as in the example given of interacting with a spice 
simulator), one's approach might be limited.

Cheers,
Henry

Re: [myhdl-list] Wrapper for shadow signal

[Christopher F. <chr...@gm...>]

On 4/20/2015 11:47 AM, Christopher Felton wrote:
> On 4/20/2015 10:01 AM, Edward Vidal wrote:
>>    Hello All,
>> The module m_flatten is used to construct a144 bit signal from 16 9 bit signals.
>
> I believe the issue is, nothing is driving the `matrix`.
> During conversion there is nothing to assign to the
> Signals referenced (shadowed).
>

I created this example that might help.  Note, I created
it very quickly.  The SignalMatrix can only be accessed
in the elaboration code, you can access the SignalMatrix
directly in the myhdl generators.

https://gist.github.com/cfelton/f6a1a1e0cfb2204cd2ee

You would want to apply a test similar to the previous.

Regards,
Chris

Re: [myhdl-list] Wrapper for shadow signal

[Christopher F. <chr...@gm...>]

On 4/20/2015 10:01 AM, Edward Vidal wrote:
>   Hello All,
> The module m_flatten is used to construct a144 bit signal from 16 9 bit signals.

I believe the issue is, nothing is driving the `matrix`.
During conversion there is nothing to assign to the
Signals referenced (shadowed).

Regards,
Chris

[myhdl-list] Wrapper for shadow signal

[Edward V. <dev...@sb...>]

 Hello All,
The module m_flatten is used to construct a144 bit signal from 16 9 bit signals.
Can someone explain how to generate a wrapper for the shadow signal flat_i in the module m_flattenin the file https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten.vhd?
The file https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/flaten.pyis used to create m_flatten.vhd.There are several lines similar to  "flat_i(144-1 downto 135) <= None;". The None values create errors in an ISE simulation.The m_flatten module works okay in a MyHDL testbenchhttps://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/test_bench_array_jpeg.pywhere I use 3 instances of    instance_mat_lf = m_flatten(matrix_lf, flat_lf)    instance_mat_sa = m_flatten(matrix_sa, flat_sa)    instance_mat_rt = m_flatten(matrix_rt, flat_rt)
What I have tried for the wrapper is the filehttps://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/matrix.py.
I use matrix.py in the file https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/test_bench_array_jpeg_ram.py.
This creates https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/top_jpeg.vhd. I get many similar errorsLine 110: <none> is not declared.Any and all help is appreciated.
ThanksEdward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Module uses globals

[Christopher F. <chr...@gm...>]

<snip>
>
> Chris:
>
> The need for multiple simulator instances is to have the simulation time
> be different across them. Then be able to pause one, advance the other,
> compare model A at time t=t1 versus model B at time t=t2, etc.

Fair enough, but I am not 100% convinced this can't be
done in a single Simulator:

     design1 = design_foo(...)
     design2 = design_bar(...)

     Simulation((design1, design2,)).run()

But it would be a little awkward because you would need
to create you own controls.  The issue with supporting
concurrent simulations is making sure there are no collision
(i.e. generators that existing in both simulations).

> There is
> no pausing/resuming in the current library, but I'm running the
> simulations in separate processes and I have them wait on given events
> for permission to continue sent from the controlling process.
>

Yes, there is no `PauseSimulation` (possibly a reasonable
enhancement).  The current mechanism to start and stop
(pause) is to run a specific number of simulation cycles:

     sim = Simulation(...)
     sim.run(100)
     # simulator is paused, now continue
     sim.run(100)

Regards,
Chris

Re: [myhdl-list] Module uses globals

[Christopher F. <chr...@gm...>]

On 4/16/15 3:11 AM, Henry Gomersall wrote:
> On 15/04/15 21:29, Christopher Felton wrote:
>> <snip>
>>>>>>>>
>>>>>>>> This totally defeats the beauty of object orientation in Python. For
>>>>>>>> example you cannot have two instances of a Simulation() at the same time.
>>>>>>
>>>>>> What is the rationale for more than one simulation
>>>>>> running at a time?  Why have two simulators running?
>>>>>>
>>>>
>>>> What is great about having a HDL simulation within a full blown language
>>>> like Python is the possibility of doing unconventional things. Some that I
>>>> can think of are, first, running a same model in delayed and asynchronous
>>>> versions, with a controlled, time varying delay and comparing states.
>> Sure, folks have experiment with aysnc simulations before
>> but did not require two simulation instances.
>>
>
> One thing that is quite hard to do is making blocking calls without
> pausing the simulator. It is always possible to run the blocking code in
> its own thread with polling on every tick, but there is plausibly a neat
> model with separate simulations representing entities that are not
> synchronous to one another.

In my opinion, you would not want to make "blocking"
calls because you are mixing the thread scheduling and
the simulator scheduling - bad idea.

Now, you might want to leverage some of the Python
communication objects like Queue but I would not use
them blocking (because of the mixed scheduling).

Taking the Queue as an example, I have wrapped it to
works with the Simulator:
https://github.com/cfelton/test_jpeg/blob/master/test/support/_SignalQueue.py

This way I can uses a Queue (non-blocking) with the
simulator scheduler.

Regards,
Chris

Re: [myhdl-list] Module uses globals

[Juan P. C. <jp...@gm...>]

Henry:

I managed to make this work with multiprocessing. I was trying with
threading and I thought they had identical behavior except for the former
creating a new process instead of just a new thread. It seems that when a
new process is spawned, global variables are copied instead of referenced,
or something like that, and there is no shared state, except for instances
of multiprocessing.Queue. I couldn't find clear documentation about this.

Chris:

The need for multiple simulator instances is to have the simulation time be
different across them. Then be able to pause one, advance the other,
compare model A at time t=t1 versus model B at time t=t2, etc. There is no
pausing/resuming in the current library, but I'm running the simulations in
separate processes and I have them wait on given events for permission to
continue sent from the controlling process.

Thanks,

JP


On Thu, Apr 16, 2015 at 4:11 AM, Henry Gomersall <he...@ca...> wrote:

> On 15/04/15 21:29, Christopher Felton wrote:
> > <snip>
> >>>> >>>
> >>>> >>>This totally defeats the beauty of object orientation in Python.
> For
> >>>> >>>example you cannot have two instances of a Simulation() at the
> same time.
> >>> >>
> >>> >>What is the rationale for more than one simulation
> >>> >>running at a time?  Why have two simulators running?
> >>> >>
> >> >
> >> >What is great about having a HDL simulation within a full blown
> language
> >> >like Python is the possibility of doing unconventional things. Some
> that I
> >> >can think of are, first, running a same model in delayed and
> asynchronous
> >> >versions, with a controlled, time varying delay and comparing states.
> > Sure, folks have experiment with aysnc simulations before
> > but did not require two simulation instances.
> >
>
> One thing that is quite hard to do is making blocking calls without
> pausing the simulator. It is always possible to run the blocking code in
> its own thread with polling on every tick, but there is plausibly a neat
> model with separate simulations representing entities that are not
> synchronous to one another.
>
> That said, it is possible to run multiple simulation instances using the
> multiprocess module (as in the example I gave). This is arguable better
> anyway as it makes it absolutely clear that you're dealing with separate
> circuits (inter process communication being much harder than
> communicating between threads, there is little risk of inadvertent state
> transfer).
>
> Cheers,
>
> Henry
>
>
> ------------------------------------------------------------------------------
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>

Re: [myhdl-list] Module uses globals

[Henry G. <he...@ca...>]

On 15/04/15 21:29, Christopher Felton wrote:
> <snip>
>>>> >>>
>>>> >>>This totally defeats the beauty of object orientation in Python. For
>>>> >>>example you cannot have two instances of a Simulation() at the same time.
>>> >>
>>> >>What is the rationale for more than one simulation
>>> >>running at a time?  Why have two simulators running?
>>> >>
>> >
>> >What is great about having a HDL simulation within a full blown language
>> >like Python is the possibility of doing unconventional things. Some that I
>> >can think of are, first, running a same model in delayed and asynchronous
>> >versions, with a controlled, time varying delay and comparing states.
> Sure, folks have experiment with aysnc simulations before
> but did not require two simulation instances.
>

One thing that is quite hard to do is making blocking calls without 
pausing the simulator. It is always possible to run the blocking code in 
its own thread with polling on every tick, but there is plausibly a neat 
model with separate simulations representing entities that are not 
synchronous to one another.

That said, it is possible to run multiple simulation instances using the 
multiprocess module (as in the example I gave). This is arguable better 
anyway as it makes it absolutely clear that you're dealing with separate 
circuits (inter process communication being much harder than 
communicating between threads, there is little risk of inadvertent state 
transfer).

Cheers,

Henry

Re: [myhdl-list] Module uses globals

[Christopher F. <chr...@gm...>]

<snip>
>>>
>>> This totally defeats the beauty of object orientation in Python. For
>>> example you cannot have two instances of a Simulation() at the same time.
>>
>> What is the rationale for more than one simulation
>> running at a time?  Why have two simulators running?
>>
>
> What is great about having a HDL simulation within a full blown language
> like Python is the possibility of doing unconventional things. Some that I
> can think of are, first, running a same model in delayed and asynchronous
> versions, with a controlled, time varying delay and comparing states.

Sure, folks have experiment with aysnc simulations before
but did not require two simulation instances.

> Another is bifurcation, this is, generating a copy of a model and
> simulation at some time instant and comparing the two based on some
> asymmetry, potentially generating copies throughout the simulation and
> discarding them when not needed. Things like this are useful in stability
> analysis of non-linear mixed-signal circuits.
>

You can still break up the design, typically the testbench
and models have a lot going on independent of the design.
I still don't see the need for two simulation instances?

I can simulate two complete unrelated designs at the same
time but in the same Simulation instance.  I am not
understanding the need for multiple simulation instances.

Regards,
Chris

Re: [myhdl-list] Handling signal in cosimulation

[Euripedes R. F. <roc...@gm...>]

Solving my own problem, The problem is that the signal range was wrong. As
always after a lot of investigations and have no more clues of the solution
the problem is a bug in the only place you assume that is correct :).

Thank you all for the help :)

2015-04-15 17:10 GMT-03:00 Euripedes Rocha Filho <roc...@gm...>
:

> After several months I come back, with the same issue now with a better
> undersatnding :).
>
> I'm using the following structure to test my VHDL code:
>
> MyHDL->Verilog tb-> VHDL dut
>
> I'm using modelsim with mixed language support and it's working with no
> flaws in the last months (the project got frozen for almost an year).
>
> The problem is:
>
> I have some intbv generated in the myhdl test (like in the following code
> https://gist.github.com/euripedesrocha/0d162251f9805d23073a )
>
> test_data_correct is the test bench, and build core is a py.test fixture
> that build the core once for test session.
>
> The verilog test bench instantiates VHDL code and the internal signals are
> all std_logic_vectors. And they are declared as follow
>
> reg
> clk_i;
>
> reg
> enable_i;
>
> reg signed  [`DATA_WIDTH-1:0]
> data_i;
>
> wire
> enable_o;
>
> wire signed [`DATA_WIDTH-1:0] data_o;
>
> Every time the generated data is negative the value returned from the VHDL
> core is interpreted as a positive number instead of a negative one. All
> bits are correct.
>
> Any suggestion for fix it?
>
>
>

[myhdl-list] Handling signal in cosimulation

[Euripedes R. F. <roc...@gm...>]

After several months I come back, with the same issue now with a better
undersatnding :).

I'm using the following structure to test my VHDL code:

MyHDL->Verilog tb-> VHDL dut

I'm using modelsim with mixed language support and it's working with no
flaws in the last months (the project got frozen for almost an year).

The problem is:

I have some intbv generated in the myhdl test (like in the following code
https://gist.github.com/euripedesrocha/0d162251f9805d23073a )

test_data_correct is the test bench, and build core is a py.test fixture
that build the core once for test session.

The verilog test bench instantiates VHDL code and the internal signals are
all std_logic_vectors. And they are declared as follow

reg
clk_i;

reg
enable_i;

reg signed  [`DATA_WIDTH-1:0]
data_i;

wire
enable_o;

wire signed [`DATA_WIDTH-1:0] data_o;

Every time the generated data is negative the value returned from the VHDL
core is interpreted as a positive number instead of a negative one. All
bits are correct.

Any suggestion for fix it?

Re: [myhdl-list] Module uses globals

[Juan P. C. <jp...@gm...>]

On Wed, Apr 15, 2015 at 1:23 PM, Christopher Felton <chr...@gm...>
wrote:

> On 4/11/2015 3:43 PM, Juan Pablo Caram wrote:
> > Hi,
> >
> > I'm starting to learn the internals of MyHDL and I see it's using global
> > variables everywhere.
>
> Those are fighting words ...
>

Not my intention at all. I apologize if it was perceived that way.


>
> >
> > This totally defeats the beauty of object orientation in Python. For
> > example you cannot have two instances of a Simulation() at the same time.
>
> What is the rationale for more than one simulation
> running at a time?  Why have two simulators running?
>

What is great about having a HDL simulation within a full blown language
like Python is the possibility of doing unconventional things. Some that I
can think of are, first, running a same model in delayed and asynchronous
versions, with a controlled, time varying delay and comparing states.
Another is bifurcation, this is, generating a copy of a model and
simulation at some time instant and comparing the two based on some
asymmetry, potentially generating copies throughout the simulation and
discarding them when not needed. Things like this are useful in stability
analysis of non-linear mixed-signal circuits.


>
> >
> > Would this qualify for a bug issue?
>
> No.
>
> >
> > Maybe there is a bigger architectural problem? Maybe it has to do with
> the
> > way it uses "inspect"?
>
> There are all kinds of issues, each simulator instance
> could not share generators, this would need to be enforced.
>

Without fully understanding the internals of MyHDL, my first thought is why
Simulation objects have shared context and cannot be fully encapsulated in
their class? Second is, wouldn't it be preferable? If so, I'd be interest
in contributing towards this. If not, am I proposing something that would
fully break the architecture and should better find another route?

Thanks,

JP

Re: [myhdl-list] Module uses globals

[Christopher F. <chr...@gm...>]

On 4/11/2015 3:43 PM, Juan Pablo Caram wrote:
> Hi,
>
> I'm starting to learn the internals of MyHDL and I see it's using global
> variables everywhere.

Those are fighting words ...

>
> This totally defeats the beauty of object orientation in Python. For
> example you cannot have two instances of a Simulation() at the same time.

What is the rationale for more than one simulation
running at a time?  Why have two simulators running?

>
> Would this qualify for a bug issue?

No.

>
> Maybe there is a bigger architectural problem? Maybe it has to do with the
> way it uses "inspect"?

There are all kinds of issues, each simulator instance
could not share generators, this would need to be enforced.

Regards,
Chris

Re: [myhdl-list] Simulation control

[Henry G. <he...@ca...>]

On 10/04/15 22:57, Juan Pablo Caram wrote:
> How did you get away with running two simulations at the same time. 
> MyHDL uses global variables. I tried an approach with threads and as 
> soon as I start the 2nd simulation, the 1st one is messed up.
>

They're run as separate processes, which have no implicit shared state.

Check out the code, which uses the multiprocess package.

Cheers,

Henry

[myhdl-list] Module uses globals

[Juan P. C. <jp...@gm...>]

Hi,

I'm starting to learn the internals of MyHDL and I see it's using global
variables everywhere.

This totally defeats the beauty of object orientation in Python. For
example you cannot have two instances of a Simulation() at the same time.

Would this qualify for a bug issue?

Maybe there is a bigger architectural problem? Maybe it has to do with the
way it uses "inspect"?

Thanks,

JP

Re: [myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

Henry,

How did you get away with running two simulations at the same time. MyHDL
uses global variables. I tried an approach with threads and as soon as I
start the 2nd simulation, the 1st one is messed up.

Thanks,

JP

On Tue, Apr 7, 2015 at 12:33 PM, Henry Gomersall <he...@ca...> wrote:

> On 07/04/15 15:56, Juan Pablo Caram wrote:
> > The link on "mixed mode" simulation is a proof of concept, but very
> > naive. I've put together a blog post discussing the difficulties that
> > one might find:
> >
> > http://caram.cl/developing-a-mixed-signal-simulator
> >
> > The link about interactive simulation is more along the lines of what
> > would be required, but using the function calls, not the interactive
> > console. I see it's using a debugger and that might make it extremely
> > slow. It would be ideal if this functionality was built into the
> > simulator. If I were to implement this functionality into the
> > simulator, any idea on where I should start? I haven't seen any
> > documentation about the operation of the simulator.
>
> I read your blog post, and I still don't see what the fundamental
> problem is.
>
> In your final example, your DAC and your ADC are going to have to be
> instantaneous samplers. It doesn't make any sense otherwise. What does
> it mean to have an event in between clock edges? MyHDL doesn't have any
> concept of signal timings. If the delay means something, you need to
> model that in the analogue side; from the perspective of the RTL model,
> there is some value at some clock edge.
>
> You can model different clock domains, you just have to go the whole hog
> and run each clock domain in a different process. You'll have to define
> your time resolution and have some kind of sync barrier on each
> resolution period (using some kind of meta clock).
>
> That is, on every resolution period, each process will sync with the
> other to keep the simulations timings the same.
>
> I've written a basic example with two clocks here:
> https://gist.github.com/hgomersall/6f9268023593ca5fd9d0
>
> I'm pretty sure the synchronisation function isn't doing what it should,
> but that just needs debugging. It might be easier to use Threading, but
> I'm not sure if MyHDL is safe for that (I don't know if there is any
> global shared state).
>
> Cheers,
> Henry
>
>
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Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Josy B. <jos...@gm...>]

> OK. I went back to a project that actually has the entity written in 
MyHDL and tried to write a testbench for it. There are two issues:1. It 
"simulates" in that "<class 'myhdl._SuspendSimulation'>: Simulated 2000 
timesteps" is written to the console, but no simulation appears. It deos 
create a vcd file though which I can convert to wlf to view in modelsim. 
Just out of curiosity, even though it's not smart to trust that 
simulation, how would I automate the viewing of that vcd file so I don't 
have to go through so many steps to view the waveform?

I do everything in Eclipse: Pydev for Python/MyHDL development, Sigasi for 
inspecting the VHDL code (and now and then write some new VHDL ...) and 
Impulse (toem.de) to view the vcd file. Other extensions/plugins for Lua, 
C/C++, Tcl, Markdown, ...

Regards,


Josy

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

<snip>
> 2. The next problem is "signal is not driven/read" warnings:
> ** ToVHDLWarning: Signal is not driven: s_wait_req_from_sdram
> ** ToVHDLWarning: Signal is driven but not read: s_vga_cache_miss
<snip>

The warnings are benign?

I didn't dig through all your stuff but this example
might help:
https://gist.github.com/cfelton/0b12dd0725eb2decbd2a

This would attempt to test:
https://github.com/xesscorp/VHDL_Lib/blob/master/buttonDebouncer.vhd

Note, it uses the `vhdl_instance` instead of `vhdl_code`.
The `vhdl_instance` is not fully tested (?) there might
be some issues but it has been used in the past successfully.

Regards,
Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

OK. I went back to a project that actually has the entity written in MyHDL
and tried to write a testbench for it.
There are two issues:
1. It "simulates" in that "<class 'myhdl._SuspendSimulation'>: Simulated
2000 timesteps" is written to the console, but no simulation appears. It
deos create a vcd file though which I can convert to wlf to view in
modelsim. Just out of curiosity, even though it's not smart to trust that
simulation, how would I automate the viewing of that vcd file so I don't
have to go through so many steps to view the waveform?

2. The next problem is "signal is not driven/read" warnings:
** ToVHDLWarning: Signal is not driven: s_wait_req_from_sdram
** ToVHDLWarning: Signal is driven but not read: s_vga_cache_miss
** ToVHDLWarning: Signal is not driven: s_data_in_from_sdram
** ToVHDLWarning: Signal is not driven: s_addr_req_by_vga
** ToVHDLWarning: Signal is driven but not read: s_addr_req_to_sdram
** ToVHDLWarning: Signal is driven but not read: s_newest_stored_addr
** ToVHDLWarning: Signal is driven but not read: s_read_req_to_sdram
** ToVHDLWarning: Signal is not driven: s_read_request_from_vga
** ToVHDLWarning: Signal is not driven: s_valid_from_sdram
** ToVHDLWarning: Signal is driven but not read: s_oldest_stored_addr
** ToVHDLWarning: Signal is driven but not read: s_data_out_to_vga
ironically this time it actually converted what I wrote instead of removing
most of my logic in the conversion. You definitely can't just put
"s_clk.driven = True" or "s_oldest_stored_addr.read = True" somewhere
because it will complain that bool doesn't not have that attribute. What
would get rid of those warnings?

On Wed, Apr 8, 2015 at 9:58 PM, Tony Stark <34f...@gm...> wrote:

> >>The only job tasked to MyHDL is to generate the VHDL version
> >> of the testbench described using the MYHDL language.
> >
> >That is complete nonsense. Change your goal and use MyHDL for simulation
> >in the first place, otherwise stop wasting everbody's time.
>
> I read the page you linked to. It is the second time I've read it. I also
> read a few other topics in search of an answer. I agree with the concept of
> a simulation-first design cycle.
>
>  I'm guessing the message you were trying to send is that MyHDL uses the
> simulation to verify that the generated code is correct. That's great but
> that's beside the issue here. Let me explain the issue again in another
> way. I want to use Quartus II for synthesis, ModelSim SE for simulation,
> MyHDL only as a possible answer to faster VHDL generation, and Sigasi for
> the final corrections and touch-up. In order to do that, MyHDL needs to be
> able to not only generate the VHDL code for a normal entity, but also the
> testbench for the top level entity which is part of a huge VHDL project
> that it is not aware of. The reason this should be perfectly fine is
> because all it has to do with the inherited entity is spit out the port
> map. It doesn't need any knowledge of the entity that has been instantiated
> since all it is required to do is generate VHDL, not simulate it.
>
> To put it in another perspective, lets say I do it the way the design of
> MyHDL is pushing me towards. Lets say I have some huge project already
> written in VHDL. I want to write the testbench for the top level entity
> using MyHDL because I hope that the process of writing the code will be
> faster this way. Now there's a problem. MyHDL appears to be designed in
> such a way that I am forced to write the code for the entity I am trying to
> test to get the VHDL testbench to be generated correctly. Now that's a
> problem because now I'm wasting time possibly rewriting the whole project
> in MyHDL when all I ever wanted was just to generate a testbench quickly.
> Now the potential efficiency advantage of MyHDL has just been ruined. Do
> you see the problem here?
>
> On Wed, Apr 8, 2015 at 4:12 PM, Tony Stark <34f...@gm...> wrote:
>
>> >> I'm trying to generate a testbench of an entity the MyHDL doesn't know
>> >> about and I'm getting a s"ignal not driven" warning along with the
>> >> problem of the rest of the signals not showing up in the conversion.
>> >
>> >That's because you need to instruct the converter that certain signals
>> >are driven because they can't be inferred.
>> >
>> >I also suspect that your code as written will not do what you want it to
>> >do.
>> >
>> >I imagine you're trying to generate the stimuli in myhdl to drive your
>> >VHDL test bench. right?
>> >
>> >For the device-under-test, you need to create a new factory function
>> >(which in your case was called top_level), and set the vhdl_code
>> >attribute of that function. You will then need to create a dummy
>> >instance as part of that.
>> >
>> >Then tell the converter how the signals are handled (e.g. driven or
>> read).
>>
>> I understand what you're saying but it's not what I'm after. I must not
>> be explaining myself well. Let me try it again:
>> Image that you have created a vhdl entity called "top_level" which was
>> written *only in VHDL* (not written in MyHDL). Now imagine you want to
>> write a testbench for it, but instead of writing it in VHDL like you did
>> with "top_level", you want to save some time and write the testbench using
>> MyHDL instead. That's your goal. Now MyHDL will be upset because it doesn't
>> know about "top_level" (since it wasn't written in MyHDL). That's ok and
>> should be bypassed somehow because you aren't planning on using MyHDL for
>> simulation anyway. You want to use ModelSim instead. The only job tasked to
>> MyHDL is to generate the VHDL version of the testbench described using the
>> MYHDL language.
>>
>> The code posted in my previous email converts without error but the
>> signals and process are left out. There shouldn't be anything more than
>> just a very minor edit to force it to leave them in there correct?
>>
>> On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...> wrote:
>>
>>> I'm trying to generate a testbench of an entity the MyHDL doesn't know
>>> about and I'm getting a s"ignal not driven" warning along with the problem
>>> of the rest of the signals not showing up in the conversion.
>>>
>>> ***********************************  MyHDL
>>> *****************************************
>>>
>>> from myhdl import *
>>>
>>> def top_level_tb():
>>>     s_sw = intbv(0)[10]
>>>     s_clk = Signal(bool(0))
>>>     s_btn = intbv(0)[3]
>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>     done = Signal(bool(0))
>>>
>>>     top_level_tb.vhdl_code = """
>>>     UUT : entity work.top_level port map(
>>>             i_sw                      => s_sw,
>>>             i_clk                     => s_clk,
>>>             i_btn                     => s_btn,
>>>             o_seven_segment_display_1 => s_seven_segment_display_1,
>>>             o_seven_segment_display_0 => s_seven_segment_display_0,
>>>             o_seven_segment_display_3 => s_seven_segment_display_3,
>>>             o_seven_segment_display_2 => s_seven_segment_display_2
>>>         );
>>>     """
>>>
>>>
>>>     @always(delay(10))
>>>     def clkGenerator():
>>>         s_clk.next = not s_clk
>>>
>>>     @always(s_clk.posedge)
>>>     def stimulus():
>>>         s_btn[2].next = 1
>>>         delay(40)
>>>         s_btn[2].next = 0
>>>         delay(680)
>>>         self.assertEqual(s_seven_segment_display_1, "0100100")
>>>         self.assertEqual(s_seven_segment_display_0, "0100100")
>>>         delay(680)
>>>         done = 1
>>>
>>>     return clkGenerator, stimulus
>>>
>>> toVHDL(top_level_tb)
>>>
>>>
>>> **************************************  VHDL
>>> ************************************
>>>
>>>
>>>
>>> library IEEE;
>>> use IEEE.std_logic_1164.all;
>>> use IEEE.numeric_std.all;
>>> use std.textio.all;
>>>
>>> use work.pck_myhdl_081.all;
>>>
>>> entity top_level_tb is
>>> end entity top_level_tb;
>>>
>>>
>>> architecture MyHDL of top_level_tb is
>>>
>>>
>>>
>>>
>>>
>>> signal s_clk: std_logic;
>>>
>>> begin
>>>
>>> s_clk <= '0';
>>>
>>>
>>>
>>>
>>>     UUT : entity work.top_level port map(
>>>             i_sw                      => s_sw,
>>>             i_clk                     => s_clk,
>>>             i_btn                     => s_btn,
>>>             o_seven_segment_display_1 => s_seven_segment_display_1,
>>>             o_seven_segment_display_0 => s_seven_segment_display_0,
>>>             o_seven_segment_display_3 => s_seven_segment_display_3,
>>>             o_seven_segment_display_2 => s_seven_segment_display_2
>>>         );
>>>
>>> end architecture MyHDL;
>>>
>>> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...> wrote:
>>>
>>>> I don't understand how the vhdl_code attribute should be used in my
>>>> case.
>>>> This simple code will generate a VHDL testbench if it weren't for the
>>>> problem of MyHDL not knowing what top_level() is.
>>>>
>>>> def top_level_tb():
>>>>     s_signalA = intbv(0)[10]
>>>>     s_clk = Signal(bool(0))
>>>>
>>>>     # Here is where I need to somehow
>>>>     # tell MyHDL to ignore the fact that it doesn't know about
>>>> top_level()
>>>>     top_level_instance = top_level(s_signalA, s_clk)
>>>>
>>>>     @always(delay(10))
>>>>     def clkGenerator():
>>>>         s_clk.next = not s_clk
>>>>
>>>>     @always(s_clk.posedge)
>>>>     def stimulus():
>>>>         # todo ....
>>>>
>>>>     return top_level_instance, clkGenerator, stimulus
>>>>
>>>> toVHDL(top_level_tb)
>>>>
>>>> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...>
>>>> wrote:
>>>>
>>>>>
>>>>> Right, I've seen examples like that but what I'm trying to do is
>>>>> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>>>> an entity not written in MyHDL, for use in modelsim. The testbench is for
>>>>> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
>>>>> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
>>>>> to exist. In the previous email I made a fake one to try to get past that
>>>>> error. MyHDL doesn't actually need to know about it since it is not
>>>>> actually testing it. All MyHDL will be doing is generating the entity
>>>>> instance declaration like the one below so it doesn't need to know about
>>>>> TimeCount() anyway.
>>>>>
>>>>> UUT : entity work.time_count
>>>>>         port map(
>>>>>             tens               => s_tens,
>>>>>             ones            => s_ones,
>>>>>             tenths          => s_tenths,
>>>>>             startstop      => s_startstop,
>>>>>             reset              => s_reset,
>>>>>             clock             => s_clock
>>>>>         );
>>>>>
>>>>> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>>>> an entity not written in MyHDL, for use in modelsim. How do I do that?
>>>>> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>>>>>
>>>>>> >	Well, the problem there is a python problem. You're trying to import
>>>>>> >	from a module that doesn't exist, or at least not in your path. Again, I
>>>>>> >	suggest that your problems so far are predominantly a lack of
>>>>>> >	understanding of the way Python works, rather than MyHDL.
>>>>>> >	
>>>>>> >	Beyond that, I don't understand what you're trying to achieve.
>>>>>> >	
>>>>>> >	Cheers,
>>>>>> >	
>>>>>> >	Henry
>>>>>>
>>>>>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>>>>>
>>>>>> ***************************** VHDL *****************************************
>>>>>> library ieee;
>>>>>> use ieee.std_logic_1164.all;
>>>>>>
>>>>>> entity top_level_tb is
>>>>>> end top_level_tb;
>>>>>>
>>>>>> architecture tb of top_level_tb is
>>>>>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>>>>>> 	signal s_clk                     			: std_logic                   			:= '0';
>>>>>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>>>>>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_done                    			: std_logic                    			:= '0';
>>>>>> begin
>>>>>> 	UUT : entity work.top_level port map(
>>>>>> 			i_sw                  				=> s_sw,
>>>>>> 			i_clk                   				=> s_clk,
>>>>>> 			i_btn                   				=> s_btn,
>>>>>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>>>>>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>>>>>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>>>>>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>>>>>> 		);
>>>>>>
>>>>>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>>>>>
>>>>>> 	process
>>>>>> 	begin
>>>>>> 		wait for 10 ns;
>>>>>> 		s_btn(2) <= '0';                 -- reset on
>>>>>> 		wait for 20 ns;
>>>>>> 		s_btn(2) <= '1';                 -- reset off
>>>>>>
>>>>>> 		-- <tests to be added here>
>>>>>> 		
>>>>>> 		--	s_done <= '1';
>>>>>> 		-- wait;
>>>>>> 	end process;
>>>>>>
>>>>>> end tb;
>>>>>>
>>>>>> ***************************** MyHDL ******************************************
>>>>>>
>>>>>> from myhdl import *
>>>>>>
>>>>>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>>>>>> def top_level(
>>>>>>         i_sw,
>>>>>>         i_clk,
>>>>>>         i_btn,
>>>>>>         o_seven_segment_display_1,
>>>>>>         o_seven_segment_display_0,
>>>>>>         o_seven_segment_display_3,
>>>>>>         o_seven_segment_display_2
>>>>>> ):
>>>>>>     s_rst = ResetSignal(0, active=0, async=True)
>>>>>>
>>>>>>     @always_seq(i_clk.posedge, reset=s_rst)
>>>>>>     def main_process():
>>>>>>         o_seven_segment_display_1 = 0
>>>>>>
>>>>>>     return main_process
>>>>>>
>>>>>> # actual entity of interest
>>>>>> def top_level_tb():
>>>>>>     s_sw = intbv(0)[10]
>>>>>>     s_clk = Signal(bool(0))
>>>>>>     s_btn = intbv(0)[3]
>>>>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>>>>
>>>>>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>>>>>
>>>>>>     @always(delay(10))
>>>>>>     def clkGenerator():
>>>>>>         s_clk.next = not s_clk
>>>>>>
>>>>>>     @always(s_clk.posedge)
>>>>>>     def stimulus():
>>>>>> 		
>>>>>> 		# <more tests to be added here>
>>>>>> 		
>>>>>>         s_btn[2].next = 0
>>>>>>
>>>>>>     return top_level_instance, clkGenerator, stimulus
>>>>>>
>>>>>> toVHDL(top_level_tb)
>>>>>>
>>>>>>
>>>>>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...>
>>>>>> wrote:
>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> I'm getting an error likely due to to a std_logic_vector being much
>>>>>>> monger than myHDL was intended to handle.
>>>>>>>
>>>>>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>>>>>
>>>>>>> I actually converted VHDL code to pyhton and want to continue
>>>>>>> development of this fifo-like-buffer entity using python, but I need to get
>>>>>>> around this error first..
>>>>>>> The reason the array is so large is because I want to go through it
>>>>>>> in one clock cycle if needed. It represents 20, 23-bit addresses.
>>>>>>>
>>>>>>> The code is attached. please advise.
>>>>>>>
>>>>>>> Thanks,
>>>>>>> David
>>>>>>>
>>>>>>
>>>>>>
>>>>
>>>
>>
>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

On 4/9/2015 1:50 AM, Chris Higgs wrote:
>> On 09 April 2015 at 03:31 Christopher Felton <chr...@gm...> wrote:
>>
>> I believe the other might have issues with Modelsim
>> VHDL Cosim because Modelsim only support FLI for a
>> foreign interface and not PLI/VPI (unless that has
>> changed recently), In general Verilog Cosim is
>> support and VHDL is tricky because only a couple
>> simulators use a standard foreign interface (VHPI).
>
> Cadence, Synopsys and Aldec support VHPI; it's only
> Mentor who stubbornly refuse to implement the standard.
<snip>
>
> Sticking with MyHDL, another option would be to wrap your
> top-level in Verilog and then co-simulate using VPI.
>

Someone started the MyHDL FLI implementation, if the
OP wants the Cosimulation route we can possibly dig
up this code.

Then the OP can use convertible testbenches, and/or
Cosimulation.

Regards,
Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Jan D. <ja...@ja...>]

On 04/09/2015 03:58 AM, Tony Stark wrote:
>>> The only job tasked to MyHDL is to generate the VHDL version of
>>> the testbench described using the MYHDL language.
>>
>> That is complete nonsense. Change your goal and use MyHDL for
>> simulation in the first place, otherwise stop wasting everbody's
>> time.
>
> I read the page you linked to. It is the second time I've read it. I
> also read a few other topics in search of an answer. I agree with the
> concept of a simulation-first design cycle.
>
> I'm guessing the message you were trying to send is that MyHDL uses
> the simulation to verify that the generated code is correct.

No, that's not what I am saying and it is exactly the issue.
The point is that you have to verify/run the *source* code in
a Python environment to make sure it is meaningful.


Let me explain the issue
> again in another way. I want to use Quartus II for synthesis,
> ModelSim SE for simulation, MyHDL only as a possible answer to faster
> VHDL generation, and Sigasi for the final corrections and touch-up.
> In order to do that, MyHDL needs to be able to not only generate the
> VHDL code for a normal entity, but also the testbench for the top
> level entity which is part of a huge VHDL project that it is not
> aware of. The reason this should be perfectly fine is because all it
> has to do with the inherited entity is spit out the port map. It
> doesn't need any knowledge of the entity that has been instantiated
> since all it is required to do is generate VHDL, not simulate it.
>
> To put it in another perspective, lets say I do it the way the design
> of MyHDL is pushing me towards. Lets say I have some huge project
> already written in VHDL. I want to write the testbench for the top
> level entity using MyHDL because I hope that the process of writing
> the code will be faster this way. Now there's a problem. MyHDL
> appears to be designed in such a way that I am forced to write the
> code for the entity I am trying to test to get the VHDL testbench to
> be generated correctly. Now that's a problem because now I'm wasting
> time possibly rewriting the whole project in MyHDL when all I ever
> wanted was just to generate a testbench quickly. Now the potential
> efficiency advantage of MyHDL has just been ruined. Do you see the
> problem here?
>
> On Wed, Apr 8, 2015 at 4:12 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>>> I'm trying to generate a testbench of an entity the MyHDL doesn't
>>> know about and I'm getting a s"ignal not driven" warning along
>>> with the problem of the rest of the signals not showing up in the
>>> conversion.
>>
>> That's because you need to instruct the converter that certain
>> signals are driven because they can't be inferred.
>>
>> I also suspect that your code as written will not do what you want
>> it to do.
>>
>> I imagine you're trying to generate the stimuli in myhdl to drive
>> your VHDL test bench. right?
>>
>> For the device-under-test, you need to create a new factory
>> function (which in your case was called top_level), and set the
>> vhdl_code attribute of that function. You will then need to create
>> a dummy instance as part of that.
>>
>> Then tell the converter how the signals are handled (e.g. driven or
>> read).
>
> I understand what you're saying but it's not what I'm after. I must
> not be explaining myself well. Let me try it again: Image that you
> have created a vhdl entity called "top_level" which was written *only
> in VHDL* (not written in MyHDL). Now imagine you want to write a
> testbench for it, but instead of writing it in VHDL like you did with
> "top_level", you want to save some time and write the testbench using
> MyHDL instead. That's your goal. Now MyHDL will be upset because it
> doesn't know about "top_level" (since it wasn't written in MyHDL).
> That's ok and should be bypassed somehow because you aren't planning
> on using MyHDL for simulation anyway. You want to use ModelSim
> instead. The only job tasked to MyHDL is to generate the VHDL version
> of the testbench described using the MYHDL language.
>
> The code posted in my previous email converts without error but the
> signals and process are left out. There shouldn't be anything more
> than just a very minor edit to force it to leave them in there
> correct?
>
> On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> I'm trying to generate a testbench of an entity the MyHDL doesn't
> know about and I'm getting a s"ignal not driven" warning along with
> the problem of the rest of the signals not showing up in the
> conversion.
>
> ***********************************  MyHDL
> *****************************************
>
> from myhdl import *
>
> def top_level_tb(): s_sw = intbv(0)[10] s_clk = Signal(bool(0)) s_btn
> = intbv(0)[3] s_seven_segment_display_1 = intbv(0)[7]
> s_seven_segment_display_0 = intbv(0)[7] s_seven_segment_display_3 =
> intbv(0)[7] s_seven_segment_display_2 = intbv(0)[7] done =
> Signal(bool(0))
>
> top_level_tb.vhdl_code = """ UUT : entity work.top_level port map(
> i_sw                      => s_sw, i_clk                     =>
> s_clk, i_btn                     => s_btn, o_seven_segment_display_1
> => s_seven_segment_display_1, o_seven_segment_display_0 =>
> s_seven_segment_display_0, o_seven_segment_display_3 =>
> s_seven_segment_display_3, o_seven_segment_display_2 =>
> s_seven_segment_display_2 ); """
>
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus(): s_btn[2].next = 1 delay(40)
> s_btn[2].next = 0 delay(680)
> self.assertEqual(s_seven_segment_display_1, "0100100")
> self.assertEqual(s_seven_segment_display_0, "0100100") delay(680)
> done = 1
>
> return clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> **************************************  VHDL
> ************************************
>
>
>
> library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
> use std.textio.all;
>
> use work.pck_myhdl_081.all;
>
> entity top_level_tb is end entity top_level_tb;
>
>
> architecture MyHDL of top_level_tb is
>
>
>
>
>
> signal s_clk: std_logic;
>
> begin
>
> s_clk <= '0';
>
>
>
>
> UUT : entity work.top_level port map( i_sw                      =>
> s_sw, i_clk                     => s_clk, i_btn
> => s_btn, o_seven_segment_display_1 => s_seven_segment_display_1,
> o_seven_segment_display_0 => s_seven_segment_display_0,
> o_seven_segment_display_3 => s_seven_segment_display_3,
> o_seven_segment_display_2 => s_seven_segment_display_2 );
>
> end architecture MyHDL;
>
> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> I don't understand how the vhdl_code attribute should be used in my
> case. This simple code will generate a VHDL testbench if it weren't
> for the problem of MyHDL not knowing what top_level() is.
>
> def top_level_tb(): s_signalA = intbv(0)[10] s_clk = Signal(bool(0))
>
> # Here is where I need to somehow # tell MyHDL to ignore the fact
> that it doesn't know about top_level() top_level_instance =
> top_level(s_signalA, s_clk)
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus(): # todo ....
>
> return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>
> Right, I've seen examples like that but what I'm trying to do is
> different. I'm trying to us MyHDL only to generate a testbench in
> VHDL, for an entity not written in MyHDL, for use in modelsim. The
> testbench is for an entity that MyHDL doesn't know about so "dut =
> TimeCount(tens, ones, tenths, startstop, reset, clock)" isn't valid
> since TimeCount() isn't going to exist. In the previous email I made
> a fake one to try to get past that error. MyHDL doesn't actually need
> to know about it since it is not actually testing it. All MyHDL will
> be doing is generating the entity instance declaration like the one
> below so it doesn't need to know about TimeCount() anyway.
>
> UUT : entity work.time_count port map( tens               => s_tens,
> ones            => s_ones, tenths          => s_tenths, startstop
> => s_startstop, reset              => s_reset, clock             =>
> s_clock );
>
> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL,
> for an entity not written in MyHDL, for use in modelsim. How do I do
> that?
>
> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>> Well, the problem there is a python problem. You're trying to
>> import from a module that doesn't exist, or at least not in your
>> path. Again, I suggest that your problems so far are predominantly
>> a lack of understanding of the way Python works, rather than
>> MyHDL.  Beyond that, I don't understand what you're trying to
>> achieve.  Cheers,  Henry
>
> Alright, I've made a little progress on this but still nothing useful
> yet. The VHDL code I've written below is what I want to have MyHDL
> generate. The Python code following that is my attempt at it. It
> generates code without error but it's not nearly useful yet.
>
> ***************************** VHDL
> ***************************************** library ieee; use
> ieee.std_logic_1164.all;
>
> entity top_level_tb is end top_level_tb;
>
> architecture tb of top_level_tb is signal s_sw
> : std_logic_vector(9 downto 0) 	:= (others => '0'); signal s_clk
> : std_logic                   			:= '0'; signal s_btn
> : std_logic_vector(2 downto 0) 	:= (others => '1'); signal
> s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others
> => '0'); signal s_seven_segment_display_0 	: std_logic_vector(6
> downto 0) 	:= (others => '0'); signal s_seven_segment_display_3 	:
> std_logic_vector(6 downto 0) 	:= (others => '0'); signal
> s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others
> => '0'); signal s_done                    			: std_logic
> := '0'; begin UUT : entity work.top_level port map( i_sw
> => s_sw, i_clk                   				=> s_clk, i_btn
> => s_btn, o_seven_segment_display_1 	=> s_seven_segment_display_1,
> o_seven_segment_display_0 	=> s_seven_segment_display_0,
> o_seven_segment_display_3 	=> s_seven_segment_display_3,
> o_seven_segment_display_2 	=> s_seven_segment_display_2 );
>
> s_clk <= not s_clk and not s_done after 10 ns;
>
> process begin wait for 10 ns; s_btn(2) <= '0';                 --
> reset on wait for 20 ns; s_btn(2) <= '1';                 -- reset
> off
>
> -- <tests to be added here>  --	s_done <= '1'; -- wait; end process;
>
> end tb;
>
> ***************************** MyHDL
> ******************************************
>
> from myhdl import *
>
> # fake entity & fake process created in an attempt to get MyHDL to
> stop complaining about not knowing what top_level() was def
> top_level( i_sw, i_clk, i_btn, o_seven_segment_display_1,
> o_seven_segment_display_0, o_seven_segment_display_3,
> o_seven_segment_display_2 ): s_rst = ResetSignal(0, active=0,
> async=True)
>
> @always_seq(i_clk.posedge, reset=s_rst) def main_process():
> o_seven_segment_display_1 = 0
>
> return main_process
>
> # actual entity of interest def top_level_tb(): s_sw = intbv(0)[10]
> s_clk = Signal(bool(0)) s_btn = intbv(0)[3] s_seven_segment_display_1
> = intbv(0)[7] s_seven_segment_display_0 = intbv(0)[7]
> s_seven_segment_display_3 = intbv(0)[7] s_seven_segment_display_2 =
> intbv(0)[7]
>
> top_level_instance = top_level(s_sw, s_clk, s_btn,
> s_seven_segment_display_1, s_seven_segment_display_0,
> s_seven_segment_display_3, s_seven_segment_display_2)
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus():  # <more tests to be added
> here>  s_btn[2].next = 0
>
> return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much
> monger than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0],
> most_recent_addr_req_to_sdram -1)
>
> I actually converted VHDL code to pyhton and want to continue
> development of this fifo-like-buffer entity using python, but I need
> to get around this error first.. The reason the array is so large is
> because I want to go through it in one clock cycle if needed. It
> represents 20, 23-bit addresses.
>
> The code is attached. please advise.
>
> Thanks, David
>
>
>
>
>
>
>
>
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>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com