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Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Jan D. <ja...@ja...>]

On 04/09/2015 04:14 AM, Jeremy Herbert wrote:
> Hello all,
>
> I'm not qualified to weigh in on any of this, just a note:
>
> Tony, you should perhaps take a look at cocotb. It's in the same
> spirit as myhdl, but specifically for the case of verilog/vhdl for
> the design and Python for the test bench. I use it with modelsim. It
> doesn't generate code however.

That is besides the point here. MyHDL also offers cosimulation
like cocotb (admittedly less developed probably) plus additional
options like convertible testbenches.

The point is that in *any* methdodology, the code should
be debugged by running it / simulating it in a Python
environment.

>
> Thanks, Jeremy On Thu, 9 Apr 2015 at 11:58 am Tony Stark
> <34f...@gm... <mailto:34f...@gm...>> wrote:
>
>>> The only job tasked to MyHDL is to generate the VHDL version of
>>> the testbench described using the MYHDL language.
>>
>> That is complete nonsense. Change your goal and use MyHDL for
>> simulation in the first place, otherwise stop wasting everbody's
>> time.
>
> I read the page you linked to. It is the second time I've read it. I
> also read a few other topics in search of an answer. I agree with the
> concept of a simulation-first design cycle.
>
> I'm guessing the message you were trying to send is that MyHDL uses
> the simulation to verify that the generated code is correct. That's
> great but that's beside the issue here. Let me explain the issue
> again in another way. I want to use Quartus II for synthesis,
> ModelSim SE for simulation, MyHDL only as a possible answer to faster
> VHDL generation, and Sigasi for the final corrections and touch-up.
> In order to do that, MyHDL needs to be able to not only generate the
> VHDL code for a normal entity, but also the testbench for the top
> level entity which is part of a huge VHDL project that it is not
> aware of. The reason this should be perfectly fine is because all it
> has to do with the inherited entity is spit out the port map. It
> doesn't need any knowledge of the entity that has been instantiated
> since all it is required to do is generate VHDL, not simulate it.
>
> To put it in another perspective, lets say I do it the way the design
> of MyHDL is pushing me towards. Lets say I have some huge project
> already written in VHDL. I want to write the testbench for the top
> level entity using MyHDL because I hope that the process of writing
> the code will be faster this way. Now there's a problem. MyHDL
> appears to be designed in such a way that I am forced to write the
> code for the entity I am trying to test to get the VHDL testbench to
> be generated correctly. Now that's a problem because now I'm wasting
> time possibly rewriting the whole project in MyHDL when all I ever
> wanted was just to generate a testbench quickly. Now the potential
> efficiency advantage of MyHDL has just been ruined. Do you see the
> problem here?
>
> On Wed, Apr 8, 2015 at 4:12 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>>> I'm trying to generate a testbench of an entity the MyHDL doesn't
>>> know about and I'm getting a s"ignal not driven" warning along
>>> with the problem of the rest of the signals not showing up in the
>>> conversion.
>>
>> That's because you need to instruct the converter that certain
>> signals are driven because they can't be inferred.
>>
>> I also suspect that your code as written will not do what you want
>> it to do.
>>
>> I imagine you're trying to generate the stimuli in myhdl to drive
>> your VHDL test bench. right?
>>
>> For the device-under-test, you need to create a new factory
>> function (which in your case was called top_level), and set the
>> vhdl_code attribute of that function. You will then need to create
>> a dummy instance as part of that.
>>
>> Then tell the converter how the signals are handled (e.g. driven or
>> read).
>
> I understand what you're saying but it's not what I'm after. I must
> not be explaining myself well. Let me try it again: Image that you
> have created a vhdl entity called "top_level" which was written *only
> in VHDL* (not written in MyHDL). Now imagine you want to write a
> testbench for it, but instead of writing it in VHDL like you did with
> "top_level", you want to save some time and write the testbench using
> MyHDL instead. That's your goal. Now MyHDL will be upset because it
> doesn't know about "top_level" (since it wasn't written in MyHDL).
> That's ok and should be bypassed somehow because you aren't planning
> on using MyHDL for simulation anyway. You want to use ModelSim
> instead. The only job tasked to MyHDL is to generate the VHDL version
> of the testbench described using the MYHDL language.
>
> The code posted in my previous email converts without error but the
> signals and process are left out. There shouldn't be anything more
> than just a very minor edit to force it to leave them in there
> correct?
>
> On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> I'm trying to generate a testbench of an entity the MyHDL doesn't
> know about and I'm getting a s"ignal not driven" warning along with
> the problem of the rest of the signals not showing up in the
> conversion.
>
> ***********************************  MyHDL
> *****************************************
>
> from myhdl import *
>
> def top_level_tb(): s_sw = intbv(0)[10] s_clk = Signal(bool(0)) s_btn
> = intbv(0)[3] s_seven_segment_display_1 = intbv(0)[7]
> s_seven_segment_display_0 = intbv(0)[7] s_seven_segment_display_3 =
> intbv(0)[7] s_seven_segment_display_2 = intbv(0)[7] done =
> Signal(bool(0))
>
> top_level_tb.vhdl_code = """ UUT : entity work.top_level port map(
> i_sw                      => s_sw, i_clk                     =>
> s_clk, i_btn                     => s_btn, o_seven_segment_display_1
> => s_seven_segment_display_1, o_seven_segment_display_0 =>
> s_seven_segment_display_0, o_seven_segment_display_3 =>
> s_seven_segment_display_3, o_seven_segment_display_2 =>
> s_seven_segment_display_2 ); """
>
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus(): s_btn[2].next = 1 delay(40)
> s_btn[2].next = 0 delay(680)
> self.assertEqual(s_seven_segment_display_1, "0100100")
> self.assertEqual(s_seven_segment_display_0, "0100100") delay(680)
> done = 1
>
> return clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> **************************************  VHDL
> ************************************
>
>
>
> library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;
> use std.textio.all;
>
> use work.pck_myhdl_081.all;
>
> entity top_level_tb is end entity top_level_tb;
>
>
> architecture MyHDL of top_level_tb is
>
>
>
>
>
> signal s_clk: std_logic;
>
> begin
>
> s_clk <= '0';
>
>
>
>
> UUT : entity work.top_level port map( i_sw                      =>
> s_sw, i_clk                     => s_clk, i_btn
> => s_btn, o_seven_segment_display_1 => s_seven_segment_display_1,
> o_seven_segment_display_0 => s_seven_segment_display_0,
> o_seven_segment_display_3 => s_seven_segment_display_3,
> o_seven_segment_display_2 => s_seven_segment_display_2 );
>
> end architecture MyHDL;
>
> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> I don't understand how the vhdl_code attribute should be used in my
> case. This simple code will generate a VHDL testbench if it weren't
> for the problem of MyHDL not knowing what top_level() is.
>
> def top_level_tb(): s_signalA = intbv(0)[10] s_clk = Signal(bool(0))
>
> # Here is where I need to somehow # tell MyHDL to ignore the fact
> that it doesn't know about top_level() top_level_instance =
> top_level(s_signalA, s_clk)
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus(): # todo ....
>
> return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>
> Right, I've seen examples like that but what I'm trying to do is
> different. I'm trying to us MyHDL only to generate a testbench in
> VHDL, for an entity not written in MyHDL, for use in modelsim. The
> testbench is for an entity that MyHDL doesn't know about so "dut =
> TimeCount(tens, ones, tenths, startstop, reset, clock)" isn't valid
> since TimeCount() isn't going to exist. In the previous email I made
> a fake one to try to get past that error. MyHDL doesn't actually need
> to know about it since it is not actually testing it. All MyHDL will
> be doing is generating the entity instance declaration like the one
> below so it doesn't need to know about TimeCount() anyway.
>
> UUT : entity work.time_count port map( tens               => s_tens,
> ones            => s_ones, tenths          => s_tenths, startstop
> => s_startstop, reset              => s_reset, clock             =>
> s_clock );
>
> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL,
> for an entity not written in MyHDL, for use in modelsim. How do I do
> that?
>
> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
>> Well, the problem there is a python problem. You're trying to
>> import from a module that doesn't exist, or at least not in your
>> path. Again, I suggest that your problems so far are predominantly
>> a lack of understanding of the way Python works, rather than
>> MyHDL.  Beyond that, I don't understand what you're trying to
>> achieve.  Cheers,  Henry
>
> Alright, I've made a little progress on this but still nothing useful
> yet. The VHDL code I've written below is what I want to have MyHDL
> generate. The Python code following that is my attempt at it. It
> generates code without error but it's not nearly useful yet.
>
> ***************************** VHDL
> ***************************************** library ieee; use
> ieee.std_logic_1164.all;
>
> entity top_level_tb is end top_level_tb;
>
> architecture tb of top_level_tb is signal s_sw
> : std_logic_vector(9 downto 0) 	:= (others => '0'); signal s_clk
> : std_logic                   			:= '0'; signal s_btn
> : std_logic_vector(2 downto 0) 	:= (others => '1'); signal
> s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others
> => '0'); signal s_seven_segment_display_0 	: std_logic_vector(6
> downto 0) 	:= (others => '0'); signal s_seven_segment_display_3 	:
> std_logic_vector(6 downto 0) 	:= (others => '0'); signal
> s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others
> => '0'); signal s_done                    			: std_logic
> := '0'; begin UUT : entity work.top_level port map( i_sw
> => s_sw, i_clk                   				=> s_clk, i_btn
> => s_btn, o_seven_segment_display_1 	=> s_seven_segment_display_1,
> o_seven_segment_display_0 	=> s_seven_segment_display_0,
> o_seven_segment_display_3 	=> s_seven_segment_display_3,
> o_seven_segment_display_2 	=> s_seven_segment_display_2 );
>
> s_clk <= not s_clk and not s_done after 10 ns;
>
> process begin wait for 10 ns; s_btn(2) <= '0';                 --
> reset on wait for 20 ns; s_btn(2) <= '1';                 -- reset
> off
>
> -- <tests to be added here>  --	s_done <= '1'; -- wait; end process;
>
> end tb;
>
> ***************************** MyHDL
> ******************************************
>
> from myhdl import *
>
> # fake entity & fake process created in an attempt to get MyHDL to
> stop complaining about not knowing what top_level() was def
> top_level( i_sw, i_clk, i_btn, o_seven_segment_display_1,
> o_seven_segment_display_0, o_seven_segment_display_3,
> o_seven_segment_display_2 ): s_rst = ResetSignal(0, active=0,
> async=True)
>
> @always_seq(i_clk.posedge, reset=s_rst) def main_process():
> o_seven_segment_display_1 = 0
>
> return main_process
>
> # actual entity of interest def top_level_tb(): s_sw = intbv(0)[10]
> s_clk = Signal(bool(0)) s_btn = intbv(0)[3] s_seven_segment_display_1
> = intbv(0)[7] s_seven_segment_display_0 = intbv(0)[7]
> s_seven_segment_display_3 = intbv(0)[7] s_seven_segment_display_2 =
> intbv(0)[7]
>
> top_level_instance = top_level(s_sw, s_clk, s_btn,
> s_seven_segment_display_1, s_seven_segment_display_0,
> s_seven_segment_display_3, s_seven_segment_display_2)
>
> @always(delay(10)) def clkGenerator(): s_clk.next = not s_clk
>
> @always(s_clk.posedge) def stimulus():  # <more tests to be added
> here>  s_btn[2].next = 0
>
> return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...
> <mailto:34f...@gm...>> wrote:
>
> Hi,
>
> I'm getting an error likely due to to a std_logic_vector being much
> monger than myHDL was intended to handle.
>
> addr_array.next = concat(addr_array[436:0],
> most_recent_addr_req_to_sdram -1)
>
> I actually converted VHDL code to pyhton and want to continue
> development of this fifo-like-buffer entity using python, but I need
> to get around this error first.. The reason the array is so large is
> because I want to go through it in one clock cycle if needed. It
> represents 20, 23-bit addresses.
>
> The code is attached. please advise.
>
> Thanks, David
>
>
>
>
>
>
> ------------------------------__------------------------------__------------------
>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Jan D. <ja...@ja...>]

On 04/09/2015 04:40 AM, Christopher Felton wrote:
> On 4/8/15 8:58 PM, Tony Stark wrote:
>>   >>The only job tasked to MyHDL is to generate the VHDL version
>>   >> of the testbench described using the MYHDL language.
>>   >
>>   >That is complete nonsense. Change your goal and use MyHDL for simulation
>>   >in the first place, otherwise stop wasting everbody's time.
>>
>> I read the page you linked to. It is the second time I've read it. I
>> also read a few other topics in search of an answer. I agree with the
>> concept of a simulation-first design cycle.
>>
>
> The message being conveyed is that we hear you
> and understand you.  Others have suggests possible
> routes to do what you want and Jan strongly suggested
> not to go down that path (i.e convertible testbench).

For the record, I have nothing against a convertible
testbench. But a convertible testbench is also first
debuggged through simulation in a Python environment.
This methodology is fully compatible with "Simulate first".


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Chris H. <chr...@po...>]

> On 09 April 2015 at 03:31 Christopher Felton <chr...@gm...> wrote:
>
> I believe the other might have issues with Modelsim
> VHDL Cosim because Modelsim only support FLI for a
> foreign interface and not PLI/VPI (unless that has
> changed recently), In general Verilog Cosim is
> support and VHDL is tricky because only a couple
> simulators use a standard foreign interface (VHPI).

Cadence, Synopsys and Aldec support VHPI; it's only
Mentor who stubbornly refuse to implement the standard.

Cocotb supports VHDL co-simulation in Modelsim/Questa via
the FLI. If you're happy to co-simulate Python that's one
potential route.

I would advise not converting your testbench to VHDL or
Verilog anyway as this puts onerous constraints on your
verification code.  Why not use the full power of Python?

Sticking with MyHDL, another option would be to wrap your
top-level in Verilog and then co-simulate using VPI.

Thanks,

Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 08/04/15 21:12, Tony Stark wrote:
> I understand what you're saying but it's not what I'm after. I must 
> not be explaining myself well. Let me try it again:
> Image that you have created a vhdl entity called "top_level" which was 
> written *only in VHDL* (not written in MyHDL).

Right, but you can't do that. You _need_ to wrap it, to tell MyHDL what 
the interface is.

Henry

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

On 4/8/15 8:58 PM, Tony Stark wrote:
>  >>The only job tasked to MyHDL is to generate the VHDL version
>  >> of the testbench described using the MYHDL language.
>  >
>  >That is complete nonsense. Change your goal and use MyHDL for simulation
>  >in the first place, otherwise stop wasting everbody's time.
>
> I read the page you linked to. It is the second time I've read it. I
> also read a few other topics in search of an answer. I agree with the
> concept of a simulation-first design cycle.
>

The message being conveyed is that we hear you
and understand you.  Others have suggests possible
routes to do what you want and Jan strongly suggested
not to go down that path (i.e convertible testbench).

What you want is the full power of Python for verification.
This means Python/MyHDL simulation or Cosimulation.

Here are two examples using MyHDL to stimulate/verify
Verilog designs via Cosimulation:

https://github.com/cfelton/test_jpeg
https://github.com/cfelton/test_gemac

Regards,
Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

On 4/8/15 9:14 PM, Jeremy Herbert wrote:
> Hello all,
>
> I'm not qualified to weigh in on any of this, just a note:
>
> Tony, you should perhaps take a look at cocotb. It's in the same spirit
> as myhdl, but specifically for the case of verilog/vhdl for the design
> and Python for the test bench. I use it with modelsim. It doesn't
> generate code however.

You can do the same Cosimulation with MyHDL and
better you can model/implement logic in Python
as well as verification.  The issue here would
be using Python/MyHDL as the verification code
and not convertible testbenches.

I believe the other might have issues with Modelsim
VHDL Cosim because Modelsim only support FLI for a
foreign interface and not PLI/VPI (unless that has
changed recently), In general Verilog Cosim is
support and VHDL is tricky because only a couple
simulators use a standard foreign interface (VHPI).

Regards,
Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Jeremy H. <jer...@gm...>]

Hello all,

I'm not qualified to weigh in on any of this, just a note:

Tony, you should perhaps take a look at cocotb. It's in the same spirit as
myhdl, but specifically for the case of verilog/vhdl for the design and
Python for the test bench. I use it with modelsim. It doesn't generate code
however.

Thanks,
Jeremy
On Thu, 9 Apr 2015 at 11:58 am Tony Stark <34f...@gm...> wrote:

> >>The only job tasked to MyHDL is to generate the VHDL version
> >> of the testbench described using the MYHDL language.
> >
> >That is complete nonsense. Change your goal and use MyHDL for simulation
> >in the first place, otherwise stop wasting everbody's time.
>
> I read the page you linked to. It is the second time I've read it. I also
> read a few other topics in search of an answer. I agree with the concept of
> a simulation-first design cycle.
>
>  I'm guessing the message you were trying to send is that MyHDL uses the
> simulation to verify that the generated code is correct. That's great but
> that's beside the issue here. Let me explain the issue again in another
> way. I want to use Quartus II for synthesis, ModelSim SE for simulation,
> MyHDL only as a possible answer to faster VHDL generation, and Sigasi for
> the final corrections and touch-up. In order to do that, MyHDL needs to be
> able to not only generate the VHDL code for a normal entity, but also the
> testbench for the top level entity which is part of a huge VHDL project
> that it is not aware of. The reason this should be perfectly fine is
> because all it has to do with the inherited entity is spit out the port
> map. It doesn't need any knowledge of the entity that has been instantiated
> since all it is required to do is generate VHDL, not simulate it.
>
> To put it in another perspective, lets say I do it the way the design of
> MyHDL is pushing me towards. Lets say I have some huge project already
> written in VHDL. I want to write the testbench for the top level entity
> using MyHDL because I hope that the process of writing the code will be
> faster this way. Now there's a problem. MyHDL appears to be designed in
> such a way that I am forced to write the code for the entity I am trying to
> test to get the VHDL testbench to be generated correctly. Now that's a
> problem because now I'm wasting time possibly rewriting the whole project
> in MyHDL when all I ever wanted was just to generate a testbench quickly.
> Now the potential efficiency advantage of MyHDL has just been ruined. Do
> you see the problem here?
>
> On Wed, Apr 8, 2015 at 4:12 PM, Tony Stark <34f...@gm...> wrote:
>
>> >> I'm trying to generate a testbench of an entity the MyHDL doesn't know
>> >> about and I'm getting a s"ignal not driven" warning along with the
>> >> problem of the rest of the signals not showing up in the conversion.
>> >
>> >That's because you need to instruct the converter that certain signals
>> >are driven because they can't be inferred.
>> >
>> >I also suspect that your code as written will not do what you want it to
>> >do.
>> >
>> >I imagine you're trying to generate the stimuli in myhdl to drive your
>> >VHDL test bench. right?
>> >
>> >For the device-under-test, you need to create a new factory function
>> >(which in your case was called top_level), and set the vhdl_code
>> >attribute of that function. You will then need to create a dummy
>> >instance as part of that.
>> >
>> >Then tell the converter how the signals are handled (e.g. driven or
>> read).
>>
>> I understand what you're saying but it's not what I'm after. I must not
>> be explaining myself well. Let me try it again:
>> Image that you have created a vhdl entity called "top_level" which was
>> written *only in VHDL* (not written in MyHDL). Now imagine you want to
>> write a testbench for it, but instead of writing it in VHDL like you did
>> with "top_level", you want to save some time and write the testbench using
>> MyHDL instead. That's your goal. Now MyHDL will be upset because it doesn't
>> know about "top_level" (since it wasn't written in MyHDL). That's ok and
>> should be bypassed somehow because you aren't planning on using MyHDL for
>> simulation anyway. You want to use ModelSim instead. The only job tasked to
>> MyHDL is to generate the VHDL version of the testbench described using the
>> MYHDL language.
>>
>> The code posted in my previous email converts without error but the
>> signals and process are left out. There shouldn't be anything more than
>> just a very minor edit to force it to leave them in there correct?
>>
>> On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...> wrote:
>>
>>> I'm trying to generate a testbench of an entity the MyHDL doesn't know
>>> about and I'm getting a s"ignal not driven" warning along with the problem
>>> of the rest of the signals not showing up in the conversion.
>>>
>>> ***********************************  MyHDL
>>> *****************************************
>>>
>>> from myhdl import *
>>>
>>> def top_level_tb():
>>>     s_sw = intbv(0)[10]
>>>     s_clk = Signal(bool(0))
>>>     s_btn = intbv(0)[3]
>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>     done = Signal(bool(0))
>>>
>>>     top_level_tb.vhdl_code = """
>>>     UUT : entity work.top_level port map(
>>>             i_sw                      => s_sw,
>>>             i_clk                     => s_clk,
>>>             i_btn                     => s_btn,
>>>             o_seven_segment_display_1 => s_seven_segment_display_1,
>>>             o_seven_segment_display_0 => s_seven_segment_display_0,
>>>             o_seven_segment_display_3 => s_seven_segment_display_3,
>>>             o_seven_segment_display_2 => s_seven_segment_display_2
>>>         );
>>>     """
>>>
>>>
>>>     @always(delay(10))
>>>     def clkGenerator():
>>>         s_clk.next = not s_clk
>>>
>>>     @always(s_clk.posedge)
>>>     def stimulus():
>>>         s_btn[2].next = 1
>>>         delay(40)
>>>         s_btn[2].next = 0
>>>         delay(680)
>>>         self.assertEqual(s_seven_segment_display_1, "0100100")
>>>         self.assertEqual(s_seven_segment_display_0, "0100100")
>>>         delay(680)
>>>         done = 1
>>>
>>>     return clkGenerator, stimulus
>>>
>>> toVHDL(top_level_tb)
>>>
>>>
>>> **************************************  VHDL
>>> ************************************
>>>
>>>
>>>
>>> library IEEE;
>>> use IEEE.std_logic_1164.all;
>>> use IEEE.numeric_std.all;
>>> use std.textio.all;
>>>
>>> use work.pck_myhdl_081.all;
>>>
>>> entity top_level_tb is
>>> end entity top_level_tb;
>>>
>>>
>>> architecture MyHDL of top_level_tb is
>>>
>>>
>>>
>>>
>>>
>>> signal s_clk: std_logic;
>>>
>>> begin
>>>
>>> s_clk <= '0';
>>>
>>>
>>>
>>>
>>>     UUT : entity work.top_level port map(
>>>             i_sw                      => s_sw,
>>>             i_clk                     => s_clk,
>>>             i_btn                     => s_btn,
>>>             o_seven_segment_display_1 => s_seven_segment_display_1,
>>>             o_seven_segment_display_0 => s_seven_segment_display_0,
>>>             o_seven_segment_display_3 => s_seven_segment_display_3,
>>>             o_seven_segment_display_2 => s_seven_segment_display_2
>>>         );
>>>
>>> end architecture MyHDL;
>>>
>>> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...> wrote:
>>>
>>>> I don't understand how the vhdl_code attribute should be used in my
>>>> case.
>>>> This simple code will generate a VHDL testbench if it weren't for the
>>>> problem of MyHDL not knowing what top_level() is.
>>>>
>>>> def top_level_tb():
>>>>     s_signalA = intbv(0)[10]
>>>>     s_clk = Signal(bool(0))
>>>>
>>>>     # Here is where I need to somehow
>>>>     # tell MyHDL to ignore the fact that it doesn't know about
>>>> top_level()
>>>>     top_level_instance = top_level(s_signalA, s_clk)
>>>>
>>>>     @always(delay(10))
>>>>     def clkGenerator():
>>>>         s_clk.next = not s_clk
>>>>
>>>>     @always(s_clk.posedge)
>>>>     def stimulus():
>>>>         # todo ....
>>>>
>>>>     return top_level_instance, clkGenerator, stimulus
>>>>
>>>> toVHDL(top_level_tb)
>>>>
>>>> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...>
>>>> wrote:
>>>>
>>>>>
>>>>> Right, I've seen examples like that but what I'm trying to do is
>>>>> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>>>> an entity not written in MyHDL, for use in modelsim. The testbench is for
>>>>> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
>>>>> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
>>>>> to exist. In the previous email I made a fake one to try to get past that
>>>>> error. MyHDL doesn't actually need to know about it since it is not
>>>>> actually testing it. All MyHDL will be doing is generating the entity
>>>>> instance declaration like the one below so it doesn't need to know about
>>>>> TimeCount() anyway.
>>>>>
>>>>> UUT : entity work.time_count
>>>>>         port map(
>>>>>             tens               => s_tens,
>>>>>             ones            => s_ones,
>>>>>             tenths          => s_tenths,
>>>>>             startstop      => s_startstop,
>>>>>             reset              => s_reset,
>>>>>             clock             => s_clock
>>>>>         );
>>>>>
>>>>> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>>>> an entity not written in MyHDL, for use in modelsim. How do I do that?
>>>>> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>>>>>
>>>>>> >	Well, the problem there is a python problem. You're trying to import
>>>>>> >	from a module that doesn't exist, or at least not in your path. Again, I
>>>>>> >	suggest that your problems so far are predominantly a lack of
>>>>>> >	understanding of the way Python works, rather than MyHDL.
>>>>>> >	
>>>>>> >	Beyond that, I don't understand what you're trying to achieve.
>>>>>> >	
>>>>>> >	Cheers,
>>>>>> >	
>>>>>> >	Henry
>>>>>>
>>>>>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>>>>>
>>>>>> ***************************** VHDL *****************************************
>>>>>> library ieee;
>>>>>> use ieee.std_logic_1164.all;
>>>>>>
>>>>>> entity top_level_tb is
>>>>>> end top_level_tb;
>>>>>>
>>>>>> architecture tb of top_level_tb is
>>>>>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>>>>>> 	signal s_clk                     			: std_logic                   			:= '0';
>>>>>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>>>>>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>>> 	signal s_done                    			: std_logic                    			:= '0';
>>>>>> begin
>>>>>> 	UUT : entity work.top_level port map(
>>>>>> 			i_sw                  				=> s_sw,
>>>>>> 			i_clk                   				=> s_clk,
>>>>>> 			i_btn                   				=> s_btn,
>>>>>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>>>>>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>>>>>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>>>>>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>>>>>> 		);
>>>>>>
>>>>>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>>>>>
>>>>>> 	process
>>>>>> 	begin
>>>>>> 		wait for 10 ns;
>>>>>> 		s_btn(2) <= '0';                 -- reset on
>>>>>> 		wait for 20 ns;
>>>>>> 		s_btn(2) <= '1';                 -- reset off
>>>>>>
>>>>>> 		-- <tests to be added here>
>>>>>> 		
>>>>>> 		--	s_done <= '1';
>>>>>> 		-- wait;
>>>>>> 	end process;
>>>>>>
>>>>>> end tb;
>>>>>>
>>>>>> ***************************** MyHDL ******************************************
>>>>>>
>>>>>> from myhdl import *
>>>>>>
>>>>>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>>>>>> def top_level(
>>>>>>         i_sw,
>>>>>>         i_clk,
>>>>>>         i_btn,
>>>>>>         o_seven_segment_display_1,
>>>>>>         o_seven_segment_display_0,
>>>>>>         o_seven_segment_display_3,
>>>>>>         o_seven_segment_display_2
>>>>>> ):
>>>>>>     s_rst = ResetSignal(0, active=0, async=True)
>>>>>>
>>>>>>     @always_seq(i_clk.posedge, reset=s_rst)
>>>>>>     def main_process():
>>>>>>         o_seven_segment_display_1 = 0
>>>>>>
>>>>>>     return main_process
>>>>>>
>>>>>> # actual entity of interest
>>>>>> def top_level_tb():
>>>>>>     s_sw = intbv(0)[10]
>>>>>>     s_clk = Signal(bool(0))
>>>>>>     s_btn = intbv(0)[3]
>>>>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>>>>
>>>>>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>>>>>
>>>>>>     @always(delay(10))
>>>>>>     def clkGenerator():
>>>>>>         s_clk.next = not s_clk
>>>>>>
>>>>>>     @always(s_clk.posedge)
>>>>>>     def stimulus():
>>>>>> 		
>>>>>> 		# <more tests to be added here>
>>>>>> 		
>>>>>>         s_btn[2].next = 0
>>>>>>
>>>>>>     return top_level_instance, clkGenerator, stimulus
>>>>>>
>>>>>> toVHDL(top_level_tb)
>>>>>>
>>>>>>
>>>>>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...>
>>>>>> wrote:
>>>>>>
>>>>>>> Hi,
>>>>>>>
>>>>>>> I'm getting an error likely due to to a std_logic_vector being much
>>>>>>> monger than myHDL was intended to handle.
>>>>>>>
>>>>>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>>>>>
>>>>>>> I actually converted VHDL code to pyhton and want to continue
>>>>>>> development of this fifo-like-buffer entity using python, but I need to get
>>>>>>> around this error first..
>>>>>>> The reason the array is so large is because I want to go through it
>>>>>>> in one clock cycle if needed. It represents 20, 23-bit addresses.
>>>>>>>
>>>>>>> The code is attached. please advise.
>>>>>>>
>>>>>>> Thanks,
>>>>>>> David
>>>>>>>
>>>>>>
>>>>>>
>>>>
>>>
>>
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Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

>>The only job tasked to MyHDL is to generate the VHDL version
>> of the testbench described using the MYHDL language.
>
>That is complete nonsense. Change your goal and use MyHDL for simulation
>in the first place, otherwise stop wasting everbody's time.

I read the page you linked to. It is the second time I've read it. I also
read a few other topics in search of an answer. I agree with the concept of
a simulation-first design cycle.

 I'm guessing the message you were trying to send is that MyHDL uses the
simulation to verify that the generated code is correct. That's great but
that's beside the issue here. Let me explain the issue again in another
way. I want to use Quartus II for synthesis, ModelSim SE for simulation,
MyHDL only as a possible answer to faster VHDL generation, and Sigasi for
the final corrections and touch-up. In order to do that, MyHDL needs to be
able to not only generate the VHDL code for a normal entity, but also the
testbench for the top level entity which is part of a huge VHDL project
that it is not aware of. The reason this should be perfectly fine is
because all it has to do with the inherited entity is spit out the port
map. It doesn't need any knowledge of the entity that has been instantiated
since all it is required to do is generate VHDL, not simulate it.

To put it in another perspective, lets say I do it the way the design of
MyHDL is pushing me towards. Lets say I have some huge project already
written in VHDL. I want to write the testbench for the top level entity
using MyHDL because I hope that the process of writing the code will be
faster this way. Now there's a problem. MyHDL appears to be designed in
such a way that I am forced to write the code for the entity I am trying to
test to get the VHDL testbench to be generated correctly. Now that's a
problem because now I'm wasting time possibly rewriting the whole project
in MyHDL when all I ever wanted was just to generate a testbench quickly.
Now the potential efficiency advantage of MyHDL has just been ruined. Do
you see the problem here?

On Wed, Apr 8, 2015 at 4:12 PM, Tony Stark <34f...@gm...> wrote:

> >> I'm trying to generate a testbench of an entity the MyHDL doesn't know
> >> about and I'm getting a s"ignal not driven" warning along with the
> >> problem of the rest of the signals not showing up in the conversion.
> >
> >That's because you need to instruct the converter that certain signals
> >are driven because they can't be inferred.
> >
> >I also suspect that your code as written will not do what you want it to
> >do.
> >
> >I imagine you're trying to generate the stimuli in myhdl to drive your
> >VHDL test bench. right?
> >
> >For the device-under-test, you need to create a new factory function
> >(which in your case was called top_level), and set the vhdl_code
> >attribute of that function. You will then need to create a dummy
> >instance as part of that.
> >
> >Then tell the converter how the signals are handled (e.g. driven or read).
>
> I understand what you're saying but it's not what I'm after. I must not be
> explaining myself well. Let me try it again:
> Image that you have created a vhdl entity called "top_level" which was
> written *only in VHDL* (not written in MyHDL). Now imagine you want to
> write a testbench for it, but instead of writing it in VHDL like you did
> with "top_level", you want to save some time and write the testbench using
> MyHDL instead. That's your goal. Now MyHDL will be upset because it doesn't
> know about "top_level" (since it wasn't written in MyHDL). That's ok and
> should be bypassed somehow because you aren't planning on using MyHDL for
> simulation anyway. You want to use ModelSim instead. The only job tasked to
> MyHDL is to generate the VHDL version of the testbench described using the
> MYHDL language.
>
> The code posted in my previous email converts without error but the
> signals and process are left out. There shouldn't be anything more than
> just a very minor edit to force it to leave them in there correct?
>
> On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...> wrote:
>
>> I'm trying to generate a testbench of an entity the MyHDL doesn't know
>> about and I'm getting a s"ignal not driven" warning along with the problem
>> of the rest of the signals not showing up in the conversion.
>>
>> ***********************************  MyHDL
>> *****************************************
>>
>> from myhdl import *
>>
>> def top_level_tb():
>>     s_sw = intbv(0)[10]
>>     s_clk = Signal(bool(0))
>>     s_btn = intbv(0)[3]
>>     s_seven_segment_display_1 = intbv(0)[7]
>>     s_seven_segment_display_0 = intbv(0)[7]
>>     s_seven_segment_display_3 = intbv(0)[7]
>>     s_seven_segment_display_2 = intbv(0)[7]
>>     done = Signal(bool(0))
>>
>>     top_level_tb.vhdl_code = """
>>     UUT : entity work.top_level port map(
>>             i_sw                      => s_sw,
>>             i_clk                     => s_clk,
>>             i_btn                     => s_btn,
>>             o_seven_segment_display_1 => s_seven_segment_display_1,
>>             o_seven_segment_display_0 => s_seven_segment_display_0,
>>             o_seven_segment_display_3 => s_seven_segment_display_3,
>>             o_seven_segment_display_2 => s_seven_segment_display_2
>>         );
>>     """
>>
>>
>>     @always(delay(10))
>>     def clkGenerator():
>>         s_clk.next = not s_clk
>>
>>     @always(s_clk.posedge)
>>     def stimulus():
>>         s_btn[2].next = 1
>>         delay(40)
>>         s_btn[2].next = 0
>>         delay(680)
>>         self.assertEqual(s_seven_segment_display_1, "0100100")
>>         self.assertEqual(s_seven_segment_display_0, "0100100")
>>         delay(680)
>>         done = 1
>>
>>     return clkGenerator, stimulus
>>
>> toVHDL(top_level_tb)
>>
>>
>> **************************************  VHDL
>> ************************************
>>
>>
>>
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>> use IEEE.numeric_std.all;
>> use std.textio.all;
>>
>> use work.pck_myhdl_081.all;
>>
>> entity top_level_tb is
>> end entity top_level_tb;
>>
>>
>> architecture MyHDL of top_level_tb is
>>
>>
>>
>>
>>
>> signal s_clk: std_logic;
>>
>> begin
>>
>> s_clk <= '0';
>>
>>
>>
>>
>>     UUT : entity work.top_level port map(
>>             i_sw                      => s_sw,
>>             i_clk                     => s_clk,
>>             i_btn                     => s_btn,
>>             o_seven_segment_display_1 => s_seven_segment_display_1,
>>             o_seven_segment_display_0 => s_seven_segment_display_0,
>>             o_seven_segment_display_3 => s_seven_segment_display_3,
>>             o_seven_segment_display_2 => s_seven_segment_display_2
>>         );
>>
>> end architecture MyHDL;
>>
>> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...> wrote:
>>
>>> I don't understand how the vhdl_code attribute should be used in my case.
>>> This simple code will generate a VHDL testbench if it weren't for the
>>> problem of MyHDL not knowing what top_level() is.
>>>
>>> def top_level_tb():
>>>     s_signalA = intbv(0)[10]
>>>     s_clk = Signal(bool(0))
>>>
>>>     # Here is where I need to somehow
>>>     # tell MyHDL to ignore the fact that it doesn't know about
>>> top_level()
>>>     top_level_instance = top_level(s_signalA, s_clk)
>>>
>>>     @always(delay(10))
>>>     def clkGenerator():
>>>         s_clk.next = not s_clk
>>>
>>>     @always(s_clk.posedge)
>>>     def stimulus():
>>>         # todo ....
>>>
>>>     return top_level_instance, clkGenerator, stimulus
>>>
>>> toVHDL(top_level_tb)
>>>
>>> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...> wrote:
>>>
>>>>
>>>> Right, I've seen examples like that but what I'm trying to do is
>>>> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>>> an entity not written in MyHDL, for use in modelsim. The testbench is for
>>>> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
>>>> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
>>>> to exist. In the previous email I made a fake one to try to get past that
>>>> error. MyHDL doesn't actually need to know about it since it is not
>>>> actually testing it. All MyHDL will be doing is generating the entity
>>>> instance declaration like the one below so it doesn't need to know about
>>>> TimeCount() anyway.
>>>>
>>>> UUT : entity work.time_count
>>>>         port map(
>>>>             tens               => s_tens,
>>>>             ones            => s_ones,
>>>>             tenths          => s_tenths,
>>>>             startstop      => s_startstop,
>>>>             reset              => s_reset,
>>>>             clock             => s_clock
>>>>         );
>>>>
>>>> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>>> an entity not written in MyHDL, for use in modelsim. How do I do that?
>>>> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>>>>
>>>>> >	Well, the problem there is a python problem. You're trying to import
>>>>> >	from a module that doesn't exist, or at least not in your path. Again, I
>>>>> >	suggest that your problems so far are predominantly a lack of
>>>>> >	understanding of the way Python works, rather than MyHDL.
>>>>> >	
>>>>> >	Beyond that, I don't understand what you're trying to achieve.
>>>>> >	
>>>>> >	Cheers,
>>>>> >	
>>>>> >	Henry
>>>>>
>>>>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>>>>
>>>>> ***************************** VHDL *****************************************
>>>>> library ieee;
>>>>> use ieee.std_logic_1164.all;
>>>>>
>>>>> entity top_level_tb is
>>>>> end top_level_tb;
>>>>>
>>>>> architecture tb of top_level_tb is
>>>>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>>>>> 	signal s_clk                     			: std_logic                   			:= '0';
>>>>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>>>>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>>> 	signal s_done                    			: std_logic                    			:= '0';
>>>>> begin
>>>>> 	UUT : entity work.top_level port map(
>>>>> 			i_sw                  				=> s_sw,
>>>>> 			i_clk                   				=> s_clk,
>>>>> 			i_btn                   				=> s_btn,
>>>>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>>>>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>>>>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>>>>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>>>>> 		);
>>>>>
>>>>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>>>>
>>>>> 	process
>>>>> 	begin
>>>>> 		wait for 10 ns;
>>>>> 		s_btn(2) <= '0';                 -- reset on
>>>>> 		wait for 20 ns;
>>>>> 		s_btn(2) <= '1';                 -- reset off
>>>>>
>>>>> 		-- <tests to be added here>
>>>>> 		
>>>>> 		--	s_done <= '1';
>>>>> 		-- wait;
>>>>> 	end process;
>>>>>
>>>>> end tb;
>>>>>
>>>>> ***************************** MyHDL ******************************************
>>>>>
>>>>> from myhdl import *
>>>>>
>>>>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>>>>> def top_level(
>>>>>         i_sw,
>>>>>         i_clk,
>>>>>         i_btn,
>>>>>         o_seven_segment_display_1,
>>>>>         o_seven_segment_display_0,
>>>>>         o_seven_segment_display_3,
>>>>>         o_seven_segment_display_2
>>>>> ):
>>>>>     s_rst = ResetSignal(0, active=0, async=True)
>>>>>
>>>>>     @always_seq(i_clk.posedge, reset=s_rst)
>>>>>     def main_process():
>>>>>         o_seven_segment_display_1 = 0
>>>>>
>>>>>     return main_process
>>>>>
>>>>> # actual entity of interest
>>>>> def top_level_tb():
>>>>>     s_sw = intbv(0)[10]
>>>>>     s_clk = Signal(bool(0))
>>>>>     s_btn = intbv(0)[3]
>>>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>>>
>>>>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>>>>
>>>>>     @always(delay(10))
>>>>>     def clkGenerator():
>>>>>         s_clk.next = not s_clk
>>>>>
>>>>>     @always(s_clk.posedge)
>>>>>     def stimulus():
>>>>> 		
>>>>> 		# <more tests to be added here>
>>>>> 		
>>>>>         s_btn[2].next = 0
>>>>>
>>>>>     return top_level_instance, clkGenerator, stimulus
>>>>>
>>>>> toVHDL(top_level_tb)
>>>>>
>>>>>
>>>>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...>
>>>>> wrote:
>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> I'm getting an error likely due to to a std_logic_vector being much
>>>>>> monger than myHDL was intended to handle.
>>>>>>
>>>>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>>>>
>>>>>> I actually converted VHDL code to pyhton and want to continue
>>>>>> development of this fifo-like-buffer entity using python, but I need to get
>>>>>> around this error first..
>>>>>> The reason the array is so large is because I want to go through it
>>>>>> in one clock cycle if needed. It represents 20, 23-bit addresses.
>>>>>>
>>>>>> The code is attached. please advise.
>>>>>>
>>>>>> Thanks,
>>>>>> David
>>>>>>
>>>>>
>>>>>
>>>
>>
>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Jan D. <ja...@ja...>]

On 04/08/2015 10:12 PM, Tony Stark wrote:

> I understand what you're saying but it's not what I'm after. I must
> not be explaining myself well.

I really don't think that's the problem. The problem is rather that
you are not listening to what people are telling you.

> Let me try it again: Image that you
> have created a vhdl entity called "top_level" which was written *only
> in VHDL* (not written in MyHDL).

Ok.

  Now imagine you want to write a
> testbench for it, but instead of writing it in VHDL like you did with
> "top_level", you want to save some time and write the testbench using
> MyHDL instead.That's your goal.

Ok.

>  Now MyHDL will be upset because it
> doesn't know about "top_level" (since it wasn't written in MyHDL).
> That's ok and should be bypassed somehow because you aren't planning
> on using MyHDL for simulation anyway.

No. Stop right there. This makes no sense at all. It will never work.
If you think about it, you should understand why, and if you don't
want to think about it, you should have the respect to read the
manual that was written for you and is clear about this:

http://docs.myhdl.org/en/latest/manual/conversion.html#simulate-first

> You want to use ModelSim
> instead. The only job tasked to MyHDL is to generate the VHDL version
> of the testbench described using the MYHDL language.

That is complete nonsense. Change your goal and use MyHDL for simulation
in the first place, otherwise stop wasting everbody's time.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

>> I'm trying to generate a testbench of an entity the MyHDL doesn't know
>> about and I'm getting a s"ignal not driven" warning along with the
>> problem of the rest of the signals not showing up in the conversion.
>
>That's because you need to instruct the converter that certain signals
>are driven because they can't be inferred.
>
>I also suspect that your code as written will not do what you want it to
>do.
>
>I imagine you're trying to generate the stimuli in myhdl to drive your
>VHDL test bench. right?
>
>For the device-under-test, you need to create a new factory function
>(which in your case was called top_level), and set the vhdl_code
>attribute of that function. You will then need to create a dummy
>instance as part of that.
>
>Then tell the converter how the signals are handled (e.g. driven or read).

I understand what you're saying but it's not what I'm after. I must not be
explaining myself well. Let me try it again:
Image that you have created a vhdl entity called "top_level" which was
written *only in VHDL* (not written in MyHDL). Now imagine you want to
write a testbench for it, but instead of writing it in VHDL like you did
with "top_level", you want to save some time and write the testbench using
MyHDL instead. That's your goal. Now MyHDL will be upset because it doesn't
know about "top_level" (since it wasn't written in MyHDL). That's ok and
should be bypassed somehow because you aren't planning on using MyHDL for
simulation anyway. You want to use ModelSim instead. The only job tasked to
MyHDL is to generate the VHDL version of the testbench described using the
MYHDL language.

The code posted in my previous email converts without error but the signals
and process are left out. There shouldn't be anything more than just a very
minor edit to force it to leave them in there correct?

On Tue, Apr 7, 2015 at 7:38 PM, Tony Stark <34f...@gm...> wrote:

> I'm trying to generate a testbench of an entity the MyHDL doesn't know
> about and I'm getting a s"ignal not driven" warning along with the problem
> of the rest of the signals not showing up in the conversion.
>
> ***********************************  MyHDL
> *****************************************
>
> from myhdl import *
>
> def top_level_tb():
>     s_sw = intbv(0)[10]
>     s_clk = Signal(bool(0))
>     s_btn = intbv(0)[3]
>     s_seven_segment_display_1 = intbv(0)[7]
>     s_seven_segment_display_0 = intbv(0)[7]
>     s_seven_segment_display_3 = intbv(0)[7]
>     s_seven_segment_display_2 = intbv(0)[7]
>     done = Signal(bool(0))
>
>     top_level_tb.vhdl_code = """
>     UUT : entity work.top_level port map(
>             i_sw                      => s_sw,
>             i_clk                     => s_clk,
>             i_btn                     => s_btn,
>             o_seven_segment_display_1 => s_seven_segment_display_1,
>             o_seven_segment_display_0 => s_seven_segment_display_0,
>             o_seven_segment_display_3 => s_seven_segment_display_3,
>             o_seven_segment_display_2 => s_seven_segment_display_2
>         );
>     """
>
>
>     @always(delay(10))
>     def clkGenerator():
>         s_clk.next = not s_clk
>
>     @always(s_clk.posedge)
>     def stimulus():
>         s_btn[2].next = 1
>         delay(40)
>         s_btn[2].next = 0
>         delay(680)
>         self.assertEqual(s_seven_segment_display_1, "0100100")
>         self.assertEqual(s_seven_segment_display_0, "0100100")
>         delay(680)
>         done = 1
>
>     return clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> **************************************  VHDL
> ************************************
>
>
>
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> use std.textio.all;
>
> use work.pck_myhdl_081.all;
>
> entity top_level_tb is
> end entity top_level_tb;
>
>
> architecture MyHDL of top_level_tb is
>
>
>
>
>
> signal s_clk: std_logic;
>
> begin
>
> s_clk <= '0';
>
>
>
>
>     UUT : entity work.top_level port map(
>             i_sw                      => s_sw,
>             i_clk                     => s_clk,
>             i_btn                     => s_btn,
>             o_seven_segment_display_1 => s_seven_segment_display_1,
>             o_seven_segment_display_0 => s_seven_segment_display_0,
>             o_seven_segment_display_3 => s_seven_segment_display_3,
>             o_seven_segment_display_2 => s_seven_segment_display_2
>         );
>
> end architecture MyHDL;
>
> On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...> wrote:
>
>> I don't understand how the vhdl_code attribute should be used in my case.
>> This simple code will generate a VHDL testbench if it weren't for the
>> problem of MyHDL not knowing what top_level() is.
>>
>> def top_level_tb():
>>     s_signalA = intbv(0)[10]
>>     s_clk = Signal(bool(0))
>>
>>     # Here is where I need to somehow
>>     # tell MyHDL to ignore the fact that it doesn't know about top_level()
>>     top_level_instance = top_level(s_signalA, s_clk)
>>
>>     @always(delay(10))
>>     def clkGenerator():
>>         s_clk.next = not s_clk
>>
>>     @always(s_clk.posedge)
>>     def stimulus():
>>         # todo ....
>>
>>     return top_level_instance, clkGenerator, stimulus
>>
>> toVHDL(top_level_tb)
>>
>> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...> wrote:
>>
>>>
>>> Right, I've seen examples like that but what I'm trying to do is
>>> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>> an entity not written in MyHDL, for use in modelsim. The testbench is for
>>> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
>>> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
>>> to exist. In the previous email I made a fake one to try to get past that
>>> error. MyHDL doesn't actually need to know about it since it is not
>>> actually testing it. All MyHDL will be doing is generating the entity
>>> instance declaration like the one below so it doesn't need to know about
>>> TimeCount() anyway.
>>>
>>> UUT : entity work.time_count
>>>         port map(
>>>             tens               => s_tens,
>>>             ones            => s_ones,
>>>             tenths          => s_tenths,
>>>             startstop      => s_startstop,
>>>             reset              => s_reset,
>>>             clock             => s_clock
>>>         );
>>>
>>> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for
>>> an entity not written in MyHDL, for use in modelsim. How do I do that?
>>> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>>>
>>>> >	Well, the problem there is a python problem. You're trying to import
>>>> >	from a module that doesn't exist, or at least not in your path. Again, I
>>>> >	suggest that your problems so far are predominantly a lack of
>>>> >	understanding of the way Python works, rather than MyHDL.
>>>> >	
>>>> >	Beyond that, I don't understand what you're trying to achieve.
>>>> >	
>>>> >	Cheers,
>>>> >	
>>>> >	Henry
>>>>
>>>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>>>
>>>> ***************************** VHDL *****************************************
>>>> library ieee;
>>>> use ieee.std_logic_1164.all;
>>>>
>>>> entity top_level_tb is
>>>> end top_level_tb;
>>>>
>>>> architecture tb of top_level_tb is
>>>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>>>> 	signal s_clk                     			: std_logic                   			:= '0';
>>>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>>>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>>> 	signal s_done                    			: std_logic                    			:= '0';
>>>> begin
>>>> 	UUT : entity work.top_level port map(
>>>> 			i_sw                  				=> s_sw,
>>>> 			i_clk                   				=> s_clk,
>>>> 			i_btn                   				=> s_btn,
>>>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>>>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>>>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>>>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>>>> 		);
>>>>
>>>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>>>
>>>> 	process
>>>> 	begin
>>>> 		wait for 10 ns;
>>>> 		s_btn(2) <= '0';                 -- reset on
>>>> 		wait for 20 ns;
>>>> 		s_btn(2) <= '1';                 -- reset off
>>>>
>>>> 		-- <tests to be added here>
>>>> 		
>>>> 		--	s_done <= '1';
>>>> 		-- wait;
>>>> 	end process;
>>>>
>>>> end tb;
>>>>
>>>> ***************************** MyHDL ******************************************
>>>>
>>>> from myhdl import *
>>>>
>>>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>>>> def top_level(
>>>>         i_sw,
>>>>         i_clk,
>>>>         i_btn,
>>>>         o_seven_segment_display_1,
>>>>         o_seven_segment_display_0,
>>>>         o_seven_segment_display_3,
>>>>         o_seven_segment_display_2
>>>> ):
>>>>     s_rst = ResetSignal(0, active=0, async=True)
>>>>
>>>>     @always_seq(i_clk.posedge, reset=s_rst)
>>>>     def main_process():
>>>>         o_seven_segment_display_1 = 0
>>>>
>>>>     return main_process
>>>>
>>>> # actual entity of interest
>>>> def top_level_tb():
>>>>     s_sw = intbv(0)[10]
>>>>     s_clk = Signal(bool(0))
>>>>     s_btn = intbv(0)[3]
>>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>>
>>>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>>>
>>>>     @always(delay(10))
>>>>     def clkGenerator():
>>>>         s_clk.next = not s_clk
>>>>
>>>>     @always(s_clk.posedge)
>>>>     def stimulus():
>>>> 		
>>>> 		# <more tests to be added here>
>>>> 		
>>>>         s_btn[2].next = 0
>>>>
>>>>     return top_level_instance, clkGenerator, stimulus
>>>>
>>>> toVHDL(top_level_tb)
>>>>
>>>>
>>>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> I'm getting an error likely due to to a std_logic_vector being much
>>>>> monger than myHDL was intended to handle.
>>>>>
>>>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>>>
>>>>> I actually converted VHDL code to pyhton and want to continue
>>>>> development of this fifo-like-buffer entity using python, but I need to get
>>>>> around this error first..
>>>>> The reason the array is so large is because I want to go through it in
>>>>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>>>>
>>>>> The code is attached. please advise.
>>>>>
>>>>> Thanks,
>>>>> David
>>>>>
>>>>
>>>>
>>
>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Christopher F. <chr...@gm...>]

<snip>
>
> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for an
> entity not written in MyHDL, for use in modelsim. How do I do that?
> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>

The `vhdl_instance` might work for you.  You can see
this older thread for some more information:
http://article.gmane.org/gmane.comp.python.myhdl/1484/match=vhdl_instance

Regards,
Chris

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 08/04/15 00:38, Tony Stark wrote:
> I'm trying to generate a testbench of an entity the MyHDL doesn't know 
> about and I'm getting a s"ignal not driven" warning along with the 
> problem of the rest of the signals not showing up in the conversion.

That's because you need to instruct the converter that certain signals 
are driven because they can't be inferred.

I also suspect that your code as written will not do what you want it to 
do.

I imagine you're trying to generate the stimuli in myhdl to drive your 
VHDL test bench. right?

For the device-under-test, you need to create a new factory function 
(which in your case was called top_level), and set the vhdl_code 
attribute of that function. You will then need to create a dummy 
instance as part of that.

Then tell the converter how the signals are handled (e.g. driven or read).

All this is in the documentation, which I suggest you read.

So something like:

def top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1,
               s_seven_segment_display_0, s_seven_segment_display_3,
               s_seven_segment_display_2):

     @instance
     def dummy_instance():
         pass

     top_level.vhdl_code = '''
UUT : entity work.top_level port map(
     i_sw                      => $s_sw,
     i_clk                     => $s_clk,
     i_btn                     => $s_btn,
     o_seven_segment_display_1 => $s_seven_segment_display_1,
     o_seven_segment_display_0 => $s_seven_segment_display_0,
     o_seven_segment_display_3 => $s_seven_segment_display_3,
     o_seven_segment_display_2 => $s_seven_segment_display_2
);
'''

     s_sw.read = True
     s_clk.read = True
     s_btn.read = True
     s_seven_segment_display_0.driven = True
     s_seven_segment_display_1.driven = True
     s_seven_segment_display_2.driven = True
     s_seven_segment_display_3.driven = True

     return dummy_instance

Note the signals are assigned using $signal_name (the vhdl_code 
attribute is a template, not the actual code). This means the converter 
will replace the variable names with the correct VHDL value.

Henry

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Jan C. <th...@mu...>]

On Tue, 7 Apr 2015 18:49:34 -0400
Tony Stark <34f...@gm...> wrote:

> I don't understand how the vhdl_code attribute should be used in my case. 

It could be used to unify your source, which you could 
then submit to a VHDL simulator.  

This would not seem to make your unusual plan any more 
practical. 

Jan Coombs. 

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

I'm trying to generate a testbench of an entity the MyHDL doesn't know
about and I'm getting a s"ignal not driven" warning along with the problem
of the rest of the signals not showing up in the conversion.

***********************************  MyHDL
*****************************************

from myhdl import *

def top_level_tb():
    s_sw = intbv(0)[10]
    s_clk = Signal(bool(0))
    s_btn = intbv(0)[3]
    s_seven_segment_display_1 = intbv(0)[7]
    s_seven_segment_display_0 = intbv(0)[7]
    s_seven_segment_display_3 = intbv(0)[7]
    s_seven_segment_display_2 = intbv(0)[7]
    done = Signal(bool(0))

    top_level_tb.vhdl_code = """
    UUT : entity work.top_level port map(
            i_sw                      => s_sw,
            i_clk                     => s_clk,
            i_btn                     => s_btn,
            o_seven_segment_display_1 => s_seven_segment_display_1,
            o_seven_segment_display_0 => s_seven_segment_display_0,
            o_seven_segment_display_3 => s_seven_segment_display_3,
            o_seven_segment_display_2 => s_seven_segment_display_2
        );
    """


    @always(delay(10))
    def clkGenerator():
        s_clk.next = not s_clk

    @always(s_clk.posedge)
    def stimulus():
        s_btn[2].next = 1
        delay(40)
        s_btn[2].next = 0
        delay(680)
        self.assertEqual(s_seven_segment_display_1, "0100100")
        self.assertEqual(s_seven_segment_display_0, "0100100")
        delay(680)
        done = 1

    return clkGenerator, stimulus

toVHDL(top_level_tb)


**************************************  VHDL
************************************



library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_081.all;

entity top_level_tb is
end entity top_level_tb;


architecture MyHDL of top_level_tb is





signal s_clk: std_logic;

begin

s_clk <= '0';




    UUT : entity work.top_level port map(
            i_sw                      => s_sw,
            i_clk                     => s_clk,
            i_btn                     => s_btn,
            o_seven_segment_display_1 => s_seven_segment_display_1,
            o_seven_segment_display_0 => s_seven_segment_display_0,
            o_seven_segment_display_3 => s_seven_segment_display_3,
            o_seven_segment_display_2 => s_seven_segment_display_2
        );

end architecture MyHDL;

On Tue, Apr 7, 2015 at 6:49 PM, Tony Stark <34f...@gm...> wrote:

> I don't understand how the vhdl_code attribute should be used in my case.
> This simple code will generate a VHDL testbench if it weren't for the
> problem of MyHDL not knowing what top_level() is.
>
> def top_level_tb():
>     s_signalA = intbv(0)[10]
>     s_clk = Signal(bool(0))
>
>     # Here is where I need to somehow
>     # tell MyHDL to ignore the fact that it doesn't know about top_level()
>     top_level_instance = top_level(s_signalA, s_clk)
>
>     @always(delay(10))
>     def clkGenerator():
>         s_clk.next = not s_clk
>
>     @always(s_clk.posedge)
>     def stimulus():
>         # todo ....
>
>     return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
> On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...> wrote:
>
>>
>> Right, I've seen examples like that but what I'm trying to do is
>> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
>> an entity not written in MyHDL, for use in modelsim. The testbench is for
>> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
>> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
>> to exist. In the previous email I made a fake one to try to get past that
>> error. MyHDL doesn't actually need to know about it since it is not
>> actually testing it. All MyHDL will be doing is generating the entity
>> instance declaration like the one below so it doesn't need to know about
>> TimeCount() anyway.
>>
>> UUT : entity work.time_count
>>         port map(
>>             tens               => s_tens,
>>             ones            => s_ones,
>>             tenths          => s_tenths,
>>             startstop      => s_startstop,
>>             reset              => s_reset,
>>             clock             => s_clock
>>         );
>>
>> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for an
>> entity not written in MyHDL, for use in modelsim. How do I do that?
>> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>>
>>> >	Well, the problem there is a python problem. You're trying to import
>>> >	from a module that doesn't exist, or at least not in your path. Again, I
>>> >	suggest that your problems so far are predominantly a lack of
>>> >	understanding of the way Python works, rather than MyHDL.
>>> >	
>>> >	Beyond that, I don't understand what you're trying to achieve.
>>> >	
>>> >	Cheers,
>>> >	
>>> >	Henry
>>>
>>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>>
>>> ***************************** VHDL *****************************************
>>> library ieee;
>>> use ieee.std_logic_1164.all;
>>>
>>> entity top_level_tb is
>>> end top_level_tb;
>>>
>>> architecture tb of top_level_tb is
>>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>>> 	signal s_clk                     			: std_logic                   			:= '0';
>>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>>> 	signal s_done                    			: std_logic                    			:= '0';
>>> begin
>>> 	UUT : entity work.top_level port map(
>>> 			i_sw                  				=> s_sw,
>>> 			i_clk                   				=> s_clk,
>>> 			i_btn                   				=> s_btn,
>>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>>> 		);
>>>
>>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>>
>>> 	process
>>> 	begin
>>> 		wait for 10 ns;
>>> 		s_btn(2) <= '0';                 -- reset on
>>> 		wait for 20 ns;
>>> 		s_btn(2) <= '1';                 -- reset off
>>>
>>> 		-- <tests to be added here>
>>> 		
>>> 		--	s_done <= '1';
>>> 		-- wait;
>>> 	end process;
>>>
>>> end tb;
>>>
>>> ***************************** MyHDL ******************************************
>>>
>>> from myhdl import *
>>>
>>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>>> def top_level(
>>>         i_sw,
>>>         i_clk,
>>>         i_btn,
>>>         o_seven_segment_display_1,
>>>         o_seven_segment_display_0,
>>>         o_seven_segment_display_3,
>>>         o_seven_segment_display_2
>>> ):
>>>     s_rst = ResetSignal(0, active=0, async=True)
>>>
>>>     @always_seq(i_clk.posedge, reset=s_rst)
>>>     def main_process():
>>>         o_seven_segment_display_1 = 0
>>>
>>>     return main_process
>>>
>>> # actual entity of interest
>>> def top_level_tb():
>>>     s_sw = intbv(0)[10]
>>>     s_clk = Signal(bool(0))
>>>     s_btn = intbv(0)[3]
>>>     s_seven_segment_display_1 = intbv(0)[7]
>>>     s_seven_segment_display_0 = intbv(0)[7]
>>>     s_seven_segment_display_3 = intbv(0)[7]
>>>     s_seven_segment_display_2 = intbv(0)[7]
>>>
>>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>>
>>>     @always(delay(10))
>>>     def clkGenerator():
>>>         s_clk.next = not s_clk
>>>
>>>     @always(s_clk.posedge)
>>>     def stimulus():
>>> 		
>>> 		# <more tests to be added here>
>>> 		
>>>         s_btn[2].next = 0
>>>
>>>     return top_level_instance, clkGenerator, stimulus
>>>
>>> toVHDL(top_level_tb)
>>>
>>>
>>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:
>>>
>>>> Hi,
>>>>
>>>> I'm getting an error likely due to to a std_logic_vector being much
>>>> monger than myHDL was intended to handle.
>>>>
>>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>>
>>>> I actually converted VHDL code to pyhton and want to continue
>>>> development of this fifo-like-buffer entity using python, but I need to get
>>>> around this error first..
>>>> The reason the array is so large is because I want to go through it in
>>>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>>>
>>>> The code is attached. please advise.
>>>>
>>>> Thanks,
>>>> David
>>>>
>>>
>>>
>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

I don't understand how the vhdl_code attribute should be used in my case.
This simple code will generate a VHDL testbench if it weren't for the
problem of MyHDL not knowing what top_level() is.

def top_level_tb():
    s_signalA = intbv(0)[10]
    s_clk = Signal(bool(0))

    # Here is where I need to somehow
    # tell MyHDL to ignore the fact that it doesn't know about top_level()
    top_level_instance = top_level(s_signalA, s_clk)

    @always(delay(10))
    def clkGenerator():
        s_clk.next = not s_clk

    @always(s_clk.posedge)
    def stimulus():
        # todo ....

    return top_level_instance, clkGenerator, stimulus

toVHDL(top_level_tb)

On Tue, Apr 7, 2015 at 12:36 PM, Tony Stark <34f...@gm...> wrote:

>
> Right, I've seen examples like that but what I'm trying to do is
> different. I'm trying to us MyHDL only to generate a testbench in VHDL, for
> an entity not written in MyHDL, for use in modelsim. The testbench is for
> an entity that MyHDL doesn't know about so "dut = TimeCount(tens, ones,
> tenths, startstop, reset, clock)" isn't valid since TimeCount() isn't going
> to exist. In the previous email I made a fake one to try to get past that
> error. MyHDL doesn't actually need to know about it since it is not
> actually testing it. All MyHDL will be doing is generating the entity
> instance declaration like the one below so it doesn't need to know about
> TimeCount() anyway.
>
> UUT : entity work.time_count
>         port map(
>             tens               => s_tens,
>             ones            => s_ones,
>             tenths          => s_tenths,
>             startstop      => s_startstop,
>             reset              => s_reset,
>             clock             => s_clock
>         );
>
> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for an
> entity not written in MyHDL, for use in modelsim. How do I do that?
> On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:
>
>> >	Well, the problem there is a python problem. You're trying to import
>> >	from a module that doesn't exist, or at least not in your path. Again, I
>> >	suggest that your problems so far are predominantly a lack of
>> >	understanding of the way Python works, rather than MyHDL.
>> >	
>> >	Beyond that, I don't understand what you're trying to achieve.
>> >	
>> >	Cheers,
>> >	
>> >	Henry
>>
>> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>>
>> ***************************** VHDL *****************************************
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity top_level_tb is
>> end top_level_tb;
>>
>> architecture tb of top_level_tb is
>> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
>> 	signal s_clk                     			: std_logic                   			:= '0';
>> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
>> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
>> 	signal s_done                    			: std_logic                    			:= '0';
>> begin
>> 	UUT : entity work.top_level port map(
>> 			i_sw                  				=> s_sw,
>> 			i_clk                   				=> s_clk,
>> 			i_btn                   				=> s_btn,
>> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
>> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
>> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
>> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
>> 		);
>>
>> 	s_clk <= not s_clk and not s_done after 10 ns;
>>
>> 	process
>> 	begin
>> 		wait for 10 ns;
>> 		s_btn(2) <= '0';                 -- reset on
>> 		wait for 20 ns;
>> 		s_btn(2) <= '1';                 -- reset off
>>
>> 		-- <tests to be added here>
>> 		
>> 		--	s_done <= '1';
>> 		-- wait;
>> 	end process;
>>
>> end tb;
>>
>> ***************************** MyHDL ******************************************
>>
>> from myhdl import *
>>
>> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
>> def top_level(
>>         i_sw,
>>         i_clk,
>>         i_btn,
>>         o_seven_segment_display_1,
>>         o_seven_segment_display_0,
>>         o_seven_segment_display_3,
>>         o_seven_segment_display_2
>> ):
>>     s_rst = ResetSignal(0, active=0, async=True)
>>
>>     @always_seq(i_clk.posedge, reset=s_rst)
>>     def main_process():
>>         o_seven_segment_display_1 = 0
>>
>>     return main_process
>>
>> # actual entity of interest
>> def top_level_tb():
>>     s_sw = intbv(0)[10]
>>     s_clk = Signal(bool(0))
>>     s_btn = intbv(0)[3]
>>     s_seven_segment_display_1 = intbv(0)[7]
>>     s_seven_segment_display_0 = intbv(0)[7]
>>     s_seven_segment_display_3 = intbv(0)[7]
>>     s_seven_segment_display_2 = intbv(0)[7]
>>
>>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>>
>>     @always(delay(10))
>>     def clkGenerator():
>>         s_clk.next = not s_clk
>>
>>     @always(s_clk.posedge)
>>     def stimulus():
>> 		
>> 		# <more tests to be added here>
>> 		
>>         s_btn[2].next = 0
>>
>>     return top_level_instance, clkGenerator, stimulus
>>
>> toVHDL(top_level_tb)
>>
>>
>> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:
>>
>>> Hi,
>>>
>>> I'm getting an error likely due to to a std_logic_vector being much
>>> monger than myHDL was intended to handle.
>>>
>>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>>
>>> I actually converted VHDL code to pyhton and want to continue
>>> development of this fifo-like-buffer entity using python, but I need to get
>>> around this error first..
>>> The reason the array is so large is because I want to go through it in
>>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>>
>>> The code is attached. please advise.
>>>
>>> Thanks,
>>> David
>>>
>>
>>

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Henry G. <he...@ca...>]

On 07/04/15 17:36, Tony Stark wrote:
> TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for 
> an entity not written in MyHDL, for use in modelsim. How do I do that?

Oh, use the vhdl_code attribute. Check the API here: 
http://docs.myhdl.org/en/latest/manual/conversion.html

See 
https://github.com/hgomersall/Veriutils/blob/master/veriutils/hdl_blocks.py 
for an example of it being used.

Cheers,

Henry

Re: [myhdl-list] Simulation control

[Henry G. <he...@ca...>]

On 07/04/15 17:33, Henry Gomersall wrote:
> I'm pretty sure the synchronisation function isn't doing what it should,
> but that just needs debugging. It might be easier to use Threading, but
> I'm not sure if MyHDL is safe for that (I don't know if there is any
> global shared state).

The sync event is never cleared.

Anyway, I think that gives the basic strategy I was getting at...

Re: [myhdl-list] TypeError: concat: inappropriate argument type: <type 'long'>

[Tony S. <34f...@gm...>]

Right, I've seen examples like that but what I'm trying to do is different.
I'm trying to us MyHDL only to generate a testbench in VHDL, for an entity
not written in MyHDL, for use in modelsim. The testbench is for an entity
that MyHDL doesn't know about so "dut = TimeCount(tens, ones, tenths,
startstop, reset, clock)" isn't valid since TimeCount() isn't going to
exist. In the previous email I made a fake one to try to get past that
error. MyHDL doesn't actually need to know about it since it is not
actually testing it. All MyHDL will be doing is generating the entity
instance declaration like the one below so it doesn't need to know about
TimeCount() anyway.

UUT : entity work.time_count
        port map(
            tens               => s_tens,
            ones            => s_ones,
            tenths          => s_tenths,
            startstop      => s_startstop,
            reset              => s_reset,
            clock             => s_clock
        );

TL;DR I'm trying to us MyHDL only to generate a testbench in VHDL, for an
entity not written in MyHDL, for use in modelsim. How do I do that?
On Apr 4, 2015 7:37 PM, "Tony Stark" <34f...@gm...> wrote:

> >	Well, the problem there is a python problem. You're trying to import
> >	from a module that doesn't exist, or at least not in your path. Again, I
> >	suggest that your problems so far are predominantly a lack of
> >	understanding of the way Python works, rather than MyHDL.
> >	
> >	Beyond that, I don't understand what you're trying to achieve.
> >	
> >	Cheers,
> >	
> >	Henry
>
> Alright, I've made a little progress on this but still nothing useful yet. The VHDL code I've written below is what I want to have MyHDL generate. The Python code following that is my attempt at it. It generates code without error but it's not nearly useful yet.
>
> ***************************** VHDL *****************************************
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity top_level_tb is
> end top_level_tb;
>
> architecture tb of top_level_tb is
> 	signal s_sw                   				: std_logic_vector(9 downto 0) 	:= (others => '0');
> 	signal s_clk                     			: std_logic                   			:= '0';
> 	signal s_btn                    		 	: std_logic_vector(2 downto 0) 	:= (others => '1');
> 	signal s_seven_segment_display_1 	: std_logic_vector(6 downto 0) 	:= (others => '0');
> 	signal s_seven_segment_display_0 	: std_logic_vector(6 downto 0) 	:= (others => '0');
> 	signal s_seven_segment_display_3 	: std_logic_vector(6 downto 0) 	:= (others => '0');
> 	signal s_seven_segment_display_2 	: std_logic_vector(6 downto 0) 	:= (others => '0');
> 	signal s_done                    			: std_logic                    			:= '0';
> begin
> 	UUT : entity work.top_level port map(
> 			i_sw                  				=> s_sw,
> 			i_clk                   				=> s_clk,
> 			i_btn                   				=> s_btn,
> 			o_seven_segment_display_1 	=> s_seven_segment_display_1,
> 			o_seven_segment_display_0 	=> s_seven_segment_display_0,
> 			o_seven_segment_display_3 	=> s_seven_segment_display_3,
> 			o_seven_segment_display_2 	=> s_seven_segment_display_2
> 		);
>
> 	s_clk <= not s_clk and not s_done after 10 ns;
>
> 	process
> 	begin
> 		wait for 10 ns;
> 		s_btn(2) <= '0';                 -- reset on
> 		wait for 20 ns;
> 		s_btn(2) <= '1';                 -- reset off
>
> 		-- <tests to be added here>
> 		
> 		--	s_done <= '1';
> 		-- wait;
> 	end process;
>
> end tb;
>
> ***************************** MyHDL ******************************************
>
> from myhdl import *
>
> # fake entity & fake process created in an attempt to get MyHDL to stop complaining about not knowing what top_level() was
> def top_level(
>         i_sw,
>         i_clk,
>         i_btn,
>         o_seven_segment_display_1,
>         o_seven_segment_display_0,
>         o_seven_segment_display_3,
>         o_seven_segment_display_2
> ):
>     s_rst = ResetSignal(0, active=0, async=True)
>
>     @always_seq(i_clk.posedge, reset=s_rst)
>     def main_process():
>         o_seven_segment_display_1 = 0
>
>     return main_process
>
> # actual entity of interest
> def top_level_tb():
>     s_sw = intbv(0)[10]
>     s_clk = Signal(bool(0))
>     s_btn = intbv(0)[3]
>     s_seven_segment_display_1 = intbv(0)[7]
>     s_seven_segment_display_0 = intbv(0)[7]
>     s_seven_segment_display_3 = intbv(0)[7]
>     s_seven_segment_display_2 = intbv(0)[7]
>
>     top_level_instance = top_level(s_sw, s_clk, s_btn, s_seven_segment_display_1, s_seven_segment_display_0, s_seven_segment_display_3, s_seven_segment_display_2)
>
>     @always(delay(10))
>     def clkGenerator():
>         s_clk.next = not s_clk
>
>     @always(s_clk.posedge)
>     def stimulus():
> 		
> 		# <more tests to be added here>
> 		
>         s_btn[2].next = 0
>
>     return top_level_instance, clkGenerator, stimulus
>
> toVHDL(top_level_tb)
>
>
> On Thu, Apr 2, 2015 at 7:31 PM, Tony Stark <34f...@gm...> wrote:
>
>> Hi,
>>
>> I'm getting an error likely due to to a std_logic_vector being much
>> monger than myHDL was intended to handle.
>>
>> addr_array.next = concat(addr_array[436:0], most_recent_addr_req_to_sdram - 1)
>>
>> I actually converted VHDL code to pyhton and want to continue development
>> of this fifo-like-buffer entity using python, but I need to get around this
>> error first..
>> The reason the array is so large is because I want to go through it in
>> one clock cycle if needed. It represents 20, 23-bit addresses.
>>
>> The code is attached. please advise.
>>
>> Thanks,
>> David
>>
>
>

Re: [myhdl-list] Simulation control

[Henry G. <he...@ca...>]

On 07/04/15 15:56, Juan Pablo Caram wrote:
> The link on "mixed mode" simulation is a proof of concept, but very 
> naive. I've put together a blog post discussing the difficulties that 
> one might find:
>
> http://caram.cl/developing-a-mixed-signal-simulator
>
> The link about interactive simulation is more along the lines of what 
> would be required, but using the function calls, not the interactive 
> console. I see it's using a debugger and that might make it extremely 
> slow. It would be ideal if this functionality was built into the 
> simulator. If I were to implement this functionality into the 
> simulator, any idea on where I should start? I haven't seen any 
> documentation about the operation of the simulator.

I read your blog post, and I still don't see what the fundamental 
problem is.

In your final example, your DAC and your ADC are going to have to be 
instantaneous samplers. It doesn't make any sense otherwise. What does 
it mean to have an event in between clock edges? MyHDL doesn't have any 
concept of signal timings. If the delay means something, you need to 
model that in the analogue side; from the perspective of the RTL model, 
there is some value at some clock edge.

You can model different clock domains, you just have to go the whole hog 
and run each clock domain in a different process. You'll have to define 
your time resolution and have some kind of sync barrier on each 
resolution period (using some kind of meta clock).

That is, on every resolution period, each process will sync with the 
other to keep the simulations timings the same.

I've written a basic example with two clocks here:
https://gist.github.com/hgomersall/6f9268023593ca5fd9d0

I'm pretty sure the synchronisation function isn't doing what it should, 
but that just needs debugging. It might be easier to use Threading, but 
I'm not sure if MyHDL is safe for that (I don't know if there is any 
global shared state).

Cheers,
Henry

Re: [myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

Henry,

Yes, I want to support asynchronous events. That's where mixed-signal
circuits get interesting. I would appreciate if you would take a look at
the blog post I put together describing some complexities in this:
http://caram.cl/developing-a-mixed-signal-simulator

Besides the ADCs and DACs, there can be comparators. ADC/DACs are clocked
from the HDL side, i.e. they are synchronous, while a comparator can toggle
at any time depending on the instantaneous analog value.

In terms of time step in myHDL, I believe setting it to be small enough
should suffice. No sub-step support required. When a spice event occurs,
the digital side can react on the next time step.

Perhaps I could run the myHDL simulator in a separate thread, and having it
block inside the function(s) that toggle the signal of interest until a
message (via queues) is received from the main thread is received. That way
I could regain control, like with a debugger, but without the performance
penalty. And wouldn't need to modify the simulator.

Thanks,

JP

On Mon, Apr 6, 2015 at 3:47 AM, Henry Gomersall <he...@ca...> wrote:

> On 05/04/15 23:22, Juan Pablo Caram wrote:
> > The problem is that I might need to stop for different signals, and
> > having them all call do_things() makes having a centralized control of
> > the mixed-signal simulation environment very complicated. On top of
> > this, how can I know them "time" at which the signal toggle inside the
> > "logic()" function"? I would need that to determine for how long to
> > run the analog simulation.
> >
> > Even worse, what if "clk" came from the analog simulation... I would
> > have to wait for each analog run complete to know when to toggle it,
> > and then manually toggle it. Here, the myhdl simulation would run
> > "behind".
> >
> > For short, I don't think I can implement the control of the whole
> > system from a single "do_things()" function. What do you think?
>
> It's not totally clear to me what you're trying to do, but I'm yet to be
> convinced it isn't possible, and certainly yet to be convinced that
> having programmatic access to a debugging layer would be better than
> doing it all inside MyHDL.
>
> You have a stateful spice simulator in a myhdl simulator. The myhdl code
> flips signals as desired until it needs to wait on the simulator doing
> something, then it blocks until the spice simulator reaches a suitable
> state and allows it to continue (let's say, when the virtual ADC flips a
> bit). Presumably you have inputs and outputs to your spice model? At
> some point, surely, you need virtual ADCs and DACs, so you're pretty
> limited in terms of directionality? In which case, you can set inputs as
> you wish and then block on outputs (or output sets).
>
> I don't see the problem with clk - in your clock driver, you just block
> until the spice simulator has moved to the correct state.
>
> Are you trying to do your myhdl logic in an asynchronous way? Or do you
> want sub-cycle times to be somehow meaningful between spice and myhdl (I
> don't have any idea what this could be)?
>
> If you need to run the spice model and the myhdl simulation
> concurrently, you can do so in different threads.
>
> cheers,
>
> Henry
>
>
> ------------------------------------------------------------------------------
> BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT
> Develop your own process in accordance with the BPMN 2 standard
> Learn Process modeling best practices with Bonita BPM through live
> exercises
> http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual-
> event?utm_
> source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

Hi Jan,

Yes, I would be interested in learning what you did.

Thanks,

JP

On Mon, Apr 6, 2015 at 6:04 AM, Jan Coombs <th...@mu...> wrote:

> On Sun, 5 Apr 2015 18:22:51 -0400
> Juan Pablo Caram <jp...@gm...> wrote:
>
> > I don't have a clear idea for the architecture yet, but I suspect it is
> not
> > that simple (or maybe it is)...
> >
> > This is what I understand you are referring to:
> >
> > def myADC(value):
> >   @always(clk.posedge)
> >   def logic():
> >     value.next = do_things()
>
> I'm doing a CDP1802 processor, and want full debug control to hookup
> with software tools. I also wanted it to have the same interface
> whether in simulation or on FPGA.
>
> Since small cheap FPGA boards generally have a FTDI comm port, the
> interface is based around byte streams.  In simulation the byte stream
> is crudely connected via mmap'd files.
>
> This allows connection of the hardware or simulation to the support
> tools in other languages, provided it is possible to use mmap in
> those environments, or build a linking module.
>
> Would any details of this help?
>
> Jan Coombs
> --
> email valid, else fix at dots and hyphen
> jan4myhdlatmurrayhyphenmicroftdotcodotuk
>
>
>
> ------------------------------------------------------------------------------
> BPM Camp - Free Virtual Workshop May 6th at 10am PDT/1PM EDT
> Develop your own process in accordance with the BPMN 2 standard
> Learn Process modeling best practices with Bonita BPM through live
> exercises
> http://www.bonitasoft.com/be-part-of-it/events/bpm-camp-virtual-
> event?utm_
> source=Sourceforge_BPM_Camp_5_6_15&utm_medium=email&utm_campaign=VA_SF
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Simulation control

[Juan P. C. <jp...@gm...>]

Hi Christopher,

The link on "mixed mode" simulation is a proof of concept, but very naive.
I've put together a blog post discussing the difficulties that one might
find:

http://caram.cl/developing-a-mixed-signal-simulator

The link about interactive simulation is more along the lines of what would
be required, but using the function calls, not the interactive console. I
see it's using a debugger and that might make it extremely slow. It would
be ideal if this functionality was built into the simulator. If I were to
implement this functionality into the simulator, any idea on where I should
start? I haven't seen any documentation about the operation of the
simulator.

Thanks,

JP

On Mon, Apr 6, 2015 at 8:24 AM, Christopher Felton <chr...@gm...>
wrote:

> On 4/5/15 3:06 PM, Juan Pablo Caram wrote:
> > I apologize for the confusion. I'm hoping to do do this with code, not a
> > debugger. I'm trying to create a mixed signal simulator exchanging data
> > between ngspice and myhdl.
>
> This might be of interest:
> http://old.myhdl.org/doku.php/projects:mixedmodesimulation
> http://old.myhdl.org/doku.php/projects:interactive_simulation_using_ipython
>
> >
> > I would like to be able to simulate until signal X toggles or changes,
> > get the time, run spice until this time is reached, update signals in
> > myhdl and spice, resume myhdl simulation, etc.
>
> Why can't you do this with the existing Python debuggers?
>
> >
> > Sometimes the clock comes from spice, I detect the change in output from
> > a comparator, stop the simulation, and must toggle the corresponding
> > signal in the digital side and resume the digital.
> >
> > I couldn't find any fine controls for the simulation in MyHDL. SimPy,
> > that looks quite similar in terms of using generators, seem to have
> > "simulate until" kind of controls. I wonder if this is already possible
> > or if someone had tried to implement such functionality.
>
> This control does not exist in the MyHDL simulator.
> Currently, you can only instruct the simulator to
> run N simulation steps: `Simulation(test()).run(1000)`
>
> Regards,
> Chris
>
>
>
>
>
>
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Re: [myhdl-list] Simulation control

[Christopher F. <chr...@gm...>]

On 4/5/15 3:06 PM, Juan Pablo Caram wrote:
> I apologize for the confusion. I'm hoping to do do this with code, not a
> debugger. I'm trying to create a mixed signal simulator exchanging data
> between ngspice and myhdl.

This might be of interest:
http://old.myhdl.org/doku.php/projects:mixedmodesimulation
http://old.myhdl.org/doku.php/projects:interactive_simulation_using_ipython

>
> I would like to be able to simulate until signal X toggles or changes,
> get the time, run spice until this time is reached, update signals in
> myhdl and spice, resume myhdl simulation, etc.

Why can't you do this with the existing Python debuggers?

>
> Sometimes the clock comes from spice, I detect the change in output from
> a comparator, stop the simulation, and must toggle the corresponding
> signal in the digital side and resume the digital.
>
> I couldn't find any fine controls for the simulation in MyHDL. SimPy,
> that looks quite similar in terms of using generators, seem to have
> "simulate until" kind of controls. I wonder if this is already possible
> or if someone had tried to implement such functionality.

This control does not exist in the MyHDL simulator.
Currently, you can only instruct the simulator to
run N simulation steps: `Simulation(test()).run(1000)`

Regards,
Chris

Re: [myhdl-list] Simulation control

[Jan C. <th...@mu...>]

On Sun, 5 Apr 2015 18:22:51 -0400
Juan Pablo Caram <jp...@gm...> wrote:

> I don't have a clear idea for the architecture yet, but I suspect it is not
> that simple (or maybe it is)...
> 
> This is what I understand you are referring to:
> 
> def myADC(value):
>   @always(clk.posedge)
>   def logic():
>     value.next = do_things()

I'm doing a CDP1802 processor, and want full debug control to hookup
with software tools. I also wanted it to have the same interface 
whether in simulation or on FPGA. 

Since small cheap FPGA boards generally have a FTDI comm port, the 
interface is based around byte streams.  In simulation the byte stream 
is crudely connected via mmap'd files.  

This allows connection of the hardware or simulation to the support 
tools in other languages, provided it is possible to use mmap in 
those environments, or build a linking module. 

Would any details of this help?

Jan Coombs
-- 
email valid, else fix at dots and hyphen
jan4myhdlatmurrayhyphenmicroftdotcodotuk

Re: [myhdl-list] Simulation control

[Henry G. <he...@ca...>]

On 05/04/15 23:22, Juan Pablo Caram wrote:
> The problem is that I might need to stop for different signals, and 
> having them all call do_things() makes having a centralized control of 
> the mixed-signal simulation environment very complicated. On top of 
> this, how can I know them "time" at which the signal toggle inside the 
> "logic()" function"? I would need that to determine for how long to 
> run the analog simulation.
>
> Even worse, what if "clk" came from the analog simulation... I would 
> have to wait for each analog run complete to know when to toggle it, 
> and then manually toggle it. Here, the myhdl simulation would run 
> "behind".
>
> For short, I don't think I can implement the control of the whole 
> system from a single "do_things()" function. What do you think?

It's not totally clear to me what you're trying to do, but I'm yet to be 
convinced it isn't possible, and certainly yet to be convinced that 
having programmatic access to a debugging layer would be better than 
doing it all inside MyHDL.

You have a stateful spice simulator in a myhdl simulator. The myhdl code 
flips signals as desired until it needs to wait on the simulator doing 
something, then it blocks until the spice simulator reaches a suitable 
state and allows it to continue (let's say, when the virtual ADC flips a 
bit). Presumably you have inputs and outputs to your spice model? At 
some point, surely, you need virtual ADCs and DACs, so you're pretty 
limited in terms of directionality? In which case, you can set inputs as 
you wish and then block on outputs (or output sets).

I don't see the problem with clk - in your clock driver, you just block 
until the spice simulator has moved to the correct state.

Are you trying to do your myhdl logic in an asynchronous way? Or do you 
want sub-cycle times to be somehow meaningful between spice and myhdl (I 
don't have any idea what this could be)?

If you need to run the spice model and the myhdl simulation 
concurrently, you can do so in different threads.

cheers,

Henry