myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] fixbv to current version of myhdl

[Christopher F. <chr...@gm...>]

> These are the results I get
> python
> Python 2.7.3 (default, Sep 26 2013, 20:03:06)
> [GCC 4.6.3] on linux2
> Type "help", "copyright", "credits" or "license" for more information.
>  >>> from myhdl import *
>  >>> ww = (26,18)
>  >>> ca1 = fixbv(-1.586134342)[ww]
>  >>> x2 = fixbv(100.0)[ww]
>  >>> print ca1
> -1.585938
>  >>> print ca1*x2
> -158.593750

Edward,

The above results make sense, I need to look into
why the fixed -> float (for the print) gave a
slightly different value and if it is expected.

Explanation:

   >>> ww = (26,18) # 7 fractional bits
   >>> ca1 = fixbv(-1.586134342)[ww]
   >>> print('{}, {}, {}'.format(
             ca1, repr(ca1), bin(ca1, 26)))

   -1.585938,
   fixbv(-1.585938,  format=(26,18,7), ),
   11111111111111111100110101

 From the above we can see the complete word format

   >>> bv = intbv('11111111111111111100110101')[26:]
   >>> bin(~bv+1, 26)

   '00000000000000000011001011'

The fractional part is .1001011 which is:

   >>> 1/2 + 1/16 + 1/64 + 1/128
   0.5859375

Given this value, the actual fixed-point value the
100 * -1.5859375 = -158.59375 makes sense.

Hope that helps,
Chris

Re: [myhdl-list] fixbv to current version of myhdl

[Jose M. G. C. <ch...@gm...>]

Dear Christopher,

You can find the classes and test under my git user, the fork numerics.

I have done all this work during the last month, but I have had no time to make any docs. Sorry for that. In any case, the way it works is equivalent to the fixed package in VHDL, so you can use it as a base. http://www.eda-stds.org/fphdl/Fixed_ug.pdf

I agree with you that it is going to be tough to make an equivalent in Verilog, but I do not see a solution that does not provide a resize to be useful, at least this is my experience.

In any case, if you have any doubts, feel free to ask and I will give you all the info. But I will not be able to make any docs, at least in a month due to my work, two deadlines in a row.

Best,

Jose M.



> El 02/05/2015, a las 17:47, Christopher Felton <chr...@gm...> escribió:
> 
>> On 5/2/15 10:19 AM, Jose M. Gomez Cama wrote:
>> Dear Edward,
>> 
>> That's the reason for the classes I made, they include the resize an it
>> is fully working.
> 
> Jose,
> 
> If you have some documentation or examples I will
> gladly look at it and provide feedback, otherwise
> your comments are odd and not helpful.
> 
> You can comment on the MEP111 here or review the
> previous mailing-list conversation and provide
> reasonable arguments why you think your approach
> is better than the fixbv approach.  Having to
> create a Verilog version of the VHDL fixed-point
> package to support Verilog conversion is going to
> be a tough sell (IMO).
> 
> Regards,
> Chris
> 
> 
> 
> 
> ------------------------------------------------------------------------------
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> Performance metrics, stats and reports that give you Actionable Insights
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Re: [myhdl-list] fixbv to current version of myhdl

[Henry G. <he...@ca...>]

On 02/05/15 16:47, Christopher Felton wrote:
> On 5/2/15 10:19 AM, Jose M. Gomez Cama wrote:
>> >Dear Edward,
>> >
>> >That's the reason for the classes I made, they include the resize an it
>> >is fully working.
>> >
> Jose,
>
> If you have some documentation or examples I will
> gladly look at it and provide feedback, otherwise
> your comments are odd and not helpful.
>
> You can comment on the MEP111 here or review the
> previous mailing-list conversation and provide
> reasonable arguments why you think your approach
> is better than the fixbv approach.  Having to
> create a Verilog version of the VHDL fixed-point
> package to support Verilog conversion is going to
> be a tough sell (IMO).

I think possibly Jose was just saying he'd written some convertible code 
for fixbv (including a resize) that might be useful; I don't think he's 
trying to step on anyone's toes - I interpreted it as a "Here's what I 
have in case anyone is interested".

Cheers,

Henry

Re: [myhdl-list] fixbv to current version of myhdl

[Henry G. <he...@ca...>]

On 02/05/15 16:47, Christopher Felton wrote:
> On 5/2/15 8:55 AM, Edward Vidal wrote:
>> >Chris,
>> >Athttp://dev.myhdl.org/meps/mep-111.html
>> >Limitations no resize (function yet).
>> >Is this still true?
> There is a resize function but it is not convertible
> at this point.  I can make a convertible version but
> I didn't like how it worked out, been experimenting
> with other methods.  The existing resize function
> can be used for modeling and testing at this point.
>

How does it work?

I've been playing with the routines in flopoco 
(https://gforge.inria.fr/scm/?group_id=1030), which (among other nicely 
portable tools) has a nice tool for resizing - actually it's a zero 
counter and a shift left, so the essence of a resize.

It's the next thing I'm going to be implementing so it would be great to 
combine effort on this. I'm not currently using fixbv, but a kind of 
meta type of an intbv and a separate exponent.

Cheers,

Henry

Re: [myhdl-list] fixbv to current version of myhdl

[Christopher F. <chr...@gm...>]

On 5/1/15 4:16 PM, Jose M. Gomez Cama wrote:
> Dear all,
>
> I have created a series of new types that allow to work with fixed point
> and is compatible with the fixed point from VHDL. I am still working on
> it, but it is presently compatible with GHDL, vcom and symplify.
>
> I have not published it before because it uses a new base class,
> bitarray. I have also created classes for the signed and unsigned types.
> It still requires some tunning, because it is slower than intbv, as it
> is fully object oriented, which adds some overhead.
>
> I do not know how to proceed as the number of changes is quite large.
> And I wanted to discuss it before hand, but as I saw this mail, I
> thought it could be useful.
>
> In brief, the package is in git, under the user jmgc, fork numeric.

This approach sounds like it would be an additional pkg
bolt on and not part of myhdl?

>
> And Jan, if you think it can be added to myhdl, please, tell me how I
> shall proceed.

Typically, for a new feature the best approach is to
follow the development guidelines, which include creating
a MEP and discussing on the mailing-list:

http://dev.myhdl.org/guide/guide.html#contributing-changes
http://dev.myhdl.org/meps/mep-001.html

Regards,
Chris

Re: [myhdl-list] fixbv to current version of myhdl

[Christopher F. <chr...@gm...>]

On 5/2/15 8:55 AM, Edward Vidal wrote:
> Chris,
> At http://dev.myhdl.org/meps/mep-111.html
> Limitations no resize (function yet).
> Is this still true?

There is a resize function but it is not convertible
at this point.  I can make a convertible version but
I didn't like how it worked out, been experimenting
with other methods.  The existing resize function
can be used for modeling and testing at this point.

> I see that you have a myhdl/_resize.py (in this merge).
>
> The steps you provided worked okay on my Ubuntu system.
>
> I will be trying on my Windows 8.1 box.
> What does "develop" do when used in the setup.py?

If you use:

     >> python setup.py develop

The snapshot (repo) will be used and you will not
need to do subsequent `setup.py installs` after
updates.

>
> These are the results I get
> python
> Python 2.7.3 (default, Sep 26 2013, 20:03:06)
> [GCC 4.6.3] on linux2
> Type "help", "copyright", "credits" or "license" for more information.
>  >>> from myhdl import *
>  >>> ww = (26,18)
>  >>> ca1 = fixbv(-1.586134342)[ww]
>  >>> x2 = fixbv(100.0)[ww]
>  >>> print ca1
> -1.585938
>  >>> print ca1*x2
> -158.593750

I will walk through the above example, initial
conversion, the operation etc. but I will need
wait till later today.

Regards,
Chris

Re: [myhdl-list] fixbv to current version of myhdl

[Christopher F. <chr...@gm...>]

On 5/2/15 10:19 AM, Jose M. Gomez Cama wrote:
> Dear Edward,
>
> That's the reason for the classes I made, they include the resize an it
> is fully working.
>

Jose,

If you have some documentation or examples I will
gladly look at it and provide feedback, otherwise
your comments are odd and not helpful.

You can comment on the MEP111 here or review the
previous mailing-list conversation and provide
reasonable arguments why you think your approach
is better than the fixbv approach.  Having to
create a Verilog version of the VHDL fixed-point
package to support Verilog conversion is going to
be a tough sell (IMO).

Regards,
Chris

Re: [myhdl-list] fixbv to current version of myhdl

[Jose M. G. C. <ch...@gm...>]

Dear Edward,

That's the reason for the classes I made, they include the resize an it is fully working.

Best,

Jose M.

> El 02/05/2015, a las 15:55, Edward Vidal <dev...@sb...> escribió:
> 
> Chris,
> At http://dev.myhdl.org/meps/mep-111.html
> Limitations no resize (function yet).   
> Is this still true?  
> I see that you have a myhdl/_resize.py (in this merge).
> 
> The steps you provided worked okay on my Ubuntu system.  
> 
> I will be trying on my Windows 8.1 box.
> What does "develop" do when used in the setup.py?
> 
> These are the results I get 
> python 
> Python 2.7.3 (default, Sep 26 2013, 20:03:06) 
> [GCC 4.6.3] on linux2
> Type "help", "copyright", "credits" or "license" for more information.
> >>> from myhdl import *
> >>> ww = (26,18)
> >>> ca1 = fixbv(-1.586134342)[ww]
> >>> x2 = fixbv(100.0)[ww]
> >>> print ca1
> -1.585938
> >>> print ca1*x2
> -158.593750
> Thanks 
> Regards
>  
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
> 
> 
> 
> On Friday, May 1, 2015 4:14 PM, Christopher Felton <chr...@gm...> wrote:
> 
> 
> On 5/1/15 2:36 PM, Edward Vidal wrote:
> > Hello all,
> > I need Chris's fixbv in myhdl current 6afefa 04/28/15.
> > What is the preferred method to add fixbv support?
> > I have _fixbv.py from an older version. This  wants to import from
> > _intbv import intbv & from _simulator import  now.
> > Are these the only files that I need in my current working directory?
> > Is fixbv going to be added sometime soon?
> 
> The latest fixbv implementation is available on my
> myhdl fork:
> 
> https://github.com/cfelton/myhdl/tree/mep111_fixbv
> 
> I believe you are familiar with the MEP that describes
> the feature:
> http://dev.myhdl.org/meps/mep-111.html
> 
> Some additional information here:
> http://www.dsprelated.com/showarticle/580.php (at the end)
> 
> 
> To merge the fixbv into your clone you should be able to
> do the following:
> 
>   >> cd <to your myhdl clone>
>   >> git remote add fixbv_repo https://github.com/cfelton/myhdl
>   >> git pull fixbv_repo mep111_fixbv
>   >> sudo python setup.py develop
> 
> This will pull the fixbv into your MyHDL. When there are
> updates you can update with a pull.
> 
> Let me know if you have any issues.
> 
> Regards,
> 
> Chris
> 
> 
> 
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud 
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> 
> 
> 
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud 
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] fixbv to current version of myhdl

[Edward V. <dev...@sb...>]

Chris,At http://dev.myhdl.org/meps/mep-111.htmlLimitations no resize (function yet).   
Is this still true?  
I see that you have a myhdl/_resize.py (in this merge).

The steps you provided worked okay on my Ubuntu system.  

I will be trying on my Windows 8.1 box.What does "develop" do when used in the setup.py?
These are the results I get 
python 
Python 2.7.3 (default, Sep 26 2013, 20:03:06) 
[GCC 4.6.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> from myhdl import *
>>> ww = (26,18)
>>> ca1 = fixbv(-1.586134342)[ww]
>>> x2 = fixbv(100.0)[ww]
>>> print ca1
-1.585938
>>> print ca1*x2
-158.593750
Thanks 
Regards
 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Friday, May 1, 2015 4:14 PM, Christopher Felton <chr...@gm...> wrote:
   

 On 5/1/15 2:36 PM, Edward Vidal wrote:
> Hello all,
> I need Chris's fixbv in myhdl current 6afefa 04/28/15.
> What is the preferred method to add fixbv support?
> I have _fixbv.py from an older version. This  wants to import from
> _intbv import intbv & from _simulator import  now.
> Are these the only files that I need in my current working directory?
> Is fixbv going to be added sometime soon?

The latest fixbv implementation is available on my
myhdl fork:

https://github.com/cfelton/myhdl/tree/mep111_fixbv

I believe you are familiar with the MEP that describes
the feature:
http://dev.myhdl.org/meps/mep-111.html

Some additional information here:
http://www.dsprelated.com/showarticle/580.php  (at the end)


To merge the fixbv into your clone you should be able to
do the following:

  >> cd <to your myhdl clone>
  >> git remote add fixbv_repo https://github.com/cfelton/myhdl
  >> git pull fixbv_repo mep111_fixbv
  >> sudo python setup.py develop

This will pull the fixbv into your MyHDL. When there are
updates you can update with a pull.

Let me know if you have any issues.

Regards,
Chris


------------------------------------------------------------------------------
One dashboard for servers and applications across Physical-Virtual-Cloud 
Widest out-of-the-box monitoring support with 50+ applications
Performance metrics, stats and reports that give you Actionable Insights
Deep dive visibility with transaction tracing using APM Insight.
http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
_______________________________________________
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https://lists.sourceforge.net/lists/listinfo/myhdl-list


  

Re: [myhdl-list] fixbv to current version of myhdl

[Christopher F. <chr...@gm...>]

On 5/1/15 2:36 PM, Edward Vidal wrote:
> Hello all,
> I need Chris's fixbv in myhdl current 6afefa 04/28/15.
> What is the preferred method to add fixbv support?
> I have _fixbv.py from an older version. This  wants to import from
> _intbv import intbv & from _simulator import  now.
> Are these the only files that I need in my current working directory?
> Is fixbv going to be added sometime soon?

The latest fixbv implementation is available on my
myhdl fork:

https://github.com/cfelton/myhdl/tree/mep111_fixbv

I believe you are familiar with the MEP that describes
the feature:
http://dev.myhdl.org/meps/mep-111.html

Some additional information here:
http://www.dsprelated.com/showarticle/580.php  (at the end)


To merge the fixbv into your clone you should be able to
do the following:

   >> cd <to your myhdl clone>
   >> git remote add fixbv_repo https://github.com/cfelton/myhdl
   >> git pull fixbv_repo mep111_fixbv
   >> sudo python setup.py develop

This will pull the fixbv into your MyHDL. When there are
updates you can update with a pull.

Let me know if you have any issues.

Regards,
Chris

Re: [myhdl-list] fixbv to current version of myhdl

[Jose M. G. C. <ch...@gm...>]

Dear all,

I have created a series of new types that allow to work with fixed point and is compatible with the fixed point from VHDL. I am still working on it, but it is presently compatible with GHDL, vcom and symplify.

I have not published it before because it uses a new base class, bitarray. I have also created classes for the signed and unsigned types. It still requires some tunning, because it is slower than intbv, as it is fully object oriented, which adds some overhead.

I do not know how to proceed as the number of changes is quite large. And I wanted to discuss it before hand, but as I saw this mail, I thought it could be useful.

In brief, the package is in git, under the user jmgc, fork numeric.

And Jan, if you think it can be added to myhdl, please, tell me how I shall proceed.

Just a last comment, I have not made a Verilog version because I lack the knowledge. But it should not be difficult to make functions that provide this functionality. There is a group of functions in opencores that can serve as a base.

Best regards,

Jose M.


> El 01/05/2015, a las 21:36, Edward Vidal <dev...@sb...> escribió:
> 
> Hello all,
> I need Chris's fixbv in myhdl current 6afefa 04/28/15. 
> What is the preferred method to add fixbv support?
> I have _fixbv.py from an older version. This  wants to import from _intbv import intbv & from _simulator import  now. 
> Are these the only files that I need in my current working directory? 
> Is fixbv going to be added sometime soon?
> 
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud 
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

[myhdl-list] fixbv to current version of myhdl

[Edward V. <dev...@sb...>]

Hello all,I need Chris's fixbv in myhdl current 6afefa 04/28/15.  What is the preferred method to add fixbv support?I have _fixbv.py from an older version. This  wants to import from _intbv import intbv & from _simulator import  now.  Are these the only files that I need in my current working directory? Is fixbv going to be added sometime soon?
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Christopher F. <chr...@gm...>]

On 4/27/2015 7:38 AM, Christopher Felton wrote:
> On 4/27/2015 12:17 AM, Günther Stangassinger wrote:
>> Thank you very much for your hint.
>> I was trying this.
>> The clock ist now running only when CSn is low.
>> But without success. :-(
>> There is still 0x0 as out put.
>> Does anybody else have any hints?
>
> There are some changes you should make, in this design
> you should only have a single clock for the internal
> logic.  The DEnano has a 50MHz clock, this should be
> the clock driving all your processes/generators.  Don't
> use the generated SCLK to clock any internal logic.
>

Warning like the following should be fixed, remove `tick`
and `tick2` as clocks and only use `CLOCK_50` as a clock:

     Warning (332060): Node: tick was determined to be a clock
     but was found without an associated clock assignment.
     Warning (332060): Node: tick2 was determined to be a clock
     but was found without an associated clock assignment.

Regards,
Chris

Re: [myhdl-list] Hello World (and tristates)

[Christopher F. <chr...@gm...>]

Gunther,

I put together a simple ADXL345 3-wire SPI model,
this might give you something to play with and test.

https://gist.github.com/cfelton/2a0106edc5bd2b1bec4c

In your test_dff add:

      mdl = ADXL345()
      gmdl = mdl.process(I2C_SCLK, I2C_SDAT,
                         G_SENSOR_CS_N, G_SENSOR_INT)

Don't forget to add `gmdl` to the return list.

I also added this around line 92 to "emulate"
a pullup (for simulation only):

      # emulate a pullup
      sdati = Signal(bool(0))
      def _pullup(I2C_SDAT, sdati):
          @always_comb
          def emupull():
              if I2C_SDAT == None:
                  sdati.next = True
              else:
                  sdati.next = False
          return emupull
      _pullup.verilog_code = 'assign $sdati = $I2C_SDAT'

      gpull = _pullup(I2C_SDAT, sdati)


Regards,
Chris

On 4/27/2015 7:38 AM, Christopher Felton wrote:
> On 4/27/2015 12:17 AM, Günther Stangassinger wrote:
>> Thank you very much for your hint.
>> I was trying this.
>> The clock ist now running only when CSn is low.
>> But without success. :-(
>> There is still 0x0 as out put.
>> Does anybody else have any hints?
>
> There are some changes you should make, in this design
> you should only have a single clock for the internal
> logic.  The DEnano has a 50MHz clock, this should be
> the clock driving all your processes/generators.  Don't
> use the generated SCLK to clock any internal logic.
>
> Then create posedge and negedge strobes based on the
> slower clock (or you can do it vise-versa have state
> machine that creates the edge strobes and the clock
> generated from there).
>
> Here is an example:
> https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23/aic23_spi.py?at=default#cl-96
> http://www.fpgarelated.com/showarticle/41.php
>
>> If you are saying the Tristatesignal is looking ok,
>> than mybe  i should focus on the sequence to read the DEVID.
>> Thank you very much.
>
> The tristate looks ok in the simulation (not fully
> decoding the bus transaction).  Personally I would
> break out the when/how the tristate is driven to
> a separate process/generator:
>
>       bitout = Signal(bool(0))
>       io = I2C_SDAT.driver()
>
>       # ....
>
>       @always_comb
>       def tristate_driver():
>           if count > 0 and count < 11:
> 	    io.next = None
>           else:
>               io.next = bitout
>
> Only the tristate is the output of this process.
> This shouldn't functionally change your code but in
> the converted code you will have a simple expression
> for the tristate.
>
> Regards,
> Chris
>

Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Christopher F. <chr...@gm...>]

On 4/27/2015 12:17 AM, Günther Stangassinger wrote:
> Thank you very much for your hint.
> I was trying this.
> The clock ist now running only when CSn is low.
> But without success. :-(
> There is still 0x0 as out put.
> Does anybody else have any hints?

There are some changes you should make, in this design
you should only have a single clock for the internal
logic.  The DEnano has a 50MHz clock, this should be
the clock driving all your processes/generators.  Don't
use the generated SCLK to clock any internal logic.

Then create posedge and negedge strobes based on the
slower clock (or you can do it vise-versa have state
machine that creates the edge strobes and the clock
generated from there).

Here is an example:
https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23/aic23_spi.py?at=default#cl-96
http://www.fpgarelated.com/showarticle/41.php

> If you are saying the Tristatesignal is looking ok,
> than mybe  i should focus on the sequence to read the DEVID.
> Thank you very much.

The tristate looks ok in the simulation (not fully
decoding the bus transaction).  Personally I would
break out the when/how the tristate is driven to
a separate process/generator:

     bitout = Signal(bool(0))
     io = I2C_SDAT.driver()

     # ....

     @always_comb
     def tristate_driver():
         if count > 0 and count < 11:
	    io.next = None
         else:
             io.next = bitout

Only the tristate is the output of this process.
This shouldn't functionally change your code but in
the converted code you will have a simple expression
for the tristate.

Regards,
Chris

Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Günther S. <gue...@gm...>]

Thank you very much for your hint.
I was trying this.
The clock ist now running only when CSn is low.
But without success. :-(
There is still 0x0 as out put.
Does anybody else have any hints?
If you are saying the Tristatesignal is looking ok,
than mybe  i should focus on the sequence to read the DEVID.
Thank you very much.
Regards,
guenther


Am 26.04.2015 um 20:12 schrieb Christopher Felton:
> On 4/26/15 10:45 AM, Günther Stangassinger wrote:
>> Are you sure?
> No, I am not sure.  I am not familiar with 3 wire
> SPI (seems odd) and when I looked at the datasheet,
> quickly ...
>
>> This is not a 4-Wire SPI. It is a 3 wire SPI.
>> For a 4 wire  there are extra ports for reading and writing,
>> but with 3-wire the SDIO-port has the possibility to set a read or a
>> write bit
>> from the accelerometer wich is described here:
>> http://www.geeetech.com/Documents/ADXL345%20Datasheet.pdf
>> And this SDIO-port of the accelerometer is connected with I2C_SDAT of
>> the Altera CyclonIV
> I see (now) that the DE board is only connected
> to support 3-wire SPI or I2C, as you indicated:
> http://www.terasic.com/downloads/cd-rom/de0-nano/
>
> I agree, the tristate is required.
>
>> The problem is, that i do not know wheater i am doing something wrong
>> with the
>> bite sequences, which get into the accelerometer.
>> So i whould very much appreciate, if someone could
>> just run the simulation and take a look at the bitsequence in
>> gtkwave and say if this bit sequence is making sense at all,
>> or i am doing something really strange here?
> I ran you code, something to try is only enable
> the clock during a valid transaction, when CSn is
> low, don't use a free running clock, as shown in
> figure 39:
> http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
>
> Digging through the complete SPI transaction requires
> more time than I have right now.
>
> Regards,
> Chris
>
>
>
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Re: [myhdl-list] Hello World

[Christopher F. <chr...@gm...>]

On 4/26/15 10:45 AM, Günther Stangassinger wrote:
> Are you sure?

No, I am not sure.  I am not familiar with 3 wire
SPI (seems odd) and when I looked at the datasheet,
quickly ...

> This is not a 4-Wire SPI. It is a 3 wire SPI.
> For a 4 wire  there are extra ports for reading and writing,
> but with 3-wire the SDIO-port has the possibility to set a read or a
> write bit
> from the accelerometer wich is described here:
> http://www.geeetech.com/Documents/ADXL345%20Datasheet.pdf
> And this SDIO-port of the accelerometer is connected with I2C_SDAT of
> the Altera CyclonIV

I see (now) that the DE board is only connected
to support 3-wire SPI or I2C, as you indicated:
http://www.terasic.com/downloads/cd-rom/de0-nano/

I agree, the tristate is required.

> The problem is, that i do not know wheater i am doing something wrong
> with the
> bite sequences, which get into the accelerometer.
> So i whould very much appreciate, if someone could
> just run the simulation and take a look at the bitsequence in
> gtkwave and say if this bit sequence is making sense at all,
> or i am doing something really strange here?

I ran you code, something to try is only enable
the clock during a valid transaction, when CSn is
low, don't use a free running clock, as shown in
figure 39:
http://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf

Digging through the complete SPI transaction requires
more time than I have right now.

Regards,
Chris

Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Günther S. <gue...@gm...>]

Are you sure?
This is not a 4-Wire SPI. It is a 3 wire SPI.
For a 4 wire  there are extra ports for reading and writing,
but with 3-wire the SDIO-port has the possibility to set a read or a 
write bit
from the accelerometer wich is described here:
http://www.geeetech.com/Documents/ADXL345%20Datasheet.pdf
And this SDIO-port of the accelerometer is connected with I2C_SDAT of 
the Altera CyclonIV
The problem is, that i do not know wheater i am doing something wrong 
with the
bite sequences, which get into the accelerometer.
So i whould very much appreciate, if someone could
just run the simulation and take a look at the bitsequence in
gtkwave and say if this bit sequence is making sense at all,
or i am doing something really strange here?
Thank you very much.
Regards,
guenther






Am 26.04.2015 um 15:13 schrieb Christopher Felton:
> On 4/26/15 12:06 AM, Günther Stangassinger wrote:
>> Thank you for your quick response.
>> Yes it is the latest board with cyclone-IV
>> No, i am communicating over SPI.
> If you are using SPI you do not need a tristate,
> only I2C requires a tri-state for the SDA bi-direction
> (usually don't need one for SCL).
>
> If you are using SPI I would remove the tristate.
> Make sure the CSn signal goes low, didn't review
> the data sheet fully, don't know if it can be tied
> low or if it needs the transition.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] IP core library

[Christopher F. <chr...@gm...>]

On 4/25/15 4:49 PM, Euripedes Rocha Filho wrote:
>
>
> 2015-04-25 18:15 GMT-03:00 Christopher Felton <chr...@gm...
> <mailto:chr...@gm...>>:
>
>     On 4/25/15 1:54 PM, Euripedes Rocha Filho wrote:
>     > Hi,
>     > I'm starting a small (actually no IP so far) library and wondering if
>      > someone has some suggestion on how to structure it.Â
>
>     This is great, more IP (cores) development the
>     better.  Using common Python package structure
>     is a good place to start.
>
>     There are various projects out there,
>     here are a couple that you can look at:
>
>     This is my small collection of "cores", I slowly
>     add to it as I have time ...
>     https://github.com/cfelton/minnesota
>
>     FPGA digital radio (SDR) using MyHDL:
>     https://github.com/testaco/whitebox
>
>     Keerthan's HDL toolbox:
>     https://github.com/jck/uhdl
>
>     >
>     > The repository (just started the package using cookiecutter)
>      > Â https://github.com/euripedesrocha/instar
>     >
>     > My idea is to use MyHDL as both simulation and hdl decription language,
>     > using verilog conversion to put the design under the regular FPGA work
>     > flow ( also I'll use Chistopher's myhdl_tools package in the build flow ).
>     >
>
>     Note, I have moved the FPGA flow from myhdl_tools
>     to gizflo (couple reasons why and I can explain
>     if interested)
>     https://github.com/cfelton/gizflo
>
>
> I'll follow your movement and will clone and eventually contribute to
> gizflo.Â
>
>
>
>     > What I have in mind now is:
>     >
>     > There's any advantage in use a class packing the interface signals and a
>     > method with the hardware description, or use another structure?
>
>     This depends, in my opinion you don't want to go
>     class/object crazy :)Â  Creating clean interfaces
>     will help the code a ton.  I tend to keep my main
>     modules not part of a class but for models I include
>     many myhdl generators in a class.
>
>
> I want to pack the interface to be as simple as possible. I'm using a
> class to pack all signals interface in my simulations I think I will
> have all modules with a class named interface+a generator for each mode
> of operation. Later I'll think in a way to add Wishbone and AXI
> interface to modules and keep some regularity among interfaces.
>

I agree, use a class to define the various interfaces.

Here is how I did the mem-map bus interfaces:

Wishbone
https://github.com/cfelton/minnesota/blob/master/mn/system/memmap/_wishbone.py#L35

Avalon:
https://github.com/cfelton/minnesota/blob/master/mn/system/memmap/_avalonmm.py#L35

Each interface has some modules associated with them, e.g. the
bus interconnect etc.  In the `mn` project, the main components
will be functions (e.g. SPI controller) and a memmap interface
is passed that then can be tied to a register-file.  The goal
is to have concise and flexible interfaces to each module.

Toy example in use:
https://github.com/cfelton/minnesota/blob/master/examples/designs/btn_led_mm/btn_led_mm.py

Most of this (above) is WIP hopefully it will help as
an example what can be done.

Here is another example of building test environment and creating
AXI interfaces (stream only):
http://www.alexforencich.com/wiki/en/verilog/start
https://github.com/alexforencich/verilog-axis/blob/master/tb/axis_ep.py

Regards,
Chris

Re: [myhdl-list] Hello World

[Christopher F. <chr...@gm...>]

On 4/26/15 12:06 AM, Günther Stangassinger wrote:
> Thank you for your quick response.
> Yes it is the latest board with cyclone-IV
> No, i am communicating over SPI.

If you are using SPI you do not need a tristate,
only I2C requires a tri-state for the SDA bi-direction
(usually don't need one for SCL).

If you are using SPI I would remove the tristate.
Make sure the CSn signal goes low, didn't review
the data sheet fully, don't know if it can be tied
low or if it needs the transition.

Regards,
Chris

Re: [myhdl-list] IP core library

[Henry G. <he...@ca...>]

On 26/04/15 11:30, Euripedes Rocha Filho wrote:
> 2015-04-26 5:16 GMT-03:00 Henry Gomersall <he...@ca... 
> <mailto:he...@ca...>>:
>
>     On 25/04/15 22:49, Euripedes Rocha Filho wrote:
>     > I'm doing some personal variation of TDD, lots of unit testing
>     but not
>     > "driving" the development. I'm not that religious :)
>
>     So you're not doing TDD at all then, you're just doing testing. TDD is
>     useful precisely because the tests are written first.
>
>     Switching to TDD is a total mindset switch (hence your religious
>     comment). It basically becomes psychologically impossible to write
>     untested code.
>
> Yes, but you will agree that such a mindset take some time to build,

I find one just has to do it. I did a project that was half-arsed for a 
while and it never felt complete.

Only when I decided to do it properly did I fully grok the joy.

>
>     I'm actually an advocate of BDD over TDD, as behaviour is actually
>     what
>     one cares about.
>
>
> I did some read about BDD but didn't practice it yet.

This is a really interesting and I think pretty misunderstood field. I 
recommend this blog post:
http://hadihariri.com/2012/04/11/what-bdd-has-taught-me/

I wrote a bit about it myself in light of that post:
https://hgomersall.wordpress.com/2014/10/03/from-test-driven-development-and-specifications/

Great stuff!

hen

Re: [myhdl-list] IP core library

[Euripedes R. F. <roc...@gm...>]

2015-04-26 5:16 GMT-03:00 Henry Gomersall <he...@ca...>:

> On 25/04/15 22:49, Euripedes Rocha Filho wrote:
> > I'm doing some personal variation of TDD, lots of unit testing but not
> > "driving" the development. I'm not that religious :)
>
> So you're not doing TDD at all then, you're just doing testing. TDD is
> useful precisely because the tests are written first.
>
> Switching to TDD is a total mindset switch (hence your religious
> comment). It basically becomes psychologically impossible to write
> untested code.
>
>
Yes, but you will agree that such a mindset take some time to build,


> I'm actually an advocate of BDD over TDD, as behaviour is actually what
> one cares about.
>

I did some read about BDD but didn't practice it yet.


>
> Cheers,
>
> Henry
>
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] IP core library

[Henry G. <he...@ca...>]

On 25/04/15 22:49, Euripedes Rocha Filho wrote:
> I'm doing some personal variation of TDD, lots of unit testing but not 
> "driving" the development. I'm not that religious :)

So you're not doing TDD at all then, you're just doing testing. TDD is 
useful precisely because the tests are written first.

Switching to TDD is a total mindset switch (hence your religious 
comment). It basically becomes psychologically impossible to write 
untested code.

I'm actually an advocate of BDD over TDD, as behaviour is actually what 
one cares about.

Cheers,

Henry

Re: [myhdl-list] *** GMX Spamverdacht *** Re: Hello World

[Günther S. <gue...@gm...>]

Thank you for your quick response.
Yes it is the latest board with cyclone-IV
No, i am communicating over SPI.
This is just the port name wich has I2C in the name.
I am sorry it is not in a github.
I think it is just to small.
The point is, i am not shure if i am using the tristate signal wich i
call "io" in a correct way.
When i look at the simulation, then i have
according to the altera documentation:
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/de0_nano_user_manual_v1.9.pdf
the adress 0x31 set with the value 0x40
after that i am trying to read the DEVID from the adress 0x00
which is 0x80 because i am setting the read-bit in the SPI-3 wire mode.
after that at the position for reading the DEVID is according to the 
simulation in a NONE Value of the tristate port.
So it is looking ok for me, but there is some error.
Mybe i am not using the tristate signal in a correct way.
If you could tell me if the tristate signal looks ok in myhdl - way than 
it would help me
a lot, than i would guess, that i still miss something in the SPI 
communication.
Than you very much.
;-)guenther






Am 25.04.2015 um 23:26 schrieb Christopher Felton:
> On 4/25/15 1:12 PM, Günther Stangassinger wrote:
>> Hello,
>> i am quite new to Myhdl and playing around with the de0-nano Board.
>> I was trying to access the  ADXL345 over the SPI 3 wire bus. (just
>> trying to read the DEVID)
>> The small code example is working in simulation mode as far as i can judge.
>> But on the real board i get 0x0 for the DEVID which should be 0xE5
> Is this the latest DE0 with the cyclone-IV?
>
> If you are intending to communicate over I2C are
> you keeping the CSn signal high to the ADXL345?
> (I have dug through the code yet).  If you are
> not
>
> Do you have this in a public repo, like github
> or bitbucket?
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
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>


-- 
Mit freundlichen Grüßen
Günther Stangassinger

Re: [myhdl-list] IP core library

[Euripedes R. F. <roc...@gm...>]

2015-04-25 18:15 GMT-03:00 Christopher Felton <chr...@gm...>:

> On 4/25/15 1:54 PM, Euripedes Rocha Filho wrote:
> > Hi,
> > I'm starting a small (actually no IP so far) library and wondering if
> > someone has some suggestion on how to structure it.Â
>
> This is great, more IP (cores) development the
> better.  Using common Python package structure
> is a good place to start.
>
> There are various projects out there,
> here are a couple that you can look at:
>
> This is my small collection of "cores", I slowly
> add to it as I have time ...
> https://github.com/cfelton/minnesota
>
> FPGA digital radio (SDR) using MyHDL:
> https://github.com/testaco/whitebox
>
> Keerthan's HDL toolbox:
> https://github.com/jck/uhdl
>
> >
> > The repository (just started the package using cookiecutter)
> > Â https://github.com/euripedesrocha/instar
> >
> > My idea is to use MyHDL as both simulation and hdl decription language,
> > using verilog conversion to put the design under the regular FPGA work
> > flow ( also I'll use Chistopher's myhdl_tools package in the build flow
> ).
> >
>
> Note, I have moved the FPGA flow from myhdl_tools
> to gizflo (couple reasons why and I can explain
> if interested)
> https://github.com/cfelton/gizflo


I'll follow your movement and will clone and eventually contribute to
gizflo.


>
> > What I have in mind now is:
> >
> > There's any advantage in use a class packing the interface signals and a
> > method with the hardware description, or use another structure?
>
> This depends, in my opinion you don't want to go
> class/object crazy :)  Creating clean interfaces
> will help the code a ton.  I tend to keep my main
> modules not part of a class but for models I include
> many myhdl generators in a class.
>

I want to pack the interface to be as simple as possible. I'm using a class
to pack all signals interface in my simulations I think I will have all
modules with a class named interface+a generator for each mode of
operation. Later I'll think in a way to add Wishbone and AXI interface to
modules and keep some regularity among interfaces.



>
> >
> > Any thoughts?
>
> One of the things you should do early is how you
> want to structure the tests.  I would suggest using
> py.test and following some of their suggestions:
> https://pytest.org/latest/goodpractises.html


I'm already using a pytest structure for testing VHDL in my job. I'm using
a "template" and adding tests when needed. I'm doing this since it's a
legacy module.


>
>
> Following a TDD flow would be an good idea but takes
> some discipline.
>
>
I'm doing some personal variation of TDD, lots of unit testing but not
"driving" the development. I'm not that religious :)


Regards

Euripedes

> Regards,
> Chris
>
>
>
>
>
>
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>