myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] TypeError: Unexpected type

[Christopher F. <chr...@gm...>]

On 3/26/15 2:22 AM, Guy Eschemann wrote:
> The workarounds you showed were actually how my initial code looked
> like. It converted to Verilog without errors, but I got synthesis errors
> because of the variable bounds in the array slices. That's why I wrote
> this ugly if-block which triggered the conversion error.

Yes, it would be a nice addition to detect this case
and flag a warning or use the Verilog-2001 [base += range]
variable part select.

Regards,
Chris

Re: [myhdl-list] TypeError: Unexpected type

[Christopher F. <chr...@gm...>]

On 3/26/15 2:25 AM, Guy Eschemann wrote:
> Thanks Chris, that does the trick.

This has been fixed in the master branch, if you
get the latest your original code should work.

https://github.com/jandecaluwe/myhdl/issues/40
https://github.com/jandecaluwe/myhdl/pull/41

Regards,
Chris

>
>
>     You can work around it with:
>
>     In [5]: from myhdl import *
>     Â  Â  ...:
>     Â  Â  ...: def mpegChannel(clk, rst):
>     Â  Â  ...:
>     Â  Â  ...:Â  Â  Â s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])
>
>     Â  Â  ...:Â  Â  Â # *** limited range type for switch ***
>     Â  Â  ...:Â  Â  Â full_case = intbv(0, min=0, max=4)
>
>     Â  Â  ...:Â  Â  Â @always_seq(clk.posedge, rst)
>     Â  Â  ...:Â  Â  Â def fsm_seq():
>     Â  Â  ...:Â  Â  Â  Â  Â for i in range(4):
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â full_case[:] = i
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â if full_case == 0:
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â  Â  Â s_tx_data_xor_mask_r.next[1 +
>     7:0] = 0
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â elif full_case == 1:
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â  Â  Â s_tx_data_xor_mask_r.next[1 +
>     15:8] = 1
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â elif full_case == 2:
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â  Â  Â s_tx_data_xor_mask_r.next[1 +
>     23:16] = 2
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â else:
>     Â  Â  ...:Â  Â  Â  Â  Â  Â  Â  Â  Â s_tx_data_xor_mask_r.next[1 +
>     31:24] = 3
>     Â  Â  ...:
>     Â  Â  ...:Â  Â  Â return instances()
>
>     The limitation is, when evaluating an if-else structure
>     the conversion code wants to determine if it full-case
>     or not, because the variable switched on is an `int` it
>     throws the type error.  But the code example seems reasonable,
>     I think?
>
>     Regards,
>     Chris
>
>
>
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Re: [myhdl-list] TypeError: Unexpected type

[Guy E. <guy...@gm...>]

Thanks Chris, that does the trick.


> You can work around it with:
>
> In [5]: from myhdl import *
>     ...:
>     ...: def mpegChannel(clk, rst):
>     ...:
>     ...:     s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])
>
>     ...:     # *** limited range type for switch ***
>     ...:     full_case = intbv(0, min=0, max=4)
>
>     ...:     @always_seq(clk.posedge, rst)
>     ...:     def fsm_seq():
>     ...:         for i in range(4):
>     ...:             full_case[:] = i
>     ...:             if full_case == 0:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 7:0] = 0
>     ...:             elif full_case == 1:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 15:8] = 1
>     ...:             elif full_case == 2:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 23:16] = 2
>     ...:             else:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 31:24] = 3
>     ...:
>     ...:     return instances()
>
> The limitation is, when evaluating an if-else structure
> the conversion code wants to determine if it full-case
> or not, because the variable switched on is an `int` it
> throws the type error.  But the code example seems reasonable,
> I think?
>
> Regards,
> Chris
>
>

Re: [myhdl-list] TypeError: Unexpected type

[Guy E. <guy...@gm...>]

The workarounds you showed were actually how my initial code looked like.
It converted to Verilog without errors, but I got synthesis errors because
of the variable bounds in the array slices. That's why I wrote this ugly
if-block which triggered the conversion error.

I tried two other workarounds:
> def mpegChannel(clk, rst, s_tx_data_xor_mask_r):
>
>     @always_seq(clk.posedge, reset=rst)
>     def fsm_seq():
>         for i in range(4):
>             s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = i
>
>     return instances()
>
> and:
> def mpegChannel(clk, rst, s_tx_data_xor_mask_r):
>
>     table = tuple([9,8,7,6])
>
>     @always_seq(clk.posedge, reset=rst)
>     def fsm_seq():
>         for i in range(4):
>             s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = table[i]
>
>
>     return instances()
>
> The second allows for any value to be loaded.
> Both convert fine.
>
>

Re: [myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

Hello All,
Continued to try and add instance of matrix_wrap.vhd
made manual chg's now do not get errors.The chg's I made are in the file at GitHub."https://github.com/develone/jpeg-2000-test/blob/master/
jpeg2k/parallel_jpeg/chgsto_matrix_wrap_vhd.txt"
Should these chg's need to be done or should MyHDL make them?
Now, I can map 3 instances of matrix_wrap_lf_u1
  matrix_wrap_lf_u1 : matrix_wrap PORT MAP (
         flat => flat_lf,
   z => z_lf,
   x => x_lf,
   mrow => mrow_lf,
   mcol => mcol_lf
  );

These items were added to tbjp_processvhd.vhd.
 type t11 is array (0 to 3) of unsigned(9 downto 0);
 type t1 is array (0 to 3) of t11;
 
 signal a : t1:=(others => (others => (others => '0')));
I was hoping a would be a 4 x 4 matrix.This is where I want to put z_lf.These values below are set okay in the simulation.   wait for 10 ns;
   mcol_lf <= "0011";
   wait for 10 ns;
   mrow_lf <= "0011";
   wait for 10 ns;
   x_lf <= "0010100100";
   wait for 10 ns;
   z_lf <= "010100100";
--   a[mrow_lf][mcol_lf]  <= z_lf;I can not store z_lf in the matrix a.
Regards,
Thanks Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Wednesday, March 25, 2015 12:24 PM, Edward Vidal <dev...@sb...> wrote:
   

  Hello All,
I am currently using Xilinx ISE for my simulation.Trying to create a wrapper for flatten.pyCreated "m_flatten_wrap.py".
"https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten_wrap.py"
Having 2 issues when I use m_flatten_wrap.vhd.
Line 41: Illegal identifier : mat__flatIf I try and remove 1 of the "_" to make the items
mat_flat.
Then I get a new error.
Line 37: <none> is not declared.
Where is None defined?
Do I have to add a Library?
With the Verilog  file I get the Line 30: <None> is not declared.
Does my file m_flatten_wrap.py create the error?
Regards,Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Wednesday, March 25, 2015 6:34 AM, Henry Gomersall <he...@ca...> wrote:
   

 On 25/03/15 13:27, Edward Vidal wrote:
> release notes.  I do have a Zedboard.  As of today only the OS is 
> running.  I built the OS using Yocto with the meta-xilinx mailing 
> list  help.  Michael Loojimans from Dyplo appears to be one of most 
> knowledgeable on the FPGA side.  Michael help me get sound working 
> which I needed for VLC.  I was able to get several things running 
> OpenCV, GSL, Java, Python and VLC.  I think I would like to work on 
> face recognition in FPGA, since the Zedboard with OpenCV is a bit 
> slow.  Do not know enough yet to add to the FPGA.  What board are you 
> running?  Currently trying to learn MyHDL and ISE using the XuLA2 
> board which has XC6SLX9 FPGA.  Thanks for the heads up on Vivado.

I'm also using a Zedboard - the zedboard license will allow you to use 
the design edition of Vivado just fine.

As an aside, your emails are really hard to read, in particular your 
code snippets. Can you try just posting in plain text with a liberal 
sprinkling of carriage returns?

Cheers,

Henry


   
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Re: [myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

 Hello All,
I am currently using Xilinx ISE for my simulation.Trying to create a wrapper for flatten.pyCreated "m_flatten_wrap.py".
"https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/m_flatten_wrap.py"
Having 2 issues when I use m_flatten_wrap.vhd.
Line 41: Illegal identifier : mat__flatIf I try and remove 1 of the "_" to make the items
mat_flat.
Then I get a new error.
Line 37: <none> is not declared.
Where is None defined?
Do I have to add a Library?
With the Verilog  file I get the Line 30: <None> is not declared.
Does my file m_flatten_wrap.py create the error?
Regards,Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Wednesday, March 25, 2015 6:34 AM, Henry Gomersall <he...@ca...> wrote:
   

 On 25/03/15 13:27, Edward Vidal wrote:
> release notes.  I do have a Zedboard.  As of today only the OS is 
> running.  I built the OS using Yocto with the meta-xilinx mailing 
> list  help.  Michael Loojimans from Dyplo appears to be one of most 
> knowledgeable on the FPGA side.  Michael help me get sound working 
> which I needed for VLC.  I was able to get several things running 
> OpenCV, GSL, Java, Python and VLC.  I think I would like to work on 
> face recognition in FPGA, since the Zedboard with OpenCV is a bit 
> slow.  Do not know enough yet to add to the FPGA.  What board are you 
> running?  Currently trying to learn MyHDL and ISE using the XuLA2 
> board which has XC6SLX9 FPGA.  Thanks for the heads up on Vivado.

I'm also using a Zedboard - the zedboard license will allow you to use 
the design edition of Vivado just fine.

As an aside, your emails are really hard to read, in particular your 
code snippets. Can you try just posting in plain text with a liberal 
sprinkling of carriage returns?

Cheers,

Henry


  

Re: [myhdl-list] Xilinx simulation

[Henry G. <he...@ca...>]

On 25/03/15 13:27, Edward Vidal wrote:
> release notes.  I do have a Zedboard.  As of today only the OS is 
> running.  I built the OS using Yocto with the meta-xilinx mailing 
> list  help.  Michael Loojimans from Dyplo appears to be one of most 
> knowledgeable on the FPGA side.  Michael help me get sound working 
> which I needed for VLC.   I was able to get several things running 
> OpenCV, GSL, Java, Python and VLC.  I think I would like to work on 
> face recognition in FPGA, since the Zedboard with OpenCV is a bit 
> slow.   Do not know enough yet to add to the FPGA.  What board are you 
> running?  Currently trying to learn MyHDL and ISE using the XuLA2 
> board which has XC6SLX9 FPGA.   Thanks for the heads up on Vivado.

I'm also using a Zedboard - the zedboard license will allow you to use 
the design edition of Vivado just fine.

As an aside, your emails are really hard to read, in particular your 
code snippets. Can you try just posting in plain text with a liberal 
sprinkling of carriage returns?

Cheers,

Henry

Re: [myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

Henry,Checking the
WebPACK Edition of the Vivado Design Suite
 release notes.  I do have a Zedboard.  As of today only the OS is running.  I built the OS using Yocto with the meta-xilinx mailing list  help.  Michael Loojimans from Dyplo appears to be one of most knowledgeable on the FPGA side.  Michael help me get sound working which I needed for VLC.   I was able to get several things running OpenCV, GSL, Java, Python and VLC.  I think I would like to work on face recognition in FPGA, since the Zedboard with OpenCV is a bit slow.   Do not know enough yet to add to the FPGA.  What board are you running?  Currently trying to learn MyHDL and ISE using the XuLA2 board which has XC6SLX9 FPGA.   Thanks for the heads up on Vivado.Regards
 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Wednesday, March 25, 2015 7:51 AM, Henry Gomersall <he...@ca...> wrote:
   

 On 24/03/15 23:28, Edward Vidal wrote:
> I am using ISE.  I don't have Vivado since I looked at Xilinx it was 
> around $2900.00

You do know there is a webpack version for zero dollars? ISE is 
end-of-life so it's worth thinking about the upgrade path (though it 
doesn't work with the older devices).

Henry


  

Re: [myhdl-list] Xilinx simulation

[Henry G. <he...@ca...>]

On 24/03/15 23:28, Edward Vidal wrote:
> I am using ISE.  I don't have Vivado since I looked at Xilinx it was 
> around $2900.00

You do know there is a webpack version for zero dollars? ISE is 
end-of-life so it's worth thinking about the upgrade path (though it 
doesn't work with the older devices).

Henry

Re: [myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

 Chris & Henry
I am using ISE.  I don't have Vivado since I looked at Xilinx it was around $2900.00
I did not get the Verilog simulation working, nothing I did. would make the res_out_x
signal respond to the stimulus.  It was always red and would not turn green.I did get a VHDL simulation working less the instances of m_flatten.
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/tbjp_procesvhd.vhdWhen I use m_flatten.v I get multiple errors of like the one.
Line 22: <None> is not declared.
When I use m_flatten.vhd I have to modify _flat to flat to get the instances to work
since I get multiple errors Line 37: Illegal identifier : _flat
Still don't know how to create the wrapper for m_flatten.As always any help will be greatly appreciated.
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Tuesday, March 24, 2015 12:52 AM, Henry Gomersall <he...@ca...> wrote:
   

 On 24/03/15 01:12, Edward Vidal wrote:
> In jp_process.v res_out_x is defined as below.
> output signed [9:0] res_out_x;
> reg signed [9:0] res_out_x;
> What do you have to do make the signal respond to Xilinux stimulus?
> Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0] 
> res_out_x;

It's not entirely clear to me what you're trying to do.

I have a project that can do a cosim of sorts with Vivado:
https://github.com/hgomersall/Veriutils

It is, unfortunately, currently VHDL only. It wouldn't  be a massive job 
to add the Verilog bits if you are keen (likely a few hours work) and 
I'd be enthusiastic to see them added.

Cheers,

Henry


  

Re: [myhdl-list] TypeError: Unexpected type

[Josy B. <jos...@gm...>]

> It gets another exception in the toVHDL conversion:
>   File "C:\Python27\lib\site-packages\myhdl\conversion\_toVHDL.py", line 
> 713, in BitRepr
>     return '"%s"' % bin(item, len(var))
> TypeError: object of type '_loopInt' has no len()
> 

The fix for _toVHDL: in function 'def mapToCase(self, node):' insert

            elif isinstance(item, (int,long)):
                itemRepr = i


in:
            if isinstance(item, EnumItemType):
                itemRepr = item._toVHDL()
->
            else:
                itemRepr = self.BitRepr(item, obj)

Regards,

Josy

Re: [myhdl-list] TypeError: Unexpected type

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:

> 
> On 3/24/2015 9:30 AM, Guy Eschemann wrote:
> > from myhdl import *
> >
> > def mpegChannel(clk, rst):
> >
> >      s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])
> >
> >       <at> always_seq(clk.posedge, rst)
> >      def fsm_seq():
> >          for i in range(4):
> >              if i == 0:
> >                  s_tx_data_xor_mask_r.next[1 + 7:0] = 0
> >              elif i == 1:
> >                  s_tx_data_xor_mask_r.next[1 + 15:8] = 1
> >              elif i == 2:
> >                  s_tx_data_xor_mask_r.next[1 + 23:16] = 2
> >              else:
> >                  s_tx_data_xor_mask_r.next[1 + 31:24] = 3
> >
> >      return instances()
> 
> I think this is a bug / limitation and an issue should
> to be created (but there might be a good reason for the
> limitation that I can't think of right now).
> 
> You can work around it with:
> 
> In [5]: from myhdl import *
>     ...:
>     ...: def mpegChannel(clk, rst):
>     ...:
>     ...:     s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])
> 
>     ...:     # *** limited range type for switch ***
>     ...:     full_case = intbv(0, min=0, max=4)
> 
>     ...:      <at> always_seq(clk.posedge, rst)
>     ...:     def fsm_seq():
>     ...:         for i in range(4):
>     ...:             full_case[:] = i
>     ...:             if full_case == 0:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 7:0] = 0
>     ...:             elif full_case == 1:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 15:8] = 1
>     ...:             elif full_case == 2:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 23:16] = 2
>     ...:             else:
>     ...:                 s_tx_data_xor_mask_r.next[1 + 31:24] = 3
>     ...:
>     ...:     return instances()
> 
> The limitation is, when evaluating an if-else structure
> the conversion code wants to determine if it full-case
> or not, because the variable switched on is an `int` it
> throws the type error.  But the code example seems reasonable,
> I think?
><snip>
I traced the process, and the exception is thrown after the 'else:' has 
ben processed. Replacing the 'else:' with 'elif i == 3:'  gets the same 
exception.
I tried two other workarounds:
def mpegChannel(clk, rst, s_tx_data_xor_mask_r):

    @always_seq(clk.posedge, reset=rst)
    def fsm_seq():
        for i in range(4):
            s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = i
           
    return instances()

and:
def mpegChannel(clk, rst, s_tx_data_xor_mask_r):

    table = tuple([9,8,7,6])

    @always_seq(clk.posedge, reset=rst)
    def fsm_seq():
        for i in range(4):
            s_tx_data_xor_mask_r.next[(i+1)*8:i*8] = table[i]


    return instances()

The second allows for any value to be loaded.
Both convert fine.

I also found a fix which works for Verilog: in _analyze in function     
def visit_If(self, node): change line 
        if (len(choices) == _getNritems(var1.obj)) or node.else_ :

into:
        if node.else_ or (len(choices) == _getNritems(var1.obj)) :

which is probably the original intention?
A final 'else' in the RTL code is than mandatory

It gets another exception in the toVHDL conversion:
  File "C:\Python27\lib\site-packages\myhdl\conversion\_toVHDL.py", line 
713, in BitRepr
    return '"%s"' % bin(item, len(var))
TypeError: object of type '_loopInt' has no len()

(The line number doesn't match, as my MyHDL source is heavily annotated 
with tracing and inspect code)

Regards,

Josy

Re: [myhdl-list] TypeError: Unexpected type

[Christopher F. <chr...@gm...>]

On 3/24/2015 9:30 AM, Guy Eschemann wrote:
> from myhdl import *
>
> def mpegChannel(clk, rst):
>
>      s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])
>
>      @always_seq(clk.posedge, rst)
>      def fsm_seq():
>          for i in range(4):
>              if i == 0:
>                  s_tx_data_xor_mask_r.next[1 + 7:0] = 0
>              elif i == 1:
>                  s_tx_data_xor_mask_r.next[1 + 15:8] = 1
>              elif i == 2:
>                  s_tx_data_xor_mask_r.next[1 + 23:16] = 2
>              else:
>                  s_tx_data_xor_mask_r.next[1 + 31:24] = 3
>
>      return instances()


I think this is a bug / limitation and an issue should
to be created (but there might be a good reason for the
limitation that I can't think of right now).

You can work around it with:

In [5]: from myhdl import *
    ...:
    ...: def mpegChannel(clk, rst):
    ...:
    ...:     s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])

    ...:     # *** limited range type for switch ***
    ...:     full_case = intbv(0, min=0, max=4)

    ...:     @always_seq(clk.posedge, rst)
    ...:     def fsm_seq():
    ...:         for i in range(4):
    ...:             full_case[:] = i
    ...:             if full_case == 0:
    ...:                 s_tx_data_xor_mask_r.next[1 + 7:0] = 0
    ...:             elif full_case == 1:
    ...:                 s_tx_data_xor_mask_r.next[1 + 15:8] = 1
    ...:             elif full_case == 2:
    ...:                 s_tx_data_xor_mask_r.next[1 + 23:16] = 2
    ...:             else:
    ...:                 s_tx_data_xor_mask_r.next[1 + 31:24] = 3
    ...:
    ...:     return instances()

The limitation is, when evaluating an if-else structure
the conversion code wants to determine if it full-case
or not, because the variable switched on is an `int` it
throws the type error.  But the code example seems reasonable,
I think?

Regards,
Chris

[myhdl-list] TypeError: Unexpected type

[Guy E. <guy...@gm...>]

Hello,

I'm wondering why I get a type error when trying to convert the following
code (extracted from a large design) to Verilog.

###

from myhdl import *

def mpegChannel(clk, rst):

    s_tx_data_xor_mask_r = Signal(intbv(0)[1 + 31:])

    @always_seq(clk.posedge, rst)
    def fsm_seq():
        for i in range(4):
            if i == 0:
                s_tx_data_xor_mask_r.next[1 + 7:0] = 0
            elif i == 1:
                s_tx_data_xor_mask_r.next[1 + 15:8] = 1
            elif i == 2:
                s_tx_data_xor_mask_r.next[1 + 23:16] = 2
            else:
                s_tx_data_xor_mask_r.next[1 + 31:24] = 3

    return instances()

if __name__ == "__main__":
    clk = Signal(bool(0))
    rst = ResetSignal(0, active=1, async=True)
    mpegChannelInst = toVerilog(mpegChannel, clk, rst)

###

Any ideas?

Thanks,
Guy.

Re: [myhdl-list] Xilinx simulation

[Henry G. <he...@ca...>]

On 24/03/15 01:12, Edward Vidal wrote:
> In jp_process.v res_out_x is defined as below.
> output signed [9:0] res_out_x;
> reg signed [9:0] res_out_x;
> What do you have to do make the signal respond to Xilinux stimulus?
> Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0] 
> res_out_x;

It's not entirely clear to me what you're trying to do.

I have a project that can do a cosim of sorts with Vivado:
https://github.com/hgomersall/Veriutils

It is, unfortunately, currently VHDL only. It wouldn't  be a massive job 
to add the Verilog bits if you are keen (likely a few hours work) and 
I'd be enthusiastic to see them added.

Cheers,

Henry

Re: [myhdl-list] *** GMX Spamverdacht *** Re: tristatesignal

[Keerthan JC <jck...@gm...>]

You can use pip to install a branch like so:
pip install git+https://github.com/cogenda/myhdl@tristate_vcd

On Mon, Mar 23, 2015 at 6:08 PM, Günther Stangassinger <
gue...@gm...> wrote:

> thank you very much.
> it is working :-)
> regards,
> guenther stangassinger
>
>
>
> Am 23.03.2015 um 22:55 schrieb Christopher Felton:
> > On 3/23/2015 4:47 PM, Günther Stangassinger wrote:
> >> Hi,
> >> i am doing
> >>     pip install --upgrade git+
> https://github.com/jandecaluwe/myhdl/pull/39
> >> but this raises an error:
> >> error: The requested URL returned error: 403 while accessing
> >> https://github.com/jandecaluwe/myhdl/pull/39/info/refs
> >>
> > I don't know if you can use pip from a PR or
> > branch, until it is merged you will probably
> > need to do:
> >
> >      >> git clone https://github.com/cogenda/myhdl/
> >      >> cd myhdl
> >      >> git checkout tristate_vcd
> >      >> python setup install
> >
> >
> > Hope that helps,
> > Chris
> >
> >
> >
> >
> ------------------------------------------------------------------------------
> > Dive into the World of Parallel Programming The Go Parallel Website,
> sponsored
> > by Intel and developed in partnership with Slashdot Media, is your hub
> for all
> > things parallel software development, from weekly thought leadership
> blogs to
> > news, videos, case studies, tutorials and more. Take a look and join the
> > conversation now. http://goparallel.sourceforge.net/
> > _______________________________________________
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> > myh...@li...
> > https://lists.sourceforge.net/lists/listinfo/myhdl-list
> >
>
>
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website,
> sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for
> all
> things parallel software development, from weekly thought leadership blogs
> to
> news, videos, case studies, tutorials and more. Take a look and join the
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-- 
have a nice day
-jck

Re: [myhdl-list] Xilinx simulation

[Christopher F. <chr...@gm...>]

> What do you have to do make the signal respond to Xilinux stimulus?
> Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0]
> res_out_x;
> All of my other signals respond to stimulus.
> Any and all help is appreciated.

Which Xilinx tools are you using?  ISE or Vivado?

You have a couple options:  First, convert a Python
testbench that generates the stimulus.  Second, use
@heng's VCD stimulus project.

Best of my knowledge co-simulation is not possible
with isim.

Regards,
Chris

[myhdl-list] Xilinx simulation

[Edward V. <dev...@sb...>]

 Hello all,Testing some code that runs okay in "python test_bench_array_jpeg_ram.py" and generates tb.vcd.  Which I can see with "gtkwave tb.vcd".https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/test_bench_array_jpeg_ram.pyModified tbjpeg_para.v to store 144 bits in
ram_lf, ram_sa, and ram_rt instead of using combine.
ran the simulation for 10.00 usec.  The res_out_x is red.
left 26
sam   a2
right a8
Xilinux simulation uses the following files:
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/jp_process.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/ram.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/ram_res.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/rom_flgs.v
https://github.com/develone/jpeg-2000-test/blob/master/jpeg2k/parallel_jpeg/tbjpeg_para.v
https://github.com/develone/jpeg-2000-test/blob/masterjpeg2k/parallel_jpeg/jpeg_para.xiseIn jp_process.v res_out_x is defined as below.output signed [9:0] res_out_x;
reg signed [9:0] res_out_x;What do you have to do make the signal respond to Xilinux stimulus?Currently using wire signed [9:0] res_out_x;  I have tried reg [9:0] res_out_x;All of my other signals respond to stimulus.Any and all help is appreciated.
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] *** GMX Spamverdacht *** Re: tristatesignal

[Günther S. <gue...@gm...>]

thank you very much.
it is working :-)
regards,
guenther stangassinger



Am 23.03.2015 um 22:55 schrieb Christopher Felton:
> On 3/23/2015 4:47 PM, Günther Stangassinger wrote:
>> Hi,
>> i am doing
>>     pip install --upgrade git+https://github.com/jandecaluwe/myhdl/pull/39
>> but this raises an error:
>> error: The requested URL returned error: 403 while accessing
>> https://github.com/jandecaluwe/myhdl/pull/39/info/refs
>>
> I don't know if you can use pip from a PR or
> branch, until it is merged you will probably
> need to do:
>
>      >> git clone https://github.com/cogenda/myhdl/
>      >> cd myhdl
>      >> git checkout tristate_vcd
>      >> python setup install
>
>
> Hope that helps,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website, sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for all
> things parallel software development, from weekly thought leadership blogs to
> news, videos, case studies, tutorials and more. Take a look and join the
> conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] *** GMX Spamverdacht *** Re: tristatesignal

[Christopher F. <chr...@gm...>]

On 3/23/2015 4:47 PM, Günther Stangassinger wrote:
> Hi,
> i am doing
>    pip install --upgrade git+https://github.com/jandecaluwe/myhdl/pull/39
> but this raises an error:
> error: The requested URL returned error: 403 while accessing
> https://github.com/jandecaluwe/myhdl/pull/39/info/refs
>

I don't know if you can use pip from a PR or
branch, until it is merged you will probably
need to do:

    >> git clone https://github.com/cogenda/myhdl/
    >> cd myhdl
    >> git checkout tristate_vcd
    >> python setup install


Hope that helps,
Chris

Re: [myhdl-list] *** GMX Spamverdacht *** Re: tristatesignal

[Günther S. <gue...@gm...>]

Hi,
i am doing
  pip install --upgrade git+https://github.com/jandecaluwe/myhdl/pull/39
but this raises an error:
error: The requested URL returned error: 403 while accessing 
https://github.com/jandecaluwe/myhdl/pull/39/info/refs

How do i get your changes.
Regards,
guenther





Am 23.03.2015 um 21:54 schrieb SHEN Chen:
>> Am 22.03.2015 um 16:46 schrieb SHEN Chen:
>>
>>>> When i use TristateSignal with the function traceSignals(), then i
>>>> get this message: ValueError: I2C_SDAT of module foo has no initial
>>>> value
>>> This is a result of pull-request 21 (which fixes issue 19) in
>>> github.
>>> I encountered similar problem last week, but was too busy travelling
>>> around to commit my fix to it. Will test and raise PR asap.
>>>
> I've raised a pull request
> (https://github.com/jandecaluwe/myhdl/pull/39) with fixes.
> Passes travis-ci and local designs tests.
> Please test and comment. thx.
>
> regards,
> shenchen
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website, sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for all
> things parallel software development, from weekly thought leadership blogs to
> news, videos, case studies, tutorials and more. Take a look and join the
> conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Mit freundlichen Grüßen
Günther Stangassinger

Re: [myhdl-list] tristatesignal

[SHEN C. <she...@co...>]

>
> Am 22.03.2015 um 16:46 schrieb SHEN Chen:
>
>>> When i use TristateSignal with the function traceSignals(), then i
>>> get this message: ValueError: I2C_SDAT of module foo has no initial
>>> value
>> This is a result of pull-request 21 (which fixes issue 19) in 
>> github.
>> I encountered similar problem last week, but was too busy travelling
>> around to commit my fix to it. Will test and raise PR asap.
>>

I've raised a pull request 
(https://github.com/jandecaluwe/myhdl/pull/39) with fixes.
Passes travis-ci and local designs tests.
Please test and comment. thx.

regards,
shenchen

Re: [myhdl-list] tristatesignal

[Christopher F. <chr...@gm...>]

On 3/23/2015 1:46 PM, Günther Stangassinger wrote:
> Hi Shen,
> how do i know, when the new fix is applied
> and how do i get the new fix.
> Can i just update it with then with:
>
> pip install --upgrade myhdl
>

The `pip install` will only work with the next
release.  You will want to clone the master branch
[1] or do:

    pip install --upgrade git+https://github.com/jandecaluwe/myhdl


Regards,
Chris

[1] http://dev.myhdl.org/guide.html#tracking-development

Re: [myhdl-list] tristatesignal

[Günther S. <gue...@gm...>]

Hi Shen,
how do i know, when the new fix is applied
and how do i get the new fix.
Can i just update it with then with:

pip install --upgrade myhdl

Regards,
guenther




Am 22.03.2015 um 16:46 schrieb SHEN Chen:
>> When i use TristateSignal with the function
>> traceSignals(), then i get this message:
>> ValueError: I2C_SDAT of module foo has no initial value
> This is a result of pull-request 21 (which fixes issue 19) in github.
>
> I encountered similar problem last week, but was too busy travelling
> around
> to commit my fix to it.
>
> Will test and raise PR asap.
>
> regards,
>
> shenchen
>
>
> ------------------------------------------------------------------------------
> Dive into the World of Parallel Programming The Go Parallel Website, sponsored
> by Intel and developed in partnership with Slashdot Media, is your hub for all
> things parallel software development, from weekly thought leadership blogs to
> news, videos, case studies, tutorials and more. Take a look and join the
> conversation now. http://goparallel.sourceforge.net/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>


-- 
Mit freundlichen Grüßen
Günther Stangassinger

[myhdl-list] Who setup freenode #myhdl IRC

[Christopher F. <chr...@gm...>]

Does anyone know who setup the freenode IRC
channel: #myhdl?

I looks like it was setup by laserbeak43 was the
IRC channel founder?

Regards,
Chris