myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] Re: more PhoenixSID sound samples added

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi all,
> 
>  I recently greatly upgraded the PhoenixSID music synthesizer I've been 
> working on, and added some more sounds to the webpage:

Congratulations with the progress.

Personally I would be quite interested in getting more insight in size
and complexity of the MyHDL part e.g. nr of hardware modules, lines
of code, size of Verilog output file, FPGA synthesis and map report
highlights.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] more PhoenixSID sound samples added

[George P. <ge...@ga...>]

Hi all,

  I recently greatly upgraded the PhoenixSID music synthesizer I've been 
working on, and added some more sounds to the webpage:

http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

PS. Thanks to the MyHDL community for your support

Enjoy,
George
 

[myhdl-list] Re: check for "signal.next == value"

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>   Could you add a check for accidental use of "signal.next == value" 
> instead of "signal.next = value" ? It saves time to have it caught at 
> the myHDL level.

This is the type of problem (not specific to MyHDL) that pychecker
can find:

    http://pychecker.sourceforge.net/

I don't use pychecker regularly, but I think I should. Also, it
might be useful to come up with some settings for the MyHDL
case (e.g. to ignore the myhdl package itself).

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] check for "signal.next == value"

[George P. <ge...@ga...>]

Hi Jan,

   Could you add a check for accidental use of "signal.next == value" 
instead of "signal.next = value" ? It saves time to have it caught at 
the myHDL level.

Thanks,
George

[myhdl-list] Wikipedia presence

[George P. <ge...@ga...>]

Hi Jan,

    When the time is right, don't forget to establish a presence on 
Wikipedia (eg, a myHDL page with links in the CPLD/FPGA related pages).

George

Re: [myhdl-list] Re: signed multiplication

[Haitao Z. <ha...@gm...>]

Jan,
Thank you very much for the reference and the example. It is a very elegant
solution.
Haitao

On 2/8/06, Jan Decaluwe <ja...@ja...> wrote:
>
> Haitao Zhang wrote:
> >
> > Does myHDL now support signed vector and how?
>
> It has always been possible to use negative intbv's - but until
> 0.5 it was not possible to convert them to Verilog. I assume
> that's what you mean. Signed support for Verilog conversion
> in 0.5 is described here:
>
>
> http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#support_for_signed_ari=
thmetic
>
> > Without signed number support specifying a signed multiplication (or
> > other arithmetics) is quite awkward.  It is also non-optimal for
> synthesis.
>
> I'll give an example to clarify. Consider:
>
>
>     from myhdl import *
>
>     def test(c, a, b):
>
>         @always_comb
>         def mult():
>             c.next =3D a * b
>
>         return mult
>
>
> to describe a multiplication. As always, you can convert a
> design instance to Verilog. For negative intbv's you have to
> constrain them using an integer range, not a bit slice. Note
> that this is higher level view than working with bit vectors,
> entirely appropriate for arithmetic and much less error-prone.
> For example:
>
>     a =3D Signal(intbv(0, min=3D-9, max=3D45))
>     b =3D Signal(intbv(0, min=3D-24, max=3D45))
>     c =3D Signal(intbv(0, min=3D-1000, max=3D1000))
>
>     toVerilog(test, c, a, b)
>
> The Verilog output is:
>
>     module test (
>         c,
>         a,
>         b
>     );
>
>     output signed [10:0] c;
>     wire signed [10:0] c;
>     input signed [6:0] a;
>     input signed [6:0] b;
>
>     assign c =3D (a * b);
>
>     endmodule
>
>
> Note how signed regs are used. Now, consider a
> different conversion:
>
>     a =3D Signal(intbv(0, min=3D0, max=3D45))
>     b =3D Signal(intbv(0, min=3D-24, max=3D45))
>     c =3D Signal(intbv(0, min=3D-1000, max=3D1000))
>
>     toVerilog(test, c, a, b)
>
> Then the output is:
>
>     module test (
>         c,
>         a,
>         b
>     );
>
>     output signed [10:0] c;
>     wire signed [10:0] c;
>     input [5:0] a;
>     input signed [6:0] b;
>
>     assign c =3D ($signed({1'b0, a}) * b);
>
>     endmodule
>
> Now the convertor uses an unsigned reg for a, but adds a
> sign bit and a cast to it in the multiplication. It's for this reason
> that I claim that working with negative numbers is much easier
> in MyHDL than in Verilog: the error-prone issues with regard to
> signed representation are taken care of by the convertor.
>
> Ain't it great :-)?
>
> Jan
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
>
> -------------------------------------------------------
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=3D121642
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>

[myhdl-list] Re: signed multiplication

[Jan D. <ja...@ja...>]

Haitao Zhang wrote:
> 
> Does myHDL now support signed vector and how?

It has always been possible to use negative intbv's - but until
0.5 it was not possible to convert them to Verilog. I assume
that's what you mean. Signed support for Verilog conversion
in 0.5 is described here:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#support_for_signed_arithmetic

> Without signed number support specifying a signed multiplication (or 
> other arithmetics) is quite awkward.  It is also non-optimal for synthesis.

I'll give an example to clarify. Consider:


     from myhdl import *

     def test(c, a, b):

         @always_comb
         def mult():
             c.next = a * b

         return mult


to describe a multiplication. As always, you can convert a
design instance to Verilog. For negative intbv's you have to
constrain them using an integer range, not a bit slice. Note
that this is higher level view than working with bit vectors,
entirely appropriate for arithmetic and much less error-prone.
For example:

     a = Signal(intbv(0, min=-9, max=45))
     b = Signal(intbv(0, min=-24, max=45))
     c = Signal(intbv(0, min=-1000, max=1000))

     toVerilog(test, c, a, b)

The Verilog output is:

     module test (
         c,
         a,
         b
     );

     output signed [10:0] c;
     wire signed [10:0] c;
     input signed [6:0] a;
     input signed [6:0] b;

     assign c = (a * b);

     endmodule


Note how signed regs are used. Now, consider a
different conversion:

     a = Signal(intbv(0, min=0, max=45))
     b = Signal(intbv(0, min=-24, max=45))
     c = Signal(intbv(0, min=-1000, max=1000))

     toVerilog(test, c, a, b)

Then the output is:

     module test (
         c,
         a,
         b
     );

     output signed [10:0] c;
     wire signed [10:0] c;
     input [5:0] a;
     input signed [6:0] b;

     assign c = ($signed({1'b0, a}) * b);

     endmodule

Now the convertor uses an unsigned reg for a, but adds a
sign bit and a cast to it in the multiplication. It's for this reason
that I claim that working with negative numbers is much easier
in MyHDL than in Verilog: the error-prone issues with regard to
signed representation are taken care of by the convertor.

Ain't it great :-)?

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] signed multiplication

[Haitao Z. <ha...@gm...>]

Does myHDL now support signed vector and how?
Without signed number support specifying a signed multiplication (or other
arithmetics) is quite awkward.  It is also non-optimal for synthesis.

Thanks,
Haitao

Re: [myhdl-list] Re: First sound samples of the PhoenixSID 65X81 synth added

[George P. <ge...@ga...>]

Thanks Jan!  I think I will be announcing there in the not-too-distant 
future. By the way, in the XGameStation forum, Andre' Lamothe (hacker, 
author, and owner of the company) asked a good question about the 
efficiency of myHDL. If you want to reply,the post is:

http://205.158.110.70/ubbcgi/ultimatebb.cgi?ubb=get_topic&f=20&t=001225

There's a very cool hardware-hacking community on that site!

George




> Jan Decaluwe wrote:
>> George Pantazopoulos wrote:
>>
>>> Hi all,
>>>
>>>    I'm pleased to have some early sound samples to post to the 
>>> PhoenixSID project page. This project is a joy to work on, thanks 
>>> for helping to make it possible!
>>
>>
>> Congratulations George, I can hear you :-)
>>
>> Why not announce your project in comp.lang.fpga? I'm pretty sure
>> you'll have a very interested audience over there.
>
> Correction: that should have been comp.arch.fpga. Quite an
> active newsgroup with fpga users and vendors, often discussing
> relevant problems :-)
>
> Jan
>

[myhdl-list] Re: First sound samples of the PhoenixSID 65X81 synth added

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> George Pantazopoulos wrote:
> 
>> Hi all,
>>
>>    I'm pleased to have some early sound samples to post to the 
>> PhoenixSID project page. This project is a joy to work on, thanks for 
>> helping to make it possible!
> 
> 
> Congratulations George, I can hear you :-)
> 
> Why not announce your project in comp.lang.fpga? I'm pretty sure
> you'll have a very interested audience over there.

Correction: that should have been comp.arch.fpga. Quite an
active newsgroup with fpga users and vendors, often discussing
relevant problems :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: First sound samples of the PhoenixSID 65X81 synth added

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi all,
> 
>    I'm pleased to have some early sound samples to post to the 
> PhoenixSID project page. This project is a joy to work on, thanks for 
> helping to make it possible!

Congratulations George, I can hear you :-)

Why not announce your project in comp.lang.fpga? I'm pretty sure
you'll have a very interested audience over there.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] First sound samples of the PhoenixSID 65X81 synth added

[George P. <ge...@ga...>]

Hi all,

    I'm pleased to have some early sound samples to post to the 
PhoenixSID project page. This project is a joy to work on, thanks for 
helping to make it possible!

http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81


George

[myhdl-list] Re: cookbook addition

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Excellent idea. How about adding the missing automated unit tests that we
> all know and love? :) And yeah, they're important, you were right about
> coming back to a project after a vacation and needing the assurance of
> automated tests :)

There you have it, my own preaching is backfiring :-)

Ok - I maintain the position that unit tests should be written for
every module, even if the test seems trivial. Now, in this case, the
modules themselves are artificially simple and actually trivial - as I
note in the intro, you normally wouldn't describe individual flip-flops.
(Or at least, I wouldn't).

The page is intended to let people make quick comparisons with other
HDLs, using things they know that require no explanation. (I use
the opportunity to demonstrate waveform tracing to let them know
it's there).

For a meaningful unit test, you try to approach the circuit from
some different angle at a (perhaps slightly) higher level. In this
case, I don't think there's anything else one can do than simply
copying the implementation. So I fear that people won't see the
point here, and the message may get lost.

However - I'm working on another page :-) that should clearly
illustrate the whole flow. I'm actually using the Xilinx ISE tutorial
and redoing it the "MyHDL way". It will show unit tests, ROM
inferencing, synthesis and retargeting to various FPGA/CPLD
technologies - so I think this is going to be an interesting page.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: .mp3 upload to wiki is forbidden

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
> I think application/octet-stream would work, based on RFC 2046 (section 
> 4.3).
> 

I should work now, I used audio/mpeg and application/ogg anyway as these
seem to be the right mime types.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Re: .mp3 upload to wiki is forbidden

[George P. <ge...@ga...>]

Hi Jan,

I think application/octet-stream would work, based on RFC 2046 (section 
4.3).

Thanks,
George
> George Pantazopoulos wrote:
>> Hi Jan,
>>
>>   I'm trying to upload some sound samples to the wiki, but it tells 
>> my that the mp3 filetype is forbidden. Would you please allow this 
>> (and .ogg)?
>
> That's possible, but I need the mime type.
> What should the mime type for these extensions be? I looked around
> and I found a whole number of alternatives. Or should it just
> be a generic application/octetstream?
>
> Jan
>

[myhdl-list] Re: .mp3 upload to wiki is forbidden

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>   I'm trying to upload some sound samples to the wiki, but it tells my 
> that the mp3 filetype is forbidden. Would you please allow this (and .ogg)?

That's possible, but I need the mime type.
What should the mime type for these extensions be? I looked around
and I found a whole number of alternatives. Or should it just
be a generic application/octetstream?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] .mp3 upload to wiki is forbidden

[George P. <ge...@ga...>]

Hi Jan,

   I'm trying to upload some sound samples to the wiki, but it tells my 
that the mp3 filetype is forbidden. Would you please allow this (and .ogg)?

Thanks,
George

Re: [myhdl-list] cookbook addition

[George P. <ge...@ga...>]

Excellent idea. How about adding the missing automated unit tests that we
all know and love? :) And yeah, they're important, you were right about
coming back to a project after a vacation and needing the assurance of
automated tests :)

George


> Hi:
>
> I am working on additional cookbook pages.
>
> There was a suggestion to add simple examples before
> adding more complex ones. Accordingly, I have created
> a page about flip-flops and latches:
>
>    http://myhdl.jandecaluwe.com/doku.php/cookbook:ff
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>      From Python to silicon:
>      http://myhdl.jandecaluwe.com
>
>
>
> -------------------------------------------------------
> This SF.net email is sponsored by: Splunk Inc. Do you grep through log
> files
> for problems?  Stop!  Download the new AJAX search engine that makes
> searching your log files as easy as surfing the  web.  DOWNLOAD SPLUNK!
> http://sel.as-us.falkag.net/sel?cmd=3Dlnk&kid=3D103432&bid=3D230486&dat=
=3D121642
> _______________________________________________
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>


--=20
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] cookbook addition

[Jan D. <ja...@ja...>]

Hi:

I am working on additional cookbook pages.

There was a suggestion to add simple examples before
adding more complex ones. Accordingly, I have created
a page about flip-flops and latches:

   http://myhdl.jandecaluwe.com/doku.php/cookbook:ff

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] EETimes article

[nicran <ni...@gm...>]

Jan,

I've already read that article, great work!


2006/1/24, Jan Decaluwe <ja...@ja...>:
>
> Hi all:
>
> MyHDL is in the news today at http://www.eetimes.com.
>
> I had asked Richard Goering to add a link in their open-source
> tool list, and he found it interesting enough for a story.
> He wrote the article based on a telephone interview. It's very
> well written, clear and complete. I have told him that I
> understand it better now :-)
>
> Regards,
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>     From Python to silicon:
>     http://myhdl.jandecaluwe.com
>
>
>
> -------------------------------------------------------
> This SF.net email is sponsored by: Splunk Inc. Do you grep through log
> files
> for problems?  Stop!  Download the new AJAX search engine that makes
> searching your log files as easy as surfing the  web.  DOWNLOAD SPLUNK!
> http://sel.as-us.falkag.net/sel?cmd=3Dlnk&kid=3D103432&bid=3D230486&dat=
=3D121642
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] EETimes article

[Jan D. <ja...@ja...>]

Hi all:

MyHDL is in the news today at http://www.eetimes.com.

I had asked Richard Goering to add a link in their open-source
tool list, and he found it interesting enough for a story.
He wrote the article based on a telephone interview. It's very
well written, clear and complete. I have told him that I
understand it better now :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Cookbook

[George P. <ge...@ga...>]

Hi Jan,

I think this cookbook section is a great idea.

Also, I think that for an open-source project such as myHDL to succeed, 
it must work well for people using the free synthesis tools.

George


> After feedback from comp.lang.fpga, I decided to start up an on-line
> "Cookbook" for MyHDL. It has a first design:
>
>    http://myhdl.jandecaluwe.com/doku.php/cookbook:jc2
>
> All feedback and suggestion welcome.
>
> Jan
>
>

[myhdl-list] Cookbook

[Jan D. <ja...@ja...>]

After feedback from comp.lang.fpga, I decided to start up an on-line
"Cookbook" for MyHDL. It has a first design:

    http://myhdl.jandecaluwe.com/doku.php/cookbook:jc2

All feedback and suggestion welcome.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: Johnson counter page

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Thanks for the example of the Johnson Counter.

Someone on comp.lang.fpga suggested to add side-by-side
comparisons of MyHDL code versus other solutions.
I liked that idea, but I thought a "cookbook" would be even
better. Over time, I hope to add widely used and well-known
examples, so that people can learn by example.

> http://myhdl.jandecaluwe.com/doku.php/cookbook:jc2
> 
> Could you have used an @always block if you pulled the state variables 
> out of the logic() function and put them in the enclosing scope, as 
> illustrated below?

No. When you assign them inside a function, they are local variables
that have nothing to do with the ones in the enclosing scope. In
particular, this means they can't keep state over multiple function
invocations.

> I noticed that the state variables are not manipulated by the .next 
> operator, but instead directly assigned (combinatorially, as you say). I 
> didn't know this was possible with variables that would end up in the 
> verilog output!
 >
> Please tell us more about your preferred coding style and why you 
> recommend it!

The point I want to make is that there is no good reason to avoid
using variables (blocking assignments in Verilog), if you can
use them to write elegant code. However, avoiding them would
be the implication if you believe the Verilog gurus who tell you
not to mix blocking and non-blocking assignments in a sequential
always block. When you simply use variables to hold intermediate
results, my observation should be obvious. However, you can even use
them to use state (and still use them combinatorially also), and this
is also no problem for (decent) synthesis tools.

Sometimes it's easier to concentrate on the behavior of code instead
of "thinking hardware". Synthesis tools can deal with this
coding style perfectly fine. (However, it seems that there are also lame
tools that refer to crazy rules like the one above to reject such input
code. Don't know about Xilinx ISE.)

Caveat: just when I wanted to announce the page (you beat me to it),
I noticed an inconsistency between the Verilog and VHDL in the original
code from the Xilinx ISE. Again related to blocking vs non-blocking
(signal) assignments :-) (Who understands these matters actually??)
I based myself on the Verilog, but I believe the VHDL is really
what's intended. In that case, all state variables
are signals anyway and the code could use an always decorator.
In other words, the example is subject to significant changes.
Perhaps I'll keep the current code as an "advanced" variant.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Johnson counter page

[George P. <ge...@ga...>]

Thanks for the example of the Johnson Counter.

http://myhdl.jandecaluwe.com/doku.php/cookbook:jc2

Could you have used an @always block if you pulled the state variables 
out of the logic() function and put them in the enclosing scope, as 
illustrated below?

I noticed that the state variables are not manipulated by the .next 
operator, but instead directly assigned (combinatorially, as you say). I 
didn't know this was possible with variables that would end up in the 
verilog output!

Please tell us more about your preferred coding style and why you 
recommend it!

Thanks,
George


from myhdl import *
 
ACTIVE = 0
DirType = enum('RIGHT', 'LEFT')

def jc2(left,right,stop,clk,q):
     ...
     ...
     ...
     dir = Signal(DirType.LEFT)
     run = Signal(bool(False))

     @always(clk.posedge)
     def logic():
          if right == ACTIVE:
               dir = DirType.RIGHT
               run = True
          ...
          ...
          ...
     return instances()