myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

On Tuesday 26 September 2006 18:09, George Pantazopoulos wrote:
> >> Also, the User-defined Verilog feature won't work because it would
> >> create
> >> nested modules that I confirmed do NOT work in Xilinx ISE.
> >
> > I don't understand what you are saying won't work in ISE. Could you
> > provide an
> > example?
>
> The User-defined Verilog works great and just as advertised for inserting
> module instantiations into the MyHDL-generated Verilog code. I didn't mean
> to imply it was broken in some way.
>
> What I mean is that I can't use that feature to declare additional, needed
> modules because it is only capable of inserting stuff *inside* existing
> modules.

I see what you are saying. I would still let ISE compile the files separately. 
That is the normal way of doing it and really doesn't cause any trouble.

Tom

[myhdl-list] Signal bundling experiment using dicts

[George P. <ge...@ga...>]

I did an experiment using dictionaries to bundle certain defined groups
of signals. I had some success with internal modules, but I wasn't able
to bundle the signals for the top module and get correct Verilog output.
(see below).

I also couldn't use the dict directly inside modules, (see wbcMaster)
which is also desirable in certain cases (sometimes it makes things
too cluttered, though)

Even with that limitation, bundling the signals using dicts
seems very attractive.

Of course, it would be even better to be able to do this with
the top module.

Feedback would be appreciated.

Thanks,
George

--- Begin code paste ---------

# myhdl_signal_bundling_experiment.py
# George Pantazopoulos
# MyHDL 0.5.1 signal bundling experiment using Python dicts
# 26 Sep 2006

from myhdl import *

#--------------------------------------------------------
# Signal bundling switch. Change and rerun this script
#
# Set to True to try bundling the top-level signals
# Set to False to use the default seperate signals
# -------------------------------------------------------
bundle_top_sigs = False

# 
----------------------------------------------------------------------------

# Toy Wishbone Master
def wbcMaster(master_sigs):

    # Unbundle the MASTER signals
    clk_i = master_sigs['clk_i']
    rst_i = master_sigs['rst_i']
    adr_o = master_sigs['adr_o']

    count = Signal(intbv(0)[8:])

    @always(clk_i.posedge)
    def Foo():

        if rst_i:
            count.next = 0
        else:
            count.next = (count + 1)
            adr_o.next = count

            # Note, we currently can't do this in MyHDL:
            # Though, it would be nice :)
            #master_sigs['adr_o'].next = count

    return instances()

# 
----------------------------------------------------------------------------

# External system controller connections.
# They are meant to link up with the top module's inputs
clk = Signal(bool(0))
rst = Signal(bool(0))

# SYSCON signal bundle
syscon_sigs = {}
syscon_sigs['clk_o'] = Signal(bool(0))
syscon_sigs['rst_o'] = Signal(bool(0))


# Top level module instantiation.


# Being able to bundle the signals for the top level module
# is desirable, but as of MyHDL 0.5.1 this does not seem to
# be supported
if bundle_top_sigs:

    print "--------------------------------"
    print " Using Bundled top-level signals"
    print "--------------------------------"
    print ""

    def top(syscon_sigs):

        master_sigs = {}

        master_sigs['clk_i'] = syscon_sigs['clk_o']
        master_sigs['rst_i'] = syscon_sigs['rst_o']
      
        master_sigs['adr_o'] = Signal(intbv(0)[16:])

        WBCM = wbcMaster(master_sigs)

        return instances()

    toVerilog.name = "myhdl_signal_packing_top_sigs_bundled"
    toVerilog(top, syscon_sigs)

    print "Created " + toVerilog.name + ".v"

# 
----------------------------------------------------------------------------

# Top signals seperate (the usual style)
else:


    print "---------------------------------"
    print " Using seperate top-level signals"
    print "---------------------------------"
    print ""
  
    def top(clk_i, rst_i):

        master_sigs = {}
        master_sigs['clk_i'] = clk_i
        master_sigs['rst_i'] = rst_i
      
        master_sigs['adr_o'] = Signal(intbv(0)[16:])

        WBCM = wbcMaster(master_sigs)

        return instances()
  
    toVerilog.name = "myhdl_signal_packing_top_sigs_separate"
    toVerilog(top, clk, rst)

    print "Created " + toVerilog.name + ".v"
   

# 
----------------------------------------------------------------------------

--------------------------------------------
Verilog code for Bundled top module signals:
--------------------------------------------

module myhdl_signal_packing_top_sigs_bundled (

);


reg [7:0] _WBCM_count;
wire _WBCM_rst_i;
reg [15:0] _WBCM_adr_o;


assign _WBCM_rst_i = 0;
always @(posedge _WBCM_clk_i) begin: 
_myhdl_signal_packing_top_sigs_bundled_WBCM_Foo
    if (_WBCM_rst_i) begin
        _WBCM_count <= 0;
    end
    else begin
        _WBCM_count <= (_WBCM_count + 1);
        _WBCM_adr_o <= _WBCM_count;
    end
end

endmodule



---------------------------------------------
Verilog code for separate top module signals:
---------------------------------------------

module myhdl_signal_packing_top_sigs_separate (
    clk_i,
    rst_i
);

input clk_i;
input rst_i;

reg [7:0] _WBCM_count;
reg [15:0] _WBCM_adr_o;


always @(posedge clk_i) begin: 
_myhdl_signal_packing_top_sigs_separate_WBCM_Foo
    if (rst_i) begin
        _WBCM_count <= 0;
    end
    else begin
        _WBCM_count <= (_WBCM_count + 1);
        _WBCM_adr_o <= _WBCM_count;
    end
end

endmodule

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

>> Also, the User-defined Verilog feature won't work because it would
>> create
>> nested modules that I confirmed do NOT work in Xilinx ISE.
>>
>
> I don't understand what you are saying won't work in ISE. Could you
> provide an
> example?
>

The User-defined Verilog works great and just as advertised for inserting
module instantiations into the MyHDL-generated Verilog code. I didn't mea=
n
to imply it was broken in some way.

What I mean is that I can't use that feature to declare additional, neede=
d
modules because it is only capable of inserting stuff *inside* existing
modules.

Something like this is not legal Verilog:

-- Begin example ----------------------------

// MyHDL-generated module
module top(...);

 // Verilog component from open-source library.
 module core(...);
   ... stuff ...
 endmodule

 core CORE_INST(...);

endmodule
-- End example -----------------------------

What I need is something like this:

-- Begin example ----------------------------


// contents of core.v pasted in by MyHDL
module core(...);

endmodule


// MyHDL-generated top module
module top(...);

  cor CORE_INST(...);

endmodule

-- End example -----------------------------

The above might be better done with an `include "core.v" or maybe an
`include "myhdl_verilog_deps.v" or something to that effect. I'm not sure
right now, and my Verilog skills could still use some sharpening.

George

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

> Also, the User-defined Verilog feature won't work because it would create
> nested modules that I confirmed do NOT work in Xilinx ISE.
>

I don't understand what you are saying won't work in ISE. Could you provide an 
example?

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

>> For my Verilog wrapping to be fully useful, I need MyHDL to do somethi=
ng
>> new.
>>
>> The problem right now is that I need to manually add any external
>> Verilog
>> files to Xilinx ISE's project manager or else the MyHDL output won't
>> synthesize due to missing modules.
>>
>> I'd love for MyHDL to automate this by slurping up any Verilog
>> dependencies specified in the MyHDL code and including them with its o=
wn
>> Verilog output.
>>
>
> I would recommend a makefile or a python script to automate this proces=
s
> for
> you.
>

I think your idea is reasonable, but having MyHDL handle it would be much
more powerful. It would allow MyHDL-wrapped Verilog modules to be treated
just like any other MyHDL module (from a synthesis standpoint anyway).

Also, the User-defined Verilog feature won't work because it would create
nested modules that I confirmed do NOT work in Xilinx ISE.

I believe it wouldn't be too hard to integrate this feature. It mainly
involves file reads and writes. No interpretation necessary.

I don't expect pure MyHDL simulation would be possible though, but
cosimulating with the user-included Verilog files should just work, right
Jan?

George

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Tom D. <TD...@di...>]

> For my Verilog wrapping to be fully useful, I need MyHDL to do something
> new.
>
> The problem right now is that I need to manually add any external Verilog
> files to Xilinx ISE's project manager or else the MyHDL output won't
> synthesize due to missing modules.
>
> I'd love for MyHDL to automate this by slurping up any Verilog
> dependencies specified in the MyHDL code and including them with its own
> Verilog output.
>

I would recommend a makefile or a python script to automate this process for 
you.

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

> George Pantazopoulos wrote:
>> This may be of interest. My verilog-wrapping and WISHBONE modules are
>> still experimental, but at some point I'd like to share them:
>>
>> http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81
>
> George:
>
> It's about time to announce all your achievements and the project page
> in comp.arch.fpga. I would think there is a large interested
> public over there (including FPGA vendors watching carefully.)
>
> Or do you prefer me to do it :-) ?
>

I'll take that as a complement, thanks! :-) Sounds like you have more
"street cred" in comp.arch.fpga right now, so I think you'd be a better
choice. I don't think I'm ready just yet, but feel free to ask again :-)

For my Verilog wrapping to be fully useful, I need MyHDL to do something =
new.

The problem right now is that I need to manually add any external Verilog
files to Xilinx ISE's project manager or else the MyHDL output won't
synthesize due to missing modules.

I'd love for MyHDL to automate this by slurping up any Verilog
dependencies specified in the MyHDL code and including them with its own
Verilog output.

For example, I could give the toVerilog convertor a set of (verilog)
filenames, or even a directory name. It then reads in all those files and
combines them with the Verilog output. The "combining" is simply pasting
the  text in somehow with the MyHDL-generated Verilog; no interpretation
necessary.

This could be as simple as appending them all to the MyHDL Verilog output
file. Alternatively, it could create a seperate verilog output file or
files containing all the "dependencies". That way, the MyHDL output would
be completely ready to use, without the user needing external knowledge
about which Verilog files to include into their synthesis tool's project.

It sounds pretty simple. What do you think?

George



> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>      From Python to silicon:
>      http://myhdl.jandecaluwe.com
>
>
> -----------------------------------------------------------------------=
--
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> _______________________________________________
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>


--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] PhoenixSID 65X81 News page updated

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> This may be of interest. My verilog-wrapping and WISHBONE modules are
> still experimental, but at some point I'd like to share them:
> 
> http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

George:

It's about time to announce all your achievements and the project page
in comp.arch.fpga. I would think there is a large interested
public over there (including FPGA vendors watching carefully.)

Or do you prefer me to do it :-) ?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Beginners question

[Thomas H. <th...@py...>]

If I have two or more events in an always decorator:

@always(a.negedge, b.negedge, delay(10))
def func():
    ...

how can I determine inside func which event is currently handled?

(my first steps with myhdl)

Thanks,
Thomas

Re: [myhdl-list] Can classes be used to synthesize hardware?

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>> Can classes be used to create synthesizable Verilog? I've tried but was
>>>unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
>>>really confused as to how this is supposed to work.
>>
>>I don't know. I haven't even started to think about if and how
>>classes could be useful for "implementation-oriented" modeling.
>>Definitely the convertor now implicitly assumes that one is using
>>generator functions, not methods. Methods would require handling
>>the "self" reference and its attributes and mapping them to Verilog
>>somehow - a completely different mechanism than what the convertor
>>can do today.
> 
> 
> Ahh, no problem. It was just one of crazy experiments. I'm much more
> comfortable  using generators right now,

Upon rereading I'd like to stress to all readers that the restrictions
mentioned are *only* related to code that is intended for conversion.
Of course, that is an important and crucial application, but not the
only one. One should appreciate the difficulties related to converting
an extremely dynamic "scripting" language to HDLs such as Verilog
and VHDL. This leads to very important restrictions. But these should
not get in the way for high-level modeling.

For modeling, MyHDL intends (and succeeds I believe) to be extremely
general. There is e.g. no problem using classes and generator
methods, and they can be very useful for high-level modeling.
As a result and because of the power of Python, you can do things
that you couldn't dream of in classical HDLs.

Just one example: a dynamic sensitivity list (that is, the list of
things that a generator waits on is created dynamically, at run time.)
I had once an example where that was natural and useful, but it's an
unknown concept in classical HDLs (I hereby claim the invention :-)).

> except for cases where there are
> many signals which can cause long, cumbersome argument lists at times. I'm
> curious if there any "tricks" to manage that complexity

There may be several possibilities. Perhaps best to discuss
on a relevant example.

> In any case, I'd much rather have native bidirectional/tristate support :-)

I'm working on it :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] PhoenixSID 65X81 News page updated

[George P. <ge...@ga...>]

This may be of interest. My verilog-wrapping and WISHBONE modules are
still experimental, but at some point I'd like to share them:

http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Can classes be used to synthesize hardware?

[George P. <ge...@ga...>]

>>  Can classes be used to create synthesizable Verilog? I've tried but w=
as
>> unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
>> really confused as to how this is supposed to work.
>
> I don't know. I haven't even started to think about if and how
> classes could be useful for "implementation-oriented" modeling.
> Definitely the convertor now implicitly assumes that one is using
> generator functions, not methods. Methods would require handling
> the "self" reference and its attributes and mapping them to Verilog
> somehow - a completely different mechanism than what the convertor
> can do today.

Ahh, no problem. It was just one of crazy experiments. I'm much more
comfortable  using generators right now, except for cases where there are
many signals which can cause long, cumbersome argument lists at times. I'=
m
curious if there any "tricks" to manage that complexity.

In any case, I'd much rather have native bidirectional/tristate support :=
-)

Regards,
--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Can classes be used to synthesize hardware?

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hey all,
>  Can classes be used to create synthesizable Verilog? I've tried but was
> unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
> really confused as to how this is supposed to work.

I don't know. I haven't even started to think about if and how
classes could be useful for "implementation-oriented" modeling.
Definitely the convertor now implicitly assumes that one is using
generator functions, not methods. Methods would require handling
the "self" reference and its attributes and mapping them to Verilog
somehow - a completely different mechanism than what the convertor
can do today.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Can classes be used to synthesize hardware?

[George P. <ge...@ga...>]

Hey all,
 Can classes be used to create synthesizable Verilog? I've tried but was
unsuccessful (mostly getting cryptic "AssertionError" exceptions). I'm
really confused as to how this is supposed to work.

 If this is possible, could I see a tiny example?

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] Verilog Bidirectional tristateable bus example

[George P. <ge...@ga...>]

Hi all,
    I managed to create a dual-unidirectional to bidirectional bus adapter
in Verilog and boil it down to a simple example (see below).

    This actually worked on my Digilent Spartan3 board! (tested using
switches and buttons).

    Jan, how could we get MyHDL to output Verilog code like this? What 
would
the MyHDL input have to look like?

What modifications are necessary to MyHDL 0.5.1? If we could do this,
then I believe that would enough to allow me to access an external SRAM 
chip
and do it all from within MyHDL!

Thanks,
George
   

// George Pantazopoulos
// Bidirectional tristateable bus example
// http://www.gammaburst.net

/////////////////////////////////////////////////////////////////////////////
//
//      --------------------------
// --/->| din         "Module Z" |
//      |                        |
// --->o| /OE                    |
//      |                        |
//      |                bi_data |<--/--->
//      |                        |
//      |                        |
// <-/--| dout                   |
//      --------------------------
//
//
// - If /OE is low, then:
//          bi_data is driven with din.
//          dout is driven with 0xA.
//
// - Otherwise,
//          bi_data's output drivers are tristated.
//          dout follows bi_data (external device must drive bi_data).
//
module top(bi_data, dout, din, nOE);

parameter DATA_BITS = 4;

// Note: inout
inout  [DATA_BITS-1:0] bi_data;
wire   [DATA_BITS-1:0] bi_data;

input  [DATA_BITS-1:0] din;
wire   [DATA_BITS-1:0] din;

output [DATA_BITS-1:0] dout;
wire   [DATA_BITS-1:0] dout;

input nOE;
wire  nOE;

assign bi_data = !nOE ? din : { DATA_BITS {1'bz} };

assign dout    = !nOE ? 4'hA : bi_data;

endmodule

[myhdl-list] Python 2.5 released!

[George P. <ge...@ga...>]

A brand new version of my favorite programming language is out, Python 2.=
5:

http://www.python.org/news/

New with Python 2.5 is an interesting new capability of passing values
into generators:

http://docs.python.org/dev/whatsnew/pep-342.html

Can this make it possible for @always and @instance blocks to have local
variables?

Rock on,

George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> 
> Wow, so toVHDL is alive. I thought we didn't need it :)

Me too. But that was 2 years ago :-)

I have changed my mind because of the following reasons.

First, from the feedback I got it is clear that VHDL is
more popular than I anticipated, especially in the FPGA
world. Naturally, a tool has more chance of adoption if
it plays well with existing design flows.

A related second reason is that having both Verilog and
VHDL output from a single source creates a capability
that is afaik unique: designing IP blocks once and
creating equivalent RTL-level Verilog and VHDL automatically.
That must be an attractive proposition to IP developers.

Third, I found a way to solve the issue of how to verify
the VHDL output without need for co-simulation. I'm using
a prototype of this currently - works great.

And fourth, it was time for a new intellecual challenge :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

> As from you. I notice that many people find their way to the MyHDL
> pages from your fpga synth project (although not many seem to
> follow your path and go for it themselves :-). What are you
> doing with this project - do you share it with other enthousiast?
> Plans to open source it? or commercial plans?
>   
:-) They don't know what they're missing.. Python and MyHDL rock!

I'm not sure yet what I want to do. I might open source some version, 
and I have had several people ask me if I will sell it. That's a 
possibility. But for a next step, I'd really like to get a board made. 
I've designed boards before, and I miss it.. its hard, exacting work, 
but its also fun and so cool being able to hold this complicated looking 
board in your hand and say "hey, I made this!"


>
> At some point I would like to take some time to think thorougly
> about tristates and inouts and come up with a satisfactory
> solution, hopefully based on user inputs and feedback.
> Currently, I'm focussed on getting toVHDL on track
> and right - which offers more than enough brain teasers :-)
>
>   
Wow, so toVHDL is alive. I thought we didn't need it :) I'm sure you 
have a good reason for pursuing it though.


By the way, I set up subversion for version control and have started to 
build my own library of reusable parts. I'm so glad I took the time to 
set this all up, its helping me get back and enjoy it even more this 
time around!

Regards,
George

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> Great to hear from you again Jan!

As from you. I notice that many people find their way to the MyHDL
pages from your fpga synth project (although not many seem to
follow your path and go for it themselves :-). What are you
doing with this project - do you share it with other enthousiast?
Plans to open source it? or commercial plans?

> I will try out your and Gunter's suggestions. What I'd like is an
> automatic way to combine the myhdl code with a user-supplied top-level
> Verilog wrapper.
> 
> This might be doable with shell scripting and/or make, but being able to
> specify the wrapper filename inside the myHDL code sounds like a better
> way right now. MyHDL could automatically incorporate the wrapper into its
> Verilog output. I'll have to experiment a bit to be sure, but what do you
> think?

At some point I would like to take some time to think thorougly
about tristates and inouts and come up with a satisfactory
solution, hopefully based on user inputs and feedback.
Currently, I'm focussed on getting toVHDL on track
and right - which offers more than enough brain teasers :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> Great to hear from you again Jan!

As from you. I notice that many people find their way to the MyHDL
pages from your fpga synth project (although not many seem to
follow your path and go for it themselves :-). What are you
doing with this project - do you share it with other enthousiast?
Plans to open source it? or commercial plans?

> I will try out your and Gunter's suggestions. What I'd like is an
> automatic way to combine the myhdl code with a user-supplied top-level
> Verilog wrapper.
> 
> This might be doable with shell scripting and/or make, but being able to
> specify the wrapper filename inside the myHDL code sounds like a better
> way right now. MyHDL could automatically incorporate the wrapper into its
> Verilog output. I'll have to experiment a bit to be sure, but what do you
> think?

At some point I would like to take some time to think thorougly
about tristates and inouts and come up with a satisfactory
solution, hopefully based on user inputs and feedback.
Currently, I'm focussed on getting toVHDL on track
and right - which offers more than enough brain teasers :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>>      Maybe I should be more clear. I'm looking to create a
>> *bidirectional*
>> bus to an external SRAM chip. I suppose somehow the output driver
>> needs to get tristated when the the bus is in input mode. I'm not
>> sure how to bring this about, or if the fpga software tool will infer
>> this for me, etc.

> But you are talking about off-chip of course. Let's separate
> the issues:

> Verilog conversion support
> --------------------------
>
> Nothing has been done. At least 2 things would be needed:
> 1) convert a None constant value to 'Z'
> 2) infer inout ports at the top-level interface when
> an interface signal is used as such.
>
> In addition, it would be nice to know what templates are
> exactly supported by the mainstream fgpa synthesis tools
> to infer tristates, tristate ports, and bidirectional ports.
> This may influence Verilog conversion choices.
>
> Because of 2), you cannot simply use the user-defined verilog
> feature to specify the verilog code you want yourself.
> I fear the workaround at this point is a manually written
> top-level Verilog wrapper, as suggested elsewhere.
>

Great to hear from you again Jan!

I will try out your and Gunter's suggestions. What I'd like is an
automatic way to combine the myhdl code with a user-supplied top-level
Verilog wrapper.

This might be doable with shell scripting and/or make, but being able to
specify the wrapper filename inside the myHDL code sounds like a better
way right now. MyHDL could automatically incorporate the wrapper into its
Verilog output. I'll have to experiment a bit to be sure, but what do you
think?

> For a possible implementation of the features discussed
> above, I need feedback from users to find out and specify
> exactly what needs to be done, and how urgent it is.
>

I'll be glad to give you any feedback I can. I'm starting to create a VGA
controller in my FPGA, and in a while, I'll need to access external RAM :=
)

Peace,

George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>Hi all,
>>
>>   I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>>me some pointers on how a tristate data bus could be implemented in
>>myHDL?
>>
> 
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 
> Any advice would be great!

I've deliberately neglected the issue because I believe there's
hardly a good reason to use tristates *on-chip*.

But you are talking about off-chip of course. Let's separate
the issues:

Modeling
--------

In 0.5 it is possible to use None as a value for an intbv:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#backwards_incompatible_changes

The idea is to use None to represent a tristate value. I believe this
is quite appropriate.

When you use a None value in an expression, you will easily get
tracebacks. Also this I think is appropriate. In other words,
I don't plan to extend operator support for intbv's to do something
"meaningful" with None values. The designer should surround such
expressions with tests for appropriate usage. (E.g. note that
any value is larger than None in Python.)

Verilog conversion support
--------------------------

Nothing has been done. At least 2 things would be needed:
1) convert a None constant value to 'Z'
2) infer inout ports at the top-level interface when
an interface signal is used as such.

In addition, it would be nice to know what templates are
exactly supported by the mainstream fgpa synthesis tools
to infer tristates, tristate ports, and bidirectional ports.
This may influence Verilog conversion choices.

Because of 2), you cannot simply use the user-defined verilog
feature to specify the verilog code you want yourself.
I fear the workaround at this point is a manually written
top-level Verilog wrapper, as suggested elsewhere.

For a possible implementation of the features discussed
above, I need feedback from users to find out and specify
exactly what needs to be done, and how urgent it is.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Bitonic sort circuit

[Jan D. <ja...@ja...>]

Hi:

Recently there has been a discussion on comp.lang.verilog
about recursive structures and their synthesizability.
The bitonic sort algorithm served as an example.

I have coded a bitonic sorter circuit in MyHDL and set up
a cookbook page about it. Basically, the page describes how
to code recursive structures in MyHDL. It also illustrates
that Verilog code generation occurs after elaboration.
Consequently, the generated Verilog code is no longer
recursive. Therefore, it doesn't matter whether the back-end
language or tools support recursion or not. See:

     http://myhdl.jandecaluwe.com/doku.php/cookbook:bitonic

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>>
>>      Maybe I should be more clear. I'm looking to create a
>> *bidirectional*
>> bus to an external SRAM chip. I suppose somehow the output driver
>> needs to get tristated when the the bus is in input mode. I'm not
>> sure how to bring this about, or if the fpga software tool will infer
>> this for me, etc.
>>
>
> You could try doing a multiplexer in Verilog and interface that to your
> Python code. Something like this:
>
>       MyHDL       |       Verilog
>                   |
>                        +\
>       Write data ----->+ \
>                        |  +<----->
>       Read data  <-----+ /
>                        +/
>                   |

I'll check that out, thanks. I also came across a verilog tutorial for
bidirectional/tristate here:
http://www.quicklogic.com/images/quicknote36.pdf#search=3D%22verilog%20tr=
istate%22

module example (OE, in1, in2, bi_ext, tri_ext);
input OE, in1, in2;
inout bi_ext;
output tri_ext;
wire bi_ext =3D OE ? (in1 & in2) : 1=92bz;
wire tri_ext =3D OE ? (bi_ext | in2) : 1=92bz;
endmodule

So between those two I think I can get something to work. Any tips on how
to smoothly integrate this with myHDL?

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Guenter D. <dan...@we...>]

George Pantazopoulos wrote:
>> Hi all,
>>
>>    I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>> me some pointers on how a tristate data bus could be implemented in
>> myHDL?
>>
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 

You could try doing a multiplexer in Verilog and interface that to your
Python code. Something like this:

      MyHDL       |       Verilog
                  |
                       +\
      Write data ----->+ \
                       |  +<----->
      Read data  <-----+ /
                       +/
                  |


You would also need a control signal to specify the direction.

Maybe that works?

Cheers,

Guenter