myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Tristate bus to external SRAM

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>Hi all,
>>
>>   I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>>me some pointers on how a tristate data bus could be implemented in
>>myHDL?
>>
> 
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 
> Any advice would be great!

I've deliberately neglected the issue because I believe there's
hardly a good reason to use tristates *on-chip*.

But you are talking about off-chip of course. Let's separate
the issues:

Modeling
--------

In 0.5 it is possible to use None as a value for an intbv:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#backwards_incompatible_changes

The idea is to use None to represent a tristate value. I believe this
is quite appropriate.

When you use a None value in an expression, you will easily get
tracebacks. Also this I think is appropriate. In other words,
I don't plan to extend operator support for intbv's to do something
"meaningful" with None values. The designer should surround such
expressions with tests for appropriate usage. (E.g. note that
any value is larger than None in Python.)

Verilog conversion support
--------------------------

Nothing has been done. At least 2 things would be needed:
1) convert a None constant value to 'Z'
2) infer inout ports at the top-level interface when
an interface signal is used as such.

In addition, it would be nice to know what templates are
exactly supported by the mainstream fgpa synthesis tools
to infer tristates, tristate ports, and bidirectional ports.
This may influence Verilog conversion choices.

Because of 2), you cannot simply use the user-defined verilog
feature to specify the verilog code you want yourself.
I fear the workaround at this point is a manually written
top-level Verilog wrapper, as suggested elsewhere.

For a possible implementation of the features discussed
above, I need feedback from users to find out and specify
exactly what needs to be done, and how urgent it is.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Bitonic sort circuit

[Jan D. <ja...@ja...>]

Hi:

Recently there has been a discussion on comp.lang.verilog
about recursive structures and their synthesizability.
The bitonic sort algorithm served as an example.

I have coded a bitonic sorter circuit in MyHDL and set up
a cookbook page about it. Basically, the page describes how
to code recursive structures in MyHDL. It also illustrates
that Verilog code generation occurs after elaboration.
Consequently, the generated Verilog code is no longer
recursive. Therefore, it doesn't matter whether the back-end
language or tools support recursion or not. See:

     http://myhdl.jandecaluwe.com/doku.php/cookbook:bitonic

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>>
>>      Maybe I should be more clear. I'm looking to create a
>> *bidirectional*
>> bus to an external SRAM chip. I suppose somehow the output driver
>> needs to get tristated when the the bus is in input mode. I'm not
>> sure how to bring this about, or if the fpga software tool will infer
>> this for me, etc.
>>
>
> You could try doing a multiplexer in Verilog and interface that to your
> Python code. Something like this:
>
>       MyHDL       |       Verilog
>                   |
>                        +\
>       Write data ----->+ \
>                        |  +<----->
>       Read data  <-----+ /
>                        +/
>                   |

I'll check that out, thanks. I also came across a verilog tutorial for
bidirectional/tristate here:
http://www.quicklogic.com/images/quicknote36.pdf#search=3D%22verilog%20tr=
istate%22

module example (OE, in1, in2, bi_ext, tri_ext);
input OE, in1, in2;
inout bi_ext;
output tri_ext;
wire bi_ext =3D OE ? (in1 & in2) : 1=92bz;
wire tri_ext =3D OE ? (bi_ext | in2) : 1=92bz;
endmodule

So between those two I think I can get something to work. Any tips on how
to smoothly integrate this with myHDL?

Thanks,

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Tristate bus to external SRAM

[Guenter D. <dan...@we...>]

George Pantazopoulos wrote:
>> Hi all,
>>
>>    I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
>> me some pointers on how a tristate data bus could be implemented in
>> myHDL?
>>
> 
>      Maybe I should be more clear. I'm looking to create a *bidirectional*
> bus to an external SRAM chip. I suppose somehow the output driver
> needs to get tristated when the the bus is in input mode. I'm not
> sure how to bring this about, or if the fpga software tool will infer
> this for me, etc.
> 

You could try doing a multiplexer in Verilog and interface that to your
Python code. Something like this:

      MyHDL       |       Verilog
                  |
                       +\
      Write data ----->+ \
                       |  +<----->
      Read data  <-----+ /
                       +/
                  |


You would also need a control signal to specify the direction.

Maybe that works?

Cheers,

Guenter

Re: [myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

>
> Hi all,
>
>    I'm gettin' hungry to do some more FPGA stuff again. Could anyone gi=
ve
> me some pointers on how a tristate data bus could be implemented in
> myHDL?
>

     Maybe I should be more clear. I'm looking to create a *bidirectional=
*
bus to an external SRAM chip. I suppose somehow the output driver
needs to get tristated when the the bus is in input mode. I'm not
sure how to bring this about, or if the fpga software tool will infer
this for me, etc.

Any advice would be great!

Thanks

--=20
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] Tristate bus to external SRAM

[George P. <ge...@ga...>]

Hi all,

   I'm gettin' hungry to do some more FPGA stuff again. Could anyone give
me some pointers on how a tristate data bus could be implemented in
myHDL?

Thanks,
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] Re: ListElementNotUnique error

[Jan D. <ja...@ja...>]

Jens Petter Abrahamsen wrote:
> Hi, I hope someone who knows more MyHDL/Python than myself can have a 
> look  at this:
> 
> I keep getting the following error from toVerilog():
> List contains Signals that are not unique to it
> 
> I have a list of signals. The signals are driven inside a module, 
> called  like this:
> 
>     signal_list = [Signal(intbv(0)[WIDTH:]) for i in range(NUMBER)]
>     insts = [module_name(signal_list[i]) for i in range(NUMBER)]
> 
> I want to compare the outputs from all the instances, to select the  
> highest one. So after the previous code, I add the following:
> 
>    @always(clk.negedge)
>     def select_best():
>         """Compare values and select the best one"""
>         best=0
>         for nr in range(NR_REGS):
>             if signal_list[nr] > signal_list[best]: # I have also tried  
> .val on them
>                 best=nr
> 
>     max.next = best
> 
> This gives me the ListElementNotUnique error from the toVerilog converter.
> 
> Is it not supposed to be possible? How should it be done?

Again, the problems is related to restrictions on how lists of signals
can be mapped to Verilog memories.

First, let me present something similar that does work :-)

     def compare(z, a, b):
         @always_comb
         def logic():
             if a > b:
                 z.next = a
             else:
                 z.next = b
         return logic

     def top(dout, din0, din1, din2, din3, clk):
         din = [din0, din1, din2, din3]
         max = [Signal(intbv(0)[4:]) for i in range(len(din))]
         max[0] = din[0]
         inst = [compare(max[i+1], max[i], din[i+1])
                     for i in range(len(din)-1)]
         dout = max[-1] # last in list

     return inst

Note how I can do all kinds of maniplations with lists. The difference
with your example is that list syntax is not used inside generator code.
All list handling is done before "elaboration", and thus before the
conversion starts. See the manual for more info on elaboration if
required.

The above example can be converted, while yours can't - but neither
could be done straightforwardly (= with similar constructs) in Verilog
directly. So we do gain something.

Verilog memories have all kinds of restrictions. Therefore, they
are in general avoided by the convertor. Instead, when a signal
is both in a list, and has a plain name at some other level in
the hierarchy, that name is used in the output, and no memory
is declared.

At first, I had actually done this differently, giving precence
to memory declarations (as is should be.) However, I had to back
off because of memory restrictions. For more info, see the
posts in this mailing list dated 08/09/2005, with subject:
"Ram inference from toVerilog output". The news url is:

   news://news.gmane.org:119/42F...@ja...

There is one exception: if you declare a list that contains
Signals that are not used in other hierarchical levels, you
can use it in your generator functions. In this way, you
can describe RAM structures. See also:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#mapping_a_list_of_signals_to_a_ram_memory

The convertor detects valid usage, and flags an error otherwise.
This is the error you see. I agree it seems mysterious, so
I'll have a thought of a better error name & explanation.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Jan D. <ja...@ja...>]

Guenter Dannoritzer wrote:

> There is a restriction to what type of signals can be converted with
> toVerilog:
> 
> http://www.jandecaluwe.com/Tools/MyHDL/manual/conv-subset-types.html

This describes the restriction for code inside generator functions.
I guess I'll have to add a specific section about the (more severe)
restrictions for the top-level interface of a module. In fact,
only Signals with intbv, bool or enum base types can be
converted.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Jan D. <ja...@ja...>]

Jens Petter Abrahamsen wrote:
> Hi.
> 
> I've been experimenting much with MyHDL, I like it, and I'd like to 
> make  some synthesizeable code real soon. I don't have any Verilog/VHDL  
> experience, maybe my questions are very basic.
> 
> All the examples I've seen of MyHDL->Verilog has a set number of  
> input/output signals. I'd like to create a program which has all the  
> signals inside a list (to be more flexible).
> 
> Consider the following example:
> 
> def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
>     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in  
> range(NR_REGS)]
>     return inst
> 
> def convert_shiftregister_to_verilog():
>     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
>     WIDTH=8
>     NR_REGS=2
>     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
>     din = [Signal(bool(0)) for i in range(NR_REGS)]
> 
>     toVerilog.name="shiftregister"
>     toVerilog(make_many_sregs,clk,din,WIDTH,out,reset,enable,NR_REGS)
> 
> The intention is that NR_REGS gives how many shift-registers I'd like. 
> I  make the same number of data in and parallel out Signals as  
> shift-registers.
> This is the generated Verilog code. Where are din/out signals?

They are not there, basically because there is no straightforward way
to map list of signals in an interface to a Verilog object. Verilog
memories cannot be used in an interface. (I'm not considering
SystemVerilog for the time being.)

> I also get complaints that Signals are either not driven or used when  
> keeping signals in a list.

That is a symptom of the above. The signal drivers are not "found"
because lists in interfaces are not considered. Not that this
only affects the top-level interface, because the other ones
are flattened out by the convertor.

This case violates the idea that if toVerilog() succeeds without errors,
then a MyHDL simulation and the converted Verilog simulation should
do the same. So there should be errors and no output instead of
warnings.

However, I cannot just turn the warnings into errors - in other
case people want this behavior (and the simulations will match).
Also, I don't want to do strict typechecking on the MyHDL interface,
in order to allow powerful parametrization. (toVerilog() works on
a particular instance and doesn't need the parameters.) So I'll
have to think about this further.

So, at the top-level you'll have to use individual signals at
this moment. However, once you have done that you can still
proceed with lists as follows:

def top(din1, din2, ..., dinn, dout1, dout2, ...doutn, ...):
    din = [din1, din2, ..., dinn] # cut and paste from interface
    dout = [dout1, dout2, ..., doutn]

    # now use list syntax here
    ...

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: List of Signals as input/output in a toVerilog()

[Guenter D. <dan...@we...>]

Jens Petter Abrahamsen wrote:
> Hi.
> 
> I've been experimenting much with MyHDL, I like it, and I'd like to make
> some synthesizeable code real soon. I don't have any Verilog/VHDL
> experience, maybe my questions are very basic.
> 
> All the examples I've seen of MyHDL->Verilog has a set number of
> input/output signals. I'd like to create a program which has all the
> signals inside a list (to be more flexible).
> 
> Consider the following example:
> 
> def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
>     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in
> range(NR_REGS)]
>     return inst
> 
> def convert_shiftregister_to_verilog():
>     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
>     WIDTH=8
>     NR_REGS=2
>     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
>     din = [Signal(bool(0)) for i in range(NR_REGS)]
> 
As an example din is:

din = [Signal(False), Signal(False), Signal(False), Signal(False)]

... a list of signals.

There is a restriction to what type of signals can be converted with
toVerilog:

http://www.jandecaluwe.com/Tools/MyHDL/manual/conv-subset-types.html


Cheers,

Guenter

Re: [myhdl-list] ListElementNotUnique error

[<dan...@we...>]

Jens Petter Abrahamsen wrote:
> Hi, I hope someone who knows more MyHDL/Python than myself can have a
> look at this:
> 
> I keep getting the following error from toVerilog():
> List contains Signals that are not unique to it

Have you tried first simulating it? Usually simulation returns more
meaningful error messages.

> 
> I have a list of signals. The signals are driven inside a module, called
> like this:
> 
>     signal_list = [Signal(intbv(0)[WIDTH:]) for i in range(NUMBER)]
>     insts = [module_name(signal_list[i]) for i in range(NUMBER)]
> 

I haven't worked with lists of instances yet, but when you look at the
following example:

http://www.jandecaluwe.com/Tools/MyHDL/manual/model-instarray.html

The instantiation is done a bit different than you do it.


> I want to compare the outputs from all the instances, to select the
> highest one. So after the previous code, I add the following:
> 
>    @always(clk.negedge)
>     def select_best():
>         """Compare values and select the best one"""
>         best=0
>         for nr in range(NR_REGS):
>             if signal_list[nr] > signal_list[best]: # I have also tried
> .val on them
>                 best=nr
> 
>     max.next = best
      ^^^^^^^^^^^^^^^
Is that indention wrong from copying it? The variable best is local to
select_best(). You should not be able to access it outside or am I am wrong?

> 
          ^^^^^^^^
I think here is a:

   return select_best

missing.

Hope that helps.

Cheers,

Guenter

[myhdl-list] ListElementNotUnique error

[Jens P. A. <je...@if...>]

Hi, I hope someone who knows more MyHDL/Python than myself can have a look  
at this:

I keep getting the following error from toVerilog():
List contains Signals that are not unique to it

I have a list of signals. The signals are driven inside a module, called  
like this:

     signal_list = [Signal(intbv(0)[WIDTH:]) for i in range(NUMBER)]
     insts = [module_name(signal_list[i]) for i in range(NUMBER)]

I want to compare the outputs from all the instances, to select the  
highest one. So after the previous code, I add the following:

    @always(clk.negedge)
     def select_best():
         """Compare values and select the best one"""
         best=0
         for nr in range(NR_REGS):
             if signal_list[nr] > signal_list[best]: # I have also tried  
.val on them
                 best=nr

	max.next = best

This gives me the ListElementNotUnique error from the toVerilog converter.

Is it not supposed to be possible? How should it be done?


Thanks,

Jens Petter Abrahamsen.

[myhdl-list] List of Signals as input/output in a toVerilog()

[Jens P. A. <je...@if...>]

Hi.

I've been experimenting much with MyHDL, I like it, and I'd like to make  
some synthesizeable code real soon. I don't have any Verilog/VHDL  
experience, maybe my questions are very basic.

All the examples I've seen of MyHDL->Verilog has a set number of  
input/output signals. I'd like to create a program which has all the  
signals inside a list (to be more flexible).

Consider the following example:

def make_many_sregs(clk,din,WIDTH,out,reset,enable,NR_REGS):
     inst = [shiftreg(clk,din[i],WIDTH,out[i],reset,enable) for i in  
range(NR_REGS)]
     return inst

def convert_shiftregister_to_verilog():
     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
     WIDTH=8
     NR_REGS=2
     out = [Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
     din = [Signal(bool(0)) for i in range(NR_REGS)]

     toVerilog.name="shiftregister"
     toVerilog(make_many_sregs,clk,din,WIDTH,out,reset,enable,NR_REGS)

The intention is that NR_REGS gives how many shift-registers I'd like. I  
make the same number of data in and parallel out Signals as  
shift-registers.
This is the generated Verilog code. Where are din/out signals?

module shiftregister (
     clk,
     reset,
     enable
);

input clk;
input reset;
input enable;

wire _inst_2_din;
reg [7:0] _inst_2_pout;
reg [7:0] _inst_2_regi;
wire _inst_1_din;
reg [7:0] _inst_1_pout;
reg [7:0] _inst_1_regi;
wire _inst_0_din;
reg [7:0] _inst_0_pout;
reg [7:0] _inst_0_regi;

If I didn't put the signals in lists, but instead had separate variables  
for each signal, e.g. out1, out2, out3 and din1, din2, din3, the module  
will become different:

def  
make_many_sregs(clk,din1,din2,din3,WIDTH,out1,out2,out3,reset,enable,NR_REGS):
     inst=[]
     inst.append(shiftreg(clk,din1,WIDTH,out1,reset,enable))
     inst.append(shiftreg(clk,din2,WIDTH,out2,reset,enable))
     inst.append(shiftreg(clk,din3,WIDTH,out3,reset,enable))
     return inst

def convert_shiftregister_to_verilog():
     clk,reset,enable = [Signal(bool(0)) for i in range(3)]
     WIDTH=8
     NR_REGS=3
     out1,out2,out3=[Signal(intbv(0)[WIDTH:]) for i in range(NR_REGS)]
     din1,din2,din3 = [Signal(bool(0)) for i in range(NR_REGS)]

     toVerilog.name="shiftregister"
     toVerilog(make_many_sregs,clk,din1,din2,din3,WIDTH,out1,out2,out3,reset,enable,NR_REGS)


Now the Verilog module has more input/output parameters:

module shiftregister (
     clk,
     din1,
     din2,
     din3,
     out1,
     out2,
     out3,
     reset,
     enable
);

input clk;
input din1;
input din2;
input din3;
output [7:0] out1;
reg [7:0] out1;
output [7:0] out2;
reg [7:0] out2;
output [7:0] out3;
reg [7:0] out3;
input reset;
input enable;


I also get complaints that Signals are either not driven or used when  
keeping signals in a list.

Since in both cases, the design that is converted will be of a specified  
size (number of shift-registers) how are they different?

I'm sorry if this an absurd question.


Thanks,
Jens Petter Abrahamsen

[myhdl-list] Re: Newbie question

[Jan D. <ja...@ja...>]

Jamie Guinan wrote:
> Hi!
> 
> I'm just getting started with MyHDL.  In fact, this is my first 
> experience with digital electronics modelling, but since I know Python 
> pretty well (I use it for about 50% of my work), MyHDL looks like a 
> great way to get started.
> 
> My question: if I have a 4-bit output signal, how can I isolate 1 bit 
> to use as an input to another item that takes a 1-bit input signal?

In MyHDL, you will have to explicitly create a 1-bit signal, e.g.

event = Signal(bool(0))
@always_comb
def driveEvent():
     event.next = output[0]

In MyHDL, slice/index operations on a Signal are not signals themselves,
but are simply delegated to the corresponding access on the current
value (as with all other operators.)

In languages like VHDL/Verilog, you can get the behavior that you
expect. Therefore, this is a weak point of MyHDL (and in fact I'm
surprized that this is the first time it was reported :-)). But
I think here we are at the limits of what you can expect from
a "scripting" language. In VHDL/Verilog, a compilation step can
disambuigate between "structural" usage (as a signal) and
"behavioral" usage (as a value.) Without such a step, the
possibilites are much more restricted.

Of course, I thought about the possibility to implement slice/index
operations that return new Signals, but this becomes very
complicated. s and s[i] are then not just separate signals, but
any assignment to either one should have the appropriate effect
in the other one. Not simple.

So I decided to keep it simple and rely on the user for explicit
"conversions" between the views where appropriate. Note that in
a higher-level design style (less signals), such conversions
should be much less required than in a lower-level design style
(with a lot of structure and signals).

Moreover, MyHDL does have a feature that can help in the
structure view: lists of signals. Instead of using
a single wide signal to start with, you can use individual signals
grouped in a list to describe iterative structures.

It is also possible to create generic modules
that convert between a wide signal and a list of signals,
and vice versa.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Newbie question

[Jamie G. <gu...@bl...>]

Hi!

I'm just getting started with MyHDL.  In fact, this is my first 
experience with digital electronics modelling, but since I know Python 
pretty well (I use it for about 50% of my work), MyHDL looks like a 
great way to get started.

My question: if I have a 4-bit output signal, how can I isolate 1 bit 
to use as an input to another item that takes a 1-bit input signal?

Here's an example, see the comments near the bottom.

<code>
#!/usr/bin/python

from myhdl import *

def ClkDriver(clk):
    halfPeriod = delay(1)
    @always(halfPeriod)
    def driveClk():
        clk.next = not clk
        # print 'clk: %s' % now()
    return driveClk


def BcdDownCounter(clk, Qout):
    @always(clk.posedge) 
    def downCount():
        if Qout == 0:  
            Qout.next = Qout + 9
        else:
            Qout.next = Qout - 1
        print 'bcd: %s' % Qout.next
    return downCount

def Trigger(input):
    @always(input.posedge)
    def logic():
        print 'trigger'
    return logic


output = Signal(intbv(0)[4:])
input = Signal(bool(0))
clk = Signal(0)

clock_inst = ClkDriver(clk)
counter_inst = BcdDownCounter(clk, output)

if 1:
    # This works, for illustration, but isn't what I'm after:
    trigger_inst = Trigger(clk)

## Here's some of my failed attempts:
if 0:
    # This returns a bool, not a Signal, so it fails with
    #  AttributeError: 'bool' object has no attribute 'posedge'
    trigger_inst = Trigger(output[0])

if 0:
    # Signal initialized only with intial value, does not track output[n]
    trigger_inst = Trigger(Signal(output[0]))

# The simulation.
sim = Simulation(clock_inst,
                 counter_inst,
                 trigger_inst)
sim.run(40)
</code>

Thanks,
-Jamie

[myhdl-list] Re: 0.5.1 released

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Thanks for your efforts, Jan.
> 
> I'll try it out as soon as I get back into PhoenixSID (I'm taking a break
> from it at the moment). 

I needed to do this release because the latest CookBook example
failed with 0.5 - some bugs in handling the Verilog signed type
with shift operations.

It's probably not urgent for you, otherwise you would have
complained earlier :-)

 > I did do a successful live demo of my synth
> (powered by MyHDL) and got several of the grad students very interested in
> using it :) I have a video of my presentation that I'll link soon

Yes, I'm seeing quite a lot of surfers who reach the MyHDL homepage
after searching for your project. After the EETimes article,
I also saw a surge in downloads, and by now it's still nearly
twice as much a before. However, it seems that this interest
has not yet triggered many others to "take the leap" like
yourself, because - somewhat suprizingly - I get less feedback
than before. Or perhaps it means that everything simply
works as desired :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: 0.5.1 released

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Thanks for your efforts, Jan.
> 
> I'll try it out as soon as I get back into PhoenixSID (I'm taking a break
> from it at the moment). 

I needed to do this release because the latest CookBook example
failed with 0.5 - some bugs in handling the Verilog signed type
with shift operations.

It's probably not urgent for you, otherwise you would have
complained earlier :-)

 > I did do a successful live demo of my synth
> (powered by MyHDL) and got several of the grad students very interested in
> using it :) I have a video of my presentation that I'll link soon

Yes, I'm seeing quite a lot of surfers who reach the MyHDL homepage
after searching for your project. After the EETimes article,
I also saw a surge in downloads, and by now it's still nearly
twice as much a before. However, it seems that this interest
has not yet triggered many others to "take the leap" like
yourself, because - somewhat suprizingly - I get less feedback
than before. Or perhaps it means that everything simply
works as desired :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] 0.5.1 released

[George P. <ge...@ga...>]

Thanks for your efforts, Jan.

I'll try it out as soon as I get back into PhoenixSID (I'm taking a break
from it at the moment). I did do a successful live demo of my synth
(powered by MyHDL) and got several of the grad students very interested i=
n
using it :) I have a video of my presentation that I'll link soon

Regards,
George



> I have released 0.5.1 - a maintenance release for 0.5.
>
> See the bug tracker for fixed issues.
>
> Regards,
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>      From Python to silicon:
>      http://myhdl.jandecaluwe.com
>
>
>
> -------------------------------------------------------
> Using Tomcat but need to do more? Need to support web services, securit=
y?
> Get stuff done quickly with pre-integrated technology to make your job
> easier
> Download IBM WebSphere Application Server v.1.0.1 based on Apache Geron=
imo
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=3D121642
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>


--=20
George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] 0.5.1 released

[Jan D. <ja...@ja...>]

I have released 0.5.1 - a maintenance release for 0.5.

See the bug tracker for fixed issues.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] 0.5.1dev1

[Jan D. <ja...@ja...>]

Hi all:

I have put development release 0.5.1dev1 under

   http://myhdl.jandecaluwe.com/doku.php/snapshots

This snapshots tackles the open issues and bugs
as documented here:

   http://sourceforge.net/tracker/?group_id=91207&atid=596332
   http://myhdl.jandecaluwe.com/doku.php/todo

This snapshot is required to run the latest CookBook
examples. All cookbook code is also included. Some
minor improvements to the manual were made.

Feedback welcome.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] SineComputer cookbook page

[Jan D. <ja...@ja...>]

Hi all:

I have added a new page to the cookbook. I'm quite excited about
it because it demonstrates a number of features that make the
MyHDL design flow unique. See:

   http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp

I would be grateful for reviews and feedback (and improvements).

After MyHDL 0.5.1 is released, I would like to announce this
page in the relevant usenet newsgroups.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: Adoption / verilog parser/stub gen

[Jan D. <ja...@ja...>]

Ken Horn wrote:
> I've just read the stopwatch example, and it certainly seems like MyHDL
> can provide a productivity benefit for HDL development. I'd like to use
> it for a project or two I'm working on, however there is one main
> barrier to adoption for me.

Welcome!

> The projects are typically very modular, and even leaf nodes in the
> hierarchy need to call vendor modules (eg block rams, DSP slices). The
> current support for black box modules - as I understand it - means I
> need to create a stub python module for the verilog one, and then
> declare that certain signals are being driven by the block. This seems
> sane and reasonable. However, what would *really* drive adoption for me,
> would be to be able to point MyHDL at a directory of verilog modules and
> have it generate the stubs, including output drivers based on the output
> signals in the verilog code.

Let me see if I understand. A typical "stub" module would contain:
1) a string with a Verilog module instantiation assigned to __verilog__
2) the declarations of signals being driven
3) some MyHDL code for simulation purposes

I believe you are talking about automating 1) and 2) - I believe it's
clear that generating 3) from Verilog is unrealistic for the forseeable
future.

By making certain assumptions this could perhaps be done, but do you
really gain that much? After all, if you stay in Verilog, you have
to do 1) anyway somewhere, right? Moreover, I think that
(unfortunately) the biggest part of the work would be 3) - writing
an equivalent MyHDL model for simulation.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Adoption / verilog parser/stub gen

[Ken H. <gen...@gm...>]

I've just read the stopwatch example, and it certainly seems like MyHDL
can provide a productivity benefit for HDL development. I'd like to use
it for a project or two I'm working on, however there is one main
barrier to adoption for me.

The projects are typically very modular, and even leaf nodes in the
hierarchy need to call vendor modules (eg block rams, DSP slices). The
current support for black box modules - as I understand it - means I
need to create a stub python module for the verilog one, and then
declare that certain signals are being driven by the block. This seems
sane and reasonable. However, what would *really* drive adoption for me,
would be to be able to point MyHDL at a directory of verilog modules and
have it generate the stubs, including output drivers based on the output
signals in the verilog code.

Ultimately full round-trip in/out of MyHDL/verilog would be ideal, but
stub generation would probably tip the balance for me. I'm currently 
working on an antlr based tool, which will do this, but thought I'd 
float the idea to see if it already exists.

Ken.

[myhdl-list] stopwatch

[Jan D. <ja...@ja...>]

Hi all:

I have added a page about a stopwatch design to the cookbook:

    http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch

Basically, this is the design from the Xilinx ISE tutorial,
redone in the "MyHDL way". Synthesis/Map results are included
to show that this is all real.

It also introduces and demonstrates the use of the py.test
unit testing framework, a compelling alternative to unittest.

I would like to announce this page in comp.arch.fpga, but
I welcome your feedback (and improvements) first. I'll
give it a week or so before announcing it there.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: Breaking a writer's block

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> 
> Wow, I think this will be very useful to me. Especially the py.test 
> part. I've been invited to present my music synthesizer project to a 
> graduate class in a few weeks, and I really would like to showcase the 
> agile development angle of things. So having this cookbook soon will 
> definitely help :)

Thanks George, it's going better :-) (py.test still needs more
explanation though.)
I notice that MyHDL is now getting attention from people looking at your
project. Very good.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com