myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] MyHDL 0.5 promotion

[George P. <ge...@ga...>]

> which MyHDL is
> used, and if you're not there yet, please consider adding
> it to the Users & Projects page (or even create a
> separate page). Of course, you can also simply mail the
> info to me and I'll add it, no problem.

Speaking of wiki's I think MoinMoin is a much better (looking and 
functioning) wiki than docuwiki. Just a thought, since you've been 
putting more work into promotion :) It's also easy to install

George

Re: [myhdl-list] MyHDL 0.5 promotion

[George P. <ge...@ga...>]

> MyHDL 0.5 will be released shortly.
>
> I would like to take some actions to promote it to potential
> new users. I'm convinced the best promotion is examples
> of real users doing real projects.
>
> Therefore, if you're doing a project in which MyHDL is
> used, and if you're not there yet, please consider adding
> it to the Users & Projects page (or even create a
> separate page). Of course, you can also simply mail the
> info to me and I'll add it, no problem.
>
> Thanks!
>
Nice! How would I go uploading pictures to the wiki? Does it do 
thumbnail previews?

George

[myhdl-list] MyHDL 0.5 promotion

[Jan D. <ja...@ja...>]

Hi all:

MyHDL 0.5 will be released shortly.

I would like to take some actions to promote it to potential
new users. I'm convinced the best promotion is examples
of real users doing real projects.

Therefore, if you're doing a project in which MyHDL is
used, and if you're not there yet, please consider adding
it to the Users & Projects page (or even create a
separate page). Of course, you can also simply mail the
info to me and I'll add it, no problem.

Thanks!

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] 0.5c1

[Jan D. <ja...@ja...>]

Release candidate 0.5c1 is available from the snapshot area.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: state enum trouble

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

>>
> Thanks, you're the best :-) Could I get the changed file(s)?

A few files were changed. I suggest to try release candidate
0.5c1, available from the snapshot area :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] state enum trouble

[George P. <ge...@ga...>]

>>
>>   When I used the state enum in the code below, the Verilog output 
>> caused an XST Error (pasted below too). It seems that the case 
>> statement refers to the nonexistent name (in the verilog code) 
>> 'state', when it should have been the 'fully qualified' name 
>> '_synthInst_SID_INST_envGen0_state'. When I fixed the Verilog code by 
>> hand, it compiled, synthesized and worked correctly. I saw this in 
>> both myhdl 0.5a1 and 0.5b1.
>>
>> Hope this helps squish a bug before the big 0.5 release :)
>
>
> Of course, a customer with a problem always gets priority :-)
>
> I have solved the bug in the code. Thanks for the report.
>
Thanks, you're the best :-) Could I get the changed file(s)?

Happy Christmahanuquanzica :)

George

Re: [myhdl-list] state enum trouble

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>   When I used the state enum in the code below, the Verilog output 
> caused an XST Error (pasted below too). It seems that the case statement 
> refers to the nonexistent name (in the verilog code) 'state', when it 
> should have been the 'fully qualified' name 
> '_synthInst_SID_INST_envGen0_state'. When I fixed the Verilog code by 
> hand, it compiled, synthesized and worked correctly. I saw this in both 
> myhdl 0.5a1 and 0.5b1.
> 
> Hope this helps squish a bug before the big 0.5 release :)

Of course, a customer with a problem always gets priority :-)

I have solved the bug in the code. Thanks for the report.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] state enum trouble

[George P. <ge...@ga...>]

Hi Jan,

   When I used the state enum in the code below, the Verilog output 
caused an XST Error (pasted below too). It seems that the case statement 
refers to the nonexistent name (in the verilog code) 'state', when it 
should have been the 'fully qualified' name 
'_synthInst_SID_INST_envGen0_state'. When I fixed the Verilog code by 
hand, it compiled, synthesized and worked correctly. I saw this in both 
myhdl 0.5a1 and 0.5b1.

Hope this helps squish a bug before the big 0.5 release :)

Thanks,
George


// Excerpt of myHDL code //

def EnvelopeGen(clk, gate, attack_rate, decay_rate, sustain_level, 
release_rate, reset_n, env_out, accum_width=24):
   
    accum = Signal(intbv(0)[accum_width:])
   
    t_State = enum('Idle', 'Attack', 'Decay', 'Sustain', 'Release')
    state = Signal(t_State.Idle)
   
    @always(clk.posedge)
    def EnvGenProcess():
       
        env_out.next = accum[accum_width:accum_width-len(env_out)]
       
        if state == t_State.Idle:
            accum.next = 0
            if gate:
                state.next = t_State.Attack

        elif state == t_State.Attack:
            accum.next = (accum + 8) % 2**accum_width
            if gate == False:
                state.next = t_State.Idle
               
        else:
            state.next = t_State.Idle

   
    return instances()


===== Excerpt of resulting Verilog code ==========

// ...

reg [2:0] _synthInst_SID_INST_envGen0_state;

// ...
// ... Much more stuff in between
// ...

always @(posedge clk) begin: _top_synthInst_SID_INST_envGen0_EnvGenProcess
    _synthInst_SID_INST_env0_out <= 
_synthInst_SID_INST_envGen0_accum[24-1:(24 - 12)];
    // synthesis parallel_case full_case
    casez (state)
        3'b000: begin
            _synthInst_SID_INST_envGen0_accum <= 0;
            if (_synthInst_SID_INST_wave0_gate) begin
                _synthInst_SID_INST_envGen0_state <= 3'b001;
            end
        end
        3'b001: begin
            _synthInst_SID_INST_envGen0_accum <= 
((_synthInst_SID_INST_envGen0_accum + 8) % (2 ** 24));
            if ((_synthInst_SID_INST_wave0_gate == 0)) begin
                _synthInst_SID_INST_envGen0_state <= 3'b000;
            end
        end
        default: begin
            _synthInst_SID_INST_envGen0_state <= 3'b000;
        end
    endcase
end


=== Xilinx XST Error =======

Started process "Synthesize".

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../../phoenixSID.v"
ERROR:HDLCompilers:28 - "../../phoenixSID.v" line 114 'state' has not 
been declared
Module <phoenixSID> compiled
Analysis of file <"phoenixSID.prj"> failed.
-->

Total memory usage is 88628 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.

[myhdl-list] Re: overview on wiki updated, feedback welcome

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi Jan,
> 
>    I thought the overview was a bit too much all at once, like drinking
> from a fire hose for a newbie :). However, I also thought it was
> well-composed and showed a strong grasp of the English language.
> 
> A native speaker, I re-organized the content to make it catchier and
> easier to read. I also added a catchy one-sentence description up top.
> 
> http://myhdl.jandecaluwe.com/doku.php/newoverview
> 
> Thanks for your hard work. Feedback welcome!

Definitely much better, thanks. I'll be making further
improvements :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: 0.5 release schedule

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>I don't plan to make further changes to the 0.5b1 code
>>(except for the name attribute issues - done already).
>>Unless someone of you complains on something in the meantime, I
>>therefore plan to skip a release candidate, and release
>>0.5 final on december 27.
>>
> 
> Hey Jan, I'm defintiely glad to see 0.5 is coming right along. I don't
> know about the other guys, but I haven't tried 0.5b1 yet, and with the
> holidays fast approaching, I likely wont until next week. So 0.5b1 won't
> be tested as thoroughly as you want.

> I don't know if that makes a big difference because I don't know what
> changed between a1 and b1.

Some changes to hierarchy extraction and hierarchical naming (again).
There were no "hard" errors, the fix was only to make things more
consistent in corner cases. All existing test continued to run
unmodified. The resulting code is simpler (again) so I'm optimistic
that all is well. But you never know.

It would be good if someone could just run his existing simulation/
waveform trace/conversion. I only need to know that 0.5b1
version is not worse than the 0.5a1 :-)

Of course it's a holiday season, so I can wait until 29 december
for a release, but I want to get it out still this year.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] overview on wiki updated, feedback welcome

[George P. <ge...@ga...>]

Hi Jan,

   I thought the overview was a bit too much all at once, like drinking
from a fire hose for a newbie :). However, I also thought it was
well-composed and showed a strong grasp of the English language.

A native speaker, I re-organized the content to make it catchier and
easier to read. I also added a catchy one-sentence description up top.

http://myhdl.jandecaluwe.com/doku.php/newoverview

Thanks for your hard work. Feedback welcome!

George

[myhdl-list] updated overview on wiki

[George P. <ge...@ga...>]

Hi Jan,

I thought the original overview was a bit like drinking from a fire hose
(for a newbie), though I also thought it was well-composed and showed an
excellent grasp of the English language.

A native speaker, I re-organized it to break up the content, make it a bi=
t
catchier, and also added a concise and catchy one-sentence description up
top.

http://myhdl.jandecaluwe.com/doku.php/newoverview

Feedback welcome!

George

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] 0.5 release schedule

[George P. <ge...@ga...>]

> I don't plan to make further changes to the 0.5b1 code
> (except for the name attribute issues - done already).
> Unless someone of you complains on something in the meantime, I
> therefore plan to skip a release candidate, and release
> 0.5 final on december 27.
>

Hey Jan, I'm defintiely glad to see 0.5 is coming right along. I don't
know about the other guys, but I haven't tried 0.5b1 yet, and with the
holidays fast approaching, I likely wont until next week. So 0.5b1 won't
be tested as thoroughly as you want.

I don't know if that makes a big difference because I don't know what
changed between a1 and b1. Next week would be a good time for a release,
though, because people have time off work and that holiday stress would b=
e
over.

>  One thing I
> want is a more appealing version of the Overview - as it's
> the first thing new users will read.
>
> I have put a working version on the wiki here:
>
>      http://myhdl.jandecaluwe.com/doku.php/newoverview
>

I take this to mean we, the great unwashed, can now edit it :)

George Pantazopoulos
http://www.gammaburst.net

[myhdl-list] 0.5 release schedule

[Jan D. <ja...@ja...>]

Hi all:

I don't plan to make further changes to the 0.5b1 code
(except for the name attribute issues - done already).
Unless someone of you complains on something in the meantime, I
therefore plan to skip a release candidate, and release
0.5 final on december 27.

I will only try to improve the documentation. One thing I
want is a more appealing version of the Overview - as it's
the first thing new users will read.

I have put a working version on the wiki here:

     http://myhdl.jandecaluwe.com/doku.php/newoverview

You can compare it to the old version to see differences.

Feedback welcome.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: Issue with toVerilog.name and traceSignals.name

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>>1) only be used for the output filename ("my_name.v")
>>>2) also for the name of the actual toplevel Verilog module
>>>
>>>Prior to 0.5b1, option 2) was implemented. The problem is that
>>>you may set it to a name which is already used elsewhere in the code,
>>>creating a problem in the output. This is not checked by MyHDL.
>>>So for 0.5b1, I though I needed to fix that and changed
>>>it to option 1).
> 
> 
> I prefer option 2, for consistency.

Ok, option 2) it will be for 0.5 final.

 > Is there a fundamental reason that
> myHDL can't check for a name clash? :)

No, but thinking about it the problem is larger. It would
be fairly easy to use Verilog keywords in MyHDL code, and
create a problem in converted output. Currently, there
are no checks.

However, the symptoms would be clear (compilation error) and
the workaround trivial. So I will defer a solution (if
required) to later.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

Re: [myhdl-list] Issue with toVerilog.name and traceSignals.name

[George P. <ge...@ga...>]

>> 1) only be used for the output filename ("my_name.v")
>> 2) also for the name of the actual toplevel Verilog module
>>
>> Prior to 0.5b1, option 2) was implemented. The problem is that
>> you may set it to a name which is already used elsewhere in the code,
>> creating a problem in the output. This is not checked by MyHDL.
>> So for 0.5b1, I though I needed to fix that and changed
>> it to option 1).

I prefer option 2, for consistency. Is there a fundamental reason that
myHDL can't check for a name clash? :)

--=20
George Pantazopoulos
http://www.gammaburst.net

Re: [myhdl-list] Issue with toVerilog.name and traceSignals.name

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

>
> 1) only be used for the output filename ("my_name.v")
> 2) also for the name of the actual toplevel Verilog module
>
> Prior to 0.5b1, option 2) was implemented. The problem is that
> you may set it to a name which is already used elsewhere in the code,
> creating a problem in the output. This is not checked by MyHDL.
> So for 0.5b1, I though I needed to fix that and changed
> it to option 1).
>
> Now I'm confused and I think it's really 2) that designers
> want, despite the potential name clash.

I like option 2 better, but either way is OK. I think normally you 
expect the file name and module name to be the same.

Tom

[myhdl-list] Issue with toVerilog.name and traceSignals.name

[Jan D. <ja...@ja...>]

Hi:

In beta release 0.5b1, I may have introduced a problem while trying
to "fix" the behavior of toVerilog.name (and traceSignals.name).

With toVerilog.name, you can set a name other than the default
for the toplevel name. For example:

toVerilog.name = "my_name"

The question is: should that name be used

1) only be used for the output filename ("my_name.v")
2) also for the name of the actual toplevel Verilog module

Prior to 0.5b1, option 2) was implemented. The problem is that
you may set it to a name which is already used elsewhere in the code,
creating a problem in the output. This is not checked by MyHDL.
So for 0.5b1, I though I needed to fix that and changed
it to option 1).

Now I'm confused and I think it's really 2) that designers
want, despite the potential name clash.

Same issue for traceSignals.name, and the output VCD file.

Feedback welcome,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Re: 0.5b1 beta release

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
>>I have released beta release 0.5b1 (see development snapshots).
>>
> 
> 
> I'm looking forward to trying it out. Currently I'm having success with
> synthesizing my myHDL code to FPGA with 0.5a1.
> 
> What I'd really like to see is a changelog of important things changed
> between each development snapshot. I noticed that the development snapshot
> contains a CHANGES.txt, but the update history stops after 0.4.1. The
> whatsnew0.5 page on the wiki is detailed and valuable, but I miss seeing
> the chronological progression found in CHANGES.txt

Since 0.5a1 (the alpha release), we are in feature freeze and bugfix
mode - the intention is now just to make it work as advertised,
and to get the docs correct.

So there are no significant changes nor will there be until the
0.5 final release. For 0.5, the CHANGES.txt document will just
contain a link to whatsnew0.5 that documents the changes extensively.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] Updated my 65X81 synth project details in the wiki's Users & Projects

[George P. <ge...@ga...>]

Hi all,

I'm thrilled to report that I've been making great progress on my music 
synthesizer. I'd like to thank all of you who have been helping me, as 
well as Jan for making it possible!

I updated my 65X81 synth project details in the wiki's Users & Projects. 
Link: http://myhdl.jandecaluwe.com/doku.php/projects

Thanks!
George

Re: [myhdl-list] 0.5b1 beta release

[George P. <ge...@ga...>]

> I have released beta release 0.5b1 (see development snapshots).
>

I'm looking forward to trying it out. Currently I'm having success with
synthesizing my myHDL code to FPGA with 0.5a1.

What I'd really like to see is a changelog of important things changed
between each development snapshot. I noticed that the development snapsho=
t
contains a CHANGES.txt, but the update history stops after 0.4.1. The
whatsnew0.5 page on the wiki is detailed and valuable, but I miss seeing
the chronological progression found in CHANGES.txt

Thanks for the new release!
George

[myhdl-list] Re: myHDL docs wiki-ized

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:

> Actually, you don't even need me for that - you can create new
> wiki pages and you have the tex sources to start from if desirable.

I just realize that my statement above is not true - I don't include the
tex sources in a release. Sorry about that.

The reason is just that the whole setup is not that simple and
involves quite some directories and files - just overhead and
potential confusion for the regular user.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] 0.5b1 beta release

[Jan D. <ja...@ja...>]

Hi:

I have released beta release 0.5b1 (see development snapshots).

I have adapted the manual. I had hoped to have a release
candidate by now, but I found and fixed several issues while
updating the manual, so I do a beta release first. Thanks
for installing and trying the code if you have time.

The snapshot now contains the manual (html and pdf), but
no longer the whatsnew docs. As whatsnew0.5 now lives
on the wiki, I thought it would be confusing to include
old whatsnew docs in a release. I plan to do the same
for the final release.

I decided to simplify the first chapter and leave at that
for a "tutorial" document. Many changes were made to the
manual, and I still have to proofread it again. You can do so
also from the snapshot, or on-line (see link in the
development zone). All comments welcome.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com

[myhdl-list] any news with regards to tristate I/O?

[George P. <ge...@ga...>]

Hi all,

   I need to interface my FPGA with a device that has a tri-state data
bus. (a FT245BM USB<->FIFO adapter). Do I still need to make a wrapper
in Verilog, or is there a better approach now? Has anyone any
examples/tips to share?

Thanks,
George

Re: [myhdl-list] my myHDL Unit test framework so far. please critique

[<dan...@we...>]

George Pantazopoulos wrote:
> How do you automate it so the same file performs steps 1 and 2 in the
> same run? Currently I have a unit test file that takes command-line
> arguments. If I run "python module_ut.py -v" it does a myHDL-only
> unittest. If I add the -cosim option, as in "python module_ut.py -v
> -cosim" then it does a unit test w/cosimulation. So I need two seperate
> runs w/different arguments. I use a Makefile to have it automatically
> run steps 1 and 2 in sequence (as well as step #3). I'm interested in
> eliminating the need for a pesky Makefile :)

Let unittest do the job for you. What you can do is have different test
cases that perform what your makefile is doing.

A split might be here appropriate. So you have, I call it testbench
code, that performs the test with your logic. In the first step this is
the myhdl logic. This code will be the same whether you test myhdl for
now or the verilog generated code later.

Put this testbench code in a test case and run it.

If that works, add a second unittest test case. This one will generate
the verilog code and then run your testbench code again, this time with
cosimulation. Here comes the beauty of myhdl, as you have one testbench
that tests both myhdl and verilog code.

To run the test, you just call your unittest file. If the project
becomes more complex you can group them. At the end you only have one
file that you call which will run all the tests.

Have a look at the examples that come along with myhdl. I believe you
just ran some to test you cosimulation. They show this grouping of test
cases very nice. You can call them individual or all together, just
depends on which file you start.

Guenter