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Re: [myhdl-list] rhea & cores

[Edward V. <dev...@sb...>]

Chris ,The example you  provided should also work with a XulA2-LX9 is that correct?I have downloaded IceCube2 but have not installed it?  Which version of IceCube2 have you tested Linux or window?I normally work on a Ubuntu 12.04 this is where I have the Xilinx 14.6.Which board has the highest priority? 
I also have been looking at the Parallella & zybo.Are these 2 boards easier to work with than the Zedboard.  I have an Yocto O/S working but nothing in the FPGA side.Are you working on theses board using the Zynq 7000?

Regards,
Thanks 
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Tuesday, December 29, 2015 3:31 PM, Christopher Felton <chr...@gm...> wrote:
 

 On 12/29/15 3:28 PM, Edward Vidal wrote:
> Hi Chris,
> Thanks for all the help it is appreciated.
>
> Which of the cores in the rhea package are ready to add to a design?

Sorry to disappoint, this is all beta and
probably will be for awhile but with that
said many of the cores are usable.  To
determine if they are can be some work
until documentation etc. is complete ...

>
> I am looking at using  the CAT-Board or XulA2-LX9 & StickIt-MB with a RPiB.
>
> In rhea/rhea/cores/uart/ there 2 cores uart.py & uartlite.py.
> Do you add both?
> python test_uart.py --convert --test uart is this not functional yet?  I
> did not see

No, one of the places to look is the __init__.py
in each of the core directories.  It will give you
indicate which are the top-levels and then you
import

    from rhea.cores.uart import uartlite

See the following example:
https://github.com/cfelton/rhea/blob/master/examples/boards/icestick/icestick_blinky_host.py

In general, it is best to look at the examples
versus the tests.  The above example I have
tested on the IceStick.  But note, the above
example did not work with Yosys+APaR when I
tried it but it does work with IceCube2.

Hope that helps,
Chris



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Re: [myhdl-list] rhea & cores

[Christopher F. <chr...@gm...>]

On 12/29/15 3:28 PM, Edward Vidal wrote:
> Hi Chris,
> Thanks for all the help it is appreciated.
>
> Which of the cores in the rhea package are ready to add to a design?

Sorry to disappoint, this is all beta and
probably will be for awhile but with that
said many of the cores are usable.  To
determine if they are can be some work
until documentation etc. is complete ...

>
> I am looking at using  the CAT-Board or XulA2-LX9 & StickIt-MB with a RPiB.
>
> In rhea/rhea/cores/uart/ there 2 cores uart.py & uartlite.py.
> Do you add both?
> python test_uart.py --convert --test uart is this not functional yet?  I
> did not see

No, one of the places to look is the __init__.py
in each of the core directories.  It will give you
indicate which are the top-levels and then you
import

     from rhea.cores.uart import uartlite

See the following example:
https://github.com/cfelton/rhea/blob/master/examples/boards/icestick/icestick_blinky_host.py

In general, it is best to look at the examples
versus the tests.  The above example I have
tested on the IceStick.  But note, the above
example did not work with Yosys+APaR when I
tried it but it does work with IceCube2.

Hope that helps,
Chris

[myhdl-list] rhea & cores

[Edward V. <dev...@sb...>]

Hi Chris,Thanks for all the help it is appreciated.
Which of the cores in the rhea package are ready to add to a design?
I am looking at using  the CAT-Board or XulA2-LX9 & StickIt-MB with a RPiB.
In rhea/rhea/cores/uart/ there 2 cores uart.py & uartlite.py.Do you add both?python test_uart.py --convert --test uart is this not functional yet?  I did not see
In rhea/rhea/models/uart/_uart_model.py  this is not added to the design is that 
correct?This works python test_uart.py --trace --test uartls output/vcd
_bench_uart.vcd 
This works okay gtkwave  output/vcd/_bench_uart.vcd.
Adding a method to pass data from the host to the fpga has been my greatest issue.I was hoping to use several GPIO to speed up the transfer of an image to the FPGA.Transferring an image over the USB takes a considerable amount of time.
This is from the e-mail that I sent you on 12/3/15.
Also in test_jpeg 

The option is python  test_jpegenc.py --vtracegtkwave vcd/_tb_jpegenc.vcd 

GTKWave Analyzer v3.3.34 (w)1999-2012 BSI

No symbols in VCD file..is it malformed?  Exiting!
Regards,

Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] adding files to top-level with rhea

[Christopher F. <chr...@gm...>]

Edward,

The the Xula2 already exists, you can use the
Xula2.

    from rhea.build.boards.xilinx import Xula2

https://github.com/cfelton/rhea/blob/master/rhea/build/boards/xilinx/__init__.py#L4

Regards,
Chris

On Wed, Dec 23, 2015 at 3:00 PM, Edward Vidal <dev...@sb...>
wrote:

> Chris,
> I see what you did with  my_board_def.py.  The problem I am having is in
> the file
> rhea/rhea/build/boards/xilinx/_xula.py device = 'XC6SLX25'.  I need to
> override to device = 'XC6SLX9'.
> There are 2 versions xula2.
>
> I tried make test instead of make.
> Thanks,
>
>
>
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> On Wednesday, December 23, 2015 9:16 AM, Christopher Felton <
> chr...@gm...> wrote:
>
>
> On 12/21/15 10:05 AM, Edward Vidal wrote:
> > Hello All,
> >
> > Yosys & arachne-pnr appear to work very well compared to Xilinx ISE.
> > It takes 2:41 to generate xula2.bit, while it only takes 0:35 to
> > generate the catboard.bin.
> >
>
> Not to diminish the efforts of the open-source
> synthesis and PaR but run-time is a small
> benefit when compared to the resource and
> timing results.  In other-words, if the flow
> executes quickly but uses twice as many
> resources it isn't a good comparison.
>
> > On the RPi2B with CAT-Board the first 2 leds appeared to always be on.
> > See the changes to blink.py in the file attached chgs_blink.txt.
> > I choose 12000000 since the freq. on my XulA2-LX9 is 12000000 Hz.
> > Using 1440000 on the XulA2-LX9 would be 8.333333 times.
> > Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
> > the same rate as leds on CAT-Board with RPi2B.
> >
>
> I haven't looked at your code, one thing you
> might want to do is verify your design works
> with the IceCub2 as well as Yosys+Ar, in
> my testing I have had icestick designs work
> with IceCube and not with Yosys.  I plan on
> adding the IceCub2 flow to the rhea.build but
> it is farther down on my list of things to do.
>
> > I generated the docs in both html & latexpdf formats.
> >
> > Running make in rhea/test appears to work okay.
> > The test_models/test_fx2_model.py just hangs up. Should the be expected
> > at this point?
>
> Yes, there seems to be an issue with py.test
> that I haven't figured out yet.  If you run
> `make test` it will run all the same tests
> but not using py.test.
>
> >
> > In the file ex_xula2.py I added the flow.add_files line.
> >      flow.add_files('jpeg_cat.v')
> >      flow.run()
> > Running ISE I see the file jpeg_cat.v is now part of the project.
> > What do I need to do, to have jpeg_cat.v instantiated in the xula2.v?
> > Or do I have to do this manually?
>
> You have to do this manually, there is an
> undocumented (beta) feature that might help
> (`verilog_instance`) otherwise the documented
> approach is to us `verilog_code` and create a
> wrapper for the module you want instantiate.
>
>
> >
> > Does anyone have a MyHDL or Verilog for a DCM?
> > I have been using the one in Xess VHDL_Lib
> >
>
> I have been slowly adding some vendor agnostic
> primitives to rhea, one of these is a clock
> manager (PLL/DCM/MMCM):
>
> https://github.com/cfelton/rhea/blob/master/examples/boards/de0nano_soc/device_primitives/de0nano_soc_device_prims.py#L20
>
> But I have only limited testing, you might
> not want to use it unless you are willing to
> debug and make changes.
>
> Regards,
> Chris
>
>
>
>
>
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>
>
>
>
> ------------------------------------------------------------------------------
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>

Re: [myhdl-list] adding files to top-level with rhea

[Edward V. <dev...@sb...>]

 make test
rm -Rf output/
mkdir output/
/usr/bin/time python ./test_cores/test_converters/test_adc128s022.py > output/run_all_tests.log
0.20user 0.01system 0:00.22elapsed 99%CPU (0avgtext+0avgdata 44912maxresident)k
0inputs+8outputs (0major+3121minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_eth/test_gemac_lite.py >> output/run_all_tests.log
0.01user 0.00system 0:00.01elapsed 94%CPU (0avgtext+0avgdata 21344maxresident)k
0inputs+0outputs (0major+1460minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_afifo.py >> output/run_all_tests.log
2.24user 0.01system 0:02.26elapsed 99%CPU (0avgtext+0avgdata 43648maxresident)k
0inputs+0outputs (0major+3032minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_ffifo.py >> output/run_all_tests.log
0.13user 0.01system 0:00.14elapsed 99%CPU (0avgtext+0avgdata 42816maxresident)k
0inputs+0outputs (0major+2978minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_fifo_ramp.py >> output/run_all_tests.log
20.45user 0.01system 0:20.48elapsed 99%CPU (0avgtext+0avgdata 44048maxresident)k
0inputs+416outputs (0major+3055minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_fifo/test_sfifo.py >> output/run_all_tests.log
5.69user 0.01system 0:05.71elapsed 99%CPU (0avgtext+0avgdata 46288maxresident)k
0inputs+0outputs (0major+3195minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_sdram/test_sdram.py >> output/run_all_tests.log
0.26user 0.02system 0:00.29elapsed 99%CPU (0avgtext+0avgdata 58672maxresident)k
0inputs+0outputs (0major+4254minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_serio.py >> output/run_all_tests.log
0.21user 0.01system 0:00.23elapsed 100%CPU (0avgtext+0avgdata 41552maxresident)k
0inputs+0outputs (0major+2896minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_spi.py >> output/run_all_tests.log
0.22user 0.02system 0:00.25elapsed 99%CPU (0avgtext+0avgdata 73008maxresident)k
0inputs+8outputs (0major+5161minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_ticks.py >> output/run_all_tests.log
1.56user 0.01system 0:01.58elapsed 99%CPU (0avgtext+0avgdata 41856maxresident)k
0inputs+0outputs (0major+2924minor)pagefaults 0swaps
/usr/bin/time python ./test_cores/test_video/test_create_image.py >> output/run_all_tests.log
Traceback (most recent call last):
  File "./test_cores/test_video/test_create_image.py", line 27, in <module>
    test_create_save()
  File "./test_cores/test_video/test_create_image.py", line 23, in test_create_save
    disp.set_pixel(col, row, rgb, last)
  File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 105, in set_pixel
    self.create_save_image()
  File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 139, in create_save_image
    print("     width ........... {}".format(im.width))
  File "/usr/lib/python2.7/dist-packages/PIL/Image.py", line 515, in __getattr__
    raise AttributeError(name)
AttributeError: width
Error in sys.excepthook:
Traceback (most recent call last):
  File "/usr/lib/python2.7/dist-packages/apport_python_hook.py", line 66, in apport_excepthook
    from apport.fileutils import likely_packaged, get_recent_crashes
  File "/usr/lib/python2.7/dist-packages/apport/__init__.py", line 1, in <module>
    from apport.report import Report
  File "/usr/lib/python2.7/dist-packages/apport/report.py", line 20, in <module>
    import apport.fileutils
  File "/usr/lib/python2.7/dist-packages/apport/fileutils.py", line 22, in <module>
    from apport.packaging_impl import impl as packaging
  File "/usr/lib/python2.7/dist-packages/apport/packaging_impl.py", line 20, in <module>
    import apt
  File "/usr/lib/python2.7/dist-packages/apt/__init__.py", line 21, in <module>
    import apt_pkg
ImportError: /opt/Xilinx/14.6/ISE_DS/ISE/lib/lin64/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/python2.7/dist-packages/apt_pkg.so)

Original exception was:
Traceback (most recent call last):
  File "./test_cores/test_video/test_create_image.py", line 27, in <module>
    test_create_save()
  File "./test_cores/test_video/test_create_image.py", line 23, in test_create_save
    disp.set_pixel(col, row, rgb, last)
  File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 105, in set_pixel
    self.create_save_image()
  File "/home/vidal/wkg/rhea/rhea/models/video/_video_display.py", line 139, in create_save_image
    print("     width ........... {}".format(im.width))
  File "/usr/lib/python2.7/dist-packages/PIL/Image.py", line 515, in __getattr__
    raise AttributeError(name)
AttributeError: width
Command exited with non-zero status 1
2.20user 0.04system 0:02.24elapsed 99%CPU (0avgtext+0avgdata 218304maxresident)k
0inputs+0outputs (0major+15170minor)pagefaults 0swaps
make: *** [test] Error 1

Re: [myhdl-list] adding files to top-level with rhea

[Christopher F. <chr...@gm...>]

On 12/21/15 10:05 AM, Edward Vidal wrote:
> Hello All,
>
> Yosys & arachne-pnr appear to work very well compared to Xilinx ISE.
> It takes 2:41 to generate xula2.bit, while it only takes 0:35 to
> generate the catboard.bin.
>

Not to diminish the efforts of the open-source
synthesis and PaR but run-time is a small
benefit when compared to the resource and
timing results.  In other-words, if the flow
executes quickly but uses twice as many
resources it isn't a good comparison.

> On the RPi2B with CAT-Board the first 2 leds appeared to always be on.
> See the changes to blink.py in the file attached chgs_blink.txt.
> I choose 12000000 since the freq. on my XulA2-LX9 is 12000000 Hz.
> Using 1440000 on the XulA2-LX9 would be 8.333333 times.
> Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
> the same rate as leds on CAT-Board with RPi2B.
>

I haven't looked at your code, one thing you
might want to do is verify your design works
with the IceCub2 as well as Yosys+Ar, in
my testing I have had icestick designs work
with IceCube and not with Yosys.  I plan on
adding the IceCub2 flow to the rhea.build but
it is farther down on my list of things to do.

> I generated the docs in both html & latexpdf formats.
>
> Running make in rhea/test appears to work okay.
> The test_models/test_fx2_model.py just hangs up. Should the be expected
> at this point?

Yes, there seems to be an issue with py.test
that I haven't figured out yet.  If you run
`make test` it will run all the same tests
but not using py.test.

>
> In the file ex_xula2.py I added the flow.add_files line.
>      flow.add_files('jpeg_cat.v')
>      flow.run()
> Running ISE I see the file jpeg_cat.v is now part of the project.
> What do I need to do, to have jpeg_cat.v instantiated in the xula2.v?
> Or do I have to do this manually?

You have to do this manually, there is an
undocumented (beta) feature that might help
(`verilog_instance`) otherwise the documented
approach is to us `verilog_code` and create a
wrapper for the module you want instantiate.


>
> Does anyone have a MyHDL or Verilog for a DCM?
> I have been using the one in Xess VHDL_Lib
>

I have been slowly adding some vendor agnostic
primitives to rhea, one of these is a clock
manager (PLL/DCM/MMCM):
https://github.com/cfelton/rhea/blob/master/examples/boards/de0nano_soc/device_primitives/de0nano_soc_device_prims.py#L20

But I have only limited testing, you might
not want to use it unless you are willing to
debug and make changes.

Regards,
Chris

Re: [myhdl-list] rhea AssertionError

[Christopher F. <chr...@gm...>]

On 12/17/2015 9:12 PM, Edward Vidal wrote:
> Hi Chris,Is blinky consided a top level? I have a XulA2-LX9, do I
> just modify the   line 39 in _xula.py   device = 'XC6SLX9' -->
> device = 'XC6SLX9'?Or should we define a new class?

No, ideally you do not modify _xula.py file.  The
Xula2 itself does not have any LEDs, so the board
definition only includes the generic channel (IO)
ports.

I added some documentation and an example that shows
how to create a custom board definition:
docs: http://rhearay.readthedocs.org/en/latest/build/board_definition.html
example: 
https://github.com/cfelton/rhea/tree/master/examples/boards/xula/custom

> I  tested on
> ubuntu 12.04 with Xilinx 14.6.  All appears to work okay.  Only one
> led was tested. Should  blinky where I start with the CAT-Board
> also?Should the ice40_primitives.py be included as part of
> rhea?Regards,

I haven't looked at your ice40_primitives yet, yes
a version of it can be included in rhea.  I have
been trying to create vendor neutral primitives,
I will look over (at some point) you ice40_primitives
and see if I can use it in that approach.

Regards,
Chris

[myhdl-list] adding files to top-level with rhea

[Edward V. <dev...@sb...>]

Modifications to blink.py on RPi2B used to create catboard.bin.
--- blink.py	2015-12-14 11:03:16.519999868 +0000
+++ blink.py.tmp	2015-12-14 11:02:09.009999894 +0000
@@ -9,12 +9,12 @@
 
     nled = len(led)
     maxcnt = int(clock.frequency)
-    cnt = Signal(intbv(0,min=0,max=maxcnt))
+    cnt = Signal(intbv(0,min=0,max=12000000))
     toggle = Signal(bool(0))
 
     @always_seq(clock.posedge, reset=reset)
     def rtl():
-        if cnt == maxcnt-1:
+        if cnt == 12000000:
             cnt.next = 0
             toggle.next = not toggle
         else:
Modifications to blink.py on Ubuntu used to create xula2.bit.

--- blink.py	2015-12-21 05:47:24.931919453 -0700
+++ blink.py.tmp	2015-12-21 05:47:09.387919627 -0700
@@ -9,12 +9,12 @@
 
     nled = len(led)
     maxcnt = int(clock.frequency)
-    cnt = Signal(intbv(0,min=0,max=maxcnt))
+    cnt = Signal(intbv(0,min=0,max=1440000))
     toggle = Signal(bool(0))
 
     @always_seq(clock.posedge, reset=reset)
     def rtl():
-        if cnt == maxcnt-1:
+        if cnt == 1440000:
             cnt.next = 0
             toggle.next = not toggle
         else:


Now, 2 leds on XulA2-LX9 with StickIt-MB and RPi2B appear to blink at
the same rate as leds on CAT-Board with RPi2B.   

Re: [myhdl-list] rhea AssertionError

[Edward V. <dev...@sb...>]

Hi Chris,Is blinky consided a top level?
I have a XulA2-LX9, do I just modify the   line 39 in _xula.py   device = 'XC6SLX9' -->    device = 'XC6SLX9'?Or should we define a new class?
I  tested on ubuntu 12.04 with Xilinx 14.6.  All appears to work okay.  Only one led was tested.
Should  blinky where I start with the CAT-Board also?Should the ice40_primitives.py be included as part of rhea?Regards,
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Thursday, December 17, 2015 9:52 AM, Christopher Felton <chr...@gm...> wrote:
 

 On 12/17/2015 10:15 AM, Edward Vidal wrote:
> Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board
>
> My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
> python buttons_display.py creates buttons_display.v with my signals and
> module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA
> pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.
>
> How do you add a port to a signal not connected to a pin?
>

You can't at least not with the current implementation.
The FPGA toolflow automation assumes you are building
for a particular development board, all top-level ports
need to be assigned to a pin.

It doesn't preclude you from creating a design with any
combination for ports just from automatically mapping a
top-level module to an FPGA board.

The main goal of the tool automation is to take a top-level
MyHDL design and automatically map it to a development
board.  If the port names don't match the pin names in
the dev board definition (typically the names from the
documentation) then there is some work to manually map
the ports to pins.

Now, if you don't really want to target a dev board but
want to see if a module will synthesize - this is currently
not support but it is something I can possibly add with
little effort.

Hope that helps,
Chris




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Re: [myhdl-list] rhea AssertionError

[Christopher F. <chr...@gm...>]

On 12/17/2015 10:15 AM, Edward Vidal wrote:
> Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board
>
> My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
> python buttons_display.py creates buttons_display.v with my signals and
> module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA
> pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.
>
> How do you add a port to a signal not connected to a pin?
>

You can't at least not with the current implementation.
The FPGA toolflow automation assumes you are building
for a particular development board, all top-level ports
need to be assigned to a pin.

It doesn't preclude you from creating a design with any
combination for ports just from automatically mapping a
top-level module to an FPGA board.

The main goal of the tool automation is to take a top-level
MyHDL design and automatically map it to a development
board.  If the port names don't match the pin names in
the dev board definition (typically the names from the
documentation) then there is some work to manually map
the ports to pins.

Now, if you don't really want to target a dev board but
want to see if a module will synthesize - this is currently
not support but it is something I can possibly add with
little effort.

Hope that helps,
Chris

[myhdl-list] rhea AssertionError

[Edward V. <dev...@sb...>]

Hello All,I am using the examples from https://github.com/xesscorp/CAT-Board

My code is at https://github.com/develone/jpeg-2000-test/tree/master/jpeg_cat
python buttons_display.py creates buttons_display.v with my signals and
module BUTTONS_DISPLAY_JPEG_RTL.  These signals are not connected to any FPGA 
pins. Several signals use brd.add_port('d0_o', 'A11') in the file ex_catboard_buttons.py.

How do you add a port to a signal not connected to a pin?

I have tried brd.add_port('left_i', 'NONE') for my signals.

python ex_catboard_buttons.py 
Traceback (most recent call last):
  File "ex_catboard_buttons.py", line 53, in <module>
    run_catboard()
  File "ex_catboard_buttons.py", line 49, in run_catboard
    flow.run()
  File "build/bdist.linux-armv7l/egg/rhea/build/toolflow/_iceriver.py", line 84, in run
  File "build/bdist.linux-armv7l/egg/rhea/build/toolflow/_convert.py", line 30, in convert
  File "build/bdist.linux-armv7l/egg/rhea/build/_fpga.py", line 239, in get_portmap
AssertionError: Error unspecified port left_i


Thanks, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] rhea questions

[Christopher F. <chr...@gm...>]

On 12/16/2015 9:03 AM, Edward Vidal wrote:
> Hello all,Should I send rhea questions to this mailing list?Cheers,
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>

Obviously my answer is biased :)  Given that the
mailing-list traffic is low and that the questions
might be applicable to various MyHDL based projects
others are developing, I think it is reasonable to
post rhea questions here.

Regards,
Chris

[myhdl-list] rhea questions

[Edward V. <dev...@sb...>]

Hello all,Should I send rhea questions to this mailing list?Cheers, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] test SDRAM_Controller

[Edward V. <dev...@sb...>]

Chris
Xstools, opencv all work okay on yocto Pi2B.

Yocto Pi2B fails

root@raspberrypi2:~/SDRAM_Controller# python
Python 2.7.9 (default, Sep 12 2015, 14:03:04) 
[GCC 4.9.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.

RaspBian Pi2B okay 
vidal@raspberrypi /usr/lib/python2.7 $ python 
Python 2.7.9 (default, Mar  8 2015, 00:52:26) 
[GCC 4.9.2] on linux2
Type "help", "copyright", "credits" or "license" for more information.

Ubuntu x86_64 okay
Python 2.7.3 (default, Sep 26 2013, 20:03:06) 
[GCC 4.6.3] on linux2
Type "help", "copyright", "credits" or "license" for more information
I tried 2to3 -l -w -v sdram.py2to3 -l -w -v test_controller.py2to3 -l -w -v test_sdram.pypython3 test_sdram.py
root@raspberrypi2:~/SDRAM_Controller# python3 test_controller.py
Traceback (most recent call last):
  File "test_controller.py", line 2, in <module>
    from SdramCntl import *
  File "/home/root/SDRAM_Controller/SdramCntl.py", line 3, in <module>
    from sd_intf import *
  File "/home/root/SDRAM_Controller/sd_intf.py", line 83
    addr = 0
           ^
TabError: inconsistent use of tabs and spaces in indentationfix the above error which has several lines with an extra space.Finally get back to same error 
python3 test_controller.py
Traceback (most recent call last):
  File "test_controller.py", line 30, in <module>
    sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
  File "/home/root/SDRAM_Controller_old/sdram.py", line 51, in sdram
    @always(clk.posedge)
  File "/usr/local/lib/python3.4/site-packages/myhdl-1.0.dev0-py3.4.egg/myhdl/_always.py", line 59, in _always_decorator
    return _Always(func, args)
  File "/usr/local/lib/python3.4/site-packages/myhdl-1.0.dev0-py3.4.egg/myhdl/_always.py", line 78, in __init__
    symdict.update(zip(freevars, closure))
  File "/usr/local/lib/python3.4/site-packages/myhdl-1.0.dev0-py3.4.egg/myhdl/_always.py", line 77, in <genexpr>
    closure = (c.cell_contents for c in func.__closure__)
ValueError: Cell is empty
 Regards
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 


     On Wednesday, October 14, 2015 6:43 PM, Christopher Felton <chr...@gm...> wrote:
   

 Edward,

Do you have the full Python version for both systems?
The RPi is 2.7.? and the other system is?

Regards,
Chris

On 10/14/15 6:54 PM, Edward Vidal wrote:
>  Hello All,
>
> Testing https://github.com/udara28/SDRAM_Controller.git
>
> python Conversion generates on Raspberry Pi 2B
> -rw-r--r--  1 root root 10774 Oct 14 19:48 MySdramCntl.v
> -rw-r--r--  1 root root 12320 Oct 14 19:48 MySdramCntl.vhd
> -rw-r--r--  1 root root  4346 Oct 14 19:48 pck_myhdl_10.vhd
>
> This works okay on several systems see below.
>
> python test_controller.py on Raspberry Pi 2B
> Traceback (most recent call last):
>    File "test_controller.py", line 30, in <module>
>      sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
>    File "/home/root/SDRAM_Controller/sdram.py", line 51, in sdram
>      @always(clk.posedge)
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 59, in _always_decorator
>      return _Always(func, args)
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 78, in __init__
>      symdict.update(zip(freevars, closure))
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 77, in <genexpr>
>      closure = (c.cell_contents for c in func.__closure__)
> ValueError: Cell is empty
>
> python test_controller.py
> vidal@vidal-MX6438:~/wkg/SDRAM_Controller$ python test_controller.py
>  BANK 0 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>  BANK 1 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>  BANK 2 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>  BANK 3 STATE : [CHANGE] Uninitialized -> Initialized @  3999
> --------------------------
>  Mode  | CAS  |  Burst
> --------|-------|---------
>  Burst  | 3    |  1
> --------------------------
>  DATA : [WRITE] Addr: 120  Data: 23
>  SDRAM : [READ] Commnad registered
>  STATE : [READ] Data Ready @  4167  value :  23
> Data Value :  23  clk :  4169
> <class 'myhdl._SuspendSimulation'>: Simulated 7500 timesteps
>
> Regards,
>
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> ------------------------------------------------------------------------------
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



------------------------------------------------------------------------------
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list


  

Re: [myhdl-list] test SDRAM_Controller

[Christopher F. <chr...@gm...>]

Edward,

Do you have the full Python version for both systems?
The RPi is 2.7.? and the other system is?

Regards,
Chris

On 10/14/15 6:54 PM, Edward Vidal wrote:
>   Hello All,
>
> Testing https://github.com/udara28/SDRAM_Controller.git
>
> python Conversion generates on Raspberry Pi 2B
> -rw-r--r--  1 root root 10774 Oct 14 19:48 MySdramCntl.v
> -rw-r--r--  1 root root 12320 Oct 14 19:48 MySdramCntl.vhd
> -rw-r--r--  1 root root  4346 Oct 14 19:48 pck_myhdl_10.vhd
>
> This works okay on several systems see below.
>
> python test_controller.py on Raspberry Pi 2B
> Traceback (most recent call last):
>    File "test_controller.py", line 30, in <module>
>      sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
>    File "/home/root/SDRAM_Controller/sdram.py", line 51, in sdram
>      @always(clk.posedge)
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 59, in _always_decorator
>      return _Always(func, args)
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 78, in __init__
>      symdict.update(zip(freevars, closure))
>    File
> "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py",
> line 77, in <genexpr>
>      closure = (c.cell_contents for c in func.__closure__)
> ValueError: Cell is empty
>
> python test_controller.py
> vidal@vidal-MX6438:~/wkg/SDRAM_Controller$ python test_controller.py
>   BANK 0 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>   BANK 1 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>   BANK 2 STATE : [CHANGE] Uninitialized -> Initialized @  3999
>   BANK 3 STATE : [CHANGE] Uninitialized -> Initialized @  3999
> --------------------------
>   Mode   | CAS   |   Burst
> --------|-------|---------
>   Burst  | 3     |   1
> --------------------------
>   DATA : [WRITE] Addr: 120  Data: 23
>   SDRAM : [READ] Commnad registered
>   STATE : [READ] Data Ready @  4167  value :  23
> Data Value :  23  clk :  4169
> <class 'myhdl._SuspendSimulation'>: Simulated 7500 timesteps
>
> Regards,
>
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> ------------------------------------------------------------------------------
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] test SDRAM_Controller

[Edward V. <dev...@sb...>]

 Hello All,
 
Testing https://github.com/udara28/SDRAM_Controller.git 

python Conversion generates on Raspberry Pi 2B 
-rw-r--r--  1 root root 10774 Oct 14 19:48 MySdramCntl.v
-rw-r--r--  1 root root 12320 Oct 14 19:48 MySdramCntl.vhd
-rw-r--r--  1 root root  4346 Oct 14 19:48 pck_myhdl_10.vhd

This works okay on several systems see below. 

python test_controller.py on Raspberry Pi 2B 
Traceback (most recent call last):
  File "test_controller.py", line 30, in <module>
    sdram_Inst = sdram(clk_i,sd_intf_Inst,show_command=False)
  File "/home/root/SDRAM_Controller/sdram.py", line 51, in sdram
    @always(clk.posedge)
  File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 59, in _always_decorator
    return _Always(func, args)
  File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 78, in __init__
    symdict.update(zip(freevars, closure))
  File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 77, in <genexpr>
    closure = (c.cell_contents for c in func.__closure__)
ValueError: Cell is empty

python test_controller.py 
vidal@vidal-MX6438:~/wkg/SDRAM_Controller$ python test_controller.py 
 BANK 0 STATE : [CHANGE] Uninitialized -> Initialized @  3999
 BANK 1 STATE : [CHANGE] Uninitialized -> Initialized @  3999
 BANK 2 STATE : [CHANGE] Uninitialized -> Initialized @  3999
 BANK 3 STATE : [CHANGE] Uninitialized -> Initialized @  3999
--------------------------
 Mode   | CAS   |   Burst 
--------|-------|---------
 Burst  | 3     |   1 
--------------------------
 DATA : [WRITE] Addr: 120  Data: 23
 SDRAM : [READ] Commnad registered 
 STATE : [READ] Data Ready @  4167  value :  23
Data Value :  23  clk :  4169
<class 'myhdl._SuspendSimulation'>: Simulated 7500 timesteps
Regards,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] Conversion generates invalid VHDL

[Josy B. <jos...@gm...>]

> I don't see anything in the VHDL standard stating that the loop range 
must be constant. That would be quite a limitation. The only requirement 
is that of a discrete range.
Guy,

Correct. Using _variables_ in the range specification will simulate but 
not synthesise (because the compiler will not know how to unroll the 
loop). As a consequence using this construct in an @always(clk.posedge) 
will not make sense, so flagging it with an error/warning would be most 
appropriate. Note that Verilog too expects static arguments.

Regards,

Josy

[myhdl-list] Hedwig's theme

[Guy E. <guy...@gm...>]

- https://www.pinterest.com/pin/172755335682605117/
- https://www.pinterest.com/pin/374221050266594082/


Guy Eschemann
FPGA Consultant
noasic GmbH
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
gu...@no... <Guy...@gm...>
Follow me on Twitter: @geschema <http://twitter.com/geschema>
http://noasic.com
http://airhdl.com
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.

Re: [myhdl-list] Conversion generates invalid VHDL

[Guy E. <guy...@gm...>]

Hi Josy,

I don't see anything in the VHDL standard stating that the loop range must
be constant. That would be quite a limitation. The only requirement is that
of a discrete range.

Regards,
Guy.

On Thu, Oct 1, 2015 at 2:42 PM, Josy Boelen <jos...@gm...> wrote:

>
> > def test(clk_i, data_i, data_o):
> >      <at> always(clk_i.posedge)
> >     def logic():
> >         start_idx_v = intbv(0, min=0, max=1 + 15)
> >         for i in range(start_idx_v, 1 + 15):
> >             data_o.next[i] = data_i[i]
> >     return instances()
> >
> > if __name__ == "__main__":
> >     clk_i = Signal(bool(0))
> >     data_i = Signal(intbv(0)[16:])
> >     data_o = Signal(intbv(0)[16:])
> >     toVHDL(test, clk_i, data_i, data_o)
>
> Hi Guy,
>
> Any particular reason you want to write it like that?
> I'd say using an intbv as an argument in the for-loop range is
> inappropriate and the conversion should detect that and raise an error. It
> may simulate fine, though.
> Anyway VHDL requires the for-loop range to be constant and I'm not sure
> the integer() cast will work either.
>
> Regards,
>
> Josy
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Conversion generates invalid VHDL

[Josy B. <jos...@gm...>]

> def test(clk_i, data_i, data_o):
>      <at> always(clk_i.posedge)
>     def logic():
>         start_idx_v = intbv(0, min=0, max=1 + 15)
>         for i in range(start_idx_v, 1 + 15):
>             data_o.next[i] = data_i[i]
>     return instances()
> 
> if __name__ == "__main__":
>     clk_i = Signal(bool(0))
>     data_i = Signal(intbv(0)[16:])
>     data_o = Signal(intbv(0)[16:])
>     toVHDL(test, clk_i, data_i, data_o)

Hi Guy,

Any particular reason you want to write it like that? 
I'd say using an intbv as an argument in the for-loop range is 
inappropriate and the conversion should detect that and raise an error. It 
may simulate fine, though.
Anyway VHDL requires the for-loop range to be constant and I'm not sure 
the integer() cast will work either.

Regards,

Josy

[myhdl-list] Conversion generates invalid VHDL

[Guy E. <guy...@gm...>]

Hi,

I've noticed that the following MyHDL code:

###
from myhdl import *

def test(clk_i, data_i, data_o):
    @always(clk_i.posedge)
    def logic():
        start_idx_v = intbv(0, min=0, max=1 + 15)
        for i in range(start_idx_v, 1 + 15):
            data_o.next[i] = data_i[i]
    return instances()

if __name__ == "__main__":
    clk_i = Signal(bool(0))
    data_i = Signal(intbv(0)[16:])
    data_o = Signal(intbv(0)[16:])
    toVHDL(test, clk_i, data_i, data_o)
###

generates invalid VHDL code:

###
TEST_LOGIC: process (clk_i) is
    variable start_idx_v: unsigned(3 downto 0);
begin
    if rising_edge(clk_i) then
        start_idx_v := to_unsigned(0, 4);
        for i in start_idx_v to (1 + 15)-1 loop
            data_o(i) <= data_i(i);
        end loop;
    end if;
end process TEST_LOGIC;
###

The problem is that VHDL doesn't allow unsigned objects in for loop bounds.
At the very least, there should be a type conversion to an integer:

        for i in to_integer(start_idx_v) to (1 + 15)-1 loop

Regards,
Guy.


Guy Eschemann
FPGA Consultant
noasic GmbH
Sundheimer Feld 6
77694 Kehl, Germany

Tel.: +49 (0) 7851 63 66 305
gu...@no... <Guy...@gm...>
Follow me on Twitter: @geschema <http://twitter.com/geschema>
http://noasic.com
http://airhdl.com
USt-IdNr.: DE296246015
HRB 711881, Amtsgericht Freiburg i. Br.

Re: [myhdl-list] Beginner Question: Loop Unrolling & Use of Tuple Elements

[Christopher F. <chr...@gm...>]

On 6/28/2015 6:51 PM, co...@ne... wrote:
> Hello,
>
> Things are well! Not sure if you'll be back at ESC-SV, but if so will buy
> you a beer or three for the helpful response there ;-)
>
> Those answers solve my problems, so am back on track. Am planning on having
> a small write-up for Circuit Cellar on MyHDL, just replicating the simple
> FIR demo I did before. Of course the MyHDL version is nicer since it can use
> scipy to generate the coefficients and compare results...
>
> Warm Regards,
>
>    -Colin O'Flynn
>

Colin,

I noticed in my email the latest CC has your article:

     PROGRAMMABLE LOGIC IN PRACTICE, Rapid FPGA Design in
     Python using MyHDL.


Congratulations, I haven't read it yet, hope to get to
it soon.

Regards,
Chris

[myhdl-list] Summer of Gateware

[Christopher F. <chr...@gm...>]

As many know, this last summer we (the myhdl project
and community) participated in the Google Summer of
Code (GSoC) as a Python Software Foundation (PSF)
sub-organization.

I created a small write-up of the experience:
http://www.fpgarelated.com/showarticle/812.php

Thanks to everyone that volunteered to be a mentor
or applied as a student.  As the blog post indicates
we were limited to two students this year.  I want
to specifically thank Dave Vandenbout (Xess corp)
for mentoring the SDRAM project.

This year went fairly well, we intend to try again
next year.  We had numerous volunteers for mentors,
hopefully next year we will be able to utilize all
the volunteers :) and support more students.

Please let me know if you seen any typos, incorrect
statements, or errors in the post.  Feedback on
the this last years GSoC is appreciated as well
(the good, band and the ugly).

Regards,
Chris

Re: [myhdl-list] Signal names for verilog conversion of interfaces

[Josy B. <jos...@gm...>]

Hi Richard,


it is a (subtle) bug. Subtle because probably the case of a module only 
having _interface_ type ports never has been imagined?

BTW. I rewrote your top-module slightly, adding Signals in the toVerilog() 
call:
    def iftest_top(i1, o1, i2, o2, clk):
        test_instance1 = test_logic(i1, o1, clk)
        test_instance2 = test_logic(i2, o2, clk)

        return test_instance1, test_instance2

    toVerilog(iftest_top, i1, o1, i2, o2, clk)

otherwise the conversion ends up with no module ports and multiple 
warnings.

Regards,

Josy

[myhdl-list] Signal names for verilog conversion of interfaces

[Richard L. <r.w...@gm...>]

Hi, I'm a new user to MyHDL and have hit an issue converting my design to
verilog. The python code structure I'm using is to define bus interface
classes and logic functions to operate exclusively between these
interfaces. When it comes to the generated code I see wire and register
name aliasing where I expected instance-specific names. I managed to
whittle it down to a test case as follows (against version 0.9.0):

#!/usr/bin/env python

# coding=utf-8


import argparse


from myhdl import *


class TestInterface():

    def __init__(self):

        self.a = Signal(bool(0))


def test_logic(i_if, o_if, clk=None):

    #@always(clk.posedge)

    @always_comb

    def logic():

        o_if.a.next = i_if.a

    return logic


def main():

    parser = argparse.ArgumentParser()

    parser.add_argument('-t', '--test', type=int, choices=[1, 2], default=1,
help='test to run')

    args = parser.parse_args()


    clk = Signal(bool(0)) if args.test == 2 else None

    i1, o1, i2, o2 = [TestInterface() for _ in range(4)]

    def iftest_top():

        test_instance1 = test_logic(i1, o1, clk)

        test_instance2 = test_logic(i2, o2, clk)

        return test_instance1, test_instance2

    dts = toVerilog(iftest_top)


if __name__ == "__main__":

    main()

In the first case the names alias:

$ ./iftest.py
** ToVerilogWarning: Signal is not driven: i_if_a
** ToVerilogWarning: Signal is driven but not read: o_if_a
$ iverilog -Wall -t null iftest_top.v
iftest_top.v:16: error: Net ``i_if_a'' has already been declared.
iftest_top.v:17: error: Net ``o_if_a'' has already been declared.
2 error(s) during elaboration.

In the second case with an additional signal passed alongside the names
inferred are unique:

$ ./iftest.py -t 2
** ToVerilogWarning: Signal is not driven: test_instance2_i_if_a
** ToVerilogWarning: Signal is driven but not read: test_instance2_o_if_a
** ToVerilogWarning: Signal is not driven: test_instance1_i_if_a
** ToVerilogWarning: Signal is driven but not read: test_instance1_o_if_a
$ iverilog -Wall -t null iftest_top.v

I can certainly use this alternative as a workaround but I'm curious if
this behaviour is a bug or intentional?

Thanks,

Richard.