myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] YOSYS

[Edward V. <dev...@sb...>]

Hello All,https://github.com/develone/raspberrypi2_yocto/blob/master/doc/yosys_manual.pdfFrom  the yosys manual 
The proposed custom HDL synthesis tool should be licensed under a Free and Open Source Software
(FOSS) licence. So an existing FOSS Verilog or VHDL synthesis tool would have been needed as basis
to build upon. The main advantages of choosing Verilog or VHDL is the ability to synthesize existing
HDL code and to mitigate the requirement for circuit-designers to learn a new language. In order to
take full advantage of any existing FOSS Verilog or VHDL tool, such a tool would have to provide a
feature-complete implementation of the synthesizable HDL subset.
Regards
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] co-simuation

[Edward V. <dev...@sb...>]

Chris,I did run this on the a Ubuntu 12.04 on an AMD processor.  I get the same results as on the Pi.  
Dave is working on Lattice ICE-40 board for the Pi and I wanted to get some tools working on the Pi.  So far I have I been able to get GTKWave, Myhdl, Iverilog, vhd2vl, FireFox, Python 2.7 & Python3, XSTOOLs(XuLA2-LX), samba and OpenCV  on the Pi.  The O/S for the Pi was created with Yocto which creates a custom Linux Distro and the supporting cross compiler.Also a tool which is needed but not running on the Pi is Yosys which is the tool used to generate the bit file for the Lattice ICE-40.  This would in turn createa standalone HDL development system at a low cost.  Dave indicates the XSTOOLs will not be needed for Lattice ICE-40.  The bit file will be downloaded using GPIO instead of the USB.  Dave tweeted last week that the board was almost ready.  I hope I stated everything correctly.

If you have any questions let me know.
 Thanks Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 


     On Monday, August 31, 2015 12:24 PM, Christopher Felton <chr...@gm...> wrote:
   

 On 8/31/2015 1:07 PM, Edward Vidal wrote:
> Yes,After installing MyHDL and Iverilog on the Raspberry Pi 2 BI did a make in mydhdl/cosimulation/icarus which created the myhdl.vpi for the arm.This was used by both alt.hdl & vhd2vl co-simulation.  If you are testing on non arm system this should be replaced by the one created on your system.
> I maybe should have not added it to the github repository.

You might want to try running it on a desktop system
first, that way you can isolate system/OS issues.
Quickly reviewing the code nothing jumps out.  My next
step to test it on an x86 desktop linux.

I have to admit, I am a little confused why you are
running the toolflow on the RPi2 - what is the goal?

Regards,
Chris


> Thanks
>  Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
>      On Monday, August 31, 2015 11:49 AM, Christopher Felton <chr...@gm...> wrote:
>
>
>  <snip>
>>
>> I created the files and folder vcd
>> https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb
>>
>> ifchain  myhdl.vpi  tb_ifchain.v  test_ifchain.py  vcd
>>
>
> Did you build the myhdl.vpi locally on the machine
> you are running?
>
> Regards,
> Chris
>
>
>
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Re: [myhdl-list] co-simuation

[Christopher F. <chr...@gm...>]

On 8/31/2015 1:07 PM, Edward Vidal wrote:
> Yes,After installing MyHDL and Iverilog on the Raspberry Pi 2 BI did a make in mydhdl/cosimulation/icarus which created the myhdl.vpi for the arm.This was used by both alt.hdl & vhd2vl co-simulation.  If you are testing on non arm system this should be replaced by the one created on your system.
> I maybe should have not added it to the github repository.

You might want to try running it on a desktop system
first, that way you can isolate system/OS issues.
Quickly reviewing the code nothing jumps out.  My next
step to test it on an x86 desktop linux.

I have to admit, I am a little confused why you are
running the toolflow on the RPi2 - what is the goal?

Regards,
Chris


> Thanks
>   Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
>       On Monday, August 31, 2015 11:49 AM, Christopher Felton <chr...@gm...> wrote:
>
>
>   <snip>
>>
>> I created the files and folder vcd
>> https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb
>>
>> ifchain  myhdl.vpi  tb_ifchain.v  test_ifchain.py  vcd
>>
>
> Did you build the myhdl.vpi locally on the machine
> you are running?
>
> Regards,
> Chris
>
>
>
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>
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Re: [myhdl-list] co-simuation

[Edward V. <dev...@sb...>]

Yes,After installing MyHDL and Iverilog on the Raspberry Pi 2 BI did a make in mydhdl/cosimulation/icarus which created the myhdl.vpi for the arm.This was used by both alt.hdl & vhd2vl co-simulation.  If you are testing on non arm system this should be replaced by the one created on your system.  
I maybe should have not added it to the github repository.
Thanks
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 


     On Monday, August 31, 2015 11:49 AM, Christopher Felton <chr...@gm...> wrote:
   

 <snip>
>
> I created the files and folder vcd
> https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb
>
> ifchain  myhdl.vpi  tb_ifchain.v  test_ifchain.py  vcd
>

Did you build the myhdl.vpi locally on the machine
you are running?

Regards,
Chris



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Re: [myhdl-list] co-simuation

[Christopher F. <chr...@gm...>]

<snip>
>
> I created the files and folder vcd
> https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb
>
> ifchain  myhdl.vpi  tb_ifchain.v  test_ifchain.py  vcd
>

Did you build the myhdl.vpi locally on the machine
you are running?

Regards,
Chris

[myhdl-list] co-simuation

[Edward V. <dev...@sb...>]

Hello All,
I am testing VHD2VL and trying to test the outputted file ifchain.v with MyHDL & Iverilog
co-simulation on a Raspberry Pi 2 B.

I created the files and folder vcd 
https://github.com/develone/raspberrypi2_yocto/tree/master/vhd2vl/examples/tb

ifchain  myhdl.vpi  tb_ifchain.v  test_ifchain.py  vcd

The above files were based on Chris Felton alt.hdl
that I had forked and tested on Raspberry Pi 2 B 
https://github.com/develone/alt.hdl/tree/master/examples/ex2_mathadds/test_verilogs
    git clone https://github.com/develone/alt.hdl.git
    cd alt.hdl/examples/ex2_mathadds/test_verilogs/
    cp ~/raspberrypi2_yocto/vhd2vl/examples/tb/myhdl.vpi .
    mkdir vcd
    python test_mathadds.py
This producee the expected output.
The output in next few lines below between the *** are  to verify GTKWAVE, MyHDL & Iverilog 
work with a Co-Simulation on Raspberry Pi 2 B.
*******************************************************************
python test_mathadds.py 
compiling ...
  *iverilog -o mathadds ../myhdl/mm_maths1.v ../bsv/mb_maths1.v ../bsv/mkMaths1.v ../chisel/generated/mc_maths1.v ./tb_mathadds.v 
cosimulation setup ...
VCD info: dumpfile vcd/maths1.vcd opened for output.
start (co)simulation ...
      33:  [       0,        0] mb     0,  mc     0,  mm     0 [20]
      34:  [       1,        1] mb    20,  mc    20,  mm    20 [20]
      35:  [       1,        1] mb    20,  mc    20,  mm    20 [20]
      36:  [       1,        1] mb    20,  mc    20,  mm    20 [20]
      37:  [       1,        1] mb    20,  mc    20,  mm    20 [5300]
      38:  [     543,      -13] mb  5300,  mc  5300,  mm  5300 [5300]
      39:  [     543,      -13] mb  5300,  mc  5300,  mm  5300 [5300]
      40:  [     543,      -13] mb  5300,  mc  5300,  mm  5300 [5300]
      41:  [     543,      -13] mb  5300,  mc  5300,  mm  5300 [-50]
      42:  [      -7,        2] mb   -50,  mc   -50,  mm   -50 [-50]
      43:  [      -7,        2] mb   -50,  mc   -50,  mm   -50 [-50]
      44:  [      -7,        2] mb   -50,  mc   -50,  mm   -50 [-50]
      45:  [      -7,        2] mb   -50,  mc   -50,  mm   -50 [630010]
      46:  [   31000,    32001] mb -25350,  mc -25350,  mm -25350 [630010]
      47:  [   31000,    32001] mb -25350,  mc -25350,  mm -25350 [630010]
      48:  [   31000,    32001] mb -25350,  mc -25350,  mm -25350 [630010]
In addition the gtkwave vcd/maths1.vcd shows the expected signal changes
*******************************************************************

If in stimlus section of test_ifchain.py.
I comment the lines 25 & 26 I get the results below.

    python test_ifchain.py
    Running test...
     0
      *{'a': Signal(intbv(0L)), 'status': Signal(False), 'b': Signal(intbv(0L)),
    compiling ...
      iverilog -o ifchain ../ifchain.v ./tb_ifchain.v
    cosimulation setup ...
      vvp -m ./myhdl.vpi ifchain
    VCD info: dumpfile vcd/ifchain1.vcd opened for output.
      <myhdl._Cosimulation.Cosimulation object at 0x769f6870>
    back from prep cosim
    start (co)simulation ...

This appears to work okay but when I gtkwave vcd/ifchain1.vcd
The signals a,b and clk red and status is yellow.

When the I uncomment lines 25 & 26 try send values to the co-simulation.
The program does not run to completion but crashes with the following error.
  File "/usr/lib/python2.7/site-packages/myhdl-1.0dev-py2.7.egg/myhdl/_Waiter.py", line 142, in next
    clause = next(self.generator)
  File "test_ifchain.py", line 25, in stimlus
    a.next = 10

Not be an experienced co-simulation user I asked if anyone can provide me insight into this
problem.  Thanks in advance. Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] Fixed-point status?

[Mark A. H. <ma...@ha...>]

Cool--thanks!  Will be following this closely.

Regards,

Mark

On Fri, 28 Aug 2015 20:24:08 -0500
Christopher Felton <chr...@gm...> wrote:
> You can follow the latest in the github issue:
> https://github.com/jandecaluwe/myhdl/issues/108
> 
> Regards,
> Chris
> 
> On 8/28/15 5:35 PM, Mark Haun wrote:
> > Hi, new mailing-list subscriber here.
> >
> > A couple years back there was a flurry of discussion about a
> > fixed-point data type (fixbv proposed in MEP-111), but google
> > doesn't find much in the past year.  I haven't been following myhdl
> > closely, but it was been on my to-do list to sit down and learn
> > it.  Lack of fixed-point is the main thing holding me back as my
> > interest in FPGAs is pretty much limited to DSP and SDR stuff.
> > Anyone know if the fixbv effort is still moving forward?
> >
> > Thanks,
> >
> > Mark

Re: [myhdl-list] vhdl to verilog

[Christopher F. <chr...@gm...>]

On 8/28/15 7:43 AM, Edward Vidal wrote:
> Hello all,
> While looking for tool to convert VHDL to Verilog for simulation with
> Iverilog & myhdl I found what appears to work.
> http://www.ocean-logic.com/downloads.htm
> I downloaded with the following wget
> http://www.ocean-logic.com/pub/vhd2vl2.tgz
> Just follow the README.txt.

A small write-up, how I used vhd2vl to convert
the open-cores JPEG encoder from VHDL to Verilog.
http://www.fpgarelated.com/showarticle/718.php

Regards,
Chris

Re: [myhdl-list] Fixed-point status?

[Christopher F. <chr...@gm...>]

You can follow the latest in the github issue:
https://github.com/jandecaluwe/myhdl/issues/108

Regards,
Chris

On 8/28/15 5:35 PM, Mark Haun wrote:
> Hi, new mailing-list subscriber here.
>
> A couple years back there was a flurry of discussion about a fixed-point
> data type (fixbv proposed in MEP-111), but google doesn't find much in the
> past year.  I haven't been following myhdl closely, but it was been on my
> to-do list to sit down and learn it.  Lack of fixed-point is the main thing
> holding me back as my interest in FPGAs is pretty much limited to DSP and
> SDR stuff.  Anyone know if the fixbv effort is still moving forward?
>
> Thanks,
>
> Mark
>
> ------------------------------------------------------------------------------
>

[myhdl-list] Fixed-point status?

[Mark H. <ha...@ke...>]

Hi, new mailing-list subscriber here.

A couple years back there was a flurry of discussion about a fixed-point
data type (fixbv proposed in MEP-111), but google doesn't find much in the
past year.  I haven't been following myhdl closely, but it was been on my
to-do list to sit down and learn it.  Lack of fixed-point is the main thing
holding me back as my interest in FPGAs is pretty much limited to DSP and
SDR stuff.  Anyone know if the fixbv effort is still moving forward?

Thanks,

Mark

[myhdl-list] vhdl to verilog

[Edward V. <dev...@sb...>]

Hello all,While looking for tool to convert VHDL to Verilog for simulation with Iverilog & myhdl I found what appears to work. http://www.ocean-logic.com/downloads.htmI downloaded with the following wget http://www.ocean-logic.com/pub/vhd2vl2.tgz
Just follow the README.txt.
I tried it on the raspberry Pi but could not get it work.  I tested on my Ubuntu and it appears to work based on examples. I need to do more testing.
The program appears to use Bision & Flex which I am not very knowledgeable. 
This would be a great tool for the Raspberry Pi HDL development that I am working on.Regards,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

[myhdl-list] gtkwave iverilog for Raspberry Pi 2 B

[Edward V. <dev...@sb...>]

All,I just completed a build of Yocto that provides myhdl, gtkwave, iverilog, and XSTOOLS.  This fits on 4GB SD card.https://github.com/develone/raspberrypi2_yocto.gitIf you have any questions let me know.  I can provide acess to files required.I just need your e-mail.
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

[myhdl-list] icstorm on Raspberry Pi 2 B

[Edward V. <dev...@sb...>]

Hello Ciffford, and MyHDL This might provide the synthesizer on the development platform that I am working on.
I located your site while working with Dave VandenboutDave sells the XuLA2  and the StickIt-MB which combines a 
XulA2 with Raspberry.
I am working to create a HDL development platform.Currently I have an image that I created from source using YoctoThis image has OpenCV which works with 2 C920 cameras,MyHDL, XSTOOLs & GTKWave.  

XSTOOLs & GTKWave need to installed after booting the image.I recently built the code icestorm after adding libftdi1 and modifing a few filessee the files icestorm_diff080615.txt & notes_test_icestorm.txtat https://github.com/develone/raspberrypi2_yocto

let me know if you have any questions.Regards,
Edward Vidal Jr. 
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] bitbake recipes to build myhdl, xstools, iverilog and gtkwave using Yocto

[Dave V. <dev...@gm...>]

On 07/31/2015 8:02 AM, Edward Vidal wrote:
> Hi Jeremy,
> If the synthesis tool is the goal not
> many boards running Linux don't fit the bill.
> Xilinx and Altera have the market
>  for the synthesis and bit file generation.

Hey, Ed, this made me think. What if you had a StickIt! motherboard with 
a Lattice ICE40 FPGA, SDRAM and a serial flash instead of the XuLA 
connector? Could you run the open source ICE40 synthesizer tools on the 
RPi? Then you would have a complete FPGA development environment on the 
RPi that could load the FPGA on the StickIt!.

>
> I started in Yocto before FPGAs since
>  I have worked in Linux for many years.
> I created images for the BeagleBoard,
> PandaBoard, BeagleBone, and ZedBoard using Yocto.
>
> My thinking was the ZedBoard was the answer at $395.00.
> Learning Linux and FPGAs takes
> quite an effort.  That is where MyHDL and Xess came.
> The XulA2 which comes in 2 verisons XulA2-LX9 or XulA2-LX25
>  The XulA2 at $69 StickIt!-MB $20 (for GPIO to Pi ) and Raspberry Pi 2 B
> at $35makes a low cost with a small foot print.
>
> Yocto which started in 2010 from Openembedded
> appears to be growing in users at the highest rate.
>
> If you just want Linux with Ethernet, USB, and HDMI
> it takes about 675MB image. This would need a mouse
> or touch screen HDI since it supports a virtual keyboard.
>
> Now if you want OpenCV with C920 camera support
> and kernel-dev xterm git
>  jasper gsl gsl-dev python-netserver python-pygtk
>  python-pygtk-dev python-numpy liba52 liba52-dev
>  libmad libmad-dev libmad-staticdev
>  chkconfig v4l-utils python-imaging parted
>  python-distribute python-pyrex python-pexpect
>  gperf tree libav libav-dev
>  x264 x264-dev libav libav-dev opencv opencv-samples
>  cmake opencv-apps python-opencv tcl tk
> The requires an image of 868.2 MB.
>
> I have the software for what I described on 32 GB
> running Debian on a Raspberry Pi 2 B.
>
> I think the next step is the Compute Module which is based
> on the RaspberryPi designs.  I also think that Yocto will
> be developing for that as well.  Most of the people at
> Yocto work for WindRiver which is an Intel company.
> Also Intel is buying Altera.
>
> GNURADIO and OpenCV are where the FPGA opportunites
> will be running some ARM processor.
> Let me know if you have any questions.
>
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
>
>
> On Thursday, July 30, 2015 4:26 PM, Jeremy Herbert 
> <jer...@gm...> wrote:
>
>
> Hi Edward,
>
> Please forgive my ignorance, but isn't this ultimately limited as a 
> development tool because there is no synthesis tool on the rpi ?
>
> Thanks,
> Jeremy
> On Fri, 31 Jul 2015 at 2:04 am Edward Vidal <dev...@sb... 
> <mailto:dev...@sb...>> wrote:
>
>     Hi all,
>     Dave the current verison of Xstools is 6.0.15?
>     Current vesion of MyHDL is 1.0.0 is that correct?
>
>     My goal is create a Yocto image for the Raspberry Pi 2 B that
>     provides the necessary tools to use MyHdl with Xstools, Iverilog &
>     GTKwave.  The combo of RaspberryPi 2 B with a StickIt-MB & XulA2 
>     would make a great low-cost development tool for developing and
>     testing FPGAs.
>
>     I currently have a working core-image-sato that I can install
>     myhdl using python setup.py develop instead of  python setup.py
>     install.  I also can install Iverilog and GTKWave compiling from
>     source on the target.
>      I can ssh to the Raspberry Pi
>     ssh -Y 192.168.1.136
>     root@192.168.1.136 <mailto:root@192.168.1.136>'s password:
>     root@raspberrypi2:~# python
>     Python 2.7.9 (default, Jul 26 2015, 21:01:54)
>     [GCC 4.9.3] on linux2
>     Type "help", "copyright", "credits" or "license" for more information.
>     >>> from myhdl import *
>     >>>
>
>     I can also download my repo
>     https://github.com/develone/jpeg-2000-test.git
>     Then cd into the jpeg-2000-test/ipython_fixbv.
>     Where I can execute python test_jpegEnc.py.
>     The above does a dwt on an image.
>     cd myhdl
>     git log
>     commit 0f106505cbf4047e6a6641b451b817615d48772f
>     Merge: c7d92c4 443024f
>     Author: jandecaluwe <ja...@ja... <mailto:ja...@ja...>>
>     Date:   Tue Jul 28 14:25:21 2015 +0200
>
>         Merge pull request #116 from jck/signamevisitor
>
>         prevent adding intbv to senslist of always_comb
>     cd iverilog
>     git log
>     commit d3bdc60201079eb22fe8506e951a57c95b19e28a
>     Author: Cary R <cy...@ya... <mailto:cy...@ya...>>
>     Date:   Wed Jul 22 00:27:13 2015 -0700
>
>         Correctly display events when dumping using the FST format
>
>         This patch is from Tony Bybell and fixes a segmentation fault
>     when dumping
>         an event to a FST file.
>
>     iverilog -h
>     Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]
>                     [-g1995|-g2001|-g2005] [-g<feature>]
>                     [-D macro[=defn]] [-I includedir] [-M depfile] [-m
>     module]
>                     [-N file] [-o filename] [-p flag=value]
>                     [-s topmodule] [-t target] [-T min|typ|max]
>                     [-W class] [-y dir] [-Y suf] source_file(s)
>
>     See the man page for details.
>
>     gtkwave -v
>     Gtk-Message: Failed to load module "canberra-gtk-module"
>
>     GTKWave Analyzer v3.3.65 (w)1999-2015 BSI
>
>     I am in the process of creating the recipes to install the above
>     tools on the image.
>     The process that I am using is found at
>     https://github.com/develone/raspberrypi2_yocto.git
>
>     I am using an AMD 6 core with 16 GB and takes about 2 hours to
>     create the image.
>
>     If you have any questions
>     Edward Vidal Jr.
>     e-mail dev...@sb... <mailto:dev...@sb...>
>     915-595-1613
>     ------------------------------------------------------------------------------
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li...
>     <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>


-- 
------------------------------------------------------------------------
Dave Vandenbout / XESS Corp.
2608 Sweetgum Drive
Apex NC 27539-8851
USA
/de...@xe.../
/www.xess.com/
------------------------------------------------------------------------

Re: [myhdl-list] bitbake recipes to build myhdl, xstools, iverilog and gtkwave using Yocto

[Edward V. <dev...@sb...>]

Hi Jeremy,
If the synthesis tool is the goal not 
many boards running Linux don't fit the bill.
Xilinx and Altera have the market
 for the synthesis and bit file generation.

I started in Yocto before FPGAs since
 I have worked in Linux for many years.
I created images for the BeagleBoard, 
PandaBoard, BeagleBone, and ZedBoard using Yocto.

My thinking was the ZedBoard was the answer at $395.00.  
Learning Linux and FPGAs takes
quite an effort.  That is where MyHDL and Xess came.
The XulA2 which comes in 2 verisons XulA2-LX9 or XulA2-LX25 
 The XulA2 at $69 StickIt!-MB $20 (for GPIO to Pi ) and Raspberry Pi 2 B at $35 makes a low cost with a small foot print. 
 
Yocto which started in 2010 from Openembedded 
appears to be growing in users at the highest rate.

If you just want Linux with Ethernet, USB, and HDMI
it takes about 675MB image. This would need a mouse
or touch screen HDI since it supports a virtual keyboard.  

Now if you want OpenCV with C920 camera support 
and kernel-dev xterm git 
 jasper gsl gsl-dev python-netserver python-pygtk
 python-pygtk-dev python-numpy liba52 liba52-dev
 libmad libmad-dev libmad-staticdev 
 chkconfig v4l-utils python-imaging parted 
 python-distribute python-pyrex python-pexpect
 gperf tree libav libav-dev 
 x264 x264-dev libav libav-dev opencv opencv-samples
 cmake opencv-apps python-opencv tcl tk
The requires an image of 868.2 MB.

I have the software for what I described on 32 GB
running Debian on a Raspberry Pi 2 B. 

I think the next step is the Compute Module which is based
on the RaspberryPi designs.  I also think that Yocto will
be developing for that as well.  Most of the people at
Yocto work for WindRiver which is an Intel company.  
Also Intel is buying Altera.  

GNURADIO and OpenCV are where the FPGA opportunites 
will be running some ARM processor. Let me know if you have any questions.
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613 


     On Thursday, July 30, 2015 4:26 PM, Jeremy Herbert <jer...@gm...> wrote:
   

 Hi Edward,

Please forgive my ignorance, but isn't this ultimately limited as a development tool because there is no synthesis tool on the rpi ?

Thanks,
Jeremy
On Fri, 31 Jul 2015 at 2:04 am Edward Vidal <dev...@sb...> wrote:

Hi all,Dave the current verison of Xstools is 6.0.15?Current vesion of MyHDL is 1.0.0 is that correct?
My goal is create a Yocto image for the Raspberry Pi 2 B that provides the necessary tools to use MyHdl with Xstools, Iverilog & GTKwave.  The combo of RaspberryPi 2 B with a StickIt-MB & XulA2  would make a great low-cost development tool for developing and testing FPGAs.

I currently have a working core-image-sato that I can install myhdl using python setup.py develop instead of  python setup.py install.  I also can install Iverilog and GTKWave compiling from source on the target.  
 I can ssh to the Raspberry Pi 
 ssh -Y 192.168.1.136
root@192.168.1.136's password: 
root@raspberrypi2:~# python
Python 2.7.9 (default, Jul 26 2015, 21:01:54) 
[GCC 4.9.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> from myhdl import *
>>> 
I can also download my repo https://github.com/develone/jpeg-2000-test.git
Then cd into the jpeg-2000-test/ipython_fixbv.Where I can execute python test_jpegEnc.py.The above does a dwt on an image.cd myhdlgit log
commit 0f106505cbf4047e6a6641b451b817615d48772f
Merge: c7d92c4 443024f
Author: jandecaluwe <ja...@ja...>
Date:   Tue Jul 28 14:25:21 2015 +0200

    Merge pull request #116 from jck/signamevisitor
    
    prevent adding intbv to senslist of always_combcd iveriloggit log
commit d3bdc60201079eb22fe8506e951a57c95b19e28a
Author: Cary R <cy...@ya...>
Date:   Wed Jul 22 00:27:13 2015 -0700

    Correctly display events when dumping using the FST format
    
    This patch is from Tony Bybell and fixes a segmentation fault when dumping
    an event to a FST file.

iverilog -h
Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]
                [-g1995|-g2001|-g2005] [-g<feature>]
                [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]
                [-N file] [-o filename] [-p flag=value]
                [-s topmodule] [-t target] [-T min|typ|max]
                [-W class] [-y dir] [-Y suf] source_file(s)

See the man page for details.

gtkwave -v
Gtk-Message: Failed to load module "canberra-gtk-module"

GTKWave Analyzer v3.3.65 (w)1999-2015 BSI

I am in the process of creating the recipes to install the above tools on the image.The process that I am using is found at https://github.com/develone/raspberrypi2_yocto.git

I am using an AMD 6 core with 16 GB and takes about 2 hours to create the image.
If you have any questions 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613------------------------------------------------------------------------------
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list



  

Re: [myhdl-list] bitbake recipes to build myhdl, xstools, iverilog and gtkwave using Yocto

[Jeremy H. <jer...@gm...>]

Hi Edward,

Please forgive my ignorance, but isn't this ultimately limited as a
development tool because there is no synthesis tool on the rpi ?

Thanks,
Jeremy
On Fri, 31 Jul 2015 at 2:04 am Edward Vidal <dev...@sb...> wrote:

> Hi all,
> Dave the current verison of Xstools is 6.0.15?
> Current vesion of MyHDL is 1.0.0 is that correct?
>
> My goal is create a Yocto image for the Raspberry Pi 2 B that provides the
> necessary tools to use MyHdl with Xstools, Iverilog & GTKwave.  The combo
> of RaspberryPi 2 B with a StickIt-MB & XulA2  would make a great low-cost
> development tool for developing and testing FPGAs.
>
> I currently have a working core-image-sato that I can install myhdl using
> python setup.py develop instead of  python setup.py install.  I also can
> install Iverilog and GTKWave compiling from source on the target.
>  I can ssh to the Raspberry Pi
> ssh -Y 192.168.1.136
> root@192.168.1.136's password:
> root@raspberrypi2:~# python
> Python 2.7.9 (default, Jul 26 2015, 21:01:54)
> [GCC 4.9.3] on linux2
> Type "help", "copyright", "credits" or "license" for more information.
> >>> from myhdl import *
> >>>
>
> I can also download my repo https://github.com/develone/jpeg-2000-test.git
> Then cd into the jpeg-2000-test/ipython_fixbv.
> Where I can execute python test_jpegEnc.py.
> The above does a dwt on an image.
> cd myhdl
> git log
> commit 0f106505cbf4047e6a6641b451b817615d48772f
> Merge: c7d92c4 443024f
> Author: jandecaluwe <ja...@ja...>
> Date:   Tue Jul 28 14:25:21 2015 +0200
>
>     Merge pull request #116 from jck/signamevisitor
>
>     prevent adding intbv to senslist of always_comb
> cd iverilog
> git log
> commit d3bdc60201079eb22fe8506e951a57c95b19e28a
> Author: Cary R <cy...@ya...>
> Date:   Wed Jul 22 00:27:13 2015 -0700
>
>     Correctly display events when dumping using the FST format
>
>     This patch is from Tony Bybell and fixes a segmentation fault when
> dumping
>     an event to a FST file.
>
> iverilog -h
> Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]
>                 [-g1995|-g2001|-g2005] [-g<feature>]
>                 [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]
>                 [-N file] [-o filename] [-p flag=value]
>                 [-s topmodule] [-t target] [-T min|typ|max]
>                 [-W class] [-y dir] [-Y suf] source_file(s)
>
> See the man page for details.
>
> gtkwave -v
> Gtk-Message: Failed to load module "canberra-gtk-module"
>
> GTKWave Analyzer v3.3.65 (w)1999-2015 BSI
>
> I am in the process of creating the recipes to install the above tools on
> the image.
> The process that I am using is found at
> https://github.com/develone/raspberrypi2_yocto.git
>
> I am using an AMD 6 core with 16 GB and takes about 2 hours to create the
> image.
>
> If you have any questions
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] success creating a recipe to install myhdl

[Edward V. <dev...@sb...>]

Hello All,Thanks to Ross Burton 
see the files https://github.com/develone/raspberrypi2_yocto.git
in recipe_myhdl folder.

Now have an rpm to install myhdl on a yocto build.
let me know if you have any questions.
 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

[myhdl-list] bitbake recipes to build myhdl, xstools, iverilog and gtkwave using Yocto

[Edward V. <dev...@sb...>]

Hi all,Dave the current verison of Xstools is 6.0.15?Current vesion of MyHDL is 1.0.0 is that correct?
My goal is create a Yocto image for the Raspberry Pi 2 B that provides the necessary tools to use MyHdl with Xstools, Iverilog & GTKwave.  The combo of RaspberryPi 2 B with a StickIt-MB & XulA2  would make a great low-cost development tool for developing and testing FPGAs.

I currently have a working core-image-sato that I can install myhdl using python setup.py develop instead of  python setup.py install.  I also can install Iverilog and GTKWave compiling from source on the target.  
 I can ssh to the Raspberry Pi 
 ssh -Y 192.168.1.136
root@192.168.1.136's password: 
root@raspberrypi2:~# python
Python 2.7.9 (default, Jul 26 2015, 21:01:54) 
[GCC 4.9.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> from myhdl import *
>>> 
I can also download my repo https://github.com/develone/jpeg-2000-test.git
Then cd into the jpeg-2000-test/ipython_fixbv.Where I can execute python test_jpegEnc.py.The above does a dwt on an image.cd myhdlgit log
commit 0f106505cbf4047e6a6641b451b817615d48772f
Merge: c7d92c4 443024f
Author: jandecaluwe <ja...@ja...>
Date:   Tue Jul 28 14:25:21 2015 +0200

    Merge pull request #116 from jck/signamevisitor
    
    prevent adding intbv to senslist of always_combcd iveriloggit log
commit d3bdc60201079eb22fe8506e951a57c95b19e28a
Author: Cary R <cy...@ya...>
Date:   Wed Jul 22 00:27:13 2015 -0700

    Correctly display events when dumping using the FST format
    
    This patch is from Tony Bybell and fixes a segmentation fault when dumping
    an event to a FST file.

iverilog -h
Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile]
                [-g1995|-g2001|-g2005] [-g<feature>]
                [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]
                [-N file] [-o filename] [-p flag=value]
                [-s topmodule] [-t target] [-T min|typ|max]
                [-W class] [-y dir] [-Y suf] source_file(s)

See the man page for details.

gtkwave -v
Gtk-Message: Failed to load module "canberra-gtk-module"

GTKWave Analyzer v3.3.65 (w)1999-2015 BSI

I am in the process of creating the recipes to install the above tools on the image.The process that I am using is found at https://github.com/develone/raspberrypi2_yocto.git

I am using an AMD 6 core with 16 GB and takes about 2 hours to create the image.
If you have any questions 
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Examples of using classes?

[Jeremy H. <jer...@gm...>]

Thanks, I'll take a look!
On Wed, 29 Jul 2015 at 10:18 am Christopher Felton <chr...@gm...>
wrote:

> On 7/28/15 5:50 PM, Jeremy Herbert wrote:
> > Hi Chris,
> >
> > I was thinking of using inheritance in defining interfaces using classes
> > like so:
> >
> > class FIFO(object):
> > ...
> >
> > class AXIFIFO(FIFO):
> > ...
> >
> > class WishboneFIFO(FIFO):
> > ...
> >
> > Or even mixins:
> >
> > class FIFO(object):
> > ...
> >
> > class AXI4SSlaveMixin(object):
> > ...
> >
> > class AXI4SMasterMixin(object):
> > ...
> >
> > class AXIFIFO(FIFO, AXI4SSlaveMixin, AXI4SMasterMixin):
> > ...
> >
> > Does this make sense? I'd basically like to be able to drop the
> > AXI4SSlaveMixin and replace it with WishboneSlaveMixin and have it "just
> > work".
>
> Yes, defining interfaces like this is great and you
> can attach transactors, adapters, etc.
>
> My approached would be to define the interfaces and
> still use a function (myhdl module/component):
>
>      def fifo(stream_in, stream_o):
>          inst_adapter_i = stream_i.adapter() # bus specific to generic
>          inst_adapter_o = stream_o.adapter() # ""
>
>          # add logic ....
>          @always_seq(stream_i.clock.posedge, ...)
>          def rtl_in():
>              if stream_i.valid:
>
>
>      stream_in = AXI4()  # instantiate the specifi bus
>      stream_out = AXI4() # instantiate the specific bus
>      inst_fifo = fifo(stream_in, stream_out)
>
> This is kinda like what I did here:
> https://github.com/cfelton/minnesota/tree/master/mn/system
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] myhdl installed on yocto RaspberryPi 2 B

[Edward V. <dev...@sb...>]

Hi All,I was able to get myhdl installed on Raspberry Pi 2 created with Yocto.See https://github.com/develone/raspberrypi2_yoctoNext I need the XSTOOLs and Iverilog
 Regards,
Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] Examples of using classes?

[Christopher F. <chr...@gm...>]

On 7/28/15 5:50 PM, Jeremy Herbert wrote:
> Hi Chris,
>
> I was thinking of using inheritance in defining interfaces using classes
> like so:
>
> class FIFO(object):
> ...
>
> class AXIFIFO(FIFO):
> ...
>
> class WishboneFIFO(FIFO):
> ...
>
> Or even mixins:
>
> class FIFO(object):
> ...
>
> class AXI4SSlaveMixin(object):
> ...
>
> class AXI4SMasterMixin(object):
> ...
>
> class AXIFIFO(FIFO, AXI4SSlaveMixin, AXI4SMasterMixin):
> ...
>
> Does this make sense? I'd basically like to be able to drop the
> AXI4SSlaveMixin and replace it with WishboneSlaveMixin and have it "just
> work".

Yes, defining interfaces like this is great and you
can attach transactors, adapters, etc.

My approached would be to define the interfaces and
still use a function (myhdl module/component):

     def fifo(stream_in, stream_o):
         inst_adapter_i = stream_i.adapter() # bus specific to generic
         inst_adapter_o = stream_o.adapter() # ""

         # add logic ....
         @always_seq(stream_i.clock.posedge, ...)
         def rtl_in():
             if stream_i.valid:


     stream_in = AXI4()  # instantiate the specifi bus
     stream_out = AXI4() # instantiate the specific bus
     inst_fifo = fifo(stream_in, stream_out)

This is kinda like what I did here:
https://github.com/cfelton/minnesota/tree/master/mn/system

Regards,
Chris

Re: [myhdl-list] Examples of using classes?

[Jeremy H. <jer...@gm...>]

Hi Chris,

I was thinking of using inheritance in defining interfaces using classes
like so:

class FIFO(object):
...

class AXIFIFO(FIFO):
...

class WishboneFIFO(FIFO):
...

Or even mixins:

class FIFO(object):
...

class AXI4SSlaveMixin(object):
...

class AXI4SMasterMixin(object):
...

class AXIFIFO(FIFO, AXI4SSlaveMixin, AXI4SMasterMixin):
...

Does this make sense? I'd basically like to be able to drop the
AXI4SSlaveMixin and replace it with WishboneSlaveMixin and have it "just
work".

Thanks,
Jeremy

On Tue, 28 Jul 2015 at 23:22 Christopher Felton <chr...@gm...>
wrote:

> On 7/28/2015 4:52 AM, Jeremy Herbert wrote:
> > Hi everyone,
> >
> > I'm currently playing with myhdl, and I was wondering if anyone has
> > examples on using python classes to describe logic? more specifically, I
> am
> > looking for examples of class inheritance being used.
> >
> > I have looked on the myhdl website and here:
> > https://github.com/jandecaluwe/myhdl-examples
> >
> > but everything seems to be defined by functions in functions rather than
> in
> > a class.
>
> This question pops up every once in awhile from new
> users.  I think most users don't use classes as the
> modules that contain the logic implementations.
> Classes are used for interfaces and objects that might
> have logic implementations (implemented in methods).
>
> You can use classes, you just need to provide the
> myhdl generators to the simulator and/or conversion
> tools.
>
> Can you elaborate how you want to use classes?  Its
> not clear to me how inheritance can help logic
> implementations.
>
>
> Regards,
> Chris
>
>
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Examples of using classes?

[Christopher F. <chr...@gm...>]

On 7/28/2015 4:52 AM, Jeremy Herbert wrote:
> Hi everyone,
>
> I'm currently playing with myhdl, and I was wondering if anyone has
> examples on using python classes to describe logic? more specifically, I am
> looking for examples of class inheritance being used.
>
> I have looked on the myhdl website and here:
> https://github.com/jandecaluwe/myhdl-examples
>
> but everything seems to be defined by functions in functions rather than in
> a class.

This question pops up every once in awhile from new
users.  I think most users don't use classes as the
modules that contain the logic implementations.
Classes are used for interfaces and objects that might
have logic implementations (implemented in methods).

You can use classes, you just need to provide the
myhdl generators to the simulator and/or conversion
tools.

Can you elaborate how you want to use classes?  Its
not clear to me how inheritance can help logic
implementations.


Regards,
Chris

[myhdl-list] Examples of using classes?

[Jeremy H. <jer...@gm...>]

Hi everyone,

I'm currently playing with myhdl, and I was wondering if anyone has
examples on using python classes to describe logic? more specifically, I am
looking for examples of class inheritance being used.

I have looked on the myhdl website and here:
https://github.com/jandecaluwe/myhdl-examples

but everything seems to be defined by functions in functions rather than in
a class.

Thanks,
Jeremy

Re: [myhdl-list] Installing on ccustom Linux System.

[Keerthan JC <jck...@gm...>]

Can you try installing python-pip and then 'pip install myhdl'?

On Sun, Jul 26, 2015 at 12:25 PM, Edward Vidal <dev...@sb...>
wrote:

> Hi All,
>
> I am Trying to install myhdl on a custom build of Linux on a Raspberry Pi
> 2 B
> which was created with Yocto.
>
> python setup.py install
> starts out okay.
>
> writing manifest file 'myhdl.egg-info/SOURCES.txt'
> installing library code to build/bdist.linux-armv7l/egg
> running install_lib
> running build_py
> creating build/lib
> creating build/lib/myhdl
> copying myhdl/_Signal.py -> build/lib/myhdl
> copying myhdl/_util.py -> build/lib/myhdl
> copying myhdl/_Cosimulation.py -> build/lib/myhdl
> copying myhdl/_compat.py -> build/lib/myhdl
> copying myhdl/_Waiter.py -> build/lib/myhdl
> copying myhdl/__init__.py -> build/lib/myhdl
> copying myhdl/_tristate.py -> build/lib/myhdl
> copying myhdl/_bin.py -> build/lib/myhdl
>     .
>          .
>     .
> many more lines
>     .
>     .
>     .
> copying build/lib/myhdl/_resolverefs.py ->
> build/bdist.linux-armv7l/egg/myhdl
> copying build/lib/myhdl/_resize.py -> build/bdist.linux-armv7l/egg/myhdl
> copying build/lib/myhdl/_ShadowSignal.py ->
> build/bdist.linux-armv7l/egg/myhdl
> copying build/lib/myhdl/_simulator.py -> build/bdist.linux-armv7l/egg/myhdl
> Traceback (most recent call last):
>   File "setup.py", line 60, in <module>
>     'Programming Language :: Python :: 3.4',
>   File "/usr/lib/python2.7/distutils/core.py", line 151, in setup
>     dist.run_commands()
>   File "/usr/lib/python2.7/distutils/dist.py", line 953, in run_commands
>     self.run_command(cmd)
>   File "/usr/lib/python2.7/distutils/dist.py", line 972, in run_command
>     cmd_obj.run()
>   File
> "/usr/lib/python2.7/site-packages/distribute-0.6.32-py2.7.egg/setuptools/command/install.py",
> line 73, in run
>     self.do_egg_install()
>   File
> "/usr/lib/python2.7/site-packages/distribute-0.6.32-py2.7.egg/setuptools/command/install.py",
> line 93, in do_egg_install
>     self.run_command('bdist_egg')
>   File "/usr/lib/python2.7/distutils/cmd.py", line 326, in run_command
>     self.distribution.run_command(command)
>   File "/usr/lib/python2.7/distutils/dist.py", line 972, in run_command
>     cmd_obj.run()
>   File
> "/usr/lib/python2.7/site-packages/distribute-0.6.32-py2.7.egg/setuptools/command/bdist_egg.py",
> line 179, in run
>     cmd = self.call_command('install_lib', warn_dir=0)
>   File
> "/usr/lib/python2.7/site-packages/distribute-0.6.32-py2.7.egg/setuptools/command/bdist_egg.py",
> line 166, in call_command
>     self.run_command(cmdname)
>   File "/usr/lib/python2.7/distutils/cmd.py", line 326, in run_command
>     self.distribution.run_command(command)
>   File "/usr/lib/python2.7/distutils/dist.py", line 972, in run_command
>     cmd_obj.run()
>   File
> "/usr/lib/python2.7/site-packages/distribute-0.6.32-py2.7.egg/setuptools/command/install_lib.py",
> line 24, in run
>     self.byte_compile(outfiles)
>   File "/usr/lib/python2.7/distutils/command/install_lib.py", line 138, in
> byte_compile
>     dry_run=self.dry_run)
>   File "/usr/lib/python2.7/distutils/util.py", line 437, in byte_compile
>     from py_compile import compile
> ImportError: No module named py_compile
> Thanks in advance.
>
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
>
> ------------------------------------------------------------------------------
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
have a nice day
-jck