myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] to_VHDL() conversion error: 'intbv' object has no attribute '__name__'

[David S. <dst...@kc...>]

I'm working on some toy problems from projecteuler.org to get a better handle on myHDL and have run into a problem converting to VHDL.

As far as I can tell, it's something to do with mysum, fib_r1, or fib_r2, but I can't figure out what aspect is a problem.  Before the wall of text that is the code and the error code, I have 2 questions: 1) what's the specific problem I'm running into here? 2) If I wasn't emailing this list, where is the right place for me to look for solutions to this problem?

Here's my code:

from myhdl import *

import unittest
from unittest import TestCase


def euler2(results, results_valid, n, clk, reset):
    """ implement a solution in hardware to https://projecteuler.net/problem=2 """

    even = Signal(bool())
    #mysum, fib_r1, fib_r2 = [Signal(intbv(1, 1, n*10)) for i in range(3)]
    mysum = Signal(intbv(1,1,40000000))
    fib_r1 = Signal(intbv(1,1,40000000))
    fib_r2 = Signal(intbv(1,1,40000000))
    results_int = Signal(intbv(0, 0, 5000000))

    @always_comb
    def a():
        even.next = True if mysum(0) == 0 else False
        results_valid.next = True if mysum >= n else False
     #   results_valid.next = results_int(0)
        results.next = results_int

    @always_comb
    def c():
        mysum.next = fib_r1 + fib_r2

    @always_seq(clk.posedge, reset)
    def b():
        fib_r1.next = mysum
        fib_r2.next = fib_r1
        if even:
            results_int.next = results_int + mysum
        #results_int.next = results_int + 1
    return a, b, c
    #return a, b

And here's the unit test:

class TestEuler2(TestCase):
    def setUp(self):
        self.reset = ResetSignal(0, active=1, async=True)
        self.results_valid, self.clk = [Signal(bool()) for i in range(2)]
        self.results = Signal(intbv(0, 0, 5000000))
        self.clk_inst = self.run_clk(self.clk)

    def run_clk(self, clk):
        half_period = delay(10)

        @always(half_period)
        def clkgen():
            clk.next = not clk

        return clkgen

    def euler2_py(self, n):
        f1 = 1
        f2 = 1
        mysum = 0
        print " "
        while (f1 + f2) < n:
            mysum = mysum + f1 + f2
            f1, f2 = f1 + (2 * f2), (2 * f1) + (3 * f2)
        return mysum

    def checkResult(self, i, results, results_valid, clk, reset):
        reset.next = 1
        yield clk.negedge
        reset.next = 0
        while 1:
            yield clk.negedge
            if results_valid:
                self.assertEqual(results, self.euler2_py(i),
                                 "does " + str(results) + " == " + str(self.euler2_py(i)) + " for i == " + str(i))
                raise StopSimulation

    def test100(self):
        i = 100
        dut = traceSignals(euler2, self.results, self.results_valid, i, self.clk, self.reset)
        check = self.checkResult(i, self.results, self.results_valid, self.clk, self.reset)
        Simulation(dut, check, self.clk_inst).run(300000)
        euler_inst = toVHDL(euler2, self.results, self.results_valid, i, self.clk, self.reset)

    def test10000(self):
        i = 10000
        dut = euler2(self.results, self.results_valid, i, self.clk, self.reset)
        check = self.checkResult(i, self.results, self.results_valid, self.clk, self.reset)
        Simulation(dut, check, self.clk_inst).run(300000)

    def test4000000(self):
        i = 4000000
        dut = euler2(self.results, self.results_valid, i, self.clk, self.reset)
        check = self.checkResult(i, self.results, self.results_valid, self.clk, self.reset)
        Simulation(dut, check, self.clk_inst).run(300000)
        #euler_inst = toVHDL(euler2, self.results, self.results_valid, 4000000, self.clk, self.reset)



unittest.main()

And here's the run:

$ python euler2.py


E

.

.
======================================================================
ERROR: test100 (__main__.TestEuler2)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "euler2.py", line 81, in test100
    euler_inst = toVHDL(euler2, self.results, self.results_valid, 100, self.clk, self.reset)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 203, in __call__
    _convertGens(genlist, siglist, memlist, vfile)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 461, in _convertGens
    v.visit(tree)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1224, in visit_Module
    self.visit(stmt)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1631, in visit_FunctionDef
    self.visit_stmt(node.body)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1432, in visit_stmt
    self.visit(stmt)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 872, in visit_Assign
    self.visit(rhs)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1073, in visit_IfExp
    self.visit(node.test)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 1012, in visit_Compare
    self.visit(node.left)
  File "/usr/lib/python2.7/ast.py", line 241, in visit
    return visitor(node)
  File "/usr/lib/python2.7/site-packages/myhdl/conversion/_toVHDL.py", line 981, in visit_Call
    self.write(f.__name__)
  File "/usr/lib/python2.7/site-packages/myhdl/_Signal.py", line 494, in __getattr__
    return getattr(self._val, attr)
AttributeError: 'intbv' object has no attribute '__name__'

----------------------------------------------------------------------
Ran 3 tests in 0.282s

FAILED (errors=1)
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[myhdl-list] Tristate top-level ports, (was Hello World)

[Christopher F. <chr...@gm...>]

<snip>
>
> I submitted a Pull Request to fix that bug.

Josy,

Do you know which PR this was?

Regards,
Chris

> One observation: in your code you are actually using a TriState pin to
> drive.read the I2C_SDAT. In reality the SDa pin in the I2C is an
> opendrain, with a pull-up in the circuit. So you can only drive it *low*
> and keep it tristated otherwise.
>
> Regards,
>
> Josy

Re: [myhdl-list] Interfaces in hierarchcal way

[Martin S. <ha...@se...>]

Hi guys,

> 
> We already talked about that, and yes you can't create parametrizable 
> systems with Qsys.
> ...
> I have been contemplating on abandoning Qsys, but then I need a good 
> alternative for connecting those master and slave interfaces together.
> 

Having a deja vu here...
I've found all the SOPC/Qsys and their Xilinx/Lattice counterparts not
really friendly for maintenance, so I've ended up with an approach based
on GNU make, kconfig (linux kernel config) and an XML device description
(called DClib/devdesc). Like IP-XACT, but way less complex. Could be
enhanced to spit out MyHDL (currently, it can only generate VHDL based
Wishbone-capable SoCs). There's also a graphical tool called "kactus2",
but I haven't looked at it in detail.
The XML approach turned out to be quite robust and future compatible,
unlike the known migration nightmares that make you freeze old software
versions in a VM...

Once hierarchy can be maintained in MyHDL, this might become very
interesting, due to a vast amount of powerful XML processing tools in
the Python domain.

Greetings,

- Martin

Re: [myhdl-list] Interfaces in hierarchcal way

[Josy B. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:


> I don't know, I really dislike Qsys and the whole
> approach.  It is impossible to create flexible and
> modular systems.
> 
> And yes you might be missing something (or I am :).
> I think in this case an AXI subsystem was created
> in myhdl and is being converted to Verilog and
> integrated with more Verilog presumably (?).
> 
> Regards,
> Chris
> 

We already talked about that, and yes you can't create parametrizable 
systems with Qsys.
But I'm not sure that bespoke AXI subsystems are that flexible either. 
And connecting them all up in an hierarchical way can be tedious. I have 
only used Avalon MM interfaces and am quite OK with wiring them in Qsys, 
but then our Qsys projects are very 'fixed'. 
I have been contemplating on abandoning Qsys, but then I need a good 
alternative for connecting those master and slave interfaces together.

I have been working on a Xilinx project (consulting for) and was 
impressed by the overhead of building such an AXI system manually.

Now I was just curious, and I had hoped that Jos Huysken enlightened me 
:)


Regards,

Josy

Re: [myhdl-list] Interfaces in hierarchcal way

[Christopher F. <chr...@gm...>]

On 7/7/2015 3:01 PM, Josy Boelen wrote:
> Jos Huisken <jos.huisken <at> gmail.com> writes:
>
>
>> I was trying to create an AXI subsystem for Altera Cyclone V boards...
>>
>
> Excuse me for barging in, but if you are using Altera components, wouldn't
> it be easier to use Qsys to connect all those AXI (and other) components?
> Or am I missing something?
>

I don't know, I really dislike Qsys and the whole
approach.  It is impossible to create flexible and
modular systems.

And yes you might be missing something (or I am :).
I think in this case an AXI subsystem was created
in myhdl and is being converted to Verilog and
integrated with more Verilog presumably (?).

Regards,
Chris

Re: [myhdl-list] Interfaces in hierarchcal way

[Christopher F. <chr...@gm...>]

On 7/6/2015 12:51 PM, Keerthan JC wrote:
> This is a known limitation:
> https://github.com/jandecaluwe/myhdl/blob/master/myhdl/conversion/_analyze.py#L1255
>
> I will add that to the docs. I'm currently working on a major restructuring
> of the conversion code. This will most likely be fixed in the next major
> release (0.10/1.0)

I think there are some other small issues as
well.  I have seen cases when single-level
interface port names are not maintained.

Meaning that the interface port name was
replaced with another identifier - assume an
artifact of the design being flattened.  The
expanded port names, in this case, seem to
be random.

Regards,
Chris

Re: [myhdl-list] Interfaces in hierarchcal way

[Josy B. <jos...@gm...>]

Jos Huisken <jos.huisken <at> gmail.com> writes:


> I was trying to create an AXI subsystem for Altera Cyclone V boards... 
> 

Excuse me for barging in, but if you are using Altera components, wouldn't 
it be easier to use Qsys to connect all those AXI (and other) components? 
Or am I missing something?

Regards,

Josy

Re: [myhdl-list] Interfaces in hierarchcal way

[Jos H. <jos...@gm...>]

Keerthan JC <jckeerthan <at> gmail.com> writes:

> 
> This is a known limitation:
> This will most likely be fixed in the
next major release (0.10/1.0)
> 

Hi JC,

Thanks for pointing out, I'll wait for it! ;-)
The work-around I just tried is quite clumsy, using conversion functions
(and taking care that signal assignments go in the correct direction).
So, as soon as you have something: I'm very much interested.
I was trying to create an AXI subsystem for Altera Cyclone V boards... 

Regards,
Jos

Re: [myhdl-list] MyHDL websites moved to GitHub

[Keerthan JC <jck...@gm...>]

Additionally, the old URL is automatically redirected to the new one!

On Mon, Jul 6, 2015 at 3:38 PM, André Prado <and...@gm...> wrote:

> Really good idea :)
>
> On Mon, Jul 6, 2015 at 8:35 PM, Keerthan JC <jck...@gm...> wrote:
>
>> Jan,
>>
>> For future reference, github has a mechanism to transfer repositories.
>> This preserves issues, forks and stars.
>> https://help.github.com/articles/transferring-a-repository/
>>
>> On Sun, Jun 21, 2015 at 9:16 AM, Jan Decaluwe <ja...@ja...>
>> wrote:
>>
>>> To streamline things, I have now also migrated the MyHDL
>>> websites myhdl.org and dev.myhdl.org to GitHub & git.
>>>
>>> To make things more representative and easier for access
>>> management, I have created the "myhdl" organization and a
>>> "documentation team". I have invited those that I found
>>> on bitbucket (except Jan Coombs, whose GitHub account was
>>> not found.)
>>>
>>> If you would like to contribute to the websites, let
>>> me know. Remember, it is just a question of writing markdown,
>>> running Urubu, and pushing to a git repo, the website is
>>> adapted based on that every few minutes.
>>>
>>>      https://github.com/myhdl
>>>
>>> --
>>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>>      Python as a HDL: http://www.myhdl.org
>>>      VHDL development, the modern way: http://www.sigasi.com
>>>      World-class digital design: http://www.easics.com
>>>
>>>
>>>
>>> ------------------------------------------------------------------------------
>>> _______________________________________________
>>> myhdl-list mailing list
>>> myh...@li...
>>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>>
>>
>>
>>
>> --
>> have a nice day
>> -jck
>>
>>
>> ------------------------------------------------------------------------------
>> Don't Limit Your Business. Reach for the Cloud.
>> GigeNET's Cloud Solutions provide you with the tools and support that
>> you need to offload your IT needs and focus on growing your business.
>> Configured For All Businesses. Start Your Cloud Today.
>> https://www.gigenetcloud.com/
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
> --
> Atenciosamente/Regards
> André Castelan Prado
>
>
> ------------------------------------------------------------------------------
> Don't Limit Your Business. Reach for the Cloud.
> GigeNET's Cloud Solutions provide you with the tools and support that
> you need to offload your IT needs and focus on growing your business.
> Configured For All Businesses. Start Your Cloud Today.
> https://www.gigenetcloud.com/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
have a nice day
-jck

Re: [myhdl-list] MyHDL websites moved to GitHub

[André P. <and...@gm...>]

Really good idea :)

On Mon, Jul 6, 2015 at 8:35 PM, Keerthan JC <jck...@gm...> wrote:

> Jan,
>
> For future reference, github has a mechanism to transfer repositories.
> This preserves issues, forks and stars.
> https://help.github.com/articles/transferring-a-repository/
>
> On Sun, Jun 21, 2015 at 9:16 AM, Jan Decaluwe <ja...@ja...> wrote:
>
>> To streamline things, I have now also migrated the MyHDL
>> websites myhdl.org and dev.myhdl.org to GitHub & git.
>>
>> To make things more representative and easier for access
>> management, I have created the "myhdl" organization and a
>> "documentation team". I have invited those that I found
>> on bitbucket (except Jan Coombs, whose GitHub account was
>> not found.)
>>
>> If you would like to contribute to the websites, let
>> me know. Remember, it is just a question of writing markdown,
>> running Urubu, and pushing to a git repo, the website is
>> adapted based on that every few minutes.
>>
>>      https://github.com/myhdl
>>
>> --
>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>      Python as a HDL: http://www.myhdl.org
>>      VHDL development, the modern way: http://www.sigasi.com
>>      World-class digital design: http://www.easics.com
>>
>>
>>
>> ------------------------------------------------------------------------------
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> have a nice day
> -jck
>
>
> ------------------------------------------------------------------------------
> Don't Limit Your Business. Reach for the Cloud.
> GigeNET's Cloud Solutions provide you with the tools and support that
> you need to offload your IT needs and focus on growing your business.
> Configured For All Businesses. Start Your Cloud Today.
> https://www.gigenetcloud.com/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>


-- 
Atenciosamente/Regards
André Castelan Prado

Re: [myhdl-list] MyHDL websites moved to GitHub

[Keerthan JC <jck...@gm...>]

Jan,

For future reference, github has a mechanism to transfer repositories. This
preserves issues, forks and stars.
https://help.github.com/articles/transferring-a-repository/

On Sun, Jun 21, 2015 at 9:16 AM, Jan Decaluwe <ja...@ja...> wrote:

> To streamline things, I have now also migrated the MyHDL
> websites myhdl.org and dev.myhdl.org to GitHub & git.
>
> To make things more representative and easier for access
> management, I have created the "myhdl" organization and a
> "documentation team". I have invited those that I found
> on bitbucket (except Jan Coombs, whose GitHub account was
> not found.)
>
> If you would like to contribute to the websites, let
> me know. Remember, it is just a question of writing markdown,
> running Urubu, and pushing to a git repo, the website is
> adapted based on that every few minutes.
>
>      https://github.com/myhdl
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>      Python as a HDL: http://www.myhdl.org
>      VHDL development, the modern way: http://www.sigasi.com
>      World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] Interfaces in hierarchcal way

[Keerthan JC <jck...@gm...>]

This is a known limitation:
https://github.com/jandecaluwe/myhdl/blob/master/myhdl/conversion/_analyze.py#L1255

I will add that to the docs. I'm currently working on a major restructuring
of the conversion code. This will most likely be fixed in the next major
release (0.10/1.0)

On Mon, Jul 6, 2015 at 10:31 AM, Christopher Felton <chr...@gm...>
wrote:

> <snip>
> >
> > Hi Chris,
> >
> > I was looking at the interface of the verilog modules, not at the body.
> > For axi4s_reg the generated verilog gives:
> > --
> > module axi4s_reg (
> >      clk,
> >      rst,
> >      ai_valid,
> >      ai_data,
> >      ai_accept,
> >      ao_valid,
> >      ao_data,
> >      ao_accept
> > );
> > --
> > For axi4_lite_reg the verilog start with:
> > --
> > module axi4_lite_reg (
> >      clk,
> >      rst
> > );
> > --
> > So all other ports (defined in a hierarchical interface) are gone... I
> was
> > expecting something like:
> > --
> > module axi4_lite_reg (
> >      clk,
> >      rst,
> >      aw_ai_valid,
> >      aw_ai_data,
> >      aw_ai_accept,
> >      aw_ao_valid,
> >      aw_ao_data,
> >      aw_ao_accept,
> > ...
> >      w_ai_valid,
> >      w_ai_data,
> >      w_ai_accept,
> > ...
> > );
> > --
> >
> > Or am I missing something? I expect all signals are used...
> >
>
> Sorry for the confusion, yes the ports should exist.
>
> Not sure what happened here?  I looks likes, as you
> suspected, with the hierarchical interfaces there
> is a top-level port conversion bug.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
> Don't Limit Your Business. Reach for the Cloud.
> GigeNET's Cloud Solutions provide you with the tools and support that
> you need to offload your IT needs and focus on growing your business.
> Configured For All Businesses. Start Your Cloud Today.
> https://www.gigenetcloud.com/
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
have a nice day
-jck

Re: [myhdl-list] Interfaces in hierarchcal way

[Christopher F. <chr...@gm...>]

<snip>
>
> Hi Chris,
>
> I was looking at the interface of the verilog modules, not at the body.
> For axi4s_reg the generated verilog gives:
> --
> module axi4s_reg (
>      clk,
>      rst,
>      ai_valid,
>      ai_data,
>      ai_accept,
>      ao_valid,
>      ao_data,
>      ao_accept
> );
> --
> For axi4_lite_reg the verilog start with:
> --
> module axi4_lite_reg (
>      clk,
>      rst
> );
> --
> So all other ports (defined in a hierarchical interface) are gone... I was
> expecting something like:
> --
> module axi4_lite_reg (
>      clk,
>      rst,
>      aw_ai_valid,
>      aw_ai_data,
>      aw_ai_accept,
>      aw_ao_valid,
>      aw_ao_data,
>      aw_ao_accept,
> ...
>      w_ai_valid,
>      w_ai_data,
>      w_ai_accept,
> ...
> );
> --
>
> Or am I missing something? I expect all signals are used...
>

Sorry for the confusion, yes the ports should exist.

Not sure what happened here?  I looks likes, as you
suspected, with the hierarchical interfaces there
is a top-level port conversion bug.

Regards,
Chris

Re: [myhdl-list] Interfaces in hierarchcal way

[Jos H. <jos...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:
> 
> On 7/6/2015 6:38 AM, Jos Huisken wrote:
> > Hi
> >
> > Suppose we have an AXI4 streamig interface:
> <snip>
> >
> > While trying verilog generation all interface signals disappear.
> 
> Jos,
> 
> When I convert the example you provided the signals
> that are used are preserved the signals that are
> not driven are not converted to the target HDL.
> 
> Example, the first ` <at> always_comb` is converted to:
> 
>      assign ai_accept = ((ao_accept && ao_valid) || accept);
> 
> This is for the first conversion, the second conversion
> converts to:
> 
>      assign aw_ai_accept = ((aw_ao_accept && aw_ao_valid) || aw_accept);
> 
> Both these look correct.  I don't see which *used* signals
> are not being converted?
> 
> Regards,
> Chris
> 

Hi Chris,

I was looking at the interface of the verilog modules, not at the body.
For axi4s_reg the generated verilog gives:
--
module axi4s_reg (
    clk,
    rst,
    ai_valid,
    ai_data,
    ai_accept,
    ao_valid,
    ao_data,
    ao_accept
);
--
For axi4_lite_reg the verilog start with:
--
module axi4_lite_reg (
    clk,
    rst
);
--
So all other ports (defined in a hierarchical interface) are gone... I was
expecting something like:
--
module axi4_lite_reg (
    clk,
    rst,
    aw_ai_valid,
    aw_ai_data,
    aw_ai_accept,
    aw_ao_valid,
    aw_ao_data,
    aw_ao_accept,
...
    w_ai_valid,
    w_ai_data,
    w_ai_accept,
...
);
--

Or am I missing something? I expect all signals are used...

Best regards,
Jos

Re: [myhdl-list] Interfaces in hierarchcal way

[Christopher F. <chr...@gm...>]

On 7/6/2015 6:38 AM, Jos Huisken wrote:
> Hi
>
> Suppose we have an AXI4 streamig interface:
<snip>
>
> While trying verilog generation all interface signals disappear.

Jos,

When I convert the example you provided the signals
that are used are preserved the signals that are
not driven are not converted to the target HDL.

Example, the first `@always_comb` is converted to:

     assign ai_accept = ((ao_accept && ao_valid) || accept);


This is for the first conversion, the second conversion
converts to:

     assign aw_ai_accept = ((aw_ao_accept && aw_ao_valid) || aw_accept);

Both these look correct.  I don't see which *used* signals
are not being converted?

Regards,
Chris

[myhdl-list] Interfaces in hierarchcal way

[Jos H. <jos...@gm...>]

Hi

Suppose we have an AXI4 streamig interface:

class AXI4S:
    '''Interface for AXI4 Streaming protocol
    '''
    def __init__(self, wd = 32):
        self.valid  = Signal(False)
        self.data   = Signal(intbv(0xe5)[wd:])
        self.accept = Signal(True)

Could we define an AXI4_lite interface like?:
--
class AXI4_lite:
    '''Interface for AXI4 Lite protocol, consisting of 5 AXI Stream Channels
    '''
    def __init__(self, wa = 32, wd = 32, wr = 8):
        self.aw = AXI4S(wa)
        self.w  = AXI4S(wd)
        self.ar = AXI4S(wa)
        self.r  = AXI4S(wd)
        self.b  = AXI4S(wr)
--
In fact we obtain the 5 transport channels of an AXI4_lite protocol.


While trying verilog generation all interface signals disappear.
You can try verilog generation for:
--
def axi4s_reg(clk, rst, ai, ao):
    ''' AXI4-Stream register. Not verified.
    '''

    accept = Signal(bool(1))

    @always_comb
    def acc():
        ai.accept.next = (ao.accept and ao.valid) or \
                         accept

    @always_seq(clk.posedge, rst)
    def reg():
        xi = ai.accept and ai.valid
        xo = ao.accept and ao.valid
        if xi:
            ao.data.next = ai.data
        ao.valid.next = xi or (ao.valid and not ao.accept)
        accept.next = (ai.accept and not ai.valid) # or not xi

    return reg, acc
--
for which verilog generation seems OK and:
--
def axi4_lite_reg(clk, rst, ai, ao):
    ''' Pipeline register on each channel
    '''

    # Master -> slave communication
    aw = axi4s_reg(clk, rst, ai.aw, ao.aw)
    w  = axi4s_reg(clk, rst, ai.w,  ao.w)
    ar = axi4s_reg(clk, rst, ai.ar, ao.ar)

    # Slave -> master communication
    r  = axi4s_reg(clk, rst, ao.r, ai.r)
    b  = axi4s_reg(clk, rst, ao.b, ai.b)

    return aw, w, ar, r, b


if __name__ == "__main__":
    clk = Signal(False)
    rst = ResetSignal(0, active=0, async=True)
    ai = AXI4S()
    ao = AXI4S()
    toVerilog(axi4s_reg, clk, rst, ai, ao)
    ai = AXI4_lite()
    ao = AXI4_lite()
    toVerilog(axi4_lite_reg, clk, rst, ai, ao)
--

Thanks,
Jos

Re: [myhdl-list] Beginner Question: Loop Unrolling & Use of Tuple Elements

[Christopher F. <chr...@gm...>]

On 6/28/2015 6:51 PM, co...@ne... wrote:
> Hello,
>
> Things are well! Not sure if you'll be back at ESC-SV, but if so will buy
> you a beer or three for the helpful response there ;-)

I will not make it to ESC-SV this year (or any of
the ESC bonanzas).

>
> Those answers solve my problems, so am back on track. Am planning on having
> a small write-up for Circuit Cellar on MyHDL, just replicating the simple
> FIR demo I did before. Of course the MyHDL version is nicer since it can use
> scipy to generate the coefficients and compare results...

Sounds fun, let us know if you have any other
questions or issues.  Also, let us know when it is
published.

Regards,
Chris

Re: [myhdl-list] Beginner Question: Loop Unrolling & Use of Tuple Elements

[<co...@ne...>]

Hello,

Things are well! Not sure if you'll be back at ESC-SV, but if so will buy
you a beer or three for the helpful response there ;-)

Those answers solve my problems, so am back on track. Am planning on having
a small write-up for Circuit Cellar on MyHDL, just replicating the simple
FIR demo I did before. Of course the MyHDL version is nicer since it can use
scipy to generate the coefficients and compare results...

Warm Regards,

  -Colin O'Flynn

-----Original Message-----
From: Christopher Felton [mailto:chr...@gm...] 
Sent: June-28-15 4:32 PM
To: myh...@li...
Subject: Re: [myhdl-list] Beginner Question: Loop Unrolling & Use of Tuple
Elements

Hey Collin, how are things going?

On 6/28/15 12:59 PM, co...@ne... wrote:
> Hello,
>
> I was attempting to make a simple FIR filter to compare MyHDL to 
> previous work I'd done using Vivado C-based HLS. I'm basing this 
> entirely on Christopher Felton's IIR example from 
> https://bitbucket.org/cfelton/examples/src/tip/siir/siir.py .
>
> Two things have tripped me up, and I'm not sure if it's some 
> limitation of MyHDL or my own failures? The first is as part of the 
> FIR I'd like to have a line like this:
>
> @always(clk.posedge)
> def rtl_fir():
>     for i in range(0, len(B-1)):
>        ffd[i+1].next = ffd[i]
>        ffd[i].next = x
>
> But I can't seem to find references to loop unrolling anywhere? There 
> was a few threads from ~2008 was all I saw. Instead I end up having to 
> do something like this:

The MyHDL converter will not un-roll the loops (currently).  The loops will
be converted as loops to the target HDL - where they will be un-rolled by
the synthesizer.

This post:
http://www.fpgarelated.com/showarticle/631.php

shows a "naive" (non-target-optimized) FIR implementation using loops.

<snip>
> The second problem is for the accumulator (which again I'm manually 
> unrolling), the most straight-forward definition to me would look like
this:
>
> @always_comb
>      def rtl_acc():
>          # Double precision accumulator
>          yacc.next = B[0]*ffd[0] + B[1]*ffd[1] + B[2]*ffd[2] + 
> B[3]*ffd[3] + B[4]*ffd[4]

I think the above link will help here as well, when you create a tuple of
ints, it is converted as a ROM [1], what you need to do is:

     def rtl_acc():
         for ii in range(4):
             btmp = B[ii]
             yacc.next = btmp + fdd[ii]


Hope that helps,
Chris

[1]
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#rom-inferenc
e


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Re: [myhdl-list] code snips look odd in new website

[Christopher F. <chr...@gm...>]

On 6/28/15 2:33 PM, Christopher Felton wrote:
> Hey Stephane hope all is well!
>
> In the past I embedded by code snips by using the
> bitbucked embedded function (easier to maintain
> and automatically update).
>
> Now the snips look awkward?  See:
> http://www.fpgarelated.com/showarticle/631.php
>
> Do you know why this might be?
>
> Regards,
> Chris
>

Well obviously this went to the incorrect destination!

[myhdl-list] code snips look odd in new website

[Christopher F. <chr...@gm...>]

Hey Stephane hope all is well!

In the past I embedded by code snips by using the
bitbucked embedded function (easier to maintain
and automatically update).

Now the snips look awkward?  See:
http://www.fpgarelated.com/showarticle/631.php

Do you know why this might be?

Regards,
Chris

Re: [myhdl-list] Beginner Question: Loop Unrolling & Use of Tuple Elements

[Christopher F. <chr...@gm...>]

Hey Collin, how are things going?

On 6/28/15 12:59 PM, co...@ne... wrote:
> Hello,
>
> I was attempting to make a simple FIR filter to compare MyHDL to previous
> work I'd done using Vivado C-based HLS. I'm basing this entirely on
> Christopher Felton's IIR example from
> https://bitbucket.org/cfelton/examples/src/tip/siir/siir.py .
>
> Two things have tripped me up, and I'm not sure if it's some limitation of
> MyHDL or my own failures? The first is as part of the FIR I'd like to have a
> line like this:
>
> @always(clk.posedge)
> def rtl_fir():
>     for i in range(0, len(B-1)):
>        ffd[i+1].next = ffd[i]
>        ffd[i].next = x
>
> But I can't seem to find references to loop unrolling anywhere? There was a
> few threads from ~2008 was all I saw. Instead I end up having to do
> something like this:

The MyHDL converter will not un-roll the loops
(currently).  The loops will be converted as loops
to the target HDL - where they will be un-rolled
by the synthesizer.

This post:
http://www.fpgarelated.com/showarticle/631.php

shows a "naive" (non-target-optimized) FIR
implementation using loops.

<snip>
> The second problem is for the accumulator (which again I'm manually
> unrolling), the most straight-forward definition to me would look like this:
>
> @always_comb
>      def rtl_acc():
>          # Double precision accumulator
>          yacc.next = B[0]*ffd[0] + B[1]*ffd[1] + B[2]*ffd[2] + B[3]*ffd[3] +
> B[4]*ffd[4]

I think the above link will help here as well,
when you create a tuple of ints, it is converted
as a ROM [1], what you need to do is:

     def rtl_acc():
         for ii in range(4):
             btmp = B[ii]
             yacc.next = btmp + fdd[ii]


Hope that helps,
Chris

[1] 
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#rom-inference

[myhdl-list] Beginner Question: Loop Unrolling & Use of Tuple Elements

[<co...@ne...>]

Hello,

I was attempting to make a simple FIR filter to compare MyHDL to previous
work I'd done using Vivado C-based HLS. I'm basing this entirely on
Christopher Felton's IIR example from
https://bitbucket.org/cfelton/examples/src/tip/siir/siir.py . 

Two things have tripped me up, and I'm not sure if it's some limitation of
MyHDL or my own failures? The first is as part of the FIR I'd like to have a
line like this:

@always(clk.posedge)
def rtl_fir():
   for i in range(0, len(B-1)):
      ffd[i+1].next = ffd[i]
      ffd[i].next = x

But I can't seem to find references to loop unrolling anywhere? There was a
few threads from ~2008 was all I saw. Instead I end up having to do
something like this:

@always(clk.posedge)
    def rtl_fir():
        ffd[4].next = ffd[3]
        ffd[3].next = ffd[2]
        ffd[2].next = ffd[1]
        ffd[1].next = ffd[0]
        ffd[0].next = x

Which I could have another chunk of python auto-generate, but seems silly.
Is there some loop unrolling mechanism I'm missing?

The second problem is for the accumulator (which again I'm manually
unrolling), the most straight-forward definition to me would look like this:

@always_comb
    def rtl_acc():        
        # Double precision accumulator
        yacc.next = B[0]*ffd[0] + B[1]*ffd[1] + B[2]*ffd[2] + B[3]*ffd[3] +
B[4]*ffd[4]

As get an error about use of tuples. Instead I've got to assign each element
(which is an int() type) to another variable and use that:

    b0 = B[0]
    b1 = B[1]
    b2 = B[2]
    b3 = B[3]
    b4 = B[4]

    @always_comb
    def rtl_acc():        
        # Double precision accumulator
        yacc.next = b0*ffd[0] + b1*ffd[1] + b2*ffd[2] + b3*ffd[3] +
b4*ffd[4]

The full code is at http://pastebin.com/E2i16whb (which again is just a
hacked version of Christopher's code that does FIR instead, I didn't finish
changing some of the names).

Is this something I'm doing incorrectly which stops me from using MyHDL in
such a manner?

Thanks,

  -Colin O'Flynn

[myhdl-list] MyHDL websites moved to GitHub

[Jan D. <ja...@ja...>]

To streamline things, I have now also migrated the MyHDL
websites myhdl.org and dev.myhdl.org to GitHub & git.

To make things more representative and easier for access
management, I have created the "myhdl" organization and a
"documentation team". I have invited those that I found
on bitbucket (except Jan Coombs, whose GitHub account was
not found.)

If you would like to contribute to the websites, let
me know. Remember, it is just a question of writing markdown,
running Urubu, and pushing to a git repo, the website is
adapted based on that every few minutes.

     https://github.com/myhdl

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

[myhdl-list] testing cosimulation & test_axis_fifo

[Edward V. <dev...@sb...>]

All,
I started working with the XESS StickIt!-MB which connects a XuLA2 with a Raspberry Pi.
I am using a Raspberry  2 B which is a quad core arm with 1 GB at 900 Mhz.

The software I have working is matplotlib, XSTOOLs, MyHDL, Icarus Verilog, LibreOffice, GTKWAVE and RPi-GPIO.

This combo appears to be good developement platform for beginners like myself
I believe that I will need the axi bfm for the pi to send and receive data with the FPGA XulA2.

Let me know if you have any questions.
Regards

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

OK.  So I've had a look at the Interface class I have in pyvivado to see
how it could be cleaned up.

Constructor is defined at
https://github.com/benreynwar/pyvivado/blob/91449e67330a053d5089aa4ba10c625cb43efb87/interface.py#L21

I think a bunch of crap could be removed to simplify it.  The important
parts are:

Interface Object
---------------------
wires - A list of wire objects.
name - The name of the module
generic_parameters - Parameters that define module (e.g. generic in VHDL)

Wire Object
----------------
name - Name of the wire
direction - Input or Output
signal_type - A signal type object

SignalType Object
------------------------
Responsible for conversion to and from bit arrays.
Responsible for conversion to and from python objects.
Responsible for generating appropriate signal definitions in VHDL or
Verilog and specifying any package dependencies for the type definition.

The interface and wire objects could just be represented as python
dictionaries since they're so simple.
The signal type object would need to be more complex.  Possibly an object
that would work here already exists in MyHDL.

Is that the kind of direction you were thinking?

I'm not sure what you're referring to with the 'use_std_logic' flag in the
previous email.

On Sun, Jun 14, 2015 at 2:01 AM, Henry Gomersall <he...@ca...> wrote:

> On 14/06/15 06:32, Ben Reynwar wrote:
> > You should be able to take advantage of pyvivado Vivado stuff just by
> > using the `pyvivado.project` module.  You could just use that along
> > with all the V* files that you generated using Veriutils.  The main
> > speedup you get is that the project only gets regenerated if the files
> > have changed, which doesn't make much difference during development
> > but is a big plus when you're running unit tests later.  Still
> > annoyingly slow though!
> >
>
> Yeah, it is crap. There is a huge overhead in doing anything in Vivado -
> all my tests are creating new instances which takes ~7 seconds or so
>
> > If I understand your comments on wrapper generation, you're suggesting
> > something similar to what I'm doing with the interface functions but
> > more formalized.  I could then use that same definition to generate
> > VHDL wrappers or a MyHDL wrapper. Is that correct?
>
> Yeah exactly. Some sort of simple interface language/definition from
> which interface wrappers can be generated. Certainly, it's a common
> problem in myhdl that is in need of a neat solution.
>
> That said, what does the new use_std_logic flag do? Is that per-module?
>
> Cheers,
>
> Henry
>
>
> ------------------------------------------------------------------------------
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> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>