myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Constant assignments in co-simulation

[Nikolay K. <nik...@gm...>]

Thanks Chris!

I don't think that preserving the combinatorial assignment is my issue,
because the module I have:


def const_assign(aBit, aByte):

    b = Signal(bool(True)) # to avoid "myhdl.AlwaysCombError:
sensitivity list is empty"

    @always_comb
    def logic():
        aBit.next = b
        aByte.next = 0x55

    return logic


Simulates as expected in MyHDL.

Converts to Vorilog as :

module const_assign (
    aBit,
    aByte
);
output aBit;
wire aBit;
output [7:0] aByte;
wire [7:0] aByte;
wire b;
assign b = 1;
assign aBit = b;
assign aByte = 85;

endmodule


Which to me looks OK.

My problem comes when I do co-simulation with Icarus. Then instead of
observing the expected aBit==True and aByte==0x55, I observe aBit==False
and aByte==0, which are the default values of the MyHDL signals connected
co-simulated module.


The problem disappears when I add a dummy print statement in the
"always_comb":

def const_assign(aBit, aByte):

    b = Signal(bool(True)) # to avoid "myhdl.AlwaysCombError:
sensitivity list is empty"

    @always_comb
    def logic():
        aBit.next = b
        aByte.next = 0x55
        print "something"

    return logic


Then the code converts to:

module const_assign (
    aBit,
    aByte
);
output aBit;
reg aBit;
output [7:0] aByte;
reg [7:0] aByte;
wire b;
assign b = 1;

always @(b) begin: CONST_ASSIGN_LOGIC
    aBit = b;
    aByte = 85;
    $write("something");
    $write("\n");
end

endmodule


And in co-simulation I see what I expect: aBit==True and aByte==0x55


It seam to me that the problem I have is related to the interface between
myhdl and icarus and a verilog statement of the type:

assign output_port = some_constant


I am not sure whether this is an issue with my local setup or it is a myhdl
issue. So to check that, can someone using Icarus, please, try to run on
his machine the gist given earlier. It should be only a matter of single
copy/paste and adjusting the path to myhdl.vpi


Regards,

Nikolay


Nikolay Kavaldjiev

E-mail: nik...@gm...
Mobile: +31 641 820 815
Address: Hogewerf 133, 1082NC, Amsterdam, Netherlands
LinkedIn Profile: http://www.linkedin.com/in/kavaldjiev

On 26 May 2015 at 15:43, Christopher Felton <chr...@gm...> wrote:

> On 5/26/2015 7:10 AM, Nikolay Kavaldjiev wrote:
> > Hi All,
> >
> > We have a co-simulation issue: when constants are assigned to signals in
> > co-simulation, the assigned values are not visible in MyHDL.
>
> In the example you linked there are two issues that
> prevent it from working:  first, the initial values
> is not (currently) used in the converted HDL.  The
> `b` Signal in `concat_assign` will not be assigned
> an initial value of `True`.
>
> Second, you can't use and `always_comb` to assign
> a Signal to a constant (as you comments indicate).
>
> >
> > The issue is demonstrated by the following gist:
> > https://gist.github.com/nkavaldj/650fafbc3693f7a501e2
> >
> > The flow we use: MyHDL - > toVerilog -> Icarus
> >
> > Is there a known workaround?
>
> I haven't run into this issue, a workaround would
> be to use the constant directly and not create a
> constant Signal.
>
> Or use a dummy(ies) Signal in the `always_comb`
> to preserve the const assignments.
>
>      d1 = Signal(bool(0))
>      d2 = Signal(bool(0))
>
>      @always_comb
>      def assign():
>         # keep the combinatorial process
>          d2.next = d1
>         # assign constants
>          x1.next = True
>          x2.next = 0x55
>
>      return assign
>
> Or you could use the ROM design pattern:
>
> http://docs.myhdl.org/en/latest/manual/conversion_examples.html#rom-inference
>
> Regards,
> Chris
>
>
>
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Re: [myhdl-list] Hello World

[Christopher F. <chr...@gm...>]

On 5/21/2015 5:20 AM, Günther Stangassinger wrote:
> Hello Christopher,
> you wrote:
>
> "The DEnano has a 50MHz clock, this should be
> the clock driving all your processes/generators.  Don't
> use the generated SCLK to clock any internal logic."
>
>
> Can you please tell me the reason for this?

It is going to be the safest design practice and
the easiest to guarantee you have met timing.  Even
with slow clocks it is best to use a single clock
and a single edge in most cases (there are always
exceptions).

The Altera Quartus synthesis guide is a reasonable
reference and will do a better job describing the
pitfalls than I would in a short response.

See section "Synchronous FPGA Design Practices" on
page12-2 in the following document and specifically
"Clocking Schemes" on page 12-7.
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/qts/qts_qii51006.pdf

Hope that helps,
Chris

Re: [myhdl-list] Constant assignments in co-simulation

[Christopher F. <chr...@gm...>]

On 5/26/2015 7:10 AM, Nikolay Kavaldjiev wrote:
> Hi All,
>
> We have a co-simulation issue: when constants are assigned to signals in
> co-simulation, the assigned values are not visible in MyHDL.

In the example you linked there are two issues that
prevent it from working:  first, the initial values
is not (currently) used in the converted HDL.  The
`b` Signal in `concat_assign` will not be assigned
an initial value of `True`.

Second, you can't use and `always_comb` to assign
a Signal to a constant (as you comments indicate).

>
> The issue is demonstrated by the following gist:
> https://gist.github.com/nkavaldj/650fafbc3693f7a501e2
>
> The flow we use: MyHDL - > toVerilog -> Icarus
>
> Is there a known workaround?

I haven't run into this issue, a workaround would
be to use the constant directly and not create a
constant Signal.

Or use a dummy(ies) Signal in the `always_comb`
to preserve the const assignments.

     d1 = Signal(bool(0))
     d2 = Signal(bool(0))

     @always_comb
     def assign():
	# keep the combinatorial process
         d2.next = d1
	# assign constants
         x1.next = True
         x2.next = 0x55

     return assign

Or you could use the ROM design pattern:
http://docs.myhdl.org/en/latest/manual/conversion_examples.html#rom-inference

Regards,
Chris

[myhdl-list] Constant assignments in co-simulation

[Nikolay K. <nik...@gm...>]

Hi All,

We have a co-simulation issue: when constants are assigned to signals in
co-simulation, the assigned values are not visible in MyHDL.

The issue is demonstrated by the following gist:
https://gist.github.com/nkavaldj/650fafbc3693f7a501e2

The flow we use: MyHDL - > toVerilog -> Icarus

Is there a known workaround?



Regards,

Nikolay

Re: [myhdl-list] Concat with a constant

[Henry G. <he...@ca...>]

On 23/05/15 08:24, Jan Decaluwe wrote:
> On 05/22/2015 04:10 PM, Josy Boelen wrote:
>> >
>>>> >>>
>>>> >>>is it something like in (closed/rejected) PR #1:
>>>> >>>https://github.com/jandecaluwe/myhdl/pull/1
>>> >>
>>> >>Uhm possibly. I think it might be much simpler than that - using
>>> >>concat() on the RHS of an assignment (which I hadn't noted!). Is that
>>> >>possible?
>>> >>
>> >
>> >concat() didn't work for me ... but I had a slightly more complex
>> >requirement:https://github.com/josyb/ControlStatus
> This was something I had promised to address in the way outlined
> in my replies.
>
> I have now committed a proposed enhancement that provides
> ConcatSignal() with and interface which is similar to concat()
> for constants, meaning one can use constrained intbv's, bools,
> and bitstrings expressed in a string.

This looks great. Thank Jan!

Henry

Re: [myhdl-list] Concat with a constant

[Jan D. <ja...@ja...>]

On 05/22/2015 04:10 PM, Josy Boelen wrote:
>
>>>
>>> is it something like in (closed/rejected) PR #1:
>>> https://github.com/jandecaluwe/myhdl/pull/1
>>
>> Uhm possibly. I think it might be much simpler than that - using
>> concat() on the RHS of an assignment (which I hadn't noted!). Is that
>> possible?
>>
>
> concat() didn't work for me ... but I had a slightly more complex
> requirement: https://github.com/josyb/ControlStatus

This was something I had promised to address in the way outlined
in my replies.

I have now committed a proposed enhancement that provides
ConcatSignal() with and interface which is similar to concat()
for constants, meaning one can use constrained intbv's, bools,
and bitstrings expressed in a string.

Documentation still to be updated.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Concat with a constant

[Christopher F. <chr...@gm...>]

On 5/22/2015 7:07 AM, Henry Gomersall wrote:
> Is there some neat way to concatenate a signal with a constant?
>

You can't simply concatenate with a constant that
is a Python `int` because it doesn't have a bit
length that MyHDL uses, the constant would need to
be an `intbv` or `bool`.

http://docs.myhdl.org/en/latest/manual/reference.html?highlight=concat#myhdl.concat

If we had initial values you could use constants
assigned outside the generators (see below).  The
best approach I can think of is to assign the constant
to a variable and then concat.

     # MYHDL
     def m_concat_const(x, y):
        # CONST1 will not work because initial values
        # is not enabled ...
        CONST1 = intbv(10, min=0, max=137)
        CONST2 = 5

        @always_comb
        def rtl():
            const2 = intbv(5, min=0, max=8)  # or intbv(CONST2 ...)?
            y.next = concat(x[4:0], CONST1, const2)
        return rtl


     # Converted VHDL
     M_CONCAT_CONST_RTL: process (x) is
         variable CONST1: unsigned(7 downto 0);
         variable const2: unsigned(2 downto 0);
     begin
         const2 := to_unsigned(5, 3);
         y <= resize(unsigned'(x & CONST1 & const2), 12);
     end process M_CONCAT_CONST_RTL;


If you want to concat outside of a generator (elaboration)
then you would want to review the thread @josyb
referenced.

You can use ConcatSignal where one of the signals is
simply assigned to the constant:

     Sig1 = ...
     Sig2 = ...
     Sig3 = ConcatSignal(Sig1, Sig2)

     @always_comb
     def assign():
         Sig2.next = CONSTANT

Hope that helps,
Chris

Re: [myhdl-list] Concat with a constant

[Henry G. <he...@ca...>]

On 22/05/15 15:10, Josy Boelen wrote:
>>> > >
>>> > >is it something like in (closed/rejected) PR #1:
>>> > >https://github.com/jandecaluwe/myhdl/pull/1
>> >
>> >Uhm possibly. I think it might be much simpler than that - using
>> >concat() on the RHS of an assignment (which I hadn't noted!). Is that
>> >possible?
>> >
> concat() didn't work for me ... but I had a slightly more complex
> requirement:https://github.com/josyb/ControlStatus

Thanks, I'll need to think about that a bit to grok your issue!

Cheers,

Henry

Re: [myhdl-list] Concat with a constant

[Josy B. <jos...@gm...>]

> >
> > is it something like in (closed/rejected) PR #1:
> > https://github.com/jandecaluwe/myhdl/pull/1
> 
> Uhm possibly. I think it might be much simpler than that - using 
> concat() on the RHS of an assignment (which I hadn't noted!). Is that 
> possible?
> 

concat() didn't work for me ... but I had a slightly more complex 
requirement: https://github.com/josyb/ControlStatus

Regards,

JOsy

Re: [myhdl-list] Concat with a constant

[Henry G. <he...@ca...>]

On 22/05/15 14:39, Josy Boelen wrote:
>   
>> >Is there some neat way to concatenate a signal with a constant?
>> >
>> >Clearly, one can use ConcatSignal with a pair of signals, one of which
>> >can be driven every cycle with a clock cycle, but this seems rather
>> >inelegant (though I dare say it would be optimised out).
>> >
>> >Cheers,
>> >
>> >Henry
> Hi Henry,
>
> is it something like in (closed/rejected) PR #1:
> https://github.com/jandecaluwe/myhdl/pull/1

Uhm possibly. I think it might be much simpler than that - using 
concat() on the RHS of an assignment (which I hadn't noted!). Is that 
possible?

Henry

Re: [myhdl-list] Concat with a constant

[Josy B. <jos...@gm...>]

 
> Is there some neat way to concatenate a signal with a constant?
> 
> Clearly, one can use ConcatSignal with a pair of signals, one of which 
> can be driven every cycle with a clock cycle, but this seems rather 
> inelegant (though I dare say it would be optimised out).
> 
> Cheers,
> 
> Henry

Hi Henry,

is it something like in (closed/rejected) PR #1: 
https://github.com/jandecaluwe/myhdl/pull/1

Regards,

Josy

Re: [myhdl-list] Concat with a constant

[Henry G. <he...@ca...>]

On 22/05/15 13:07, Henry Gomersall wrote:
> Clearly, one can use ConcatSignal with a pair of signals, one of which
> can be driven every cycle with a clock cycle

I mean:
"can be driven every cycle with a *constant*"

[myhdl-list] Concat with a constant

[Henry G. <he...@ca...>]

Is there some neat way to concatenate a signal with a constant?

Clearly, one can use ConcatSignal with a pair of signals, one of which 
can be driven every cycle with a clock cycle, but this seems rather 
inelegant (though I dare say it would be optimised out).

Cheers,

Henry

Re: [myhdl-list] Hello World

[Günther S. <gue...@gm...>]

Hello Christopher,
you wrote:

"The DEnano has a 50MHz clock, this should be
the clock driving all your processes/generators.  Don't
use the generated SCLK to clock any internal logic."


Can you please tell me the reason for this?
Because obviously it is working with when i use the generated SCLK
Is it because of timing issues or are there any other reasons?
I saw in your example that you are using posedge and negedge.
But the frequency of the system clock is so much higher than
the frequency i am working with, so  does it matter  if i use posedge
and in another process negedge.
So i could combine all together in only for example posedge.
Or did i get something wrong?
Thank you.
Regards
guenther






On 27.04.2015 14:38, Christopher Felton wrote:
> On 4/27/2015 12:17 AM, Günther Stangassinger wrote:
>> Thank you very much for your hint.
>> I was trying this.
>> The clock ist now running only when CSn is low.
>> But without success. :-(
>> There is still 0x0 as out put.
>> Does anybody else have any hints?
> There are some changes you should make, in this design
> you should only have a single clock for the internal
> logic.  The DEnano has a 50MHz clock, this should be
> the clock driving all your processes/generators.  Don't
> use the generated SCLK to clock any internal logic.
>
> Then create posedge and negedge strobes based on the
> slower clock (or you can do it vise-versa have state
> machine that creates the edge strobes and the clock
> generated from there).
>
> Here is an example:
> https://bitbucket.org/cfelton/examples/src/tip/mycores/aic23/aic23_spi.py?at=default#cl-96
> http://www.fpgarelated.com/showarticle/41.php
>
>> If you are saying the Tristatesignal is looking ok,
>> than mybe  i should focus on the sequence to read the DEVID.
>> Thank you very much.
> The tristate looks ok in the simulation (not fully
> decoding the bus transaction).  Personally I would
> break out the when/how the tristate is driven to
> a separate process/generator:
>
>       bitout = Signal(bool(0))
>       io = I2C_SDAT.driver()
>
>       # ....
>
>       @always_comb
>       def tristate_driver():
>           if count > 0 and count < 11:
> 	    io.next = None
>           else:
>               io.next = bitout
>
> Only the tristate is the output of this process.
> This shouldn't functionally change your code but in
> the converted code you will have a simple expression
> for the tristate.
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
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> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
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> _______________________________________________
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>

-- 
Mit freundlichen Grüßen
Günther Stangassinger

Re: [myhdl-list] zedboard

[Christopher F. <chr...@gm...>]

On 5/20/2015 12:45 PM, Christopher Felton wrote:
<snip>
>
> Costs:
>     Xula2-LX9:  $69
>     Xula2-LX25: $119
>     Zedboard:   $289 (with 7020)
>     Parallella: $265 (with 7020, digikey)
>

You can get the parallalla for $99 with a 7010.

Regards,
Chris

Re: [myhdl-list] zedboard

[Christopher F. <chr...@gm...>]

On 5/18/2015 5:32 PM, Edward Vidal wrote:
> Henry or Anyone else running a Zedboard, First thanks to Jose M. his
> help on the FSM delay was right on! You indicated that you are
> running a ZedBoard.What O/S are you running Ubuntu, Yocto, or some
> other distro?Do you have any examples, of how your transfer data to
> the FPGA and back to CPU side?  Also, how do you add to the bin file,
> the bin file that has the (hdmi, Ethernet USB) and other CPU
> devices?  I am currently running on an XESS XulA2 with XC6SLX9 which I
> believe has 9152 logic cells, 666 Kbits of RAM.

The XC6SLX9, as you state, has 9152 logic cells and
1430 slices.  There are 4 LUTs per slice, which is
5720 LUTs (roughly 1.6 LC per LUT?).  The Z-7020
indicates it has 85K logic cells, which is closer
to one of the larger Spartan6 devices (don't recall
if the Zynq programmable fabric is similar to the S6).

         |  LC   | LUTS |
   ------+-------+------+
   LX9   | 9K    | 5.7K |
   LX25  | 25K   | 15K  |
   Z7020 | 85K   | ??   |
   LX100 | 100K  | 63K  |

Costs:
   Xula2-LX9:  $69
   Xula2-LX25: $119
   Zedboard:   $289 (with 7020)
   Parallella: $265 (with 7020, digikey)

> How does this compare
> with what is remaining Zedboard after  (hdmi, Ethernet USB) and other
> CPU devices?

It really depends on what you want to do, the Xula
boards and the misc motherboards are good (IMO) for
experimenting or using the Xula as an FPGA module
in a larger design.  The Zed board, as you point
out, has some higher-end interfaces.  I don't think
they are comparable, they would be for different
purposes (problems).

It might be worthwhile to step back and look at the
project from an architectural view and decide if a
processor is needed or not.  Or if this is for fun
and you want to play with the processor subsystem.
If a processor is required, the Znyq would be a
reasonable option if not the Spartan6 or the newer
7 series would be appropriate.

> Are most people using Xilinx or Altera?

In my opinion it doesn't really matter and you should
strive to develop agnostic designs as much as possible.
When one vendor pisses you off you have options!

Regards,
Chris

Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** Hello World

[Josy B. <jos...@gm...>]

> Hello Josy,
> 
> This conviced me, i will stay with myhdl, i think its really great.
> If there is a problem with tristate at the moment i can live with that,
> as i know now how to work around.
> Thanks a lot.
> Regards,
> guenther
> 

Welcome to our growing community!

I submitted a Pull Request to fix that bug.

One observation: in your code you are actually using a TriState pin to 
drive.read the I2C_SDAT. In reality the SDa pin in the I2C is an 
opendrain, with a pull-up in the circuit. So you can only drive it *low* 
and keep it tristated otherwise.

Regards,

Josy

Re: [myhdl-list] zedboard

[Henry G. <he...@ca...>]

On 18/05/15 23:32, Edward Vidal wrote:
>
> You indicated that you are running a ZedBoard.
> What O/S are you running Ubuntu, Yocto, or some other distro?
> Do you have any examples, of how your transfer data to the FPGA
> and back to CPU side?

I recommend the Zynq book for everything about the zynq (free PDF online):
http://www.zynqbook.com/

It's the manual that Xilinx never wrote (though I believe it was written 
in collaboration with them) and is very readable.

It's really quite easy to do stuff using Vivado.

Cheers,

Henry

Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** Hello World

[Günther S. <gue...@gm...>]

Hello Josy,

This conviced me, i will stay with myhdl, i think its really great.
If there is a problem with tristate at the moment i can live with that,
as i know now how to work around.
Thanks a lot.
Regards,
guenther


Am 17.05.2015 um 21:25 schrieb Josy Boelen:
> Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:
>
>> Hello Josy,
>> thank you for your answer.
>> My problem is that i have to modify the generated verilog(vhdl) code
> to
>> make it work.
>> Is myhdl meant to be like this or do i just have bad luck with this
> example?
>> I am asking because i am very new to myhdl and this is
>> acually my second example what i was trying.
>> Are you doing large projects with myhdl?
>> I am asking because i want to know if i should
>> dig more into myhdl or should i focus more on vhdl, when i do have
>> to modify vhdl afterwards anyway.
>> So what is your experiance?
>>
>
> Hi Günther,
>
> It is a bit of bad luck, you just hit a bug in the conversion of
> TristateSignal ...
>
> I essentially switched to MyHDL *completely*. For new code, of course I
> have to maintain some 10 years+ of VHDL coding.
> Most of my MyHDL modules are components I instantiate inside Qsys, so
> they tend to be not that large (not being small either). However I did a
> quite large project in MyHDL implementing a 'Support Vector Machine' ->
> http://de.wikipedia.org/wiki/Support_Vector_Machine, which produced 6703
> lines of VHDL code.
>
> So yes, use MyHDL.
> One caveat: MyHDL is no silver bullet (there are no silver bullets ...).
> The design of RTL is very close to what you do in either VHDL or
> Verilog. But development is a factor quicker, essentially the simulation
> is where you gain most as you can use full Python to generate data for
> your testbenches and make these self-checking. E.g. in the Support
> Vector Machine module we could import a libsvm library to calculate the
> results to compare our simulation with. And to debug the RTL I wrote an
> integer version of it with lots of output written to the console to
> compare to the signals in the simulation window.
> I'm using Eclipse with PyDev for MyHDL editing/running and Impulse to
> view the simulation waveforms (under Windows 8.1)
>
> So once again, MyHDL is definitely preferable over VHDL or Verilog, and
> it is production ready. If a bug however shows up, there is a ready
> community to fix it. I already have a fix for the VHDL (others => 'Z')
> bug, but I have to inspect/fix the Verilog conversion too before I can
> issue a pull request to update the MyHDL 0.9 master development branch.
>
> Regards,
>
> Josy
> ------------------------------------------------------------------------------
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Re: [myhdl-list] zedboard

[Jeremy H. <jer...@gm...>]

Hi Edward,

I play with the Zynq chips on occasion. You can load the bitfile in one of
three ways:

- Using linux by piping it to a special device node
- Bootloader from SPI flash, SD, etc
- JTAG

You can see how many LUTs you get using the following table:
http://www.xilinx.com/publications/prod_mktg/zynq7000/Zynq-7000-combined-product-table.pdf

The chip on the zedboard is a Zynq 7020 (unless that has changed, I have
one of the original academic pre-production ones). Transfer of data occurs
via the AXI bus internally, so you need to create logic with an
AXI-compatible interface if you want to send data across. You can attach
"logic devices" manually in the device tree binary loaded at boot,
instantiate them at runtime using system calls or simply read and write the
bus in kernel space using a standard memory mapped approach. Hopefully with
the upcoming device tree overlay support in the kernel (this is basically
hot-swappable hardware configuration overlays) this fiddling will be a
thing of the past. If you'd like a high-ish level overview on the topic:
http://www.zynqbook.com/downloads.php is a free book, and it has got some
good examples to go with it.

I personally use Ubuntu because I like apt-get and I run ubuntu on all my
other machines. I do all development for the Zynq on Ubuntu as well.

I am yet to play with the Altera Cyclone V, but I imagine it's the same
sort of thing. I have a dev kit for it sitting on my desk for it, I just
need to find the time ;)

Thanks,
Jeremy

On Tue, 19 May 2015 at 08:35 Edward Vidal <dev...@sb...> wrote:

>  Henry or Anyone else running a Zedboard,
>
> First thanks to Jose M. his help on the FSM delay was right on!
>
> You indicated that you are running a ZedBoard.
> What O/S are you running Ubuntu, Yocto, or some other distro?
> Do you have any examples, of how your transfer data to the FPGA
> and back to CPU side?
> Also, how do you add to the bin file,  the bin file that has the (hdmi,
> Ethernet
> USB) and other CPU devices?
> I am currently running on an XESS XulA2 with XC6SLX9 which I believe
> has 9152 logic cells, 666 Kbits of RAM.
> How does this compare with what is remaining Zedboard after  (hdmi,
> Ethernet
> USB) and other CPU devices?
> Are most people using Xilinx or Alter?
> I saw on the market today that Altera Shares Jump on Potential Merger With
> Intel.
> Thanks
>
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] zedboard

[Edward V. <dev...@sb...>]

 Henry or Anyone else running a Zedboard,
First thanks to Jose M. his help on the FSM delay was right on!
You indicated that you are running a ZedBoard.What O/S are you running Ubuntu, Yocto, or some other distro?Do you have any examples, of how your transfer data to the FPGAand back to CPU side?Also, how do you add to the bin file,  the bin file that has the (hdmi, Ethernet USB) and other CPU devices?I am currently running on an XESS XulA2 with XC6SLX9 which I believe has 9152 logic cells, 666 Kbits of RAM.How does this compare with what is remaining Zedboard after  (hdmi, Ethernet USB) and other CPU devices?Are most people using Xilinx or Alter?I saw on the market today that Altera Shares Jump on Potential Merger With Intel.Thanks Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

Re: [myhdl-list] *** Hello World

[Josy B. <jos...@gm...>]

Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:

> 
> Hello Josy,
> thank you for your answer.
> My problem is that i have to modify the generated verilog(vhdl) code 
to 
> make it work.
> Is myhdl meant to be like this or do i just have bad luck with this 
example?
> I am asking because i am very new to myhdl and this is
> acually my second example what i was trying.
> Are you doing large projects with myhdl?
> I am asking because i want to know if i should
> dig more into myhdl or should i focus more on vhdl, when i do have
> to modify vhdl afterwards anyway.
> So what is your experiance?
> 


Hi Günther,

It is a bit of bad luck, you just hit a bug in the conversion of 
TristateSignal ...

I essentially switched to MyHDL *completely*. For new code, of course I 
have to maintain some 10 years+ of VHDL coding.
Most of my MyHDL modules are components I instantiate inside Qsys, so 
they tend to be not that large (not being small either). However I did a 
quite large project in MyHDL implementing a 'Support Vector Machine' -> 
http://de.wikipedia.org/wiki/Support_Vector_Machine, which produced 6703 
lines of VHDL code.

So yes, use MyHDL. 
One caveat: MyHDL is no silver bullet (there are no silver bullets ...). 
The design of RTL is very close to what you do in either VHDL or 
Verilog. But development is a factor quicker, essentially the simulation 
is where you gain most as you can use full Python to generate data for 
your testbenches and make these self-checking. E.g. in the Support 
Vector Machine module we could import a libsvm library to calculate the 
results to compare our simulation with. And to debug the RTL I wrote an 
integer version of it with lots of output written to the console to 
compare to the signals in the simulation window.
I'm using Eclipse with PyDev for MyHDL editing/running and Impulse to 
view the simulation waveforms (under Windows 8.1)

So once again, MyHDL is definitely preferable over VHDL or Verilog, and 
it is production ready. If a bug however shows up, there is a ready 
community to fix it. I already have a fix for the VHDL (others => 'Z') 
bug, but I have to inspect/fix the Verilog conversion too before I can 
issue a pull request to update the MyHDL 0.9 master development branch.

Regards,

Josy

Re: [myhdl-list] *** Hello World

[Günther S. <gue...@gm...>]

Hello Josy,
thank you for your answer.
My problem is that i have to modify the generated verilog(vhdl) code to 
make it work.
Is myhdl meant to be like this or do i just have bad luck with this example?
I am asking because i am very new to myhdl and this is
acually my second example what i was trying.
Are you doing large projects with myhdl?
I am asking because i want to know if i should
dig more into myhdl or should i focus more on vhdl, when i do have
to modify vhdl afterwards anyway.
So what is your experiance?

-- 
Regards
guenther






Am 17.05.2015 um 20:13 schrieb Josy Boelen:
> Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:
>
>> Hello Josy,
>> thank you.
>> yes i saw that in VHDL there was this error.
>> Therefore i tried it with verilog.
>> But what i really do not understand what you mean you
>> do not use read at all.
>> Can you please explain this to me?
>> When i have this:
>>
>> I2C_SDAT = TristateSignal(False)
>>
>> How would i have to write it to avoid this and
>> how can i use this opendrain primitive than??
>>
> Hello Günther,
>
> The one essential part of my answer was that the conversion of
> TristateSignal() seems to be incorrect, both for Verilog and VHDL.
> Also the VHDL conversion gives quite a few warnings:
> ** ToVHDLWarning: Output port is read internally: G_SENSOR_CS_N
> ** ToVHDLWarning: Port is not used: G_SENSOR_INT
> ** ToVHDLWarning: Output port is read internally: I2C_SCLK
> ** ToVHDLWarning: Output port is read internally: I2C_SDAT
> ** ToVHDLWarning: Signal is driven but not read:
> drive_spi_inst_read_Adr_inst_r_data2
> ** ToVHDLWarning: Signal is driven but not read:
> drive_spi_inst_read_Adr_inst_io
> ** ToVHDLWarning: Signal is not driven:
> drive_spi_inst_read_Adr_inst_w_data1
> ** ToVHDLWarning: Signal is not driven:
> drive_spi_inst_read_Adr_inst_w_adr_2
> ** ToVHDLWarning: Signal is not driven:
> drive_spi_inst_read_Adr_inst_w_adr_1
>
> Some of them are benign, some of them are to avoid.
> Not that I am converting your code as you posted yesterday.
> 1. ** ToVHDLWarning: Output port is read internally: G_SENSOR_CS_N
> This is (very probably) not your intention, and will (in VHDL) produce
> an *inout* port in stead of an *out* port. You can correct that by using
> local signals and assign the output port in a separate combinatorial
> procress.
>
> 2.** ToVHDLWarning: Port is not used: G_SENSOR_INT
> You actually are not using it.
>
> 3.** ToVHDLWarning: Output port is read internally: I2C_SCLK
> This is like 1.
>
> 4.** ToVHDLWarning: Output port is read internally: I2C_SDAT
> For a top-level module this can't be easily avoided. Note that in a VHDL
> top-file we would use a primitive like this:
> 	-- drive SDa via an open drain primitive
> 	od1 : opndrn port map(qs_SdaOut, IfSDa);
> which would be warning-free
>
> 5.** ToVHDLWarning: Signal is driven but not read:
> drive_spi_inst_read_Adr_inst_r_data2
>
> 6.** ToVHDLWarning: Signal is not driven:
> drive_spi_inst_read_Adr_inst_w_data1
> ** ToVHDLWarning: Signal is not driven:
> drive_spi_inst_read_Adr_inst_w_adr_2
> ** ToVHDLWarning: Signal is not driven:
> drive_spi_inst_read_Adr_inst_w_adr_1
> I'm not sure whether these three warnings should be there at all. You
> are using a Signal(intbv() as a constant. The generated VHDL is correct.
> The warning is correct though in stating that the Signal is not driven,
> read: depending on an input port.
>
> Perhaps I shouldn't have mentioned my preference of splitting opendrain
> and tristate signals into inputs, outputs and for the tristate enable.
> Now for your gw.py file this is no solution either as I understood that
> you are using the converted result as the top-file in your Quartus II
> project.
>
>
> Regards,
>
> Josy
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Hello World

[Josy B. <jos...@gm...>]

Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:

> 
> Hello Josy,
> thank you.
> yes i saw that in VHDL there was this error.
> Therefore i tried it with verilog.
> But what i really do not understand what you mean you
> do not use read at all.
> Can you please explain this to me?
> When i have this:
> 
> I2C_SDAT = TristateSignal(False)
> 
> How would i have to write it to avoid this and
> how can i use this opendrain primitive than??
> 

Hello Günther,

The one essential part of my answer was that the conversion of 
TristateSignal() seems to be incorrect, both for Verilog and VHDL.
Also the VHDL conversion gives quite a few warnings:
** ToVHDLWarning: Output port is read internally: G_SENSOR_CS_N
** ToVHDLWarning: Port is not used: G_SENSOR_INT
** ToVHDLWarning: Output port is read internally: I2C_SCLK
** ToVHDLWarning: Output port is read internally: I2C_SDAT
** ToVHDLWarning: Signal is driven but not read: 
drive_spi_inst_read_Adr_inst_r_data2
** ToVHDLWarning: Signal is driven but not read: 
drive_spi_inst_read_Adr_inst_io
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_data1
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_2
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_1

Some of them are benign, some of them are to avoid.
Not that I am converting your code as you posted yesterday.
1. ** ToVHDLWarning: Output port is read internally: G_SENSOR_CS_N
This is (very probably) not your intention, and will (in VHDL) produce 
an *inout* port in stead of an *out* port. You can correct that by using 
local signals and assign the output port in a separate combinatorial 
procress.

2.** ToVHDLWarning: Port is not used: G_SENSOR_INT
You actually are not using it. 

3.** ToVHDLWarning: Output port is read internally: I2C_SCLK
This is like 1.

4.** ToVHDLWarning: Output port is read internally: I2C_SDAT
For a top-level module this can't be easily avoided. Note that in a VHDL 
top-file we would use a primitive like this:
	-- drive SDa via an open drain primitive
	od1 : opndrn port map(qs_SdaOut, IfSDa);
which would be warning-free

5.** ToVHDLWarning: Signal is driven but not read: 
drive_spi_inst_read_Adr_inst_r_data2

6.** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_data1
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_2
** ToVHDLWarning: Signal is not driven: 
drive_spi_inst_read_Adr_inst_w_adr_1
I'm not sure whether these three warnings should be there at all. You 
are using a Signal(intbv() as a constant. The generated VHDL is correct. 
The warning is correct though in stating that the Signal is not driven, 
read: depending on an input port.

Perhaps I shouldn't have mentioned my preference of splitting opendrain 
and tristate signals into inputs, outputs and for the tristate enable.
Now for your gw.py file this is no solution either as I understood that 
you are using the converted result as the top-file in your Quartus II 
project.


Regards,

Josy

Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Hello World

[Günther S. <gue...@gm...>]

Hello Josy,
thank you.
yes i saw that in VHDL there was this error.
Therefore i tried it with verilog.
But what i really do not understand what you mean you
do not use read at all.
Can you please explain this to me?
When i have this:

I2C_SDAT = TristateSignal(False)


How would i have to write it to avoid this and
how can i use this opendrain primitive than??


-- 
Regards
guenther




Am 17.05.2015 um 12:53 schrieb Josy Boelen:
> Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:
>
>> Hello,
>> it is working:
>> https://github.com/stangassinger/de0_nano_adxl345
>> I am getting the DEVID 0xE5
>> The problem was not the myhdl code.
>> The problem was the generated verilog code.
>> At the beginning of the generated code where the ports are declared
>> it says:
>> output I2C_SDAT;
>>
>> And this was one and only problem !!
>> Because the I2C_SDAT is tristate it should not be a output port.
>> There fore i changed it to:
>> inout I2C_SDAT;
>>
>> And with this change it is working
>>
>> But my question now is:
>> How do i have to declare the I2C_SDAT port in myhdl
>> so that it generates to "inout" ???
>>
>> I declared it with:
>>
>> I2C_SDAT = TristateSignal(False)
>>
>> What do i have to do the it generates this code:
>> inout I2C_SDAT;
>>
>> I would be very glad if someone could help me?
>> Thank you very much.
>> Best regards
>> guenther stangassinger
>>
> Hallo Günther,
>
> I converted your code to VHDL and there we get an *inout* for I2C_SDAT.
> But there is one error though:
> we get :             drive_spi_inst_read_Adr_inst_io <= (others => 'Z');
> where it should be:  drive_spi_inst_read_Adr_inst_io <= 'Z';
>
> I suggest you make an issue out of it as the conversion of
> TristateSignal doesn't look to be error-free.
>
> Personally I avoid (read: don't use at all) internal tristate signals:
> my I2C modules have a separate input and output signal for SDa, which I
> then drive to the SDa pin via an **opendrain** primitive in the toplevel
> file.
>
> Regards,
>
> Josy
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
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> _______________________________________________
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