myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Hello World

[Josy B. <jos...@gm...>]

Günther Stangassinger <guenther.stangassinger <at> gmx.net> writes:

> 
> Hello,
> it is working:
> https://github.com/stangassinger/de0_nano_adxl345
> I am getting the DEVID 0xE5
> The problem was not the myhdl code.
> The problem was the generated verilog code.
> At the beginning of the generated code where the ports are declared
> it says:
> output I2C_SDAT;
> 
> And this was one and only problem !!
> Because the I2C_SDAT is tristate it should not be a output port.
> There fore i changed it to:
> inout I2C_SDAT;
> 
> And with this change it is working     
> 
> But my question now is:
> How do i have to declare the I2C_SDAT port in myhdl
> so that it generates to "inout" ???
> 
> I declared it with:
> 
> I2C_SDAT = TristateSignal(False)
> 
> What do i have to do the it generates this code:
> inout I2C_SDAT;
> 
> I would be very glad if someone could help me?
> Thank you very much.
> Best regards
> guenther stangassinger
> 
Hallo Günther,

I converted your code to VHDL and there we get an *inout* for I2C_SDAT. 
But there is one error though:
we get :             drive_spi_inst_read_Adr_inst_io <= (others => 'Z');
where it should be:  drive_spi_inst_read_Adr_inst_io <= 'Z';

I suggest you make an issue out of it as the conversion of 
TristateSignal doesn't look to be error-free.

Personally I avoid (read: don't use at all) internal tristate signals: 
my I2C modules have a separate input and output signal for SDa, which I 
then drive to the SDa pin via an **opendrain** primitive in the toplevel 
file.

Regards,

Josy

Re: [myhdl-list] *** GMX Spamverdacht *** Re: *** GMX Spamverdacht *** Hello World

[Günther S. <gue...@gm...>]

Hello,
it is working:
https://github.com/stangassinger/de0_nano_adxl345
I am getting the DEVID 0xE5
The problem was not the myhdl code.
The problem was the generated verilog code.
At the beginning of the generated code where the ports are declared
it says:
output I2C_SDAT;

And this was one and only problem !!
Because the I2C_SDAT is tristate it should not be a output port.
There fore i changed it to:
inout I2C_SDAT;

And with this change it is working  :-)   :-)

But my question now is:
How do i have to declare the I2C_SDAT port in myhdl
so that it generates to "inout" ???

I declared it with:

I2C_SDAT = TristateSignal(False)

What do i have to do the it generates this code:
inout I2C_SDAT;

I would be very glad if someone could help me?
Thank you very much.
Best regards
guenther stangassinger








Am 15.05.2015 um 10:53 schrieb Günther Stangassinger:
> Hello together,
> unfortunatelly i was not really successfull with my ADXL345 reading the
> DEVID with de0-nano
> I managed to get the same sequence in simulation as someone who was
> doing the same here:
> http://www.mikrocontroller.net/topic/350597
> At the bottom you can see sequences which are quite the same, as what i get
> when i run my code in simulation with
> python gw.py
> I have my code here now:
> https://github.com/stangassinger/de0_nano_adxl345
>
> So if someone has also a de0-nano board, it would be great if he could
> test it on his board.
>
> So i am quite pleased with the output in simulation mode.(Also the
> expected tristate signal is on the right position!)
> But when i run the converted verilog code on my de0-nano
> i only get 0x0 as the output instead of 0xE5
>
> So any hints for this, mybe very small problem are very wellcome.
>
> Until now i am very convinced of myhdl but i want to transfer it to real
> word problems.
> Thank you very much.
>


-- 
Mit freundlichen Grüßen
Günther Stangassinger

Re: [myhdl-list] toVHDL - lazy debug?

[Jan C. <jen...@mu...>]

On Fri, 15 May 2015 18:07:49 -0400
"Jose M. Gomez Cama" <ch...@gm...> wrote:

> Dear Jan,
> 
> I think this should come from a non initialized
> Signal, or some forgot .next.
> 
> In any case, I have this lines just after the
> visit_Compare:
> 
>     def visit_Compare(self, node):
>         node.vhd = vhd_boolean()
>         self.generic_visit(node)
>         left, op, right = node.left,
> node.ops[0], node.comparators[0] if left.vhd is
> None: print(ast.dump(node))
> 
> The dump should provide you some hints.

Thanks, all fixed.  I had to put the dump at the
indicated line number, ~1006, and remove the
conditional, as I could not adapt it quickly. 

The problem was consistent use of bitwise
operators in a boolean expression. 

I noticed that if there is a mixture of logical
and boolean operators you get a nice error
message:

"myhdl.ConversionError: in
file /.../bcDscHndls.py, line 214: Not supported:
non-boolean argument in logical operator"

but no help for the completely stupid! 

Help much appreciated, now I'll check the rest of
this old code set. 

Kind regards, Jan Coombs. 
-- 

> > El 15/5/2015, a las 16:44, Jan Coombs
> > 
> > I have a convoluted module which passes
> > outline testing, and converts to ~500 lines
> > of Verilog, but will not convert to VHDL. 
> > 
> > On VHDL conversion failure the call stack has
> > entries for toVHDL and ast, and ends with the
> > message: 
> > 
> > "AttributeError: 'NoneType' object has no
> > attribute 'size'"
> > 
> > The resulting .vhd file has a complete list of
> > signals, but no code. 
> > 
> > Jan Coombs. 

Re: [myhdl-list] delay of signals

[Jose M. G. C. <ch...@gm...>]

Dear Edward,

The usual way is to add some spare states to your state machine (you can use a counter if the delay is large).

	Best,

		Jose M.

> El 15/5/2015, a las 17:35, Edward Vidal <dev...@sb...> escribió:
> 
> Hello All,
> 
> In process of creating a FSM to address ram.
> I need to store 256 values received
> on the USB from the PC.
> I then need to extract 3 locations
> and write back a result.
> for every 3 extractions
> (odd and even samples) of column from image.
> 
> 
> The version that I initially started can be found at
> https://github.com/develone/jpeg-2000-test/blob/master/
> ipython_fixbv/test_lifting_jpeg_step/odd_even_fsm.py
> 
> Can someone provide some idea how to delay signals in a FSM.
> I trie added delay(100) in the FSM which results in 100 ns in the VHDL
> file.  
> I have two issues that I am trying to fix.
> 1.) How to delay addr_left, addr_sam, and addr_rht signals to access ram
> 2.) How to mix addr_left, addr_sam, and addr_rht signals to use a single addr_1
> ODD state
> addr_left addr_sam addr_rht
> 0    1    2
>     .
>     .
> 252    253    254
> EVEN state
> addr_left addr_sam addr_rht
> 1    2    3
>     .
>     .
> 253    254    255
> Storing the result back for addr_sam.
> 
> I am already using a mux found at
> 
> https://github.com/develone/jpeg-2000-test/blob/master/ipython_fixbv/test_lifting_jpeg_step/mux.py
> To select between ram address when receiving data from the USB and running the
> the lifting_step.  I am trying to run this on a XulA2 XC6SXL9.
> 
> Any and all help is appreciated.
> Thanks
> 
> 
> 
> 
>  
> Edward Vidal Jr.
> e-mail dev...@sb...
> 915-595-1613
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud 
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y_______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] toVHDL - lazy debug?

[Jose M. G. C. <ch...@gm...>]

Dear Jan,

I think this should come from a non initialized Signal, or some forgot .next.

In any case, I have this lines just after the visit_Compare:

    def visit_Compare(self, node):
        node.vhd = vhd_boolean()
        self.generic_visit(node)
        left, op, right = node.left, node.ops[0], node.comparators[0]
        if left.vhd is None:
            print(ast.dump(node))

The dump should provide you some hints.

	Best,

		Jose M.

> El 15/5/2015, a las 16:44, Jan Coombs <jen...@mu...> escribió:
> 
> I have a convoluted module which passes outline
> testing, and converts to ~500 lines of Verilog,
> but will not convert to VHDL. 
> 
> On VHDL conversion failure the call stack has
> entries for toVHDL and ast, and ends with the
> message: 
> 
> "AttributeError: 'NoneType' object has no
> attribute 'size'"
> 
> The resulting .vhd file has a complete list of
> signals, but no code. 
> 
> 
> I'd prefer not to hack the code apart to find the
> problem, are there any simpler ways of
> unravelling this problem?
> 
> 
> Jan Coombs. 
> --
> 
> toVHDL
> Traceback (most recent call last):
>  File "./testStackCacheHandles.py", line 253, in
> <module> clk,coreClkEn,rst, NumHndls)
>  File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 203, in __call__ _convertGens(genlist,
> siglist, memlist, vfile) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 461, in _convertGens v.visit(tree) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1224, in visit_Module self.visit(stmt) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1606, in visit_FunctionDef
> self.visit_stmt(node.body) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1432, in visit_stmt self.visit(stmt) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 872, in visit_Assign self.visit(rhs) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 644, in visit_BinOp self.BitOp(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 729, in BitOp self.visit(node.left) File
> "/usr/lib/python2.7/ast.py", line 241, in visit
> return visitor(node) File
> "/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
> line 1003, in visit_Compare ns = node.vhd.size
> AttributeError: 'NoneType' object has no
> attribute 'size'
> 
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud 
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

[myhdl-list] delay of signals

[Edward V. <dev...@sb...>]

Hello All,

In process of creating a FSM to address ram.
I need to store 256 values received
on the USB from the PC.
I then need to extract 3 locations
and write back a result.
for every 3 extractions
(odd and even samples) of column from image.


The version that I initially started can be found at
https://github.com/develone/jpeg-2000-test/blob/master/
ipython_fixbv/test_lifting_jpeg_step/odd_even_fsm.py

Can someone provide some idea how to delay signals in a FSM.
I trie added delay(100) in the FSM which results in 100 ns in the VHDL
file.  
I have two issues that I am trying to fix.
1.) How to delay addr_left, addr_sam, and addr_rht signals to access ram
2.) How to mix addr_left, addr_sam, and addr_rht signals to use a single addr_1
ODD state
addr_left addr_sam addr_rht
0    1    2
    .
    .
252    253    254
EVEN state
addr_left addr_sam addr_rht
1    2    3
    .
    .
253    254    255
Storing the result back for addr_sam.

I am already using a mux found at

https://github.com/develone/jpeg-2000-test/blob/master/ipython_fixbv/test_lifting_jpeg_step/mux.py
To select between ram address when receiving data from the USB and running the
the lifting_step.  I am trying to run this on a XulA2 XC6SXL9.

Any and all help is appreciated.
Thanks




 Edward Vidal Jr.
e-mail dev...@sb...
915-595-1613

[myhdl-list] toVHDL - lazy debug?

[Jan C. <jen...@mu...>]

I have a convoluted module which passes outline
testing, and converts to ~500 lines of Verilog,
but will not convert to VHDL. 

On VHDL conversion failure the call stack has
entries for toVHDL and ast, and ends with the
message: 

"AttributeError: 'NoneType' object has no
attribute 'size'"

The resulting .vhd file has a complete list of
signals, but no code. 


I'd prefer not to hack the code apart to find the
problem, are there any simpler ways of
unravelling this problem?


Jan Coombs. 
--

toVHDL
Traceback (most recent call last):
  File "./testStackCacheHandles.py", line 253, in
<module> clk,coreClkEn,rst, NumHndls)
  File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 203, in __call__ _convertGens(genlist,
siglist, memlist, vfile) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 461, in _convertGens v.visit(tree) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1224, in visit_Module self.visit(stmt) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1606, in visit_FunctionDef
self.visit_stmt(node.body) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1432, in visit_stmt self.visit(stmt) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 872, in visit_Assign self.visit(rhs) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 644, in visit_BinOp self.BitOp(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 729, in BitOp self.visit(node.left) File
"/usr/lib/python2.7/ast.py", line 241, in visit
return visitor(node) File
"/usr/local/lib/python2.7/dist-packages/myhdl/conversion/_toVHDL.py",
line 1003, in visit_Compare ns = node.vhd.size
AttributeError: 'NoneType' object has no
attribute 'size'

Re: [myhdl-list] *** GMX Spamverdacht *** Hello World

[Günther S. <gue...@gm...>]

Hello together,
unfortunatelly i was not really successfull with my ADXL345 reading the 
DEVID with de0-nano
I managed to get the same sequence in simulation as someone who was 
doing the same here:
http://www.mikrocontroller.net/topic/350597
At the bottom you can see sequences which are quite the same, as what i get
when i run my code in simulation with
python gw.py
I have my code here now:
https://github.com/stangassinger/de0_nano_adxl345

So if someone has also a de0-nano board, it would be great if he could 
test it on his board.

So i am quite pleased with the output in simulation mode.(Also the 
expected tristate signal is on the right position!)
But when i run the converted verilog code on my de0-nano
i only get 0x0 as the output instead of 0xE5

So any hints for this, mybe very small problem are very wellcome.

Until now i am very convinced of myhdl but i want to transfer it to real 
word problems.
Thank you very much.

-- 
Best Regards
Günther Stangassinger

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Christopher F. <chr...@gm...>]

On 5/11/15 4:48 PM, Henry Gomersall wrote:
> On 11/05/15 21:43, Christopher Felton wrote:
>> On 5/11/2015 6:34 AM, Euripedes Rocha Filho wrote:
>>>> I agree with Henry about the configuration. A .cfg or Yaml file do a better
>>>> job.
>>>>
>> Hey guys, I think collaborating is a good idea
>> and probably the best approach to create a tool
>> that meets the needs of many users.
>>
>> It doesn't sound like gizflo is the best starting
>> point and I am not in a position to lead a project.
>>
>> I have some short-term needs that I need to use
>> gizflo for, I will continue to make changes.  Hopefully,
>> whatever you guys come up with can be the defacto
>> tool in the future.  Keep us informed of your progress.
>
> Hi Chris, I didn't mean to sound like a dick, I'm sorry. I sent the last
> email when I was a bit short of time. I actually think gizflo looks like
> a great starting point; my point was just that now is a good time to
> fiddle with the config layout.

No offense taken, all comments were reasonable.
It sounded like you guys had a good vision what
you wanted to accomplish (and on the same page)
I want to encourage it.  Building off of gizflo
works also - I don't want to limit anyone's
ambitions.

It is a good time to wade through the design
goals and architecture.  I think the cfg will
be too limiting and not the right fit.  I won't
explore the cfg but I encourage anyone to
demonstrate capturing the full board definitions
with cfg and we can discuss from there.

>
> Anyway, I too am lacking in time, so I should really shut up. My
> apologies for wading in, though clearly I'd also love to have a more
> myhdl oriented tool chain, and I dare say I'll start to commit patches
> when as and when I use something like gizflo.

No need for apologies, ideas can and should be
challenged and often we will disagree.  In the
cases where we disagree on technical issue we
need a method to move forward.  More often than
not we will eventually agree based on our
arguments :)

Regards,
Chris

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Jan C. <jen...@mu...>]

On Mon, 11 May 2015 15:43:43 -0500
Christopher Felton <chr...@gm...> wrote:

> Hey guys, I think collaborating is a good idea
> and probably the best approach to create a tool
> that meets the needs of many users.
> 
> It doesn't sound like gizflo is the best
> starting point and I am not in a position to
> lead a project.
> 
> I have some short-term needs that I need to use
> gizflo for, I will continue to make changes.
> Hopefully, whatever you guys come up with can
> be the defacto tool in the future.  Keep us
> informed of your progress.

I also have short-term needs, and would rather
add to your tree than design my own. 

It may be a good time to review the detail once
a reasonable number of differing flows are tried
and tested. 

Jan Coombs. 

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Euripedes R. F. <roc...@gm...>]

I also had no intention to be rude. I think that gizflo is a great starting
point, acomodate all workflows is a complex task . As said I wish to able
to colaborate instead of create a new tool . Unless we agree on this path .
Em 11/05/2015 18:48, "Henry Gomersall" <he...@ca...> escreveu:

> On 11/05/15 21:43, Christopher Felton wrote:
> > On 5/11/2015 6:34 AM, Euripedes Rocha Filho wrote:
> >> >I agree with Henry about the configuration. A .cfg or Yaml file do a
> better
> >> >job.
> >> >
> > Hey guys, I think collaborating is a good idea
> > and probably the best approach to create a tool
> > that meets the needs of many users.
> >
> > It doesn't sound like gizflo is the best starting
> > point and I am not in a position to lead a project.
> >
> > I have some short-term needs that I need to use
> > gizflo for, I will continue to make changes.  Hopefully,
> > whatever you guys come up with can be the defacto
> > tool in the future.  Keep us informed of your progress.
>
> Hi Chris, I didn't mean to sound like a dick, I'm sorry. I sent the last
> email when I was a bit short of time. I actually think gizflo looks like
> a great starting point; my point was just that now is a good time to
> fiddle with the config layout.
>
> Anyway, I too am lacking in time, so I should really shut up. My
> apologies for wading in, though clearly I'd also love to have a more
> myhdl oriented tool chain, and I dare say I'll start to commit patches
> when as and when I use something like gizflo.
>
> Cheers,
>
> Henry
>
>
> ------------------------------------------------------------------------------
> One dashboard for servers and applications across Physical-Virtual-Cloud
> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
> http://ad.doubleclick.net/ddm/clk/290420510;117567292;y
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Henry G. <he...@ca...>]

On 11/05/15 21:43, Christopher Felton wrote:
> On 5/11/2015 6:34 AM, Euripedes Rocha Filho wrote:
>> >I agree with Henry about the configuration. A .cfg or Yaml file do a better
>> >job.
>> >
> Hey guys, I think collaborating is a good idea
> and probably the best approach to create a tool
> that meets the needs of many users.
>
> It doesn't sound like gizflo is the best starting
> point and I am not in a position to lead a project.
>
> I have some short-term needs that I need to use
> gizflo for, I will continue to make changes.  Hopefully,
> whatever you guys come up with can be the defacto
> tool in the future.  Keep us informed of your progress.

Hi Chris, I didn't mean to sound like a dick, I'm sorry. I sent the last 
email when I was a bit short of time. I actually think gizflo looks like 
a great starting point; my point was just that now is a good time to 
fiddle with the config layout.

Anyway, I too am lacking in time, so I should really shut up. My 
apologies for wading in, though clearly I'd also love to have a more 
myhdl oriented tool chain, and I dare say I'll start to commit patches 
when as and when I use something like gizflo.

Cheers,

Henry

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Christopher F. <chr...@gm...>]

On 5/11/2015 6:34 AM, Euripedes Rocha Filho wrote:
> I agree with Henry about the configuration. A .cfg or Yaml file do a better
> job.
>

Hey guys, I think collaborating is a good idea
and probably the best approach to create a tool
that meets the needs of many users.

It doesn't sound like gizflo is the best starting
point and I am not in a position to lead a project.

I have some short-term needs that I need to use
gizflo for, I will continue to make changes.  Hopefully,
whatever you guys come up with can be the defacto
tool in the future.  Keep us informed of your progress.

Regards,
Chris

> Euripedes
>
> 2015-05-11 8:30 GMT-03:00 Henry Gomersall <he...@ca...>:
>
>> On 11/05/15 12:20, Euripedes Rocha Filho wrote:
>>> I will work with gizflo in the next weeks for an altera based design,
>>> simple one, to thest a new board.
>>> As a result in this discussion we can say that we'll combine efforts
>>> around gizflo?
>>
>> An issue I have with Gizflo is the config options are written in Python
>> and imported as such. Board import definitions shouldn't need to be
>> vetted for security implications.
>>
>> It would be pretty easy to fix I think at the moment. There are various
>> easy batteries-included solutions for defining configurations with Python.
>>
>> Cheers,
>>
>> Henry
>>

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Euripedes R. F. <roc...@gm...>]

I agree with Henry about the configuration. A .cfg or Yaml file do a better
job.

Euripedes

2015-05-11 8:30 GMT-03:00 Henry Gomersall <he...@ca...>:

> On 11/05/15 12:20, Euripedes Rocha Filho wrote:
> > I will work with gizflo in the next weeks for an altera based design,
> > simple one, to thest a new board.
> > As a result in this discussion we can say that we'll combine efforts
> > around gizflo?
>
> An issue I have with Gizflo is the config options are written in Python
> and imported as such. Board import definitions shouldn't need to be
> vetted for security implications.
>
> It would be pretty easy to fix I think at the moment. There are various
> easy batteries-included solutions for defining configurations with Python.
>
> Cheers,
>
> Henry
>
>
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Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Henry G. <he...@ca...>]

On 11/05/15 12:20, Euripedes Rocha Filho wrote:
> I will work with gizflo in the next weeks for an altera based design, 
> simple one, to thest a new board.
> As a result in this discussion we can say that we'll combine efforts 
> around gizflo?

An issue I have with Gizflo is the config options are written in Python 
and imported as such. Board import definitions shouldn't need to be 
vetted for security implications.

It would be pretty easy to fix I think at the moment. There are various 
easy batteries-included solutions for defining configurations with Python.

Cheers,

Henry

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Euripedes R. F. <roc...@gm...>]

I will work with gizflo in the next weeks for an altera based design,
simple one, to thest a new board.
As a result in this discussion we can say that we'll combine efforts around
gizflo?

2015-05-11 7:37 GMT-03:00 Christopher Felton <chr...@gm...>:

> On 5/9/15 9:12 AM, Jan Coombs wrote:
> > hi Chris,
> >
> >> The gizflo currently goes all the way to
> >> bitstream and adding programming should be
> >> straightforward.
> >
> >     . . .
> >
> >> The gizflo package already supports ISE, the
> >> start of Vivado, and Quartus.  It shouldn't be
> >> too difficult to add Lattice Diamond, actually
> >> I think someone already started this when the
> >> flow was part of myhdl_tools.
> >
> > I'd like to be able to distribute some fpga toys
> > with single-click rebuild.  I'm using Lattice
> > Diamond, and the Lattice (ex SiliconBlue) tools
> > to target small low power devices.
> >
> > Do you have any links to previous work?
>
> No, not right now. I will have to do some digging
> to see who was working on it and then ping them.
>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
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> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
> Deep dive visibility with transaction tracing using APM Insight.
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Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Christopher F. <chr...@gm...>]

On 5/9/15 9:12 AM, Jan Coombs wrote:
> hi Chris,
>
>> The gizflo currently goes all the way to
>> bitstream and adding programming should be
>> straightforward.
>
>     . . .
>
>> The gizflo package already supports ISE, the
>> start of Vivado, and Quartus.  It shouldn't be
>> too difficult to add Lattice Diamond, actually
>> I think someone already started this when the
>> flow was part of myhdl_tools.
>
> I'd like to be able to distribute some fpga toys
> with single-click rebuild.  I'm using Lattice
> Diamond, and the Lattice (ex SiliconBlue) tools
> to target small low power devices.
>
> Do you have any links to previous work?

No, not right now. I will have to do some digging
to see who was working on it and then ping them.

Regards,
Chris

[myhdl-list] Removal of globals

[Henry G. <he...@ca...>]

I appreciate that many of the emails I sent about eliminating globals 
were rather in the noise given they were parted of a rather protracted 
thread on the issue.

It would be great to have some feedback on the approach that I've 
implemented here:
https://github.com/hgomersall/myhdl/tree/globals_free_sim

I made various comments on the current implementation in that thread 
"Global state and multiple instances".

Cheers,

Henry

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Jan C. <jen...@mu...>]

hi Chris, 

> The gizflo currently goes all the way to
> bitstream and adding programming should be
> straightforward.

   . . .

> The gizflo package already supports ISE, the
> start of Vivado, and Quartus.  It shouldn't be
> too difficult to add Lattice Diamond, actually
> I think someone already started this when the
> flow was part of myhdl_tools.

I'd like to be able to distribute some fpga toys
with single-click rebuild.  I'm using Lattice
Diamond, and the Lattice (ex SiliconBlue) tools
to target small low power devices.  

Do you have any links to previous work?  

Either way, I'll copy the most used route in
gizflo and see if I can add paths for the tools
and boards I'm using.  Then I'll need to read
the git manual. 

Jan Coombs. 

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

> @Ben, are you adding Vivado simulator as a cosimulation option to myhdl?

We can't do this properly.  But potentially we could have a hack where both
side (Vivado and python) monitor files to see if new lines have been added.

On Wed, May 6, 2015 at 6:11 PM, Euripedes Rocha Filho <
roc...@gm...> wrote:

> I'm also interested in have a python package to handle the fpga synthesis
> flow, and will try to find some time to colaborate to it in the next weeks.
> I think that there's a common structure in the fpga flow and also believe
> that is possible to be flexible enough to meet several requirements.
>
> In the last mile every project will need to be composed by a set of
> Verilog/VHDL/ngc(?) files. We should go from this idea.
>
> I like the simulation possibilities provided by MyHDL.
> @Ben, are you adding Vivado simulator as a cosimulation option to myhdl?
>
>
>
> 2015-05-06 15:11 GMT-03:00 Christopher Felton <chr...@gm...>:
>
> <snip>
>> >
>> > We should probably combine our efforts! What are your goals? So far, the
>> > intention has to be quite limited in scope, simply allow a back
>> > verification from Vivado, with the motivation driven by the need to
>> > allow encrypted IP blocks.
>>
>> This is probably worth discussion, I have a similar
>> project as well that currently supports Quartus
>> and ISE, I will push the Vivado when I get a breathe:
>>
>> https://github.com/cfelton/gizflo
>>
>> There are 2-3 others that indicated they will be
>> contributing.
>>
>> The question will be, is there a useful project
>> structure that meets all our needs?  Or will we
>> need to settle with separate projects?
>>
>> Regards,
>> Chris
>>
>>
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> One dashboard for servers and applications across Physical-Virtual-Cloud
>> Widest out-of-the-box monitoring support with 50+ applications
>> Performance metrics, stats and reports that give you Actionable Insights
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>> _______________________________________________
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>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
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> Widest out-of-the-box monitoring support with 50+ applications
> Performance metrics, stats and reports that give you Actionable Insights
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>

Re: [myhdl-list] Global state and multiple instances

[Henry G. <he...@ca...>]

On 07/05/15 17:54, Henry Gomersall wrote:
> In a running sim, this is not necessary as the context is set up by the
> simulator (so you can merrily place now() inside instances without
> worrying, as in the example).
That is, as in the gists.

https://gist.github.com/hgomersall/350a007980972a75859c
https://gist.github.com/hgomersall/59e3d2b151e7931b1965

Cheers,

Henry

Re: [myhdl-list] Global state and multiple instances

[Henry G. <he...@ca...>]

On 07/05/15 17:44, Juan Pablo Caram wrote:
> So nothing changed on the user side. That's great.
> It will take me a while to go through the code and fully understand 
> how you accomplished it before I can provide any useful feedback.

Yes, nothing much is changed in terms of the user API.

The only real change is if you want to access the simulation parameters 
from outside the simulation (say after the sim has run, getting the 
value from now() ). Then it is necessary to renter the context.

The simulation instance is used as the context id, so it's something like:

sim.run(200)
with _simulate.simulation_context(sim):
     print now()

will print out the time corresponding to the simulation instance `sim`.

In a running sim, this is not necessary as the context is set up by the 
simulator (so you can merrily place now() inside instances without 
worrying, as in the example).

Cheers,

Henry

Re: [myhdl-list] Mixing MyHDL-generated source with other code

[Ben R. <be...@re...>]

> I think there are at least two clear packages
> here:
>
>     1. the FPGA flow automation
>     2. PLI/VPI less (no FLI) simulator (isim)

Yes, although there is some overlap in the use of the toolchain.  For
example if I want to do a timing simulation, then I would need to use the
appropriate toolchain to do the synthesis and implementation.  I would be
inclined to put the functionality to run a Vivado simulation in the Vivado
toolchain.

Under this model we would have
1. A package for toolchains (or perhaps a package for each toolchain)
2. The FPGA flow automation (making use of the appropriate toolchain)
3. PLI/VPI less simulator (making use of the appropriate toolchain)

The other big area is taking a top level description of the module and
turning that into the files required by the toolchain.
For MyHDL this is straightforward since our top level description is the
top level function along with it's arguments.
For a project that consists of VHDL and Verilog it is straightforward but
tedious to determine what files are required.  If you're using code that
adheres to the hdlmake <http://www.ohwr.org/projects/hdl-make> or fusesoc
<https://github.com/olofk/fusesoc> then things are better since you can
work out dependencies automatically.
If you have a mix of VHDL, Verilog and MyHDL, and perhaps a script to
generate some VHDL then there's no good solution that I've found, which is
why I ended up rolling my own in pyvivado.  I think what we really need is
something like a parameterized package manager than plays nicely with
hdlmake and fusesoc but is flexible enough to allow generated code.


On Thu, May 7, 2015 at 4:12 AM, Christopher Felton <chr...@gm...>
wrote:

> On 5/6/15 12:54 PM, Ben Reynwar wrote:
> > At the moment pyvivado is doing four fairly independent things for me:
> >
> > 1) I use it as a build system to keep track of which modules depend on
> > which other modules and IP blocks and to specify how files that need to
> > be generated are generated.
> > 2) I use it to run python unittests (very similar to what you do with
> > veriutils)
> > 3) I use it to automate Vivado (simulation, synthesis, implementation
> > and deployment)
> > 4) I use it to communicate with the FPGA from python.
> >
> > Things that I don't like about it are:
> > Â  - Doesn't support MyHDL yet.
> > Â  - Tests aren't interactive (i.e. I specify all the inputs and then
> > read all the outputs)
> > Â  - Too many different things rolled into one and more interdependent
> > than they could be.  It should probably be 4 python packages for those
> > 4 purposes.
>
> I think there are at least two clear packages
> here:
>
>      1. the FPGA flow automation
>      2. PLI/VPI less (no FLI) simulator (isim)
>
> It seems your and Henry's work can be combined to
> create the NoFLICosimulation and pyvivado and gizflo
> can be leveraged for the tool-flow automation?
>
> Regards,
> Chris
>
>
>
>
> ------------------------------------------------------------------------------
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Re: [myhdl-list] Global state and multiple instances

[Juan P. C. <jp...@gm...>]

So nothing changed on the user side. That's great.
It will take me a while to go through the code and fully understand how you
accomplished it before I can provide any useful feedback.
JP

On Thu, May 7, 2015 at 12:41 PM, Henry Gomersall <he...@ca...> wrote:

> On 07/05/15 15:10, Henry Gomersall wrote:
> > It's fairly clean and shouldn't break_too_  much. Most of the changes
> > are in _simulator.py.
> Not sure about the cosim stuff - that may be flaky at the moment...
>
> Henry
>
>
> ------------------------------------------------------------------------------
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>

Re: [myhdl-list] Global state and multiple instances

[Henry G. <he...@ca...>]

On 07/05/15 15:10, Henry Gomersall wrote:
> It's fairly clean and shouldn't break_too_  much. Most of the changes
> are in _simulator.py.
Not sure about the cosim stuff - that may be flaky at the moment...

Henry