myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Setting of enum values

[Christopher F. <chr...@gm...>]

>>> You should be able to use constant values in an object,
>>> this code snip might help:
>>
>> Is this a relatively recent fix?
>>
>
> Not sure and it depends on your definition
> of recent.
>
> Yes, there was a fix for constants in an object
> at some point I don't recall the time frame.
>

Looks like it was fixed for VHDL (always worked
for Verilog) here:
https://github.com/jandecaluwe/myhdl/pull/64

Regards,
Chris

Re: [myhdl-list] Setting of enum values

[Christopher F. <chr...@gm...>]

On 1/21/2016 10:38 AM, Henry Gomersall wrote:
> On 21/01/16 16:34, Christopher Felton wrote:
>> On 1/21/2016 5:15 AM, Marcel Hellwig wrote:
>>>> On 21.01.2016 09:47, Thomas Heller wrote:
>>>>>> [...]
>>>>>> I had the same problem and currently only see these two possibilities:
>>>>>>
>>>>>> 1. Import each constant and assign it in the myhdl code, like this:
>>>>>>
>>>>>> from cpumode import CpuMode
>>>>>> cpumode_User = CpuMode.User
>>>>>> ...
>>>>
>>>> ugly as hell :D but yeah, it kind of works...
>>>>
>>>>>>
>>>>>> 2. Define the constants as module level constants
>>>>>> and use 'from mymodule import *' in the myhdl code.
>>>>
>>>> I decided myself to this design. Would be nice though to have some kind
>>>> of namespace seperation.
>>>>
>> Disclaimer: I quickly review the previous posts in this
>> thread (I might not understand the intent) - if this is
>> off base ignore.
>>
>> You should be able to use constant values in an object,
>> this code snip might help:
>
> Is this a relatively recent fix?
>

Not sure and it depends on your definition
of recent.

Yes, there was a fix for constants in an object
at some point I don't recall the time frame.

Regards,
Chris

Re: [myhdl-list] Setting of enum values

[Henry G. <he...@ca...>]

On 21/01/16 16:34, Christopher Felton wrote:
> On 1/21/2016 5:15 AM, Marcel Hellwig wrote:
>> > On 21.01.2016 09:47, Thomas Heller wrote:
>>> >> [...]
>>> >> I had the same problem and currently only see these two possibilities:
>>> >>
>>> >> 1. Import each constant and assign it in the myhdl code, like this:
>>> >>
>>> >> from cpumode import CpuMode
>>> >> cpumode_User = CpuMode.User
>>> >> ...
>> >
>> > ugly as hell :D but yeah, it kind of works...
>> >
>>> >>
>>> >> 2. Define the constants as module level constants
>>> >> and use 'from mymodule import *' in the myhdl code.
>> >
>> > I decided myself to this design. Would be nice though to have some kind
>> > of namespace seperation.
>> >
> Disclaimer: I quickly review the previous posts in this
> thread (I might not understand the intent) - if this is
> off base ignore.
> 
> You should be able to use constant values in an object,
> this code snip might help:

Is this a relatively recent fix?

Cheers,

Henry

Re: [myhdl-list] pullups for inputs on CAT-Board require 2 signals per input with pullup?

[Christopher F. <chr...@gm...>]

On 1/19/2016 7:09 PM, Edward Vidal wrote:
> Hi Chris, As you recall I asked you, if the file ice40_primitives.py
> from Dave's CAT-Board/tests
>
> https://github.com/xesscorp/CAT-Board.git
>
> needed to added to the rhea package.
>

As stated before, I don't want to add this directly.  You can
use the ice40_primitives.  The goal in rhea will be to have a
generic `input_buffer` that will insert the correct primitive
depending on the board/fpga.  For your project you can use the
ice40_primitives that Dave V. has put together directly.

Hope that helps,
Chris

Re: [myhdl-list] Setting of enum values

[Christopher F. <chr...@gm...>]

On 1/21/2016 5:15 AM, Marcel Hellwig wrote:
> On 21.01.2016 09:47, Thomas Heller wrote:
>> [...]
>> I had the same problem and currently only see these two possibilities:
>>
>> 1. Import each constant and assign it in the myhdl code, like this:
>>
>> from cpumode import CpuMode
>> cpumode_User = CpuMode.User
>> ...
>
> ugly as hell :D but yeah, it kind of works...
>
>>
>> 2. Define the constants as module level constants
>> and use 'from mymodule import *' in the myhdl code.
>
> I decided myself to this design. Would be nice though to have some kind
> of namespace seperation.
>

Disclaimer: I quickly review the previous posts in this
thread (I might not understand the intent) - if this is
off base ignore.

You should be able to use constant values in an object,
this code snip might help:


     from myhdl import *

     class MyConstants(object):
         def __init__(self):
             self.const1 = int(intbv("1111_0001"))
             self.const2 = int(intbv("1010_0101"))

     def const_select(sel, x):
         const = MyConstants()

         @always_comb
         def beh_select():
             if sel == 1:
                 x.next = const.const1
             elif sel == 2:
                 x.next = const.const2
             else:
                 x.next = 0

         return beh_select


The above converts as expected.  You could also
convert the object to a tuple of ints, something
like (for this example):

     rom = [int(v) for k, v in vars(const)]

Regards,
Chris

Re: [myhdl-list] Howto Lookup-Table

[Marcel H. <1he...@in...>]

On 21.01.2016 15:28, Christopher Felton wrote:
[...]
> Yes, as you discovered dictionaries are not directly
> convertible.  The convertible types are described
> here:
> http://docs.myhdl.org/en/stable/manual/conversion.html#supported-types
> 
> This doesn't mean you can't use dicts to manage the
> information in your design it just means you are limited
> to using dicts in elaboration (outside the myhdl
> generators).

Thanks for the clarification.


> 
>> Okay, I thought, then I will just outsource the tuples to variables and
>> make a "big" if/elif switch-case. But that don't work either :/
>>
> 
> I am not sure I am following but I think you need this
> simple change
> 
>      offset = USER[rd]
>      regs[offset].next = din
>
I'm used to write everything as compact as possible (especially in
python), so this seems a bit of weird to me, but okay. It works now. :)

Thanks for the help
Marcel

Re: [myhdl-list] Howto Lookup-Table

[Christopher F. <chr...@gm...>]

On 1/21/2016 5:07 AM, Marcel Hellwig wrote:
> Hello everyone,
>
> for my current project I need some kind of lookup-table.
> Setting:
>      I have different CPU Modes and depending on the mode, I need to
> access certain registerbanks (yeah, it's an arm-ripof)
>
> My intentional idea was to create a dictionary where the keys are the
> modes and the values are the register numbers, e.g.
>
>>
>> regbank = {
>>      cpumode_User : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11,
>> R12, R13, R14, PC, CPSR),
>>      ..... }
>>
>> registers = [Signal(intbv(0)[32:]) for _ in range(37)]
>
>
> and then access them via registers[regbank[mode][rd]] whereas mode is
> the mode (just an Signal(int)) and rd is the destionation register. R0,
> R1, ... etc are ints as well
>
> This leads to:
>> Object type is not supported in this context: regbank, <type 'dict'>
>

Yes, as you discovered dictionaries are not directly
convertible.  The convertible types are described
here:
http://docs.myhdl.org/en/stable/manual/conversion.html#supported-types

This doesn't mean you can't use dicts to manage the
information in your design it just means you are limited
to using dicts in elaboration (outside the myhdl
generators).


> Okay, I thought, then I will just outsource the tuples to variables and
> make a "big" if/elif switch-case. But that don't work either :/
>

I am not sure I am following but I think you need this
simple change

     offset = USER[rd]
     regs[offset].next = din

When using a tuple-of-ints (ROM) the values can't be
accessed directly in an expression, you first have to
get the value and then use it in an expression.

The above is a FAQ, we should add it do the documentation
in the following section:

http://docs.myhdl.org/en/stable/manual/conversion_examples.html#rom-inference


Regards,
Chris

Re: [myhdl-list] Setting of enum values

[Marcel H. <1he...@in...>]

On 21.01.2016 09:47, Thomas Heller wrote:
> [...]
> I had the same problem and currently only see these two possibilities:
> 
> 1. Import each constant and assign it in the myhdl code, like this:
> 
> from cpumode import CpuMode
> cpumode_User = CpuMode.User
> ...

ugly as hell :D but yeah, it kind of works...

> 
> 2. Define the constants as module level constants
> and use 'from mymodule import *' in the myhdl code.

I decided myself to this design. Would be nice though to have some kind
of namespace seperation.


On 21.01.2016 01:33, Jan Coombs wrote:
> Agreed, it is a complex one, and I accept the reasons for not
> pursuing this



I have an Idea and would like to know your thoughts about this:

> from myhdl import enum
> 
> procmode = enum(('User', 0b10001, ('System', 0b11111), (...), ...)


so giving them tuples (or a dict) with predefined values? This means
that you can pass constant values and names to it. You can check the
nrbits and everything else while creating the enum. I find this is an
quite elegant solution. What do you thinK?


Greetings,
Marcel

[myhdl-list] Howto Lookup-Table

[Marcel H. <1he...@in...>]

Hello everyone,

for my current project I need some kind of lookup-table.
Setting:
    I have different CPU Modes and depending on the mode, I need to
access certain registerbanks (yeah, it's an arm-ripof)

My intentional idea was to create a dictionary where the keys are the
modes and the values are the register numbers, e.g.

>
> regbank = {
>     cpumode_User : (R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11,
> R12, R13, R14, PC, CPSR),
>     ..... }
>
> registers = [Signal(intbv(0)[32:]) for _ in range(37)]


and then access them via registers[regbank[mode][rd]] whereas mode is
the mode (just an Signal(int)) and rd is the destionation register. R0,
R1, ... etc are ints as well

This leads to:
> Object type is not supported in this context: regbank, <type 'dict'>

Okay, I thought, then I will just outsource the tuples to variables and
make a "big" if/elif switch-case. But that don't work either :/

> AssertionError: var MYHDL2_getRegisterbank has unexpected type <class
> 'myhdl.conversion._analyze._Rom'>
or
> Object type is not supported in this context: USER, <type 'tuple'>


This is frustrating and I don't know why, because ROM works with tuples
too. So, what kind of mistake I am doing here?

My idea would also to add a section in the examples for a LUT, because I
think that is something you use from time to time.

Thanks in advance,
Marcel


Ps. here is a gist for a better overview
https://gist.github.com/punkkeks/d09e26f67d15cd2caf6a

Re: [myhdl-list] Setting of enum values

[Thomas H. <th...@ct...>]

Am 20.01.2016 um 23:11 schrieb Marcel Hellwig:
> Hello everyone,
>
> As far as I can see, there is no action on this topic anymore. I'm
> currently encounter a Problem with exactly this.
> My Problem is, that I have some (cpu-)modes, which I'd like to have in
> an extra file, because I use them from some points in my code. So I
> create a file cpumode.py with the following content:
>
> cpumode.py:
>> class CpuMode(object):
>>      User = 0b10000
>>      FIQ = 0b10001
>>      IRQ = 0b10010
>>      Supervisor = 0b10011
>>      Abort = 0b101111
>>      Undefined = 0b11011
>>      System = 0b111111
>
> In the next file, I import it via
>
>> from cpumode import CpuMode
>
>
> Now, myhdl tells me:
>
>> myhdl.ConversionError: in file xxx.py, line 63:
>>      Unsupported attribute: User
>
> line 63:
>> if mode == CpuMode.User:

I had the same problem and currently only see these two possibilities:

1. Import each constant and assign it in the myhdl code, like this:

from cpumode import CpuMode
cpumode_User = CpuMode.User
...

2. Define the constants as module level constants
and use 'from mymodule import *' in the myhdl code.


Thomas

Re: [myhdl-list] Setting of enum values

[Jan C. <jen...@mu...>]

On Wed, 20 Jan 2016 23:11:46 +0100
Marcel Hellwig <1he...@in...> wrote:

> As far as I can see, there is no action on this topic anymore.

Agreed, it is a complex one, and I accept the reasons for not
pursuing this. Where I want to have close control of bits I
import values.  These are created using simple assignments, 
which are sometimes shortened using range(x,y,z)

> I'm currently encounter a Problem with exactly this.
> My Problem is, that I have some (cpu-)modes, which I'd like to
> have in an extra file, because I use them from some points in
> my code. So I create a file cpumode.py with the following
> content:
> 
> cpumode.py:
> > class CpuMode(object):
> >     User = 0b10000
> >     FIQ = 0b10001
> >     IRQ = 0b10010
> >     Supervisor = 0b10011
> >     Abort = 0b101111
> >     Undefined = 0b11011
> >     System = 0b111111
> 
> In the next file, I import it via
> 
> > from cpumode import CpuMode
> 
> 
> Now, myhdl tells me:
> 
> > myhdl.ConversionError: in file xxx.py, line 63:
> >     Unsupported attribute: User
> 
> line 63:
> > if mode == CpuMode.User:

I had this type of problem with VHDL, something like 'data not
locally static' but have not seen it with MyHDL.  Perhaps this
is because simple named constant values are just converted
into numbers in the Verilog or VHDL files.  

In one large processor design most of the ~24 source files
import basic configuration parameters, like buss width, and
perhaps a third import opcode constants. There seems to be no
problem using this method. 

Hope this helps, else, for sample code email me directly.

Regards, Jan Coombs.

Re: [myhdl-list] Setting of enum values

[Marcel H. <1he...@in...>]

Hello everyone,

As far as I can see, there is no action on this topic anymore. I'm
currently encounter a Problem with exactly this.
My Problem is, that I have some (cpu-)modes, which I'd like to have in
an extra file, because I use them from some points in my code. So I
create a file cpumode.py with the following content:

cpumode.py:
> class CpuMode(object):
>     User = 0b10000
>     FIQ = 0b10001
>     IRQ = 0b10010
>     Supervisor = 0b10011
>     Abort = 0b101111
>     Undefined = 0b11011
>     System = 0b111111

In the next file, I import it via

> from cpumode import CpuMode


Now, myhdl tells me:

> myhdl.ConversionError: in file xxx.py, line 63:
>     Unsupported attribute: User

line 63:
> if mode == CpuMode.User:

This is garbage... :/ If I declare User outside of the class, but
directly in the cpumode.py, the same error occurs. Only iff I delcare
User, FIQ, IRQ, ... in the same file (in this case xxx.py) it will work.

Is there any way out or thoughts about implementing a enum with given
values? (In the thread, there was a tought about exporting the Enum
class and create it via that :/

Greetings,
Marcel

Re: [myhdl-list] pullups for inputs on CAT-Board require 2 signals per input with pullup?

[Edward V. <dev...@sb...>]

Hi All,I failed to reference the exchange between Dave & Clifford Wolf at 

https://hackaday.io/project/7982-cat-board

The following is what appears in iceriver/catboard.v
SB_IO #(
  .PIN_TYPE(6'b000001),
  .PULLUP(1'b1)
) input_pin_1  (
  .PACKAGE_PIN(reset_i),
  .D_IN_0(reset)
); Thanks,
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Tuesday, January 19, 2016 6:10 PM, Edward Vidal <dev...@sb...> wrote:
 

 Hi Chris,
As you recall I asked you, if the file ice40_primitives.py from Dave's CAT-Board/tests

https://github.com/xesscorp/CAT-Board.git 

needed to added to the rhea package.

I am doing some testing and created a file

jpeg-2000-test/pc_fast_blinker_jpeg/test_top_cat.py which 

https://github.com/develone/jpeg-2000-test.git

is imported by ex_catboard_jpeg.py with the chgs below.
 
diff ex_catboard_jpeg.py pc_fast_blinker_jpeg/ex_catboard_jpeg.py
26c26
< from test_top_cat import dwt_top
---
> from test_top import dwt_top
48c48
<     brd.add_port('reset_i', 'T2')
---
>     brd.add_port('reset', 'T2')

Running the test_top_cat.py --test and looking at the reset & reset_i signals.
The signal reset is always hi.
The signal reset_i goes lo when driven by the simulation.
 
For XulA2-LX9 I used the pullup=True see the file 
jpeg-2000-test/pc_fast_blinker_jpeg/ex_jpeg_xula2.py from the repository

https://github.com/develone/jpeg-2000-test.git/
This creates the xula2.ucf
#
NET "reset" LOC = "J14"  | pullup ;
NET "si2" LOC = "M15"  | pullup ;
NET "si1" LOC = "F16"  | pullup ;
NET "si0" LOC = "E2"  | pullup ;
NET "fB3" LOC = "J16"  | pullup ;
NET "clock" LOC = "A9" ;
NET "fB1" LOC = "C16"  | pullup ;
NET "ss0" LOC = "H1"  | pullup ;
NET "fB0" LOC = "R7"  | pullup ;
NET "si3" LOC = "K16"  | pullup ;
NET "ld" LOC = "B1" ;
NET "pp0" LOC = "K15" ;
NET "fB2" LOC = "M16"  | pullup ;
#
NET "clock" TNM_NET = "clock"; 
TIMESPEC "TS_clock" = PERIOD "clock" 83.3333333 ns HIGH 50%;
# Thanks,

Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
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[myhdl-list] pullups for inputs on CAT-Board require 2 signals per input with pullup?

[Edward V. <dev...@sb...>]

Hi Chris,
As you recall I asked you, if the file ice40_primitives.py from Dave's CAT-Board/tests

https://github.com/xesscorp/CAT-Board.git 

needed to added to the rhea package.

I am doing some testing and created a file

jpeg-2000-test/pc_fast_blinker_jpeg/test_top_cat.py which 

https://github.com/develone/jpeg-2000-test.git

is imported by ex_catboard_jpeg.py with the chgs below.
 
diff ex_catboard_jpeg.py pc_fast_blinker_jpeg/ex_catboard_jpeg.py
26c26
< from test_top_cat import dwt_top
---
> from test_top import dwt_top
48c48
<     brd.add_port('reset_i', 'T2')
---
>     brd.add_port('reset', 'T2')

Running the test_top_cat.py --test and looking at the reset & reset_i signals.
The signal reset is always hi.
The signal reset_i goes lo when driven by the simulation.
 
For XulA2-LX9 I used the pullup=True see the file 
jpeg-2000-test/pc_fast_blinker_jpeg/ex_jpeg_xula2.py from the repository

https://github.com/develone/jpeg-2000-test.git/
This creates the xula2.ucf
#
NET "reset" LOC = "J14"  | pullup ;
NET "si2" LOC = "M15"  | pullup ;
NET "si1" LOC = "F16"  | pullup ;
NET "si0" LOC = "E2"  | pullup ;
NET "fB3" LOC = "J16"  | pullup ;
NET "clock" LOC = "A9" ;
NET "fB1" LOC = "C16"  | pullup ;
NET "ss0" LOC = "H1"  | pullup ;
NET "fB0" LOC = "R7"  | pullup ;
NET "si3" LOC = "K16"  | pullup ;
NET "ld" LOC = "B1" ;
NET "pp0" LOC = "K15" ;
NET "fB2" LOC = "M16"  | pullup ;
#
NET "clock" TNM_NET = "clock"; 
TIMESPEC "TS_clock" = PERIOD "clock" 83.3333333 ns HIGH 50%;
# Thanks,

Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

Re: [myhdl-list] Weird error

[Josy B. <jos...@gm...>]

 
> def dff(q,d,clk,rst):
> 
>         <at> always(clk.posedge,rst.posedge)
>        def logic():
>              if rst==1:
>                    q.next=0
>              else:
>                    q.next=d
> 
>        return logic
> 
> def param_reg(q,d,clk,rst,width=4,n=2):
> 
>       signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>       instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for 
i 
> in range(n)]
> 
>        <at> always_comb
>       def logic():
>            signal_list[0].next=d
>            q.next=signal_list[n+1]
> 
>       return logic,instance_list
> 
> but I get the following error:AlwaysCombError: signal (signal_list) 
used 
> as inout in always_comb function argument
> 
> when i change the code of param_reg to :
> 
> def param_reg(q,d,clk,rst,width=4,n=2):
> 
>       signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>       instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for 
i 
> in range(n)]
> 
>        <at> always_comb
>       def logic():
>            signal_list[0].next=d
>        <at> always_comb
>       def logic2():
>            q.next=signal_list[n+1]
> 
>       return logic,instance_list,logic2
> 
> It works fine. Do you know whats the problem?

This is a choice made by our BFDL. I suspect that at the time of MyHDL's 
initial creation it was an error (or not supported by synthesis tools) 
in Verilog. VHDL has no issue. I just tried a similar Verilog module 
with Quartus Prime, without any problem.
I commented out this section in _always_comb.py:
        inouts = v.results['inout'] | 
self.inputs.intersection(self.outputs)
        if inouts:
            raise AlwaysCombError(_error.SignalAsInout % inouts)

I currently don't have the time to make a PR for this ...

Regards,

Josy

Re: [myhdl-list] Weird error

[Merkourios K. <mer...@gm...>]

Hallo Nicolas,

Thanks for the reply.You are right it should be "q.next=signal_list[n]". 
I have corrected it after I have sent the email.


Best regards,
Merk

On 18/01/2016 01:07 μμ, Nicolas Pinault wrote:
> Le 16/01/2016 12:55, Merkourios Katsimpris a écrit :
>> Hallo guys,
>>
>> I tried to run this code:
>>
>> def dff(q,d,clk,rst):
>>
>>         @always(clk.posedge,rst.posedge)
>>         def logic():
>>               if rst==1:
>>                     q.next=0
>>               else:
>>                     q.next=d
>>
>>         return logic
>>
>>
>> def param_reg(q,d,clk,rst,width=4,n=2):
>>
>>        signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>>        instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i
>> in range(n)]
>>
>>        @always_comb
>>        def logic():
>>             signal_list[0].next=d
>>             q.next=signal_list[n+1]
>>
>>        return logic,instance_list
>>
>>
>> but I get the following error:AlwaysCombError: signal (signal_list) used
>> as inout in always_comb function argument
>>
>> when i change the code of param_reg to :
>>
>> def param_reg(q,d,clk,rst,width=4,n=2):
>>
>>        signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>>        instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i
>> in range(n)]
>>
>>        @always_comb
>>        def logic():
>>             signal_list[0].next=d
>>        @always_comb
>>        def logic2():
>>             q.next=signal_list[n+1]
>>
>>        return logic,instance_list,logic2
>>
>> It works fine. Do you know whats the problem?
> Looks like a bug. I reproduced it with latest version from github.
> However, be careful that  "q.next=signal_list[n+1]" is not correct. It 
> should be "q.next=signal_list[n]".
>
> regards,
> Nicolas
>> Thanks
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
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>> _______________________________________________
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>> .
>>
>
>
> -- 
> *Nicolas PINAULT
> R&D electronics engineer
> *** ni...@aa... <mailto:ni...@aa...>
>
> *AATON-Digital*
> 38000 Grenoble - France
> Tel +33 4 7642 9550
>
> http://www.aaton.com
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> French Technologies for Film and Digital Cinematography
>
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> @Aaton_Digital
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>
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>
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Re: [myhdl-list] Weird error

[Nicolas P. <ni...@aa...>]

Le 16/01/2016 12:55, Merkourios Katsimpris a écrit :
> Hallo guys,
>
> I tried to run this code:
>
> def dff(q,d,clk,rst):
>
>         @always(clk.posedge,rst.posedge)
>         def logic():
>               if rst==1:
>                     q.next=0
>               else:
>                     q.next=d
>
>         return logic
>
>
> def param_reg(q,d,clk,rst,width=4,n=2):
>
>        signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>        instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i
> in range(n)]
>
>        @always_comb
>        def logic():
>             signal_list[0].next=d
>             q.next=signal_list[n+1]
>
>        return logic,instance_list
>
>
> but I get the following error:AlwaysCombError: signal (signal_list) used
> as inout in always_comb function argument
>
> when i change the code of param_reg to :
>
> def param_reg(q,d,clk,rst,width=4,n=2):
>
>        signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
>        instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i
> in range(n)]
>
>        @always_comb
>        def logic():
>             signal_list[0].next=d
>        @always_comb
>        def logic2():
>             q.next=signal_list[n+1]
>
>        return logic,instance_list,logic2
>
> It works fine. Do you know whats the problem?
Looks like a bug. I reproduced it with latest version from github.
However, be careful that  "q.next=signal_list[n+1]" is not correct. It 
should be "q.next=signal_list[n]".

regards,
Nicolas
>
> Thanks
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
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> .
>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
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[myhdl-list] best practices for use of signals

[Edward V. <dev...@sb...>]

Hello All,I am trying to take advantage of the parallel feature of a FPGA.  I want to send enough data to keep the FPGA working.
My JPEG-2000 application repeats 2 step many times first on 3 values lft sam rht for even samples of image then for odd.My current code is trying to 16 of these.  Which is require many signals.  Jan has stated that signals are expensivein FPGA application. 
I moved most of the signals out of my https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top.py to  https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/jpeg_sig.py for the reason to make the code more readable.I would also like to index the signals easier.  Does any have any suggestion?My Code converts to a Verilog with this command.
python test_top.py --convertA test bench is created with 
python test_top.py --test
Also trying to determine what resources are needed in the FPGA.
Any and all help is welcomed.Thanks in advance. 
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

[myhdl-list] Weird error

[Merkourios K. <mer...@gm...>]

Hallo guys,

I tried to run this code:

def dff(q,d,clk,rst):

       @always(clk.posedge,rst.posedge)
       def logic():
             if rst==1:
                   q.next=0
             else:
                   q.next=d

       return logic


def param_reg(q,d,clk,rst,width=4,n=2):

      signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
      instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i 
in range(n)]

      @always_comb
      def logic():
           signal_list[0].next=d
           q.next=signal_list[n+1]

      return logic,instance_list


but I get the following error:AlwaysCombError: signal (signal_list) used 
as inout in always_comb function argument

when i change the code of param_reg to :

def param_reg(q,d,clk,rst,width=4,n=2):

      signal_list=[Signal(intbv(0)[width+1:]) for i in range(n+1)]
      instance_list=[dff(signal_list[i+1],signal_list[i],clk,rst) for i 
in range(n)]

      @always_comb
      def logic():
           signal_list[0].next=d
      @always_comb
      def logic2():
           q.next=signal_list[n+1]

      return logic,instance_list,logic2

It works fine. Do you know whats the problem?

Thanks

Re: [myhdl-list] parallel to serial

[Edward V. <dev...@sb...>]

Hello All,What Chris provided worked okay.Jan is correct in one of tries the code converted but would not simulate.The https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/para2ser.py was added to my 
https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_top.py  
python test_top.py --test is a simulation python test_top.py --convert generates a Verilog file.
Placing the files para2ser.py, ex_catboard_jpeg.py, jpeg.py, l2r.py, sh_reg.py, signed2twoscomplement.py, and 
test_top.py in my rhea/examples/build folder. 
This done on a Ubuntu 12.04 with Xilinx 14.6 also testing on RPi2B w/Yosys, Arachne-pnr, and ICEPack

Should I be seeing more usage with around 30 plus instances?see below 

vidal@ws009:~/wkg/rhea/examples/build$ python ex_jpeg_xula2.py 
** ToVerilogWarning: Signal is driven but not read: ss0
** ToVerilogWarning: Signal is not driven: ld
** ToVerilogWarning: Signal is not driven: si1
** ToVerilogWarning: Signal is not driven: si0
** ToVerilogWarning: Signal is not driven: sig1
** ToVerilogWarning: Signal is not driven: sig0
** ToVerilogWarning: Signal is not driven: sig3
** ToVerilogWarning: Signal is not driven: sig2
** ToVerilogWarning: Signal is not driven: sig5
** ToVerilogWarning: Signal is not driven: sig4
** ToVerilogWarning: Signal is not driven: sig7
** ToVerilogWarning: Signal is not driven: sig6
** ToVerilogWarning: Signal is driven but not read: z4
** ToVerilogWarning: Signal is driven but not read: z5
** ToVerilogWarning: Signal is driven but not read: done5
** ToVerilogWarning: Signal is driven but not read: done4
** ToVerilogWarning: Signal is driven but not read: done7
** ToVerilogWarning: Signal is driven but not read: done6
** ToVerilogWarning: Signal is driven but not read: done1
** ToVerilogWarning: Signal is driven but not read: done0
** ToVerilogWarning: Signal is driven but not read: done3
** ToVerilogWarning: Signal is driven but not read: done2
** ToVerilogWarning: Signal is driven but not read: z6
** ToVerilogWarning: Signal is driven but not read: z7
** ToVerilogWarning: Signal is driven but not read: z0
** ToVerilogWarning: Signal is driven but not read: z1
** ToVerilogWarning: Signal is driven but not read: z2
** ToVerilogWarning: Signal is driven but not read: z3
** ToVerilogWarning: Signal is not driven: fB3
** ToVerilogWarning: Signal is not driven: fB2
** ToVerilogWarning: Signal is driven but not read: po6
** ToVerilogWarning: Signal is driven but not read: po4
** ToVerilogWarning: Signal is driven but not read: po2
** ToVerilogWarning: Signal is driven but not read: po1
** ToVerilogWarning: Signal is not driven: pp0
** ToVerilogWarning: Signal is not driven: fB7
** ToVerilogWarning: Signal is not driven: si6
** ToVerilogWarning: Signal is not driven: reset
** ToVerilogWarning: Signal is not driven: si5
** ToVerilogWarning: Signal is not driven: si4
** ToVerilogWarning: Signal is driven but not read: po7
** ToVerilogWarning: Signal is driven but not read: po5
** ToVerilogWarning: Signal is driven but not read: po3
** ToVerilogWarning: Signal is driven but not read: po0
** ToVerilogWarning: Signal is not driven: si3
** ToVerilogWarning: Signal is not driven: si2
** ToVerilogWarning: Signal is not driven: fB1
** ToVerilogWarning: Signal is not driven: fB0
** ToVerilogWarning: Signal is not driven: si7
** ToVerilogWarning: Signal is not driven: fB6
** ToVerilogWarning: Signal is not driven: fB5
** ToVerilogWarning: Signal is not driven: fB4
   removing xilinx/xula2.v
   moving xula2.v --> xilinx/
Project name : xula2.xise 
Number of Slice Registers:                     0 out of  11,440    0%
Number of LUT Flip Flop pairs used:            0
Number of Slice Registers:                     0 out of  11,440    0%
Number of LUT Flip Flop pairs used:            0
{'fmax': -1, 'syn': {'dsp': (0, 2, 0), 'reg': (0, 11440, 0)}}
   removing xilinx/xula2.v
   moving xula2.v --> xilinx/
Project name : xula2.xise 
Number of Slice Registers:                     0 out of  11,440    0%
Number of LUT Flip Flop pairs used:            0
Number of Slice Registers:                     0 out of  11,440    0%
Number of LUT Flip Flop pairs used:            0
{'fmax': -1, 'syn': {'dsp': (0, 2, 0), 'reg': (0, 11440, 0)}}


Thanks for the help.
 Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Friday, January 15, 2016 3:39 PM, Jan Decaluwe <ja...@ja...> wrote:
 

 On 15/01/16 18:45, Edward Vidal wrote:
> Hello All,
> I can not believe that 3 lines are such a problem.
> This t.next = (temp[36:35]) generates  t <= temp(36-1 downto 35)(0);
> which does not appear correct.

Why not?

But still, if working with single bits, why don't you simply
assign an index instead of a slice?

> This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0);
> which be taking the lower  34 bits to upper 34 of temp.

That makes no sense in MyHDL, and will not simulate. Hence, you
cannot draw any conclusions from conversion, even if it doesn't complain.

Simulate first.

> I am using @always(clk.posedge) could this be the problem?

No.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    World-class digital design: http://www.easics.com


------------------------------------------------------------------------------
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Re: [myhdl-list] parallel to serial

[Jan D. <ja...@ja...>]

On 15/01/16 18:45, Edward Vidal wrote:
> Hello All,
> I can not believe that 3 lines are such a problem.
> This t.next = (temp[36:35]) generates   t <= temp(36-1 downto 35)(0);
> which does not appear correct.

Why not?

But still, if working with single bits, why don't you simply
assign an index instead of a slice?

> This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0);
> which be taking the lower  34 bits to upper 34 of temp.

That makes no sense in MyHDL, and will not simulate. Hence, you
cannot draw any conclusions from conversion, even if it doesn't complain.

Simulate first.

> I am using @always(clk.posedge) could this be the problem?

No.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] parallel to serial

[Christopher F. <chr...@gm...>]

On 1/15/2016 11:45 AM, Edward Vidal wrote:
> Hello All,I can not believe that 3 lines are such a problem.

I posted a short reply in the gist comments:
https://gist.github.com/develone/77732a2a1ab452e5f1f8

Re: [myhdl-list] parallel to serial

[Edward V. <dev...@sb...>]

Hello All,I can not believe that 3 lines are such a problem.This t.next = (temp[36:35]) generates   t <= temp(36-1 downto 35)(0);which does not appear correct.  This is what I t <= temp(35);
This t.next = int(temp[36:35]) generates t <= stdl(to_integer(temp(36-1 downto 35)));which I believe might be okay.
This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0);which be taking the lower  34 bits to upper 34 of temp.
I am using @always(clk.posedge) could this be the problem?
 
https://gist.github.com/develone/77732a2a1ab452e5f1f8
python gistfile1.txt --test does not perform the desired results.python gistfile1.txt --convert generates the Verilog & VHDL files Thanks for all the help.
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Friday, January 15, 2016 1:16 AM, Jan Decaluwe <ja...@ja...> wrote:
 

 Also, why not assign single bits to indices
instead of slices, like in the VHDL?

On 15/01/16 03:58, Christopher Felton wrote:
> Edward,
>
> When assign intbv bit slices you need to:
>
>      temp.next[1:0] = 0
>
> Hope that helps,
> Chris
>
> On 1/14/16 8:26 PM, Edward Vidal wrote:
>> Hello All,
>> I found this VHDL code on the web.
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity piso is
>>      port(
>>            clk,load  : in std_logic;
>>            pi        : in std_logic_vector(35 downto 0);
>>            so        : out std_logic);
>> end piso;
>>
>> architecture arch of piso is
>>
>>      signal t  : std_logic;
>>      signal temp: std_logic_vector(35 downto 0);
>>
>> begin
>>
>>      process (clk,pi,load)
>>      begin
>>          if (load='1') then
>>                temp(35 downto 0) <= pi(35 downto 0);
>>          elsif (CLK'event and CLK='1') then
>>                t <= temp(35);
>>                temp(35 downto 1) <= temp(34 downto 0);
>>                temp(0) <= '0';
>>          end if;
>>      end process;
>>
>> so <= t;
>>
>> end arch;
>> I create a test bench in ise and it appears to be okay.
>> from myhdl import *
>> import argparse
>> W0 = 36
>> pp0 = Signal(intbv(0)[W0:])
>> ss0 = Signal(bool(0))
>> clk = Signal(bool(0))
>> ld = Signal(bool(0))
>> def cliparse():
>>      parser = argparse.ArgumentParser()
>>      parser.add_argument("--build", default=False, action='store_true')
>>      parser.add_argument("--test", default=False, action='store_true')
>>      parser.add_argument("--convert", default=False, action='store_true')
>>      args = parser.parse_args()
>>      return args
>>
>> def para2ser(clk, pp0, ss0, ld):
>>
>>      t = Signal(bool(0))
>>      temp = Signal(intbv(0)[W0:])
>>      @always(clk.posedge)
>>      def logic():
>>
>>          if (ld == 1):
>>            temp[36:0].next = pp0[36:0]
>>          else:
>>            t.next = int(temp[36:35])
>>
>>            temp[36:1].next = temp[35:0]
>>            temp[1:].next = int(0)
>>          ss0.next = t
>>
>>      return logic
>>
>> def tb(clk, pp0, ss0, ld):
>>      instance_1 = para2ser(clk, pp0, ss0, ld)
>>
>>      @always(delay(10))
>>      def clkgen():
>>          clk.next = not clk
>>      @instance
>>      def stimulus():
>>
>>          pp0.next = 34359738368
>>          yield clk.posedge
>>          ld.next = 1
>>          yield clk.posedge
>>          ld.next = 0
>>          yield clk.posedge
>>          print ("%s %d") % (bin(pp0,36), ss0 )
>>          for i in range(36):
>>              yield clk.posedge
>>              print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
>>          raise StopSimulation
>>
>>      return instances()
>> def convert(args):
>>      toVHDL(para2ser,clk, pp0, ss0, ld)
>>      toVerilog(para2ser,clk, pp0, ss0, ld)
>>
>>
>> def main():
>>      args = cliparse()
>>      if args.test:
>>          tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>>          sim = Simulation(tb_fsm)
>>          sim.run()
>>      if args.convert:
>>          convert(args)
>>
>> if __name__ == '__main__':
>>      main()
>> Can someone tell me what I am doing wrong?
>> I think it this line
>> temp[1:].next = int(0)
>> I have tried without the int and I get the same results when I run
>> python para2ser.py --test
>> Thanks
>> Regards,
>> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>>
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    World-class digital design: http://www.easics.com


------------------------------------------------------------------------------
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Monitor end-to-end web transactions and take corrective actions now
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Re: [myhdl-list] parallel to serial

[Jan D. <ja...@ja...>]

Also, why not assign single bits to indices
instead of slices, like in the VHDL?

On 15/01/16 03:58, Christopher Felton wrote:
> Edward,
>
> When assign intbv bit slices you need to:
>
>       temp.next[1:0] = 0
>
> Hope that helps,
> Chris
>
> On 1/14/16 8:26 PM, Edward Vidal wrote:
>> Hello All,
>> I found this VHDL code on the web.
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity piso is
>>       port(
>>            clk,load  : in std_logic;
>>            pi        : in std_logic_vector(35 downto 0);
>>            so        : out std_logic);
>> end piso;
>>
>> architecture arch of piso is
>>
>>       signal t   : std_logic;
>>       signal temp: std_logic_vector(35 downto 0);
>>
>> begin
>>
>>      process (clk,pi,load)
>>       begin
>>          if (load='1') then
>>                temp(35 downto 0) <= pi(35 downto 0);
>>          elsif (CLK'event and CLK='1') then
>>                t <= temp(35);
>>                temp(35 downto 1) <= temp(34 downto 0);
>>                temp(0) <= '0';
>>          end if;
>>       end process;
>>
>> so <= t;
>>
>> end arch;
>> I create a test bench in ise and it appears to be okay.
>> from myhdl import *
>> import argparse
>> W0 = 36
>> pp0 = Signal(intbv(0)[W0:])
>> ss0 = Signal(bool(0))
>> clk = Signal(bool(0))
>> ld = Signal(bool(0))
>> def cliparse():
>>       parser = argparse.ArgumentParser()
>>       parser.add_argument("--build", default=False, action='store_true')
>>       parser.add_argument("--test", default=False, action='store_true')
>>       parser.add_argument("--convert", default=False, action='store_true')
>>       args = parser.parse_args()
>>       return args
>>
>> def para2ser(clk, pp0, ss0, ld):
>>
>>       t = Signal(bool(0))
>>       temp = Signal(intbv(0)[W0:])
>>       @always(clk.posedge)
>>       def logic():
>>
>>           if (ld == 1):
>>             temp[36:0].next = pp0[36:0]
>>           else:
>>             t.next = int(temp[36:35])
>>
>>             temp[36:1].next = temp[35:0]
>>             temp[1:].next = int(0)
>>           ss0.next = t
>>
>>       return logic
>>
>> def tb(clk, pp0, ss0, ld):
>>       instance_1 = para2ser(clk, pp0, ss0, ld)
>>
>>       @always(delay(10))
>>       def clkgen():
>>           clk.next = not clk
>>       @instance
>>       def stimulus():
>>
>>           pp0.next = 34359738368
>>           yield clk.posedge
>>           ld.next = 1
>>           yield clk.posedge
>>           ld.next = 0
>>           yield clk.posedge
>>           print ("%s %d") % (bin(pp0,36), ss0 )
>>           for i in range(36):
>>               yield clk.posedge
>>               print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
>>           raise StopSimulation
>>
>>       return instances()
>> def convert(args):
>>       toVHDL(para2ser,clk, pp0, ss0, ld)
>>       toVerilog(para2ser,clk, pp0, ss0, ld)
>>
>>
>> def main():
>>       args = cliparse()
>>       if args.test:
>>          tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>>          sim = Simulation(tb_fsm)
>>          sim.run()
>>       if args.convert:
>>           convert(args)
>>
>> if __name__ == '__main__':
>>       main()
>> Can someone tell me what I am doing wrong?
>> I think it this line
>> temp[1:].next = int(0)
>> I have tried without the int and I get the same results when I run
>> python para2ser.py --test
>> Thanks
>> Regards,
>> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>>
>>
>> ------------------------------------------------------------------------------
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>>
>>
>>
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>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
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>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Unsupported list comprehension form

[Christopher F. <chr...@gm...>]

On 1/14/16 9:37 PM, Jock Tanner wrote:
> Chris, thank you for your swift reply!
>

That was a little bit of luck :)

> Speaking of boolean logic in Python, all() and any() seemed so
> well-placed and pythonic to me, I just could not imagine they are not
> supported.

Might be so, but it will need to be a future enhancement.
The functions (any and all) need to be compiled to synthesizable
Verilog and VHDL.

Let us know if you have any other questions,
Chris