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From: Christopher F. <chr...@gm...> - 2016-01-27 17:57:49
|
> My question, what would taking all of time? The pypy jit has a "warm-up" time it will not improve run-time on simulations that execute quickly (less than a minute?). Regards, Chris |
From: Edward V. <dev...@sb...> - 2016-01-27 16:01:59
|
Hello All, When you convert to Verilog, I see that `timescale 1ns/10ps near the top of the file .I don't see any timing information when you convert to VHDL. On the CAT-Board the default clock is 100MHz & on XulA2-LX9 the default clock is 12MHz.With the DCM I convert to 120MHz. For my simulation my clock is always 20nsec or 50MHz. Why? Can someone explain? @always(delay(10)) def clkgen(): clock.next = not clock If my simulation takes 1m35.611s using pypy, but total simulation time is 9139190 ns. What is the FPGA time? What is taking most of time? Modified to send more values to simulation. Now pypy is 2.3 times faster than python. pi@mysshserver ~/jpeg-2000-test/pc_fast_blinker_jpeg $ time python test_top.py --test real 3m38.582s user 3m36.950s sys 0m0.630s pi@mysshserver ~/jpeg-2000-test/pc_fast_blinker_jpeg $ rm -f tb.vcd*pi@mysshserver ~/jpeg-2000-test/pc_fast_blinker_jpeg $ time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top.py --test real 1m35.611s user 1m34.780s sys 0m0.800s Thanks, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, January 26, 2016 2:51 PM, Edward Vidal <dev...@sb...> wrote: Hello All,I was reading David's post and found it very interesting. I tested on a RPi2B and did not get the results that David posted. At first, I thought the Pillow was taking all of time. My question, what would taking all of time? These are the steps that I used. Testing pypy on RPi2B jessie >From the site below http://pypy.org/download.html Python2.7 compatible PyPy 4.0.1 https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 wget https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 bzip2 -d pypy-4.0.1-linux-armhf-raspbian.tar.bz2 cd /opt/ sudo tar xvf /home/pi/pypy-4.0.1-linux-armhf-raspbian.tar Needed to install myhdl in pypy cd ~/myhdl/ sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy setup.py install Needed to install pip in pypy wget https://bootstrap.pypa.io/get-pip.py sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy get-pip.py Needed to install Pillow in pypy sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy -m pip install Pillow ls /opt/pypy-4.0.1-linux-armhf-raspbian/site-packages/ easy_install.py _markerlib myhdl-1.0dev-py2.7.egg-info Pillow-3.1.0.dist-info pip-8.0.2.dist-info README setuptools-19.6.dist-info wheel-0.26.0.dist-info easy_install.pyc myhdl PIL pip pkg_resources setuptools wheel Testing the times to run with python & pypy time python test_top.py --test real 0m8.363s user 0m8.210s sys 0m0.080s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top.py --test real 0m40.811s user 0m38.620s sys 0m0.480s I created a version that did not use the Image libtime python nopil_test_top.py --test real 0m7.943s user 0m7.790s sys 0m0.140s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy nopil_test_top.py --test real 0m26.320s user 0m26.060s sys 0m0.220s As before the pypy took longer than the python one. It appears that the Image reading only took less than .5 sec. Did I fail to do something?https://github.com/develone/jpeg-2000-test/tree/master/pc_fast_blinker_jpeg Do you not get the benefit, until you exceed the time, to convert the python to compiled? Initially I was only testing a few values. To do the complete image the test bench will grow very quickly. Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, January 26, 2016 8:44 AM, David Belohrad <da...@be...> wrote: belohrad@beesknees:~/git/didt/MyHDL/FIR$ pypy --version Python 2.7.8 (2.4.0+dfsg-3, Dec 20 2014, 13:30:46) [PyPy 2.4.0 with GCC 4.9.2] debian (testing?) Christopher Felton <chr...@gm...> writes: > On 1/26/2016 8:51 AM, David Belohrad wrote: >> Just checked >> >> and it seems that it improves performance by roughly 8 times! That is >> indeed massive and I think I'm around the times I get with modelsim. >> > > Which version of pypy did you use? > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Edward V. <dev...@sb...> - 2016-01-26 21:51:34
|
Hello All,I was reading David's post and found it very interesting. I tested on a RPi2B and did not get the results that David posted. At first, I thought the Pillow was taking all of time. My question, what would taking all of time? These are the steps that I used. Testing pypy on RPi2B jessie >From the site below http://pypy.org/download.html Python2.7 compatible PyPy 4.0.1 https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 wget https://bitbucket.org/pypy/pypy/downloads/pypy-4.0.1-linux-armhf-raspbian.tar.bz2 bzip2 -d pypy-4.0.1-linux-armhf-raspbian.tar.bz2 cd /opt/ sudo tar xvf /home/pi/pypy-4.0.1-linux-armhf-raspbian.tar Needed to install myhdl in pypy cd ~/myhdl/ sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy setup.py install Needed to install pip in pypy wget https://bootstrap.pypa.io/get-pip.py sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy get-pip.py Needed to install Pillow in pypy sudo /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy -m pip install Pillow ls /opt/pypy-4.0.1-linux-armhf-raspbian/site-packages/ easy_install.py _markerlib myhdl-1.0dev-py2.7.egg-info Pillow-3.1.0.dist-info pip-8.0.2.dist-info README setuptools-19.6.dist-info wheel-0.26.0.dist-info easy_install.pyc myhdl PIL pip pkg_resources setuptools wheel Testing the times to run with python & pypy time python test_top.py --test real 0m8.363s user 0m8.210s sys 0m0.080s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy test_top.py --test real 0m40.811s user 0m38.620s sys 0m0.480s I created a version that did not use the Image libtime python nopil_test_top.py --test real 0m7.943s user 0m7.790s sys 0m0.140s time /opt/pypy-4.0.1-linux-armhf-raspbian/bin/pypy nopil_test_top.py --test real 0m26.320s user 0m26.060s sys 0m0.220s As before the pypy took longer than the python one. It appears that the Image reading only took less than .5 sec. Did I fail to do something?https://github.com/develone/jpeg-2000-test/tree/master/pc_fast_blinker_jpeg Do you not get the benefit, until you exceed the time, to convert the python to compiled? Initially I was only testing a few values. To do the complete image the test bench will grow very quickly. Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Tuesday, January 26, 2016 8:44 AM, David Belohrad <da...@be...> wrote: belohrad@beesknees:~/git/didt/MyHDL/FIR$ pypy --version Python 2.7.8 (2.4.0+dfsg-3, Dec 20 2014, 13:30:46) [PyPy 2.4.0 with GCC 4.9.2] debian (testing?) Christopher Felton <chr...@gm...> writes: > On 1/26/2016 8:51 AM, David Belohrad wrote: >> Just checked >> >> and it seems that it improves performance by roughly 8 times! That is >> indeed massive and I think I'm around the times I get with modelsim. >> > > Which version of pypy did you use? > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. Signup Now! http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 _______________________________________________ myhdl-list mailing list myh...@li... https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: David B. <da...@be...> - 2016-01-26 15:43:55
|
belohrad@beesknees:~/git/didt/MyHDL/FIR$ pypy --version Python 2.7.8 (2.4.0+dfsg-3, Dec 20 2014, 13:30:46) [PyPy 2.4.0 with GCC 4.9.2] debian (testing?) Christopher Felton <chr...@gm...> writes: > On 1/26/2016 8:51 AM, David Belohrad wrote: >> Just checked >> >> and it seems that it improves performance by roughly 8 times! That is >> indeed massive and I think I'm around the times I get with modelsim. >> > > Which version of pypy did you use? > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2016-01-26 15:00:20
|
On 1/26/2016 8:51 AM, David Belohrad wrote: > Just checked > > and it seems that it improves performance by roughly 8 times! That is > indeed massive and I think I'm around the times I get with modelsim. > Which version of pypy did you use? Regards, Chris |
From: David B. <da...@be...> - 2016-01-26 14:55:41
|
Just checked and it seems that it improves performance by roughly 8 times! That is indeed massive and I think I'm around the times I get with modelsim. belohrad@beesknees:~/git/didt/MyHDL/FIR$ time pypy ./FIR_tb.py Working Loaded 891 coefficients Done real 0m19.081s user 0m16.208s sys 0m0.640s belohrad@beesknees:~/git/didt/MyHDL/FIR$ time python ./FIR_tb.py Working Loaded 891 coefficients Done real 2m21.629s user 2m17.020s sys 0m1.476s belohrad@beesknees:~/git/didt/MyHDL/FIR$ .d. Christopher Felton <chr...@gm...> writes: > On 1/26/2016 2:13 AM, David Belohrad wrote: >> i've been fiddling with myhdl for about a week or so. I've tried to >> do some real stuff I do at work using myhdl. As a part of the project >> involves FIR filtering, I have used the example found on Christopher >> Felton's page (https://bitbucket.org/cfelton/examples) and hacked >> away m_firfilt entity using my own coefficients. Now, my filter has >> 891 taps and I've tried to simulate using a testbench how it reacts >> on unit-amplitude (it is a bandpass) input signal. >> >> It works great, at the same time it takes 'ages'. Simulation of such >> filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times >> longer than I do with modelsim (from mentor). > > If you haven't seen this page it has some useful information: > http://www.myhdl.org/docs/performance.html > > >> >> So I wanted to check, whether it is feasible to use cython for these >> things. Following >> http://docs.cython.org/src/tutorial/cython_tutorial.html I hae >> created the setup and compiled in-the module using build_ext >> --inplace. >> > > I have not tried cython but I won't be surprised that > it would fail. It seems reasonable that you could > maybe compile only the function > > As far as the error posted, it seems the cython changed > the function somehow but that is just a guess. > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: David B. <da...@be...> - 2016-01-26 14:05:08
|
Ok, It seems that I have missed that page. I'll check with PyPy then. Thanks .d. Christopher Felton <chr...@gm...> writes: > On 1/26/2016 2:13 AM, David Belohrad wrote: >> i've been fiddling with myhdl for about a week or so. I've tried to >> do some real stuff I do at work using myhdl. As a part of the project >> involves FIR filtering, I have used the example found on Christopher >> Felton's page (https://bitbucket.org/cfelton/examples) and hacked >> away m_firfilt entity using my own coefficients. Now, my filter has >> 891 taps and I've tried to simulate using a testbench how it reacts >> on unit-amplitude (it is a bandpass) input signal. >> >> It works great, at the same time it takes 'ages'. Simulation of such >> filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times >> longer than I do with modelsim (from mentor). > > If you haven't seen this page it has some useful information: > http://www.myhdl.org/docs/performance.html > > >> >> So I wanted to check, whether it is feasible to use cython for these >> things. Following >> http://docs.cython.org/src/tutorial/cython_tutorial.html I hae >> created the setup and compiled in-the module using build_ext >> --inplace. >> > > I have not tried cython but I won't be surprised that > it would fail. It seems reasonable that you could > maybe compile only the function > > As far as the error posted, it seems the cython changed > the function somehow but that is just a guess. > > Regards, > Chris > > > ------------------------------------------------------------------------------ > Site24x7 APM Insight: Get Deep Visibility into Application Performance > APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month > Monitor end-to-end web transactions and take corrective actions now > Troubleshoot faster and improve end-user experience. Signup Now! > http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140 > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list |
From: Christopher F. <chr...@gm...> - 2016-01-26 13:36:04
|
On 1/26/2016 7:29 AM, Henry Gomersall wrote: > I'm somewhat unfamiliar with the tracing code, but it is (at least it > used to be) necessary to manually call the _finalize method on the > simulator before being able to run it again. I assume this carries > through to the trace code? > No not true in most cases, there was a bug that was discovered when using "pause" (only run for a certain duration). There is an issue for this: https://github.com/jandecaluwe/myhdl/issues/104 It is a good issue for a new contributor. Regards, Chris |
From: Henry G. <he...@ca...> - 2016-01-26 13:29:51
|
On 25/01/16 19:14, Marcel Hellwig wrote: > I use python unittest for testing things and sometimes I want to have a > closer look, why something fails and create a vcd dump. > The problem is, when I want to dump multiple test-cases, this won't > work, because of > >> > ERROR: test_write_read (__main__.MyTestCase) >> > ---------------------------------------------------------------------- >> > Traceback (most recent call last): >> > File "test_registerbank.py", line 30, in wrapper >> > return Simulation(self.dut_cl, clkGen, stimulus).run() >> > File >> > "/home/marcel/projects/micro/VE2/lib/python2.7/site-packages/myhdl/_Simulation.py", >> > line 129, in run >> > _extend(s._update()) >> > File >> > "/home/marcel/projects/micro/VE2/lib/python2.7/site-packages/myhdl/_Signal.py", >> > line 201, in _update >> > self._printVcd() >> > File >> > "/home/marcel/projects/micro/VE2/lib/python2.7/site-packages/myhdl/_Signal.py", >> > line 321, in _printVcdBit >> > print("%d%s" % (self._val, self._code), file=sim._tf) >> > ValueError: I/O operation on closed file > Is there a change to do a clean shutdown of the old trace-run and start > a new one (e.g. putting that code in setup and teardown method of the > testcase) I'm somewhat unfamiliar with the tracing code, but it is (at least it used to be) necessary to manually call the _finalize method on the simulator before being able to run it again. I assume this carries through to the trace code? Henry |
From: Christopher F. <chr...@gm...> - 2016-01-26 13:13:40
|
On 1/26/2016 2:13 AM, David Belohrad wrote: > i've been fiddling with myhdl for about a week or so. I've tried to > do some real stuff I do at work using myhdl. As a part of the project > involves FIR filtering, I have used the example found on Christopher > Felton's page (https://bitbucket.org/cfelton/examples) and hacked > away m_firfilt entity using my own coefficients. Now, my filter has > 891 taps and I've tried to simulate using a testbench how it reacts > on unit-amplitude (it is a bandpass) input signal. > > It works great, at the same time it takes 'ages'. Simulation of such > filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times > longer than I do with modelsim (from mentor). If you haven't seen this page it has some useful information: http://www.myhdl.org/docs/performance.html > > So I wanted to check, whether it is feasible to use cython for these > things. Following > http://docs.cython.org/src/tutorial/cython_tutorial.html I hae > created the setup and compiled in-the module using build_ext > --inplace. > I have not tried cython but I won't be surprised that it would fail. It seems reasonable that you could maybe compile only the function As far as the error posted, it seems the cython changed the function somehow but that is just a guess. Regards, Chris |
From: Jan C. <jen...@mu...> - 2016-01-26 13:12:52
|
On Tue, 26 Jan 2016 09:13:16 +0100 David Belohrad <da...@be...> wrote: > It works great, at the same time it takes 'ages'. Simulation > of such filter with roughly 5000 clock cycles takes almost 2 > minutes. 4 times longer than I do with modelsim (from mentor). > > So I wanted to check, whether it is feasible to use cython for > these things. Following > http://docs.cython.org/src/tutorial/cython_tutorial.html I hae > created the setup and compiled in-the module using build_ext Might this help a little: http://www.myhdl.org/docs/performance.html Jan Coombs |
From: Christopher F. <chr...@gm...> - 2016-01-26 13:00:30
|
On 1/25/2016 1:14 PM, Marcel Hellwig wrote: > Hello everyone, > > I use python unittest for testing things and sometimes I want to have a > closer look, why something fails and create a vcd dump. > The problem is, when I want to dump multiple test-cases, this won't > work, because of > I don't use unittest, I have been using pytest I don't know what might be going on. Others have used unittest and it is used in some of the "core" tests in the myhdl test suite. > > Is there a change to do a clean shutdown of the old trace-run and start > a new one (e.g. putting that code in setup and teardown method of the > testcase) > This seems odd, when the simulation ends it should clean up, I imagine it is no different that the pytest case that run multiple simulations with tracing. As an example I added a second test to the gist used in the other thread, if run with pytest (`>> py.test constant_type.py`) the test runs and creates two VCD files. https://gist.github.com/cfelton/50cb0fbed5f188fcc1bb If you have a sandbox example that fails with unittest we can create an issue for it. Regards, Chris |
From: David B. <da...@be...> - 2016-01-26 08:43:03
|
Dear All, i've been fiddling with myhdl for about a week or so. I've tried to do some real stuff I do at work using myhdl. As a part of the project involves FIR filtering, I have used the example found on Christopher Felton's page (https://bitbucket.org/cfelton/examples) and hacked away m_firfilt entity using my own coefficients. Now, my filter has 891 taps and I've tried to simulate using a testbench how it reacts on unit-amplitude (it is a bandpass) input signal. It works great, at the same time it takes 'ages'. Simulation of such filter with roughly 5000 clock cycles takes almost 2 minutes. 4 times longer than I do with modelsim (from mentor). So I wanted to check, whether it is feasible to use cython for these things. Following http://docs.cython.org/src/tutorial/cython_tutorial.html I hae created the setup and compiled in-the module using build_ext --inplace. All that works OK, but then I tried to import the compiled module in python, and I get: -------------------------------------------------------------------------------- >>> import FIR_tb Working Loaded 891 coefficients Traceback (most recent call last): File "<stdin>", line 1, in <module> File "FIR_tb.pyx", line 46, in init FIR_tb (FIR_tb.c:2580) tbm = traceSignals(tb) File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_traceSignals.py", line 85, in __call__ h = _HierExtr(name, dut, *args, **kwargs) File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_extractHierarchy.py", line 238, in __init__ _top = dut(*args, **kwargs) File "FIR_tb.pyx", line 19, in FIR_tb.tb (FIR_tb.c:1720) @always(delay(10)) File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/_always.py", line 54, in _always_decorator raise AlwaysError(_error.ArgType) myhdl.AlwaysError: decorated object should be a classic (non-generator) function -------------------------------------------------------------------------------- for a testbench, which works OK when ran as a python module (non-compiled). For the sake of completeness here is the testbench (the entity itself is the same as in Christopher's examples) -------------------------------------------------------------------------------- from myhdl import * from FIR import * print "Working" def tb(): # read FIR coeffs coeffs = map(int, open("/home/belohrad/git/didt/Python/firfilter/filter_coefficients_newline.txt", "rt").readlines()) print "Loaded ", len(coeffs), " coefficients" DxD, QxD = [Signal(intbv(0)[32:0].signed()) for x in xrange(2)] ResetxRN = ResetSignal(0, active = 0, async=True) ClkxC = Signal(bool(0)) i_fir = m_firfilt (ClkxC, ResetxRN, DxD, QxD, coeffs) @always(delay(10)) def driveClk(): ClkxC.next = not ClkxC @instance def tbi(): ResetxRN.next = 0 DxD.next = 0 yield(delay(150)) yield (ClkxC.posedge) ResetxRN.next = 1 yield (ClkxC.posedge) # test unity but this is a band-pass filter for i in xrange(4906): DxD.next = 1 yield (ClkxC.posedge) DxD.next = 0 yield (ClkxC.posedge) DxD.next = -1 yield (ClkxC.posedge) DxD.next = 0 yield (ClkxC.posedge) raise StopSimulation() return tbi, driveClk, i_fir tbm = traceSignals(tb) sim = Simulation(tbm).run() print "Done" -------------------------------------------------------------------------------- Now, the error message is very cryptic to me. Is there anyone who tried to use cython for simulation? Is this error fatal and I cannot use cython at all due to some technical restrictions? Thanks .david. |
From: Marcel H. <1he...@in...> - 2016-01-25 19:14:18
|
Hello everyone, I use python unittest for testing things and sometimes I want to have a closer look, why something fails and create a vcd dump. The problem is, when I want to dump multiple test-cases, this won't work, because of > ERROR: test_write_read (__main__.MyTestCase) > ---------------------------------------------------------------------- > Traceback (most recent call last): > File "test_registerbank.py", line 30, in wrapper > return Simulation(self.dut_cl, clkGen, stimulus).run() > File > "/home/marcel/projects/micro/VE2/lib/python2.7/site-packages/myhdl/_Simulation.py", > line 129, in run > _extend(s._update()) > File > "/home/marcel/projects/micro/VE2/lib/python2.7/site-packages/myhdl/_Signal.py", > line 201, in _update > self._printVcd() > File > "/home/marcel/projects/micro/VE2/lib/python2.7/site-packages/myhdl/_Signal.py", > line 321, in _printVcdBit > print("%d%s" % (self._val, self._code), file=sim._tf) > ValueError: I/O operation on closed file Is there a change to do a clean shutdown of the old trace-run and start a new one (e.g. putting that code in setup and teardown method of the testcase) Regards, Marcel |
From: Edward V. <dev...@sb...> - 2016-01-23 17:59:16
|
Hi All,As I said in the previous e-mail. For testing just para2ser on Xula2 & CAT-Board To get a bit (Xula2-LX9) or bin (CAT-Board) file I use "python ex_xula_sending.py" with Xilinx Tools on a Ubuntu system. On a RPi2B with Yosys, Arachne-pnr, IcePack "python ex_sending.py" creates the files to program the ICE40. The gpio_test.py is used to read the GPIO on the RPi2B. Are you using you using ICECube2 to generate a bin file for ICE40? I have been trying to get this installed on my Ubuntu system. The Diamond software installed I downloaded "diamond_3_6-base_x64-83-4-x86_64-linux.rpm" which I converted with alien --scriptsdiamond_3_6-base_x64-83-4-x86_64-linux.rpm diamond-3-6-base-x64_3.6-84_amd64.debgenerated with dpkg -i diamond-3-6-base-x64_3.6-84_amd64.debThe license.dat that has VENDOR_STRING="ispLEVER System with Synplicity \ Pro 1" HOSTID=6c626def84d9 was used for Diamond. sudo cplattice/diamond/license.dat/usr/local/diamond/3.6_x64/bin/lin64/../../license/ When I execute "/usr/local/diamond/3.6_x64/bin/lin64/diamond" my diamond gui appears. I downloaded iCEcube2_2015-08.tgz. After extraction I get iCEcube2setup_Oct_14_2015_1508.When I execute as root ./iCEcube2setup_Oct_14_2015_1508 bash: ./iCEcube2setup_Oct_14_2015_1508: No such file or directory What am I missing? Does anyone have any ideas what I am doing wrong? Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Saturday, January 23, 2016 10:14 AM, Jan Coombs <jen...@mu...> wrote: On Sat, 23 Jan 2016 15:39:34 +0000 (UTC) Edward Vidal <dev...@sb...> wrote: > Hi All, > Most of the files in the pc_fast_blinker_jpeg folder have 2 > options --test to run a simulation > > and --convert to create a Verilog file. Trying to follow > Chris's examples. Ok, it is all new to me. Next time perhaps you could give clear instructions. I missed the opportunity to interpret: Hello All, ran python test_sending31.py --test which generates tb.vcd into: Hello All, ran python test_sending31.py --test which generates tb.vcd I now have a tb.vcd file, so feel that with this mornings work, and your additional hint I can now re-create your work. > The file test_top.py imports several files > > > from jpeg import dwt > from signed2twoscomplement import signed2twoscomplement > from l2r import lift2res > from sh_reg import ShiftReg, toSig > from para2ser import para2ser > from div_clk import div_4 > from jpeg_sig import * [Did I need to know that?] > > Running "python test_top.py --test" is my overall goal. Ok dune it, seems to work, if this is what you expected: jan:pc_fast_blinker_jpeg$ jan:pc_fast_blinker_jpeg$ python test_top.py --test 256 256 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 1 1 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010100100 164 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 1 5 31 bits 0000000000000001111010100100010 0 4 31 bits 0000000000000011110101001000101 0 3 31 bits 0000000000000111101010010001010 1 2 31 bits 0000000000001111010100100010100 0 1 LSB sam 0000000000011110101001000101001 0 0 Left 010011100 156 31 bits 0000000000111101010010001010010 0 8 31 bits 0000000001111010100100010100100 1 7 31 bits 0000000011110101001000101001000 0 6 31 bits 0000000111101010010001010010001 0 5 31 bits 0000001111010100100010100100010 1 4 31 bits 0000011110101001000101001000100 1 3 31 bits 0000111101010010001010010001001 1 2 31 bits 0001111010100100010100100010011 0 1 LSB lft 0011110101001000101001000100111 0 0 fB0 0 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 1 1 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010100100 164 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 1 5 31 bits 0000000000000001111010100100010 0 4 31 bits 0000000000000011110101001000101 0 3 31 bits 0000000000000111101010010001010 1 2 31 bits 0000000000001111010100100010100 0 1 LSB sam 0000000000011110101001000101001 0 0 Left 010100100 164 31 bits 0000000000111101010010001010010 0 8 31 bits 0000000001111010100100010100100 1 7 31 bits 0000000011110101001000101001000 0 6 31 bits 0000000111101010010001010010001 1 5 31 bits 0000001111010100100010100100010 0 4 31 bits 0000011110101001000101001000101 0 3 31 bits 0000111101010010001010010001010 1 2 31 bits 0001111010100100010100100010100 0 1 LSB lft 0011110101001000101001000101001 0 0 fB1 0 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 0 0 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010011100 156 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 0 5 31 bits 0000000000000001111010100100010 1 4 31 bits 0000000000000011110101001000100 1 3 31 bits 0000000000000111101010010001001 1 2 31 bits 0000000000001111010100100010011 0 1 LSB sam 0000000000011110101001000100111 0 0 Left 010100100 164 31 bits 0000000000111101010010001001110 0 8 31 bits 0000000001111010100100010011100 1 7 31 bits 0000000011110101001000100111000 0 6 31 bits 0000000111101010010001001110001 1 5 31 bits 0000001111010100100010011100010 0 4 31 bits 0000011110101001000100111000101 0 3 31 bits 0000111101010010001001110001010 1 2 31 bits 0001111010100100010011100010100 0 1 LSB lft 0011110101001000100111000101001 0 0 fB2 0 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 0 0 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010011100 156 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 0 5 31 bits 0000000000000001111010100100010 1 4 31 bits 0000000000000011110101001000100 1 3 31 bits 0000000000000111101010010001001 1 2 31 bits 0000000000001111010100100010011 0 1 LSB sam 0000000000011110101001000100111 0 0 Left 010100100 164 31 bits 0000000000111101010010001001110 0 8 31 bits 0000000001111010100100010011100 1 7 31 bits 0000000011110101001000100111000 0 6 31 bits 0000000111101010010001001110001 1 5 31 bits 0000001111010100100010011100010 0 4 31 bits 0000011110101001000100111000101 0 3 31 bits 0000111101010010001001110001010 1 2 31 bits 0001111010100100010011100010100 0 1 LSB lft 0011110101001000100111000101001 0 0 fB3 0 1 2 3 156 164 164 010011100 010100100 010100100 3 4 5 164 164 164 010100100 010100100 010100100 5 6 7 164 156 164 010100100 010011100 010100100 7 8 9 164 156 164 010100100 010011100 010100100 jan:pc_fast_blinker_jpeg$ jan:pc_fast_blinker_jpeg$ is this the expected output? Jan Coombs -- |
From: Jan C. <jen...@mu...> - 2016-01-23 17:14:32
|
On Sat, 23 Jan 2016 15:39:34 +0000 (UTC) Edward Vidal <dev...@sb...> wrote: > Hi All, > Most of the files in the pc_fast_blinker_jpeg folder have 2 > options --test to run a simulation > > and --convert to create a Verilog file. Trying to follow > Chris's examples. Ok, it is all new to me. Next time perhaps you could give clear instructions. I missed the opportunity to interpret: Hello All, ran python test_sending31.py --test which generates tb.vcd into: Hello All, ran python test_sending31.py --test which generates tb.vcd I now have a tb.vcd file, so feel that with this mornings work, and your additional hint I can now re-create your work. > The file test_top.py imports several files > > > from jpeg import dwt > from signed2twoscomplement import signed2twoscomplement > from l2r import lift2res > from sh_reg import ShiftReg, toSig > from para2ser import para2ser > from div_clk import div_4 > from jpeg_sig import * [Did I need to know that?] > > Running "python test_top.py --test" is my overall goal. Ok dune it, seems to work, if this is what you expected: jan:pc_fast_blinker_jpeg$ jan:pc_fast_blinker_jpeg$ python test_top.py --test 256 256 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 1 1 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010100100 164 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 1 5 31 bits 0000000000000001111010100100010 0 4 31 bits 0000000000000011110101001000101 0 3 31 bits 0000000000000111101010010001010 1 2 31 bits 0000000000001111010100100010100 0 1 LSB sam 0000000000011110101001000101001 0 0 Left 010011100 156 31 bits 0000000000111101010010001010010 0 8 31 bits 0000000001111010100100010100100 1 7 31 bits 0000000011110101001000101001000 0 6 31 bits 0000000111101010010001010010001 0 5 31 bits 0000001111010100100010100100010 1 4 31 bits 0000011110101001000101001000100 1 3 31 bits 0000111101010010001010010001001 1 2 31 bits 0001111010100100010100100010011 0 1 LSB lft 0011110101001000101001000100111 0 0 fB0 0 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 1 1 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010100100 164 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 1 5 31 bits 0000000000000001111010100100010 0 4 31 bits 0000000000000011110101001000101 0 3 31 bits 0000000000000111101010010001010 1 2 31 bits 0000000000001111010100100010100 0 1 LSB sam 0000000000011110101001000101001 0 0 Left 010100100 164 31 bits 0000000000111101010010001010010 0 8 31 bits 0000000001111010100100010100100 1 7 31 bits 0000000011110101001000101001000 0 6 31 bits 0000000111101010010001010010001 1 5 31 bits 0000001111010100100010100100010 0 4 31 bits 0000011110101001000101001000101 0 3 31 bits 0000111101010010001010010001010 1 2 31 bits 0001111010100100010100100010100 0 1 LSB lft 0011110101001000101001000101001 0 0 fB1 0 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 0 0 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010011100 156 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 0 5 31 bits 0000000000000001111010100100010 1 4 31 bits 0000000000000011110101001000100 1 3 31 bits 0000000000000111101010010001001 1 2 31 bits 0000000000001111010100100010011 0 1 LSB sam 0000000000011110101001000100111 0 0 Left 010100100 164 31 bits 0000000000111101010010001001110 0 8 31 bits 0000000001111010100100010011100 1 7 31 bits 0000000011110101001000100111000 0 6 31 bits 0000000111101010010001001110001 1 5 31 bits 0000001111010100100010011100010 0 4 31 bits 0000011110101001000100111000101 0 3 31 bits 0000111101010010001001110001010 1 2 31 bits 0001111010100100010011100010100 0 1 LSB lft 0011110101001000100111000101001 0 0 fB2 0 reset 1 reset 0 reset 1 update firstBit 0000000000000000000000000000000 1 1 first flgs firstBit 0000000000000000000000000000000 1 1 2nd flg firstBit 0000000000000000000000000000001 0 0 3rd flgs 0000000000000000000000000000011 1 Right 010100100 164 31 bits 0000000000000000000000000000111 0 8 31 bits 0000000000000000000000000001111 1 7 31 bits 0000000000000000000000000011110 0 6 31 bits 0000000000000000000000000111101 1 5 31 bits 0000000000000000000000001111010 0 4 31 bits 0000000000000000000000011110101 0 3 31 bits 0000000000000000000000111101010 1 2 31 bits 0000000000000000000001111010100 0 1 LSB rht 0000000000000000000011110101001 0 0 Sam 010011100 156 31 bits 0000000000000000000111101010010 0 8 31 bits 0000000000000000001111010100100 1 7 31 bits 0000000000000000011110101001000 0 6 31 bits 0000000000000000111101010010001 0 5 31 bits 0000000000000001111010100100010 1 4 31 bits 0000000000000011110101001000100 1 3 31 bits 0000000000000111101010010001001 1 2 31 bits 0000000000001111010100100010011 0 1 LSB sam 0000000000011110101001000100111 0 0 Left 010100100 164 31 bits 0000000000111101010010001001110 0 8 31 bits 0000000001111010100100010011100 1 7 31 bits 0000000011110101001000100111000 0 6 31 bits 0000000111101010010001001110001 1 5 31 bits 0000001111010100100010011100010 0 4 31 bits 0000011110101001000100111000101 0 3 31 bits 0000111101010010001001110001010 1 2 31 bits 0001111010100100010011100010100 0 1 LSB lft 0011110101001000100111000101001 0 0 fB3 0 1 2 3 156 164 164 010011100 010100100 010100100 3 4 5 164 164 164 010100100 010100100 010100100 5 6 7 164 156 164 010100100 010011100 010100100 7 8 9 164 156 164 010100100 010011100 010100100 jan:pc_fast_blinker_jpeg$ jan:pc_fast_blinker_jpeg$ is this the expected output? Jan Coombs -- |
From: Edward V. <dev...@sb...> - 2016-01-23 15:39:42
|
Hi All, Most of the files in the pc_fast_blinker_jpeg folder have 2 options --test to run a simulation and --convert to create a Verilog file. Trying to follow Chris's examples. The file test_top.py imports several files from jpeg import dwt from signed2twoscomplement import signed2twoscomplement from l2r import lift2res from sh_reg import ShiftReg, toSig from para2ser import para2ser from div_clk import div_4 from jpeg_sig import * Running "python test_top.py --test" is my overall goal. Testing the transfer from the FPGA to RPi2B which uses para2ser.py. is why I am working with "python test_send31.py --test". On CAT-Board the clock is 100MHz which I believed was too fast for the RPi2B. That is why I divided by 4. The signal clkInOut is 25MHz. The signal ld_o is when the 4 10 bit values get loaded in pp0 which is then shifted out using signal ss0. On the RPi I can see the signals clkInOut & ld_o changing state but the signal ss0 is always 0. To get a bit (Xula2-LX9) or bin (CAT-Board) file I use "python ex_xula_sending.py" with Xilinx Tools on a Ubuntu system. On a RPi2B with Yosys, Arachne-pnr, IcePack "python ex_sending.py" creates the files to program the ICE40. The gpio_test.py is used to read the GPIO on the RPi2B. If I can provide any additional information just let me know. Thanks, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 On Saturday, January 23, 2016 1:21 AM, Jan Coombs <jen...@mu...> wrote: hi Edward, It was good to speak with you earlier this week. On Sat, 23 Jan 2016 01:18:28 +0000 (UTC) Edward Vidal <dev...@sb...> wrote: > Hello All, > ran python test_sending31.py --test which generates tb.vcd I cloned your git repo, installed rhea properly, changed to the relevant folder: /home/jan/.../EdwardVidal/git/jpeg-2000-test/pc_fast_blinker_jpeg then ran the above command: "pythontest_sending31.py" and found only these new files: ./ ├── [2016-01-23_07:40:11] iceriver │ ├── [2016-01-23_07:40:11] build_iceriver.log │ ├── [2016-01-23_07:40:11] catboard.bin │ ├── [2016-01-23_07:40:09] catboard.blif │ ├── [2016-01-23_07:40:08] catboard.pcf │ ├── [2016-01-23_07:40:11] catboard.txt │ ├── [2016-01-23_07:40:06] catboard.v │ ├── [2016-01-23_07:40:08] catboard.ys │ └── [2016-01-23_06:39:58] pck_myhdl_10.vhd ├── [2016-01-23_07:44:51] test_sending31.py 2 directories, 51 files The related .vcd (signal trace) file you refer to seems to be missing, what is needed to fix this? Jan Coombs |
From: Jan C. <jen...@mu...> - 2016-01-23 08:35:55
|
hi Edward, It was good to speak with you earlier this week. On Sat, 23 Jan 2016 01:18:28 +0000 (UTC) Edward Vidal <dev...@sb...> wrote: > Hello All, > ran python test_sending31.py --test which generates tb.vcd I cloned your git repo, installed rhea properly, changed to the relevant folder: /home/jan/.../EdwardVidal/git/jpeg-2000-test/pc_fast_blinker_jpeg then ran the above command: "pythontest_sending31.py" and found only these new files: ./ ├── [2016-01-23_07:40:11] iceriver │ ├── [2016-01-23_07:40:11] build_iceriver.log │ ├── [2016-01-23_07:40:11] catboard.bin │ ├── [2016-01-23_07:40:09] catboard.blif │ ├── [2016-01-23_07:40:08] catboard.pcf │ ├── [2016-01-23_07:40:11] catboard.txt │ ├── [2016-01-23_07:40:06] catboard.v │ ├── [2016-01-23_07:40:08] catboard.ys │ └── [2016-01-23_06:39:58] pck_myhdl_10.vhd ├── [2016-01-23_07:44:51] test_sending31.py 2 directories, 51 files The related .vcd (signal trace) file you refer to seems to be missing, what is needed to fix this? Jan Coombs |
From: Edward V. <dev...@sb...> - 2016-01-23 01:18:35
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Hello All, ran python test_sending31.py --test which generates tb.vcd see the png file below adding the signals clkInOut clock ld ld_o pp0 ss0 ex_sending.py uses from test_sending31.py import top_sending On the RPi2B with the CAT-Board python ex_sending.py generates iceriver/catboard.v, iceriver/catboard.pcf, and iceriver/catboard.bin set_io clock C8 set_io ss0 P9 set_io clkInOut T14 set_io ld_o R10 The signals are BCM23, BCM15, and BCM27. testing with gpio.py which reads the 3 GPIO only 2 signals toggle. clkInOut okay ld_o okay ss0 does not toggle. https://github.com/develone/jpeg-2000-test/blob/master/pc_fast_blinker_jpeg/test_sending.png I also tested with Xula2-LX9 with StickIt-MB on RPi2B same results as on CAT-Board. I swapped clkInOut & ss0 with same results. Can anyone suggest what could be the problem? Thanks Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 |
From: Christopher F. <chr...@gm...> - 2016-01-22 21:15:56
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On 1/22/16 12:39 PM, Marcel Hellwig wrote: > On 20.01.2016 23:11, Marcel Hellwig wrote: >> >> Now, myhdl tells me: >> >>>> myhdl.ConversionError: in file xxx.py, line 63: >>>> Unsupported attribute: User >> line 63: >>>> if mode == CpuMode.User: > > > I finally found out, why this happens. > Because I don't like to write the same code twice, I outsourced the > if/elif section into a seperate function. > Hmmm, yes this doesn't appear to be currently supported, that is accessing attributes in a combinatorial function. Not sure why it is not? Could you use a module instead of a function? rb_inst = register_bank(mode, mul) @always_seq(clk.posedge, reset=reset) def write(): # ... re = regbank[mul*18 + rs] @always_comb def read(): re = regbank[mul*18 + rs] return rb_inst, write, read Regards, Chris |
From: Marcel H. <1he...@in...> - 2016-01-22 18:39:44
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On 20.01.2016 23:11, Marcel Hellwig wrote: > > Now, myhdl tells me: > >> > myhdl.ConversionError: in file xxx.py, line 63: >> > Unsupported attribute: User > line 63: >> > if mode == CpuMode.User: I finally found out, why this happens. Because I don't like to write the same code twice, I outsourced the if/elif section into a seperate function. > def getRegisterbank(mode): > if mode == ProcMode.User or mode == ProcMode.System: > return 0 > elif mode == ProcMode.Supervisor: > return 1 > elif mode == ProcMode.Abort: > return 2 > elif mode == ProcMode.IRQ: > return 4 > elif mode == ProcMode.FIQ: > return 5 > else: > return 3 > > @always_seq(clk.posedge, reset=reset) > def write(): > if we: > mul = 0 > if mode == ProcMode.User or mode == ProcMode.System: > mul = 0 > # ... > else: > mul = 3 > # mul = getRegisterbank(mode) > re = regbank[mul*18 + rd] > regs[re].next = din > > @always_comb > def read(): > # mul = getRegisterbank(mode) > mul = 0 > re = regbank[mul*18 + rs] > sout.next = regs[re] > > return write, read And here is the problem. When I write it directly in the write/read methods, everything works fine, but as soon as I call the getRegisterbank function, it will complain about unsupported Attribute. Is there a way around this? :/ |
From: Christopher F. <chr...@gm...> - 2016-01-21 19:10:10
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> > I'm not happy about the solutions yet, altough I really appreciate the > help I'm getting here (thanks!), but in my eyes, I just want to solve a > simple problem. Has never anyone encountered this and made some > thoughts? :/ > Given your first example snips, this is one way to generate constants: https://gist.github.com/cfelton/50cb0fbed5f188fcc1bb#file-constant_type-py Regards, Chris |
From: Christopher F. <chr...@gm...> - 2016-01-21 18:25:05
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On 1/21/2016 11:19 AM, Marcel Hellwig wrote: > On 21.01.2016 17:34, Christopher Felton wrote: >> >> from myhdl import * >> >> class MyConstants(object): >> def __init__(self): >> self.const1 = int(intbv("1111_0001")) >> self.const2 = int(intbv("1010_0101")) > > why the intbv -> int conversion here? Just for using bitwise representation? Correct, I could have done int("11110001", 2). The only reason I used `intbv` was so I could use the '_' separator :) Or as you did in your original example, 0b11110001. > > Although I can reproduce your example in some test-cases, I can't use it > in my project... > > I use two approaches here. First is to create a instance of the class in > the __init__.py. Then I will get a > >> Local variable may be referenced before assignment: ProcMode > > When I create the instance directly in my myhdl-method, I will get > >> Free variable should be a Signal or an int: ProcMode Hmm, I am not following what you are trying to do different. From your description, it sounds like the object is not defined when the generator is analyzed? I modified my example slightly to match your original class attribute (instead of instance attribute): https://gist.github.com/cfelton/50cb0fbed5f188fcc1bb > > The advantage of having the enum over, that you can use it directly in a > Signal, e.g. > >> mode = Signal(ProcMode.User) > > currently, it will complain about not havin the bitsize (I have set it > manually, which will work fine) What are you interested in here, using the value or the type? If it is the value you can still use it, if it is the type can create a method in your function mode = Signal(ProcMode.const_type()) Then the method can look at all the constants defined and determine the appropriate bitwidth and return the appropriate type (e.g `intbv(0)[8:]`). Regards, Chris |
From: Marcel H. <1he...@in...> - 2016-01-21 17:19:46
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On 21.01.2016 17:34, Christopher Felton wrote: > > from myhdl import * > > class MyConstants(object): > def __init__(self): > self.const1 = int(intbv("1111_0001")) > self.const2 = int(intbv("1010_0101")) why the intbv -> int conversion here? Just for using bitwise representation? > > def const_select(sel, x): > const = MyConstants() > > @always_comb > def beh_select(): > if sel == 1: > x.next = const.const1 > elif sel == 2: > x.next = const.const2 > else: > x.next = 0 > > return beh_select > Although I can reproduce your example in some test-cases, I can't use it in my project... I use two approaches here. First is to create a instance of the class in the __init__.py. Then I will get a > Local variable may be referenced before assignment: ProcMode When I create the instance directly in my myhdl-method, I will get > Free variable should be a Signal or an int: ProcMode The advantage of having the enum over, that you can use it directly in a Signal, e.g. > mode = Signal(ProcMode.User) currently, it will complain about not havin the bitsize (I have set it manually, which will work fine) I'm not happy about the solutions yet, altough I really appreciate the help I'm getting here (thanks!), but in my eyes, I just want to solve a simple problem. Has never anyone encountered this and made some thoughts? :/ |
From: Henry G. <he...@ca...> - 2016-01-21 17:09:39
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On 21/01/16 17:04, Christopher Felton wrote: >>>> >>> You should be able to use constant values in an object, >>>> >>> this code snip might help: >>> >> >>> >> Is this a relatively recent fix? >>> >> >> > >> > Not sure and it depends on your definition >> > of recent. >> > >> > Yes, there was a fix for constants in an object >> > at some point I don't recall the time frame. >> > > Looks like it was fixed for VHDL (always worked > for Verilog) here: > https://github.com/jandecaluwe/myhdl/pull/64 Ok, great, thanks. I think namespace encapsulation of constants goes a long way to solving this problem. Henry |