myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] parallel to serial

[Christopher F. <chr...@gm...>]

On 1/15/2016 11:45 AM, Edward Vidal wrote:
> Hello All,I can not believe that 3 lines are such a problem.

I posted a short reply in the gist comments:
https://gist.github.com/develone/77732a2a1ab452e5f1f8

Re: [myhdl-list] parallel to serial

[Edward V. <dev...@sb...>]

Hello All,I can not believe that 3 lines are such a problem.This t.next = (temp[36:35]) generates   t <= temp(36-1 downto 35)(0);which does not appear correct.  This is what I t <= temp(35);
This t.next = int(temp[36:35]) generates t <= stdl(to_integer(temp(36-1 downto 35)));which I believe might be okay.
This temp[36:1].next = temp[35:0] generates temp(36-1 downto 1) <= temp(35-1 downto 0);which be taking the lower  34 bits to upper 34 of temp.
I am using @always(clk.posedge) could this be the problem?
 
https://gist.github.com/develone/77732a2a1ab452e5f1f8
python gistfile1.txt --test does not perform the desired results.python gistfile1.txt --convert generates the Verilog & VHDL files Thanks for all the help.
Edward Vidal Jr. e-mail dev...@sb... 915-595-1613 

    On Friday, January 15, 2016 1:16 AM, Jan Decaluwe <ja...@ja...> wrote:
 

 Also, why not assign single bits to indices
instead of slices, like in the VHDL?

On 15/01/16 03:58, Christopher Felton wrote:
> Edward,
>
> When assign intbv bit slices you need to:
>
>      temp.next[1:0] = 0
>
> Hope that helps,
> Chris
>
> On 1/14/16 8:26 PM, Edward Vidal wrote:
>> Hello All,
>> I found this VHDL code on the web.
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity piso is
>>      port(
>>            clk,load  : in std_logic;
>>            pi        : in std_logic_vector(35 downto 0);
>>            so        : out std_logic);
>> end piso;
>>
>> architecture arch of piso is
>>
>>      signal t  : std_logic;
>>      signal temp: std_logic_vector(35 downto 0);
>>
>> begin
>>
>>      process (clk,pi,load)
>>      begin
>>          if (load='1') then
>>                temp(35 downto 0) <= pi(35 downto 0);
>>          elsif (CLK'event and CLK='1') then
>>                t <= temp(35);
>>                temp(35 downto 1) <= temp(34 downto 0);
>>                temp(0) <= '0';
>>          end if;
>>      end process;
>>
>> so <= t;
>>
>> end arch;
>> I create a test bench in ise and it appears to be okay.
>> from myhdl import *
>> import argparse
>> W0 = 36
>> pp0 = Signal(intbv(0)[W0:])
>> ss0 = Signal(bool(0))
>> clk = Signal(bool(0))
>> ld = Signal(bool(0))
>> def cliparse():
>>      parser = argparse.ArgumentParser()
>>      parser.add_argument("--build", default=False, action='store_true')
>>      parser.add_argument("--test", default=False, action='store_true')
>>      parser.add_argument("--convert", default=False, action='store_true')
>>      args = parser.parse_args()
>>      return args
>>
>> def para2ser(clk, pp0, ss0, ld):
>>
>>      t = Signal(bool(0))
>>      temp = Signal(intbv(0)[W0:])
>>      @always(clk.posedge)
>>      def logic():
>>
>>          if (ld == 1):
>>            temp[36:0].next = pp0[36:0]
>>          else:
>>            t.next = int(temp[36:35])
>>
>>            temp[36:1].next = temp[35:0]
>>            temp[1:].next = int(0)
>>          ss0.next = t
>>
>>      return logic
>>
>> def tb(clk, pp0, ss0, ld):
>>      instance_1 = para2ser(clk, pp0, ss0, ld)
>>
>>      @always(delay(10))
>>      def clkgen():
>>          clk.next = not clk
>>      @instance
>>      def stimulus():
>>
>>          pp0.next = 34359738368
>>          yield clk.posedge
>>          ld.next = 1
>>          yield clk.posedge
>>          ld.next = 0
>>          yield clk.posedge
>>          print ("%s %d") % (bin(pp0,36), ss0 )
>>          for i in range(36):
>>              yield clk.posedge
>>              print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
>>          raise StopSimulation
>>
>>      return instances()
>> def convert(args):
>>      toVHDL(para2ser,clk, pp0, ss0, ld)
>>      toVerilog(para2ser,clk, pp0, ss0, ld)
>>
>>
>> def main():
>>      args = cliparse()
>>      if args.test:
>>          tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>>          sim = Simulation(tb_fsm)
>>          sim.run()
>>      if args.convert:
>>          convert(args)
>>
>> if __name__ == '__main__':
>>      main()
>> Can someone tell me what I am doing wrong?
>> I think it this line
>> temp[1:].next = int(0)
>> I have tried without the int and I get the same results when I run
>> python para2ser.py --test
>> Thanks
>> Regards,
>> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>>
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
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>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    World-class digital design: http://www.easics.com


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Re: [myhdl-list] parallel to serial

[Jan D. <ja...@ja...>]

Also, why not assign single bits to indices
instead of slices, like in the VHDL?

On 15/01/16 03:58, Christopher Felton wrote:
> Edward,
>
> When assign intbv bit slices you need to:
>
>       temp.next[1:0] = 0
>
> Hope that helps,
> Chris
>
> On 1/14/16 8:26 PM, Edward Vidal wrote:
>> Hello All,
>> I found this VHDL code on the web.
>> library ieee;
>> use ieee.std_logic_1164.all;
>>
>> entity piso is
>>       port(
>>            clk,load  : in std_logic;
>>            pi        : in std_logic_vector(35 downto 0);
>>            so        : out std_logic);
>> end piso;
>>
>> architecture arch of piso is
>>
>>       signal t   : std_logic;
>>       signal temp: std_logic_vector(35 downto 0);
>>
>> begin
>>
>>      process (clk,pi,load)
>>       begin
>>          if (load='1') then
>>                temp(35 downto 0) <= pi(35 downto 0);
>>          elsif (CLK'event and CLK='1') then
>>                t <= temp(35);
>>                temp(35 downto 1) <= temp(34 downto 0);
>>                temp(0) <= '0';
>>          end if;
>>       end process;
>>
>> so <= t;
>>
>> end arch;
>> I create a test bench in ise and it appears to be okay.
>> from myhdl import *
>> import argparse
>> W0 = 36
>> pp0 = Signal(intbv(0)[W0:])
>> ss0 = Signal(bool(0))
>> clk = Signal(bool(0))
>> ld = Signal(bool(0))
>> def cliparse():
>>       parser = argparse.ArgumentParser()
>>       parser.add_argument("--build", default=False, action='store_true')
>>       parser.add_argument("--test", default=False, action='store_true')
>>       parser.add_argument("--convert", default=False, action='store_true')
>>       args = parser.parse_args()
>>       return args
>>
>> def para2ser(clk, pp0, ss0, ld):
>>
>>       t = Signal(bool(0))
>>       temp = Signal(intbv(0)[W0:])
>>       @always(clk.posedge)
>>       def logic():
>>
>>           if (ld == 1):
>>             temp[36:0].next = pp0[36:0]
>>           else:
>>             t.next = int(temp[36:35])
>>
>>             temp[36:1].next = temp[35:0]
>>             temp[1:].next = int(0)
>>           ss0.next = t
>>
>>       return logic
>>
>> def tb(clk, pp0, ss0, ld):
>>       instance_1 = para2ser(clk, pp0, ss0, ld)
>>
>>       @always(delay(10))
>>       def clkgen():
>>           clk.next = not clk
>>       @instance
>>       def stimulus():
>>
>>           pp0.next = 34359738368
>>           yield clk.posedge
>>           ld.next = 1
>>           yield clk.posedge
>>           ld.next = 0
>>           yield clk.posedge
>>           print ("%s %d") % (bin(pp0,36), ss0 )
>>           for i in range(36):
>>               yield clk.posedge
>>               print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
>>           raise StopSimulation
>>
>>       return instances()
>> def convert(args):
>>       toVHDL(para2ser,clk, pp0, ss0, ld)
>>       toVerilog(para2ser,clk, pp0, ss0, ld)
>>
>>
>> def main():
>>       args = cliparse()
>>       if args.test:
>>          tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>>          sim = Simulation(tb_fsm)
>>          sim.run()
>>       if args.convert:
>>           convert(args)
>>
>> if __name__ == '__main__':
>>       main()
>> Can someone tell me what I am doing wrong?
>> I think it this line
>> temp[1:].next = int(0)
>> I have tried without the int and I get the same results when I run
>> python para2ser.py --test
>> Thanks
>> Regards,
>> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>>
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Unsupported list comprehension form

[Christopher F. <chr...@gm...>]

On 1/14/16 9:37 PM, Jock Tanner wrote:
> Chris, thank you for your swift reply!
>

That was a little bit of luck :)

> Speaking of boolean logic in Python, all() and any() seemed so
> well-placed and pythonic to me, I just could not imagine they are not
> supported.

Might be so, but it will need to be a future enhancement.
The functions (any and all) need to be compiled to synthesizable
Verilog and VHDL.

Let us know if you have any other questions,
Chris

Re: [myhdl-list] Unsupported list comprehension form

[Jock T. <tan...@gm...>]

Chris, thank you for your swift reply!

Speaking of boolean logic in Python, all() and any() seemed so well-placed
and pythonic to me, I just could not imagine they are not supported.

Thanks for the insight, I’ll continue struggling.

2016-01-15 13:04 GMT+10:00 Christopher Felton <chr...@gm...>:

> The code that is convertible is limited, not all Python
> constructs are supported.
>
> Your line of code (line 89):
>
>     im_cl[i].next = im_gl[i] | any([(im_gl[j-1] if j > 0 else i_c) &
> all(im_pl[j:i+1]) for j in range(i+1)])
>
> Will need to be implemented with loops and basic conditional.
> I am fairly sure "any" and "all" are not convertible.
>
> Refer to the manual to see what constructs are convertible:
>
> http://docs.myhdl.org/en/stable/manual/conversion.html#the-convertible-subset
>
> Regards,
> Chris
>
> On 1/14/16 8:56 PM, Jock Tanner wrote:
>
>> Hello!
>>
>> I’m a Python web developer and a bit of radio hobbyist, and as such
>> I’ve been playing with MyHDL for a couple of weeks. I’d like to
>> apologize in advance if I have got some basics completely wrong from the
>> start, because that’s pretty possible. But I’d like to get a bit of
>> a clarification, or even better, an advice, concerning an error I
>> recently stuck with.
>>
>> I’m trying to implement a carry-lookahead adder from
>> http://www.ece.lsu.edu/ee3755/2013f/cla.pdf, and that’s how I wrote a
>> carry generator part (from page 5):
>>
>>
>> https://bitbucket.org/jock-tanner/asceticore/src/e0dce2f822639b66a024fe2f53ef2bcc98e8d2f2/components/adder.py?at=master&fileviewer=file-view-default#adder.py-64:92
>>
>> The code simulates fine, but when I try to convert it to Verilog, the
>> error comes up:
>>
>> “myhdl.ConversionError: in file
>>
>> /home/tanner/workspace/pr043-asceticore/project/asceticore/components/adder.py,
>> line 89:
>>
>> Unsupported list comprehension form: should be [intbv()[n:] for i in
>> range(m)]â€
>> Since I wish to put this design into an FPGA (I haven’t got the board
>> yet, but definitely will), I consider the conversion part important. But
>> right now I’m clueless of what I have done wrong conversion-wise.
>> I’ve read the manual
>> (http://docs.myhdl.org/en/stable/manual/conversion.html), but it
>> didn’t get me any further.
>>
>> Any ideas about how I should rework my code? Sorry again for bothering
>> you with such small and (hopefully) trivial matters.
>>
>> JT
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Site24x7 APM Insight: Get Deep Visibility into Application Performance
>> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
>> Monitor end-to-end web transactions and take corrective actions now
>> Troubleshoot faster and improve end-user experience. Signup Now!
>> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>>
>>
>>
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] Unsupported list comprehension form

[Christopher F. <chr...@gm...>]

The code that is convertible is limited, not all Python
constructs are supported.

Your line of code (line 89):

     im_cl[i].next = im_gl[i] | any([(im_gl[j-1] if j > 0 else i_c) & 
all(im_pl[j:i+1]) for j in range(i+1)])

Will need to be implemented with loops and basic conditional.
I am fairly sure "any" and "all" are not convertible.

Refer to the manual to see what constructs are convertible:
http://docs.myhdl.org/en/stable/manual/conversion.html#the-convertible-subset

Regards,
Chris

On 1/14/16 8:56 PM, Jock Tanner wrote:
> Hello!
>
> I’m a Python web developer and a bit of radio hobbyist, and as such
> I’ve been playing with MyHDL for a couple of weeks. I’d like to
> apologize in advance if I have got some basics completely wrong from the
> start, because that’s pretty possible. But I’d like to get a bit of
> a clarification, or even better, an advice, concerning an error I
> recently stuck with.
>
> I’m trying to implement a carry-lookahead adder from
> http://www.ece.lsu.edu/ee3755/2013f/cla.pdf, and that’s how I wrote a
> carry generator part (from page 5):
>
> https://bitbucket.org/jock-tanner/asceticore/src/e0dce2f822639b66a024fe2f53ef2bcc98e8d2f2/components/adder.py?at=master&fileviewer=file-view-default#adder.py-64:92
>
> The code simulates fine, but when I try to convert it to Verilog, the
> error comes up:
>
> “myhdl.ConversionError: in file
> /home/tanner/workspace/pr043-asceticore/project/asceticore/components/adder.py,
> line 89:
>
> Unsupported list comprehension form: should be [intbv()[n:] for i in
> range(m)]â€
>
> Since I wish to put this design into an FPGA (I haven’t got the board
> yet, but definitely will), I consider the conversion part important. But
> right now I’m clueless of what I have done wrong conversion-wise.
> I’ve read the manual
> (http://docs.myhdl.org/en/stable/manual/conversion.html), but it
> didn’t get me any further.
>
> Any ideas about how I should rework my code? Sorry again for bothering
> you with such small and (hopefully) trivial matters.
>
> JT
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] parallel to serial

[Christopher F. <chr...@gm...>]

Edward,

When assign intbv bit slices you need to:

     temp.next[1:0] = 0

Hope that helps,
Chris

On 1/14/16 8:26 PM, Edward Vidal wrote:
> Hello All,
> I found this VHDL code on the web.
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity piso is
>      port(
>           clk,load  : in std_logic;
>           pi        : in std_logic_vector(35 downto 0);
>           so        : out std_logic);
> end piso;
>
> architecture arch of piso is
>
>      signal t   : std_logic;
>      signal temp: std_logic_vector(35 downto 0);
>
> begin
>
>     process (clk,pi,load)
>      begin
>         if (load='1') then
>               temp(35 downto 0) <= pi(35 downto 0);
>         elsif (CLK'event and CLK='1') then
>               t <= temp(35);
>               temp(35 downto 1) <= temp(34 downto 0);
>               temp(0) <= '0';
>         end if;
>      end process;
>
> so <= t;
>
> end arch;
> I create a test bench in ise and it appears to be okay.
> from myhdl import *
> import argparse
> W0 = 36
> pp0 = Signal(intbv(0)[W0:])
> ss0 = Signal(bool(0))
> clk = Signal(bool(0))
> ld = Signal(bool(0))
> def cliparse():
>      parser = argparse.ArgumentParser()
>      parser.add_argument("--build", default=False, action='store_true')
>      parser.add_argument("--test", default=False, action='store_true')
>      parser.add_argument("--convert", default=False, action='store_true')
>      args = parser.parse_args()
>      return args
>
> def para2ser(clk, pp0, ss0, ld):
>
>      t = Signal(bool(0))
>      temp = Signal(intbv(0)[W0:])
>      @always(clk.posedge)
>      def logic():
>
>          if (ld == 1):
>            temp[36:0].next = pp0[36:0]
>          else:
>            t.next = int(temp[36:35])
>
>            temp[36:1].next = temp[35:0]
>            temp[1:].next = int(0)
>          ss0.next = t
>
>      return logic
>
> def tb(clk, pp0, ss0, ld):
>      instance_1 = para2ser(clk, pp0, ss0, ld)
>
>      @always(delay(10))
>      def clkgen():
>          clk.next = not clk
>      @instance
>      def stimulus():
>
>          pp0.next = 34359738368
>          yield clk.posedge
>          ld.next = 1
>          yield clk.posedge
>          ld.next = 0
>          yield clk.posedge
>          print ("%s %d") % (bin(pp0,36), ss0 )
>          for i in range(36):
>              yield clk.posedge
>              print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
>          raise StopSimulation
>
>      return instances()
> def convert(args):
>      toVHDL(para2ser,clk, pp0, ss0, ld)
>      toVerilog(para2ser,clk, pp0, ss0, ld)
>
>
> def main():
>      args = cliparse()
>      if args.test:
>         tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
>         sim = Simulation(tb_fsm)
>         sim.run()
>      if args.convert:
>          convert(args)
>
> if __name__ == '__main__':
>      main()
> Can someone tell me what I am doing wrong?
> I think it this line
> temp[1:].next = int(0)
> I have tried without the int and I get the same results when I run
> python para2ser.py --test
> Thanks
> Regards,
> Edward Vidal Jr. e-mail dev...@sb... 915-595-1613
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] Unsupported list comprehension form

[Jock T. <tan...@gm...>]

Hello!

I’m a Python web developer and a bit of radio hobbyist, and as such I’ve
been playing with MyHDL for a couple of weeks. I’d like to apologize in
advance if I have got some basics completely wrong from the start, because
that’s pretty possible. But I’d like to get a bit of a clarification, or
even better, an advice, concerning an error I recently stuck with.

I’m trying to implement a carry-lookahead adder from
http://www.ece.lsu.edu/ee3755/2013f/cla.pdf, and that’s how I wrote a carry
generator part (from page 5):

https://bitbucket.org/jock-tanner/asceticore/src/e0dce2f822639b66a024fe2f53ef2bcc98e8d2f2/components/adder.py?at=master&fileviewer=file-view-default#adder.py-64:92

The code simulates fine, but when I try to convert it to Verilog, the error
comes up:

“myhdl.ConversionError: in file
/home/tanner/workspace/pr043-asceticore/project/asceticore/components/adder.py,
line 89:

Unsupported list comprehension form: should be [intbv()[n:] for i in
range(m)]”

Since I wish to put this design into an FPGA (I haven’t got the board yet,
but definitely will), I consider the conversion part important. But right
now I’m clueless of what I have done wrong conversion-wise. I’ve read the
manual (http://docs.myhdl.org/en/stable/manual/conversion.html), but it
didn’t get me any further.

Any ideas about how I should rework my code? Sorry again for bothering you
with such small and (hopefully) trivial matters.

JT

[myhdl-list] parallel to serial

[Edward V. <dev...@sb...>]

Hello All,I found this VHDL code on the web.library ieee;
use ieee.std_logic_1164.all;

entity piso is
    port(
         clk,load  : in std_logic;
         pi        : in std_logic_vector(35 downto 0);
         so        : out std_logic);
end piso;

architecture arch of piso is

    signal t   : std_logic;
    signal temp: std_logic_vector(35 downto 0);

begin

   process (clk,pi,load)
    begin
       if (load='1') then
             temp(35 downto 0) <= pi(35 downto 0);
       elsif (CLK'event and CLK='1') then
             t <= temp(35);
             temp(35 downto 1) <= temp(34 downto 0);
             temp(0) <= '0';
       end if;
    end process;

so <= t;

end arch;I create a test bench in ise and it appears to be okay.from myhdl import *
import argparse
W0 = 36
pp0 = Signal(intbv(0)[W0:])
ss0 = Signal(bool(0))
clk = Signal(bool(0))
ld = Signal(bool(0))
def cliparse():
    parser = argparse.ArgumentParser()
    parser.add_argument("--build", default=False, action='store_true')
    parser.add_argument("--test", default=False, action='store_true')
    parser.add_argument("--convert", default=False, action='store_true')
    args = parser.parse_args()
    return args 

def para2ser(clk, pp0, ss0, ld):
 
    t = Signal(bool(0))
    temp = Signal(intbv(0)[W0:])
    @always(clk.posedge)
    def logic():

        if (ld == 1):
          temp[36:0].next = pp0[36:0]
        else:
          t.next = int(temp[36:35])
           
          temp[36:1].next = temp[35:0]
          temp[1:].next = int(0)
        ss0.next = t
        
    return logic
  
def tb(clk, pp0, ss0, ld):
    instance_1 = para2ser(clk, pp0, ss0, ld)

    @always(delay(10))
    def clkgen():
        clk.next = not clk
    @instance
    def stimulus():
        
        pp0.next = 34359738368
        yield clk.posedge
        ld.next = 1
        yield clk.posedge
        ld.next = 0
        yield clk.posedge
        print ("%s %d") % (bin(pp0,36), ss0 )
        for i in range(36):
            yield clk.posedge
            print ("%d %s  %d") % (i, bin(pp0,36), ss0 )
        raise StopSimulation
    
    return instances()
def convert(args): 
    toVHDL(para2ser,clk, pp0, ss0, ld)
    toVerilog(para2ser,clk, pp0, ss0, ld)    
 
 
def main():
    args = cliparse()
    if args.test:
       tb_fsm = traceSignals(tb,clk, pp0, ss0, ld)
       sim = Simulation(tb_fsm)
       sim.run()  
    if args.convert:
        convert(args)

if __name__ == '__main__':
    main()   
Can someone tell me what I am doing wrong? I think it this line 
 temp[1:].next = int(0)I have tried without the int and I get the same results when I run python para2ser.py --test
Thanks 
Regards, Edward Vidal Jr. e-mail dev...@sb... 915-595-1613

[myhdl-list] The Stoic of Open Source

[Jan D. <ja...@ja...>]

http://amasad.me/2016/01/13/the-stoic-of-open-source/

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Asynchronous double port RAM

[Henry G. <he...@ca...>]

On 12/01/16 14:45, Christopher Felton wrote:
> On 1/11/2016 7:45 AM, Nicolas Pinault wrote:
> 
>>> >>
>>> >> I have no idea whether Vivado and ISE are also forgiving.
>> > The code I sent in my first message has been formatted following Xilinx
>> > rules.
>> > However, I did not tried to compile it with Xilinx tools. I'll have a
>> > try and tell you.
>>> >>
>>> >> Your other request: initialising the ram-array is not that much work.
>>> >> I'll try to submit a PR shortly.
>> > That's good news :)
> 
> You can refer to the issue #105 for some info:
> https://github.com/jandecaluwe/myhdl/issues/105
> 
> There has been some work that might be useful (or not):
> https://github.com/jandecaluwe/myhdl/pull/102
> 
> Henry's first pass (see PR comments), we should limit
> the feature to just "initial value" changes.
> https://github.com/hgomersall/myhdl/tree/initial_value_support
> 
> I was assisting Henry some but I don't recall where I
> (we) left off:
> https://github.com/cfelton/myhdl/tree/initial_value_support

It's working*, it just needs the tests to be written. I implemented and
tested it against Vivado, which depended on an external library a wrote,
which wasn't acceptable to Jan for inclusion.

I've basically had other things that have been absorbing (literally) all
my time for quite a while. I'm likely to get back to some FPGA work
soonish though.

I think that PR suggests the suitable test scenario if you fancy a bash.

Cheers,

Henry

*it _was_ working - I haven't checked it against a recent master.

Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 12/01/2016 15:45, Christopher Felton a écrit :
> On 1/11/2016 7:45 AM, Nicolas Pinault wrote:
>
>>> I have no idea whether Vivado and ISE are also forgiving.
>> The code I sent in my first message has been formatted following Xilinx
>> rules.
>> However, I did not tried to compile it with Xilinx tools. I'll have a
>> try and tell you.
>>> Your other request: initialising the ram-array is not that much work.
>>> I'll try to submit a PR shortly.
>> That's good news :)
>
> You can refer to the issue #105 for some info:
> https://github.com/jandecaluwe/myhdl/issues/105
>
> There has been some work that might be useful (or not):
> https://github.com/jandecaluwe/myhdl/pull/102
>
> Henry's first pass (see PR comments), we should limit
> the feature to just "initial value" changes.
> https://github.com/hgomersall/myhdl/tree/initial_value_support
>
> I was assisting Henry some but I don't recall where I
> (we) left off:
> https://github.com/cfelton/myhdl/tree/initial_value_support
Thanks for clarifying.

Regards,
Nicolas

>
> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
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> Monitor end-to-end web transactions and take corrective actions now
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> _______________________________________________
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> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> .
>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
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Re: [myhdl-list] Ram initialisation

[Nicolas P. <ni...@aa...>]

Le 12/01/2016 15:36, Christopher Felton a écrit :
> On 1/11/2016 1:24 AM, Nicolas Pinault wrote:
>> Le 08/01/2016 19:09, Christopher Felton a écrit :
>>> On 1/8/16 9:08 AM, Nicolas Pinault wrote:
>>>> Hi,
>>>>
>>>> I am trying to generate a RAM with initial values.
>>>>
>>> <snip>
>>>> The ram array is not initialised.
>>>>
>>>> Bug or bad code ?
>>>>
>>> Neither, the feature has not been completed and enabled
>>> yet https://github.com/jandecaluwe/myhdl/issues/105
>> Ok. Great !
>> Any idea for release time ?
> More complicated question than most would like :)
> All devs are volunteers and most have other commitments.
> Bugs are typically addressed timely enhancements depend
> on availability.  Based on past releases, the next release
> 1.0 will be awhile.  But with that said, the trunk is
> very stable, many use the latest master branch.
In fact, I was talking about patch release time, not release time for 
version 1.0.
I already use trunk version.
Anyway, thanks for clarifying.

Regards,
Nicolas

> Regards,
> Chris
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> .
>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

Follow us on Twitter
@Aaton_Digital
@Transvideo_HD

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Re: [myhdl-list] Asynchronous double port RAM

[Christopher F. <chr...@gm...>]

On 1/11/2016 7:45 AM, Nicolas Pinault wrote:

>>
>> I have no idea whether Vivado and ISE are also forgiving.
> The code I sent in my first message has been formatted following Xilinx
> rules.
> However, I did not tried to compile it with Xilinx tools. I'll have a
> try and tell you.
>>
>> Your other request: initialising the ram-array is not that much work.
>> I'll try to submit a PR shortly.
> That's good news :)


You can refer to the issue #105 for some info:
https://github.com/jandecaluwe/myhdl/issues/105

There has been some work that might be useful (or not):
https://github.com/jandecaluwe/myhdl/pull/102

Henry's first pass (see PR comments), we should limit
the feature to just "initial value" changes.
https://github.com/hgomersall/myhdl/tree/initial_value_support

I was assisting Henry some but I don't recall where I
(we) left off:
https://github.com/cfelton/myhdl/tree/initial_value_support

Regards,
Chris

Re: [myhdl-list] Ram initialisation

[Christopher F. <chr...@gm...>]

On 1/11/2016 1:24 AM, Nicolas Pinault wrote:
> Le 08/01/2016 19:09, Christopher Felton a écrit :
>> On 1/8/16 9:08 AM, Nicolas Pinault wrote:
>>> Hi,
>>>
>>> I am trying to generate a RAM with initial values.
>>>
>> <snip>
>>> The ram array is not initialised.
>>>
>>> Bug or bad code ?
>>>
>> Neither, the feature has not been completed and enabled
>> yet https://github.com/jandecaluwe/myhdl/issues/105
> Ok. Great !
> Any idea for release time ?

More complicated question than most would like :)
All devs are volunteers and most have other commitments.
Bugs are typically addressed timely enhancements depend
on availability.  Based on past releases, the next release
1.0 will be awhile.  But with that said, the trunk is
very stable, many use the latest master branch.

Regards,
Chris

Re: [myhdl-list] Regarding Contribution to MyHDL

[Christopher F. <chr...@gm...>]

On 1/12/2016 4:28 AM, Tanu Hari Dixit wrote:
> Hello Devs,
> I am Tanu Hari Dixit, third year undergraduate in Electronic Engineering,
> from Indian Institute of Technology (BHU), Varanasi, India. I am interested
> in contributing to MyHDL. Please help me get started.
> Tanu Hari Dixit.
>

Hello Tanu,

First review the development guide:
http://dev.myhdl.org/guide/guide.html

GSoC might be of interest:
http://dev.myhdl.org/gsoc/gsoc_2016.html

After you understand MyHDL and the development flow you can
review the issues and find a beginner issue for a first
contribution:
https://github.com/jandecaluwe/myhdl/issues?q=is%3Aopen+is%3Aissue+label%3A%22help+wanted%22

Issue #104 is an appropriate task for a new contributor.

Regards,
Chris

Re: [myhdl-list] Contribute to MyHDL through GSOC.

[Christopher F. <chr...@gm...>]

On 1/11/2016 11:02 AM, Nagabhushan Baddi wrote:
>      The project DDR3 controller is quite interesting and I would love to
> contribute to this project. Since the project requires familiarity with
> Verilog, Python and digital design, this should be a challenging and
> interesting project experience for me.
>
>      I am going through the MyHDL docs and the sample examples and quite got
> acquainted with. I would love to hear from the mentors and other developers
> and get help for me to get started.
>

Hello Nagabhushan,

Welcome and thanks for the interest.  Last year we participated
as a sub-org under PSF.  The plan this year is the same.
It will probably be a month before everyone has their pages
updated but you can view what is posted now.

MyHDL page: http://dev.myhdl.org/gsoc_2016.html
PSF page: https://wiki.python.org/moin/SummerOfCode/2016
GsoC page: https://www.google-melange.com/

In addition to the manual and examples you can review last years
GSoC SDRAM project: https://github.com/udara28/SDRAM_Controller

Any MyHDL specific questions we can help with, you can also
discuss with others on IRC (#myhdl on freenode[1]) and gitter[2]

Regards,
Chris

[1] https://freenode.net/
[2] https://gitter.im/jandecaluwe/myhdl

[myhdl-list] Regarding Contribution to MyHDL

[Tanu H. D. <tok...@gm...>]

Hello Devs,
I am Tanu Hari Dixit, third year undergraduate in Electronic Engineering,
from Indian Institute of Technology (BHU), Varanasi, India. I am interested
in contributing to MyHDL. Please help me get started.
Tanu Hari Dixit.

[myhdl-list] Contribute to MyHDL through GSOC.

[Nagabhushan B. <nag...@gm...>]

Hello Developers,
    I am Nagabhushan Baddi, a 3rd year electrical engineering student at
Indian Institute of Technology Roorkee. Being an enthusiastic digital
designer and a python programmer I find MyHDL a perfect project team to
work with during GSOC 2016.
I am familiar with programming in Verilog and Python for 2 years for now
and also with digital design and CMOS VLSI design.

    The project DDR3 controller is quite interesting and I would love to
contribute to this project. Since the project requires familiarity with
Verilog, Python and digital design, this should be a challenging and
interesting project experience for me.

    I am going through the MyHDL docs and the sample examples and quite got
acquainted with. I would love to hear from the mentors and other developers
and get help for me to get started.

Have a nice day.
Thank You.

Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 11/01/2016 14:45, Nicolas Pinault a écrit :
> Le 11/01/2016 14:26, Josy Boelen a écrit :
>> Hi Nicolas,
>>
>> I slightly modified your code to have Quartus Prime infer a RAM :)
>>
>>      @myhdl.always(clka.posedge)
>>      def portA():
>>          doa.next = ram[addra]
>>          if ena :
>>              if wea :
>>                  ram[addra].next = dia
>>
>>      @myhdl.always(clkb.posedge)
>>      def portB():
>>          dob.next = ram[addrb]
>>          if enb :
>>              if web :
>>                  ram[addrb].next = dib
>> as Quartus needs a register on the output path I moved the read-
>> statement before the enable.
>>
>> Apparently Quartus Prime has no problem with *ram* being a *signal*
>> rather than a *shared variable*. Although in  the "Recommended HDL
>> Coding Styles" they also show the example with a *shared variable*.
>>
>> I have no idea whether Vivado and ISE are also forgiving.
> The code I sent in my first message has been formatted following 
> Xilinx rules.
> However, I did not tried to compile it with Xilinx tools. I'll have a 
> try and tell you.
Good new.
I tested with Xilinx Tools : ISE and Vivado, synthesiser/compiler and 
simulator. All configurations worked.

Regards,
Nicolas

Re: [myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Le 11/01/2016 14:26, Josy Boelen a écrit :
> Hi Nicolas,
>
> I slightly modified your code to have Quartus Prime infer a RAM :)
>
>      @myhdl.always(clka.posedge)
>      def portA():
>          doa.next = ram[addra]
>          if ena :
>              if wea :
>                  ram[addra].next = dia
>
>      @myhdl.always(clkb.posedge)
>      def portB():
>          dob.next = ram[addrb]
>          if enb :
>              if web :
>                  ram[addrb].next = dib
> as Quartus needs a register on the output path I moved the read-
> statement before the enable.
>
> Apparently Quartus Prime has no problem with *ram* being a *signal*
> rather than a *shared variable*. Although in  the "Recommended HDL
> Coding Styles" they also show the example with a *shared variable*.
>
> I have no idea whether Vivado and ISE are also forgiving.
The code I sent in my first message has been formatted following Xilinx 
rules.
However, I did not tried to compile it with Xilinx tools. I'll have a 
try and tell you.
>
> Your other request: initialising the ram-array is not that much work.
> I'll try to submit a PR shortly.
That's good news :)

Thanks
Nicolas
>
> Regards,
>
> JOsy
>
>
>
> ------------------------------------------------------------------------------
> Site24x7 APM Insight: Get Deep Visibility into Application Performance
> APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month
> Monitor end-to-end web transactions and take corrective actions now
> Troubleshoot faster and improve end-user experience. Signup Now!
> http://pubads.g.doubleclick.net/gampad/clk?id=267308311&iu=/4140
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> .
>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

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Re: [myhdl-list] Asynchronous double port RAM

[Josy B. <jos...@gm...>]

Nicolas Pinault <nicolas <at> aaton.com> writes:

> 
> 
>     Hi,
>     I am experimenting with asynchronous DPR (ie : with 2 clock 
domains)
>     Here is my code :
<snip>
>     The generated VHDL code is not correct. 
>     ram array is declared as a signal while this is not correct since 
2
>     processes access this object. 
>     ram array should be declared as a shared variable. Right ?
>     Simulation seems to be ok.
>     Nicolas-- 
<snip>

Hi Nicolas,

I slightly modified your code to have Quartus Prime infer a RAM :)

    @myhdl.always(clka.posedge)
    def portA():
        doa.next = ram[addra]
        if ena :
            if wea :
                ram[addra].next = dia

    @myhdl.always(clkb.posedge)
    def portB():
        dob.next = ram[addrb]
        if enb :
            if web :
                ram[addrb].next = dib
as Quartus needs a register on the output path I moved the read-
statement before the enable.

Apparently Quartus Prime has no problem with *ram* being a *signal* 
rather than a *shared variable*. Although in  the "Recommended HDL 
Coding Styles" they also show the example with a *shared variable*.

I have no idea whether Vivado and ISE are also forgiving.

Your other request: initialising the ram-array is not that much work. 
I'll try to submit a PR shortly.

Regards,

JOsy

[myhdl-list] Asynchronous double port RAM

[Nicolas P. <ni...@aa...>]

Hi,

I am experimenting with asynchronous DPR (ie : with 2 clock domains)

Here is my code :

def MemoryGene1000Hz(
                      # Port A
                      clka,
                      addra,
                      wea,
                      dia,
                      ena,
                      doa,

                      # Port B
                      clkb,
                      addrb,
                      web,
                      dib,
                      enb,
                      dob
                     ):

     data_length = len(dia)

     # Instanciate RAM array
     ram = [Signal(intbv(0)[data_length:]) for i in range(2**len(addra))]

     # Init RAM with full scale sinus (48 samples)
     scale_factor = (2**(data_length-1)) - 1
     for i in range(48) :
         v = int(sin(i*2*pi/48) * scale_factor)
         ram[i] = Signal(intbv(v)[data_length:])
         #print(i, "%6.6X" % ram[i])

     @always(clka.posedge)
     def portA():
         if ena :
             doa.next = ram[addra]
             if wea :
                 ram[addra].next = dia

     @always(clkb.posedge)
     def portB():
         if enb :
             dob.next = ram[addrb]
             if web :
                 ram[addrb].next = dib

     return portA, portB


def convert():
     from myhdl import toVHDL

     clka  = Signal(bool(0))
     addra = Signal(intbv(0)[8:])
     wea   = Signal(bool(0))
     dia   = Signal(intbv(0)[24:])
     ena   = Signal(bool(0))
     doa   = Signal(intbv(0)[24:])

     clkb  = Signal(bool(0))
     addrb = Signal(intbv(0)[8:])
     web   = Signal(bool(0))
     dib   = Signal(intbv(0)[24:])
     enb   = Signal(bool(0))
     dob   = Signal(intbv(0)[24:])

     toVHDL.directory = "../vhdl"
     #toVHDL.std_logic_ports = True
     toVHDL(MemoryGene1000Hz,
            clka,
            addra,
            wea,
            dia,
            ena,
            doa,

            clkb,
            addrb,
            web,
            dib,
            enb,
            dob
           )

The generated VHDL code is not correct.
ram array is declared as a signal while this is not correct since 2 
processes access this object.
ram array should be declared as a shared variable. Right ?

Simulation seems to be ok.

Nicolas

-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
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French Technologies for Film and Digital Cinematography

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Re: [myhdl-list] Ram initialisation

[Nicolas P. <ni...@aa...>]

Le 08/01/2016 19:09, Christopher Felton a écrit :
> On 1/8/16 9:08 AM, Nicolas Pinault wrote:
>> Hi,
>>
>> I am trying to generate a RAM with initial values.
>>
> <snip>
>> The ram array is not initialised.
>>
>> Bug or bad code ?
>>
> Neither, the feature has not been completed and enabled
> yet https://github.com/jandecaluwe/myhdl/issues/105
Ok. Great !
Any idea for release time ?

Nicolas
>
> Regards
> Chris
>
>
>
> ------------------------------------------------------------------------------
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> .
>


-- 
*Nicolas PINAULT
R&D electronics engineer
*** ni...@aa... <mailto:ni...@aa...>

*AATON-Digital*
38000 Grenoble - France
Tel +33 4 7642 9550

http://www.aaton.com
http://www.transvideo.eu
French Technologies for Film and Digital Cinematography

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Re: [myhdl-list] Ram initialisation

[Christopher F. <chr...@gm...>]

On 1/8/16 9:08 AM, Nicolas Pinault wrote:
> Hi,
>
> I am trying to generate a RAM with initial values.
>
<snip>
>
> The ram array is not initialised.
>
> Bug or bad code ?
>

Neither, the feature has not been completed and enabled
yet https://github.com/jandecaluwe/myhdl/issues/105

Regards
Chris