myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] beginning with unittests

[Martín G. <ga...@gm...>]

Hi everybody.

I'm very happy because my project is progressing and, not a minor point, I'm
learning a lot in the way. My teachers are also very interested in my
heteredoxy (and myhdl, of course).

because I want to do the right things, I'm trying to begin write/use unit
tests.  my first attempt  fails :(

here it is:
https://github.com/nqnwebs/pymips/blob/unittest/alu.py

I'm very newbie to unittesting field in general, so I'm not sure if it's
fails because the design or the test is wrong. What I want to do is very
simple: set up the control lines of 'alu' to the operation 'add' and check
if it effectively add the input signals.  Instead it, control lines never
changes (it keeps in 0) doing another operation ( AND function) on the ALU.

The mystery (for me) is that my original testbenchs seems to work

https://github.com/nqnwebs/pymips/blob/master/alu.py

in this testbench I iterate over every valid 'control' value and set inputs
signals with random values. The outputs are right.

Control: 0000 | 156 AND 118 | 20 | z=0
Control: 0001 | 55 OR 196 | 247 | z=0
Control: 0010 | 248 add 195 | 247 | z=0
Control: 0110 | 108 substract 19 | 89 | z=0
Control: 0111 | 88 set on < 220 | 0 | z=1
Control: 1100 | 232 NOR 115 | -252 | z=0

so, has  anybody a clue?

thanks for the patience.
Martín

Re: [myhdl-list] Setting signal attributes

[Christopher F. <cf...@uc...>]

>
>
>
> I'd like to know if there is a way in MyHDL to set signal attributes such
> as those that can be set in VHDL by using the "attribute" keyword.
> For example, if I want to give a hint to the Xilinx XST tool so that a
> certain memory is inferred as block ram I could use the following VHDL code:
>
>    attribute ram_style: string;
>    attribute ram_style of MY_MEMORY: signal is "block";
>
>
You can use the "user defined code" to implement something specific.

http://www.myhdl.org/doc/current/manual/conversion.html#user-defined-code

You would use the VHDL attributes you are familiar with.  In this case MyHDL
would simply pass the attributes to the generated code.

Hope that helps,

Chris Felton


> To force the MY_MEMORY string to be implemented as block ram. Or I could
> set it to "distributed" to have it implemented as distributed memory.
> Is this possible with MyHDL? Please excuse me if this has been asked
> before. I seem to recall having read about this in the mailing list but
> Google did not find any good answers.
>
> On a related note,  different synthesis tools have different constraints
> regarding when they are able to infer block rams vs using distributed ram.
> For instance you may need to make sure that the read address is registered,
> etc. Have you had any experience or any trouble making sure that the
> generated VHDL code follows these kinds of constraints?
>
> The reason I ask is that in our current project we use VHDL yet we've had
> some issues controlling the way that the Xilinx XST tool infers the type of
> RAM that must be used. In particular we are not always able to force it use
> block rams (even though the ram_style attribute was properly set). When this
> happens we have often needed to tweaking the VHDL code and sometimes we have
> had to manually instantiate the block rams (which is a pain in VHDL). Since
> interfacing with VHDL blocks is still a bit cumbersome in MyHDL I am a bit
> worried that it will be hard to control the behavior of the synthesizer if
> we ever use MyHDL for our projects. So if you guys could share your
> experiences with this sort of thing it would be great.
>
> Cheers,
>
> Angel
>
>
>

[myhdl-list] Setting signal attributes

[Angel E. M. <ang...@gm...>]

Hi,

I'd like to know if there is a way in MyHDL to set signal attributes such as
those that can be set in VHDL by using the "attribute" keyword.
For example, if I want to give a hint to the Xilinx XST tool so that a
certain memory is inferred as block ram I could use the following VHDL code:

   attribute ram_style: string;
   attribute ram_style of MY_MEMORY: signal is "block";

To force the MY_MEMORY string to be implemented as block ram. Or I could set
it to "distributed" to have it implemented as distributed memory.
Is this possible with MyHDL? Please excuse me if this has been asked before.
I seem to recall having read about this in the mailing list but Google did
not find any good answers.

On a related note,  different synthesis tools have different constraints
regarding when they are able to infer block rams vs using distributed ram.
For instance you may need to make sure that the read address is registered,
etc. Have you had any experience or any trouble making sure that the
generated VHDL code follows these kinds of constraints?

The reason I ask is that in our current project we use VHDL yet we've had
some issues controlling the way that the Xilinx XST tool infers the type of
RAM that must be used. In particular we are not always able to force it use
block rams (even though the ram_style attribute was properly set). When this
happens we have often needed to tweaking the VHDL code and sometimes we have
had to manually instantiate the block rams (which is a pain in VHDL). Since
interfacing with VHDL blocks is still a bit cumbersome in MyHDL I am a bit
worried that it will be hard to control the behavior of the synthesizer if
we ever use MyHDL for our projects. So if you guys could share your
experiences with this sort of thing it would be great.

Cheers,

Angel

Re: [myhdl-list] compiling generated VHDL code

[Jan D. <ja...@ja...>]

Probably the reason is that there is no and/or in
numeric_std that returns a signed for unsigned arguments.

I checked this with 0.7dev, and it seems this bug is solved
with an additional cast (I don't remember though fixing this
though :-))

I suggest to use 0.7dev by pulling it from mercurial - this
should be more or less the 0.7 release for within a few weeks or
so anyway, and so you help with getting the bugs out :-)

Jan

Martín Gaitán wrote:
> Hi,
> 
> I've been working on my project for the university (I called it
> "pymips"). Now I know (with a bit effort) how to code convertible
> things. But I don't know why the code I get fails when I try to
> compile it.
> 
> For example, the converted version of the alu
> http://github.com/nqnwebs/pymips/blob/master/alu.py
> 
> is this
> 
> http://github.com/nqnwebs/pymips/blob/master/vhdl/alu.vhd
> 
> when I try to compile or check that I get this:
> 
> (hdl)tin@azulita:~/facu/arq/project/vhdl$ ghdl -a alu.vhd
> alu.vhd:31:22: no function declarations for operator "and"
> alu.vhd:33:22: no function declarations for operator "or"
> /usr/lib/ghdl/bin/ghdl: compilation error
> 
> what's wrong?
> 
> thanks
> Martín
> 
> ------------------------------------------------------------------------------
> Nokia and AT&T present the 2010 Calling All Innovators-North America contest
> Create new apps & games for the Nokia N8 for consumers in  U.S. and Canada
> $10 million total in prizes - $4M cash, 500 devices, nearly $6M in marketing
> Develop with Nokia Qt SDK, Web Runtime, or Java and Publish to Ovi Store 
> http://p.sf.net/sfu/nokia-dev2dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] compiling generated VHDL code

[Martín G. <ga...@gm...>]

On Thu, Oct 28, 2010 at 2:46 AM, Christopher L. Felton
<chr...@gm...> wrote:
> This might help, from the MyHDL manaul the default simulator for VHDL is
> GHDL.  You can see in the default config you need to inlcude the
> pck_myhdl_*.vhd file as well.
>
>

Thanks Chris, but that appears not work.

(hdl)tin@azulita:~/facu/arq/project/vhdl$ ghdl -a pck_myhdl_06.vhd alu.vhd
alu.vhd:31:22: no function declarations for operator "and"
alu.vhd:33:22: no function declarations for operator "or"
/usr/lib/ghdl/bin/ghdl: compilation error

I also replaced toVHDL() to compile.analyze on the python code, and I
get the same compilation error but a failed* testbench  also.

(*) all output are always 0, which is wrong


(hdl)tin@azulita:~/facu/arq/project$ python alu.py
/usr/lib/python2.6/sets.py:85: DeprecationWarning: functions
overriding warnings.showwarning() must support the 'line' argument
  stacklevel=2)
** DeprecationWarning: the sets module is deprecated
/home/tin/.virtualenvs/hdl/lib/python2.6/site-packages/myhdl-0.6-py2.6.egg/myhdl/conversion/_toVHDL.py:219:
DeprecationWarning: functions overriding warnings.showwarning() must
support the 'line' argument
  category=ToVHDLWarning
** ToVHDLWarning: Output port is read internally: out_
alu.vhd:31:22: no function declarations for operator "and"
alu.vhd:33:22: no function declarations for operator "or"
/usr/lib/ghdl/bin/ghdl: compilation error
Analysis failed
Control: 0000 | 251 AND 150 | 0 | z=0
Control: 0001 | 196 OR 100 | 0 | z=0
Control: 0010 | 187 add 56 | 0 | z=0
Control: 0110 | 167 substract 185 | 0 | z=0
Control: 0111 | 79 set on < 214 | 0 | z=0
Control: 1100 | 167 NOR 231 | 0 | z=0
<class 'myhdl.StopSimulation'>: No more events
(hdl)tin@azulita:~/facu/arq/project$

any other idea?

Re: [myhdl-list] compiling generated VHDL code

[Christopher L. F. <chr...@gm...>]

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
  <head>
    <meta content="text/html; charset=UTF-8" http-equiv="Content-Type">
    <title></title>
  </head>
  <body text="#000000" bgcolor="#ffffff">
    This might help, from the MyHDL manaul the default simulator for
    VHDL is GHDL.  You can see in the default config you need to inlcude
    the pck_myhdl_*.vhd file as well.<br>
    <br>
    <a
      href="http://www.myhdl.org/doc/0.6/whatsnew/0.6.html?highlight=ghdl">http://www.myhdl.org/doc/0.6/whatsnew/0.6.html?highlight=ghdl</a><br>
    <span class="Apple-style-span" style="border-collapse: separate;
      color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-style:
      normal; font-variant: normal; font-weight: normal; letter-spacing:
      normal; line-height: normal; orphans: 2; text-indent: 0px;
      text-transform: none; white-space: normal; widows: 2;
      word-spacing: 0px; font-size: medium;"><span
        class="Apple-style-span" style="font-family: 'Lucida
        Grande','Lucida Sans Unicode',Geneva,Verdana,sans-serif;
        font-size: 14px; line-height: 21px; text-align: left;">
        <pre style="font-family: Consolas,'Deja Vu Sans Mono','Bitstream Vera Sans Mono',monospace; font-size: 0.95em; letter-spacing: 0.015em; padding: 0.5em; border: 1px solid rgb(204, 204, 204); background-color: rgb(248, 248, 248); line-height: 15px;"><span class="n">registerSimulator</span><span class="p">(</span>
    <span class="n">name</span><span class="o" style="color: rgb(102, 102, 102);">=</span><span class="s" style="color: rgb(64, 112, 160);">"<span class="highlight" style="background-color: rgb(251, 229, 78);">GHDL</span>"</span><span class="p">,</span>
    <span class="n">hdl</span><span class="o" style="color: rgb(102, 102, 102);">=</span><span class="s" style="color: rgb(64, 112, 160);">"VHDL"</span><span class="p">,</span>
    <span class="n">analyze</span><span class="o" style="color: rgb(102, 102, 102);">=</span><span class="s" style="color: rgb(64, 112, 160);">"<span class="highlight" style="background-color: rgb(251, 229, 78);">ghdl</span> -a --workdir=work pck_myhdl_</span><span class="si" style="color: rgb(112, 160, 208); font-style: italic;">%(version)s</span><span class="s" style="color: rgb(64, 112, 160);">.vhd </span><span class="si" style="color: rgb(112, 160, 208); font-style: italic;">%(topname)s</span><span class="s" style="color: rgb(64, 112, 160);">.vhd"</span><span class="p">,</span>
    <span class="n">elaborate</span><span class="o" style="color: rgb(102, 102, 102);">=</span><span class="s" style="color: rgb(64, 112, 160);">"<span class="highlight" style="background-color: rgb(251, 229, 78);">ghdl</span> -e --workdir=work -o </span><span class="si" style="color: rgb(112, 160, 208); font-style: italic;">%(unitname)s</span><span class="s" style="color: rgb(64, 112, 160);">_<span class="highlight" style="background-color: rgb(251, 229, 78);">ghdl</span> </span><span class="si" style="color: rgb(112, 160, 208); font-style: italic;">%(topname)s</span><span class="s" style="color: rgb(64, 112, 160);">"</span><span class="p">,</span>
    <span class="n">simulate</span><span class="o" style="color: rgb(102, 102, 102);">=</span><span class="s" style="color: rgb(64, 112, 160);">"<span class="highlight" style="background-color: rgb(251, 229, 78);">ghdl</span> -r </span><span class="si" style="color: rgb(112, 160, 208); font-style: italic;">%(unitname)s</span><span class="s" style="color: rgb(64, 112, 160);">_<span class="highlight" style="background-color: rgb(251, 229, 78);">ghdl</span>"</span>
    <span class="p">)
</span></pre>
      </span></span><br>
    Hope that helps<br>
    .chris<br>
    <br>
    On 10/28/2010 12:42 AM, Martín Gaitán wrote:
    <blockquote
      cite="mid:AAN...@ma..."
      type="cite">
      <pre wrap="">Hi,

I've been working on my project for the university (I called it
"pymips"). Now I know (with a bit effort) how to code convertible
things. But I don't know why the code I get fails when I try to
compile it.

For example, the converted version of the alu
<a class="moz-txt-link-freetext" href="http://github.com/nqnwebs/pymips/blob/master/alu.py">http://github.com/nqnwebs/pymips/blob/master/alu.py</a>

is this

<a class="moz-txt-link-freetext" href="http://github.com/nqnwebs/pymips/blob/master/vhdl/alu.vhd">http://github.com/nqnwebs/pymips/blob/master/vhdl/alu.vhd</a>

when I try to compile or check that I get this:

(hdl)tin@azulita:~/facu/arq/project/vhdl$ ghdl -a alu.vhd
alu.vhd:31:22: no function declarations for operator "and"
alu.vhd:33:22: no function declarations for operator "or"
/usr/lib/ghdl/bin/ghdl: compilation error

what's wrong?

thanks
Martín

------------------------------------------------------------------------------
Nokia and AT&amp;T present the 2010 Calling All Innovators-North America contest
Create new apps &amp; games for the Nokia N8 for consumers in  U.S. and Canada
$10 million total in prizes - $4M cash, 500 devices, nearly $6M in marketing
Develop with Nokia Qt SDK, Web Runtime, or Java and Publish to Ovi Store 
<a class="moz-txt-link-freetext" href="http://p.sf.net/sfu/nokia-dev2dev">http://p.sf.net/sfu/nokia-dev2dev</a>
_______________________________________________
myhdl-list mailing list
<a class="moz-txt-link-abbreviated" href="mailto:myh...@li...">myh...@li...</a>
<a class="moz-txt-link-freetext" href="https://lists.sourceforge.net/lists/listinfo/myhdl-list">https://lists.sourceforge.net/lists/listinfo/myhdl-list</a>
</pre>
    </blockquote>
    <br>
  </body>
</html>

[myhdl-list] compiling generated VHDL code

[Martín G. <ga...@gm...>]

Hi,

I've been working on my project for the university (I called it
"pymips"). Now I know (with a bit effort) how to code convertible
things. But I don't know why the code I get fails when I try to
compile it.

For example, the converted version of the alu
http://github.com/nqnwebs/pymips/blob/master/alu.py

is this

http://github.com/nqnwebs/pymips/blob/master/vhdl/alu.vhd

when I try to compile or check that I get this:

(hdl)tin@azulita:~/facu/arq/project/vhdl$ ghdl -a alu.vhd
alu.vhd:31:22: no function declarations for operator "and"
alu.vhd:33:22: no function declarations for operator "or"
/usr/lib/ghdl/bin/ghdl: compilation error

what's wrong?

thanks
Martín

Re: [myhdl-list] first attemp: failing in toVHDL conversion

[Jan D. <ja...@ja...>]

Martín Gaitán wrote:
> On Thu, Oct 21, 2010 at 4:25 AM, Jan Decaluwe <ja...@ja...> wrote:
>>> The FM said that a tuple of integer is part of the convertible subset,
>>> so... what's wrong?
>> I believe the Notes are clear about the restrictions:
>>
>> - A MyHDL tuple of int is used for ROM inference, and can only be used in a very
>> specific way: an indexing operation into the tuple should be the rhs of an assignment.
>>
>> Jan
> 
> That remember me this comic: http://www.dosisdiarias.com/2010/09/2010-09-09.html
> 
> It says:  "everybody is afraid of the tiny letter"

Mm, the notes are really not intented to be fineprint -
it's just that you can't get everything squeezed in
a table :-)

> Thanks Jan, now it works
> 
> http://github.com/nqnwebs/pymips/blob/master/sandbox/exercise1.py
> 
> I need to put my mind in the right 'HDL' way.

Correct. Unfortunately, that's more difficult than it sounds.

I'm glad you said "HDL", and not "hardware". The two are
related of course, but not the same. Many people that come
from the hardware side use HDL's in a very low level way,
thereby using them suboptimally. Unfortunately, most texts
on the subject encourage this.

On the other hand, people coming from the software side
may easily have unrealistic expectations, such as expecting
that MyHDL can magically transform high-level Python code
into hardware.

My personal view has always been to write synthesizable HDL
code at a level that is as high as possible without compromising
implementation efficiency, as measured by synthesis experiments.
However, I can't give you a good reference text that explains
things according to such a view.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] first attemp: failing in toVHDL conversion

[Martín G. <ga...@gm...>]

On Thu, Oct 21, 2010 at 4:25 AM, Jan Decaluwe <ja...@ja...> wrote:
>> The FM said that a tuple of integer is part of the convertible subset,
>> so... what's wrong?
>
> I believe the Notes are clear about the restrictions:
>
> - A MyHDL tuple of int is used for ROM inference, and can only be used in a very
> specific way: an indexing operation into the tuple should be the rhs of an assignment.
>
> Jan

That remember me this comic: http://www.dosisdiarias.com/2010/09/2010-09-09.html

It says:  "everybody is afraid of the tiny letter"

Thanks Jan, now it works

http://github.com/nqnwebs/pymips/blob/master/sandbox/exercise1.py

I need to put my mind in the right 'HDL' way.

Re: [myhdl-list] first attemp: failing in toVHDL conversion

[Jan D. <ja...@ja...>]

Martín Gaitán wrote:
> Hi there. a few days ago I said here I would be bothering for a while,
> but really I've just got some time to learn MyHDL.
> With more mimic from the manual than deep understanding I made a first
> exercise .
> 
> http://github.com/nqnwebs/pymips/blob/d669d4f460d7f59286a9d1a6974570c3adbbda2b/sandbox/exercise1.py
> 
> And the good thing: seems to work!
> 
> But when I tried to get a VHDL version it fails. The problem is the
> line 17. For example, returning always False from that function, the
> conversion works.

In general, this is what you will find. Modeling is very generic, and
it should be easy to get things to work, even when doing powerful
Python stuff.

But conversion is subject to very important restrictions. Its
primary target is the "synthesizable subset" in Verilog and VHDL, and
it makes sense to study this a little if you have a good reference.
In fact, conversion can do much more than that, but it is still
extremely restricted compared to full Python power.

Any piece of code inside a generator has to be mapped in some way or
another into equivalent Verilog and VHDL. So, to understand restrictions,
it may help to think about what Verilog/VHDL can do, not just what
Python can do.


> The FM said that a tuple of integer is part of the convertible subset,
> so... what's wrong?

I believe the Notes are clear about the restrictions:

- A MyHDL tuple of int is used for ROM inference, and can only be used in a very
specific way: an indexing operation into the tuple should be the rhs of an assignment.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] first attemp: failing in toVHDL conversion

[Martín G. <ga...@gm...>]

Hi there. a few days ago I said here I would be bothering for a while,
but really I've just got some time to learn MyHDL.
With more mimic from the manual than deep understanding I made a first
exercise .

http://github.com/nqnwebs/pymips/blob/d669d4f460d7f59286a9d1a6974570c3adbbda2b/sandbox/exercise1.py

And the good thing: seems to work!

But when I tried to get a VHDL version it fails. The problem is the
line 17. For example, returning always False from that function, the
conversion works.

The FM said that a tuple of integer is part of the convertible subset,
so... what's wrong?

thanks in advance

PS: I'm a very newbie at all, but myhdl rulez!

Re: [myhdl-list] List of signals unsupported in top-level instance in toVHDL

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
> Hi,
> input or output-signals in list are silently ignored in toVHDL. Is there 
> something I do wrong in my small example? 

No, this was a bug.

The problem is that Verilog doesn't permit memories as ports.
As my goal is to support both Verilog and VHDL equally, I have
to use the lowest common demoninator. Therefore, list of signals
as ports are not supported.

I don't think this a very large problem in practice - it is
only a restriction at the very top level, not when such a
module is used internally (thanks to the hierarchical flattening
by the convertor.) Verilog has done without this for over
25 years :-)

Based on your example (thanks) I have added an error check
and a unit test to avoid this, and pushed it to the public repo's.

Jan


I have not found any method to 
> fix this other than to change the generated vhdl-file after generation.
> 
> Sigve
> 
> An example:
> 
> from myhdl import *
> 
> def my_register(clk, input, output):
>     @always(clk.posedge)
>     def my_register_impl():
>         for index in range(len(input)):
>             output[index].next = input[index]
>     return my_register_impl
> 
> def my_register_to_vhdl():
>     count = 3
>     clk = Signal(False)
>     input = [Signal(intbv(0)[8:0]) for index in range(count)]
>     output = [Signal(intbv(0)[8:0]) for index in range(count)]
>     
>     toVHDL(my_register, clk, input, output)
>     
> if __name__=="__main__":
>     my_register_to_vhdl()
> 
> 
> generates the following VHDL without any warnings or errors:
> -------------------------------------------------------------------------------------------------------------------------------------------------------------
> -- File: my_register.vhd
> -- Generated by MyHDL 0.7dev
> -- Date: Mon Oct 18 19:44:40 2010
> 
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> use std.textio.all;
> 
> use work.pck_myhdl_07dev.all;
> 
> entity my_register is
>     port (
>         clk: in std_logic
>     );
> end entity my_register;
> 
> 
> architecture MyHDL of my_register is
> 
> type t_array_output is array(0 to 3-1) of unsigned(7 downto 0);
> signal output: t_array_output;
> type t_array_input is array(0 to 3-1) of unsigned(7 downto 0);
> signal input: t_array_input;
> 
> begin
> 
> MY_REGISTER_MY_REGISTER_IMPL: process (clk) is
> begin
>     if rising_edge(clk) then
>         for index in 0 to 3-1 loop
>             output(index) <= input(index);
>         end loop;
>     end if;
> end process MY_REGISTER_MY_REGISTER_IMPL;
> 
> end architecture MyHDL;
> 
> -------------------------------------------------------------------------------------------------------------------------------------------------------------
> The code I would expect is something like:
> 
> -------------------------------------------------------------------------------------------------------------------------------------------------------------
> -- File: my_register.vhd
> -- Generated by MyHDL 0.7dev
> -- Date: Mon Oct 18 19:47:05 2010
> 
> 
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.numeric_std.all;
> use std.textio.all;
> 
> use work.pck_myhdl_07dev.all;
> 
> entity my_register is
>   port (
>     clk    : in  std_logic;
>     input  : in  array(0 to 3-1) of unsigned(7 downto 0);
>     output : out array(0 to 3-1) of unsigned(7 downto 0)
>     );
> end entity my_register;
> 
> architecture MyHDL of my_register is
> 
> begin
> 
>   MY_REGISTER_MY_REGISTER_IMPL : process (clk) is
>   begin
>     if rising_edge(clk) then
>       for index in 0 to 3-1 loop
>         output(index) <= input(index);
>       end loop;
>     end if;
>   end process MY_REGISTER_MY_REGISTER_IMPL;
> 
> end architecture MyHDL;
> 
> 
> ------------------------------------------------------------------------
> 
> ------------------------------------------------------------------------------
> Download new Adobe(R) Flash(R) Builder(TM) 4
> The new Adobe(R) Flex(R) 4 and Flash(R) Builder(TM) 4 (formerly 
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] List of signals unsupported in top-level instance in toVHDL

[Sigve T. <pu...@tj...>]

Hi,
input or output-signals in list are silently ignored in toVHDL. Is there
something I do wrong in my small example? I have not found any method to fix
this other than to change the generated vhdl-file after generation.

Sigve

An example:

from myhdl import *

def my_register(clk, input, output):
    @always(clk.posedge)
    def my_register_impl():
        for index in range(len(input)):
            output[index].next = input[index]
    return my_register_impl

def my_register_to_vhdl():
    count = 3
    clk = Signal(False)
    input = [Signal(intbv(0)[8:0]) for index in range(count)]
    output = [Signal(intbv(0)[8:0]) for index in range(count)]

    toVHDL(my_register, clk, input, output)

if __name__=="__main__":
    my_register_to_vhdl()


generates the following VHDL without any warnings or errors:
-------------------------------------------------------------------------------------------------------------------------------------------------------------
-- File: my_register.vhd
-- Generated by MyHDL 0.7dev
-- Date: Mon Oct 18 19:44:40 2010


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07dev.all;

entity my_register is
    port (
        clk: in std_logic
    );
end entity my_register;


architecture MyHDL of my_register is

type t_array_output is array(0 to 3-1) of unsigned(7 downto 0);
signal output: t_array_output;
type t_array_input is array(0 to 3-1) of unsigned(7 downto 0);
signal input: t_array_input;

begin

MY_REGISTER_MY_REGISTER_IMPL: process (clk) is
begin
    if rising_edge(clk) then
        for index in 0 to 3-1 loop
            output(index) <= input(index);
        end loop;
    end if;
end process MY_REGISTER_MY_REGISTER_IMPL;

end architecture MyHDL;

-------------------------------------------------------------------------------------------------------------------------------------------------------------
The code I would expect is something like:

-------------------------------------------------------------------------------------------------------------------------------------------------------------
-- File: my_register.vhd
-- Generated by MyHDL 0.7dev
-- Date: Mon Oct 18 19:47:05 2010


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_07dev.all;

entity my_register is
  port (
    clk    : in  std_logic;
    input  : in  array(0 to 3-1) of unsigned(7 downto 0);
    output : out array(0 to 3-1) of unsigned(7 downto 0)
    );
end entity my_register;

architecture MyHDL of my_register is

begin

  MY_REGISTER_MY_REGISTER_IMPL : process (clk) is
  begin
    if rising_edge(clk) then
      for index in 0 to 3-1 loop
        output(index) <= input(index);
      end loop;
    end if;
  end process MY_REGISTER_MY_REGISTER_IMPL;

end architecture MyHDL;

[myhdl-list] What's new in 0.7 - draft

[Jan D. <ja...@ja...>]

I have a draft of a what's new document in 0.7:

http://www.myhdl.org/doc/dev/whatsnew/0.7.html

Thanks for reviewing it and giving feedback.

The development code should be up-to-date with this document.
Thanks for trying it out. 

At this point, the manual itself has not yet been updated.
If you have any feedback, suggestions, or remarks on the
manual - now is the time. I plan to update it in the coming
month, and then do the release.

It's bug-fixing and clarification time now, once the
release is done there will be time for new features!

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Blog post about Verilog

[Jan D. <ja...@ja...>]

Andrew Stone wrote:
> Hi Jan,
> 
> I'm a dabbler at HDL but am experienced at software on von-neumann 
> machines and well, I feel like I can just barely NOT follow what you are 
> trying to say :-(.  Which is a lot more frustrating than it being 
> completely over my head.

Perhaps this means I have achieved my goal: in VHDL (and MyHDL), you
don't really have to worry about these matters as a designer.

But in Verilog, it you are not aware of all this, you are in for
big trouble sooner or later.

It's a difference that is seldom talked about, but I think language
decision makers should be aware of.

> I would think that any reasonable simulator would execute concurrent 
> hardware in random order, or multiple times in multiple orders (and 
> compare the outputs), or even better, model each bit as "1", "0" or 
> "undetermined" -- i.e. in the process of being changed -- and raise a 
> BIG flag if you access an "undetermined" bit! :-).  I'm guessing from 
> your post that that is not the case.

No. VHDL's contribution is that it guarantees determinism, even though
the processes are executed in random order. Verilog has no such guarantee,
so a designer has to take his own measures. For all kinds of reasons,
including language history, that's not an obvious task.

BTW, MyHDL is mostly like VHDL in this respect, with one big exception:
it doesn't have resolution functions like in VHDL, so when you drive
a signal from several processes, the result will be non-deterministic.

> If you are targeting the blog for wider audiences, maybe a quick 
> definition of what synchronous RTL design IS, maybe an example of when 
> you would use it.  Also some verilog code snippets would really help! concepts.


My target audience are hardware designers who consider themselves
relatively experienced, and my goal is to challenge their conventional
wisdom. I don't think there's a lack of tutorial-level info, but
there definitely is a lack of critical and historical review of the
concepts.

> Also I am confused about whether the simulator's non-deterministic 
> behaviour is caused because your code is actually non-deterministic on 
> the chip...

The two are not really related. For digital design to be
possible, it should be deterministic. A lot of what is done when
developing silicon processes or gate-level libraries is related
to this. How a simulator supports determinism is another matter.
VHDL does it automatically, Verilog makes it surprizingly hard.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Blog post about Verilog

[Andrew S. <g.a...@gm...>]

Hi Jan,

I'm a dabbler at HDL but am experienced at software on von-neumann machines
and well, I feel like I can just barely NOT follow what you are trying to
say :-(.  Which is a lot more frustrating than it being completely over my
head.

I would think that any reasonable simulator would execute concurrent
hardware in random order, or multiple times in multiple orders (and compare
the outputs), or even better, model each bit as "1", "0" or "undetermined"
-- i.e. in the process of being changed -- and raise a BIG flag if you
access an "undetermined" bit! :-).  I'm guessing from your post that that is
not the case.

If you are targeting the blog for wider audiences, maybe a quick definition
of what synchronous RTL design IS, maybe an example of when you would use
it.  Also some verilog code snippets would really help!

Also I am confused about whether the simulator's non-deterministic behaviour
is caused because your code is actually non-deterministic on the chip...

Cheers!
Andrew



On Thu, Oct 14, 2010 at 2:14 PM, Jan Decaluwe <ja...@ja...> wrote:

> Kevin Stanton wrote:
> > Excellent writeup.
> >
> > I wish someone had written such a clear explanation back when I was
> > using Verilog for my college design project. We were so confused by that.
>
> Nice to hear, especially from an American ;-)
>
> After 20 years in this business, I find it astonishing
> that my view on HDL design is only shared by a small minority.
> Moreover, I don't know *any* Verilog-only guru that shares
> them - and I blame the confusing aspects of the language for this.
> The problem is - I think I'm right :-) This blog is an
> opportunity to explain my thinking as clearly as possible.
> A (hopefully) intermediate testament, so to speak.
>
> Much more to come!
>
> Jan
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Beautiful is writing same markup. Internet Explorer 9 supports
> standards for HTML5, CSS3, SVG 1.1,  ECMAScript5, and DOM L2 & L3.
> Spend less time writing and  rewriting code and more time creating great
> experiences on the web. Be a part of the beta today.
> http://p.sf.net/sfu/beautyoftheweb
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Blog post about Verilog

[Jan D. <ja...@ja...>]

Kevin Stanton wrote:
> Excellent writeup.
> 
> I wish someone had written such a clear explanation back when I was 
> using Verilog for my college design project. We were so confused by that.

Nice to hear, especially from an American ;-)

After 20 years in this business, I find it astonishing
that my view on HDL design is only shared by a small minority.
Moreover, I don't know *any* Verilog-only guru that shares
them - and I blame the confusing aspects of the language for this.
The problem is - I think I'm right :-) This blog is an
opportunity to explain my thinking as clearly as possible.
A (hopefully) intermediate testament, so to speak.

Much more to come!

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Default value of intbv - proposed change

[Jan D. <ja...@ja...>]

Kevin Stanton wrote:
> Jan,
> 
> Any reason to not model signal resolution with 'Z', 'H', 'L' as in VHDL, 
> or is this handled in some other manner?

Tristates are now interpreted as a kind of shadow signal.

http://www.myhdl.org/doku.php/meps:mep-103

http://www.myhdl.org/doku.php/meps:mep-105

Should work in simulation and conversion, but is not documented
currently in the manual, and I personally didn't use it yet.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Default value of intbv - proposed change

[Kevin S. <sta...@gm...>]

Jan,

Any reason to not model signal resolution with 'Z', 'H', 'L' as in VHDL, or
is this handled in some other manner?

Kevin

On Sun, Oct 10, 2010 at 3:24 PM, Jan Decaluwe <ja...@ja...> wrote:

> There is just one last thing I'd like to change
> before feature-freezing 0.7.
>
> At some point the default intbv value was 0, but
> then I changed it to None. I thought this would be
> necessary to support tristates.
>
> In the mean time, tristates can be supported rather well
> by ShadowSignals, and the None default for intbv's doesn't
> really make sense. It only takes away some performance
> due to superfluous testing.
>
> I propose to change the default value back to 0.
>
> The difference:
>
>  intbv() currently has None as initial value
>         would now have 0 as initial value
>
> Objections?
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Beautiful is writing same markup. Internet Explorer 9 supports
> standards for HTML5, CSS3, SVG 1.1,  ECMAScript5, and DOM L2 & L3.
> Spend less time writing and  rewriting code and more time creating great
> experiences on the web. Be a part of the beta today.
> http://p.sf.net/sfu/beautyoftheweb
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Verilator as a backend to myhdl?

[Terry C. <ter...@gm...>]

Hi myhdl gurus,

I finally managed to get the verilator model into python via boost.python
and got it working w/ myhdl. Here are my experiences with it:
1. I really enjoyed using myhdl. It is just such a joy to use compare to
verilog. Once the verilator model was in python getting the myhdl testbench
to work was almost effortless.
2. Unfortunately, just as Jan had predicted, the simulation time went up
drastically b/c python's in the loop. Especially when the testbench
environment started to get complicated with all sorts of dram backdoor
access and soft cpus set-up. I ran myhdl w/ Python cProfile and realized
that it was spending a good 60 to 70% of its times in python function
calls.

So, the python/myhdl as a top level driver idea is probably a no-go at this
point. I am toying with the idea of using a light-weight C threading system
and using Google Test as the unit testing environment.

The question now remains is whether anyone would be interested in the
verilator/myhdl makefile-based flow I have here. I could spend maybe 30mins
cleaning stuff up and removing all the proprietary RTL code and push it into
github or bitbucket. It is nothing amazing, but maybe someone might find it
interesting as a mechanism to get legacy verilog code to work w/ new (or
existing) myhdl code.

Regards,
Terry

Re: [myhdl-list] Blog post about Verilog

[Kevin S. <sta...@gm...>]

Excellent writeup.

I wish someone had written such a clear explanation back when I was using
Verilog for my college design project. We were so confused by that.

I've used VHDL ever since.

On Wed, Oct 6, 2010 at 10:13 AM, Jan Decaluwe <ja...@ja...> wrote:

> For those interested, I have blogged about my
> experiences with Verilog. They explain some design
> decision in MyHDL.
>
> http://www.sigasi.com/content/verilogs-major-flaw
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Beautiful is writing same markup. Internet Explorer 9 supports
> standards for HTML5, CSS3, SVG 1.1,  ECMAScript5, and DOM L2 & L3.
> Spend less time writing and  rewriting code and more time creating great
> experiences on the web. Be a part of the beta today.
> http://p.sf.net/sfu/beautyoftheweb
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

[myhdl-list] Default value of intbv - proposed change

[Jan D. <ja...@ja...>]

There is just one last thing I'd like to change
before feature-freezing 0.7.

At some point the default intbv value was 0, but
then I changed it to None. I thought this would be
necessary to support tristates.

In the mean time, tristates can be supported rather well
by ShadowSignals, and the None default for intbv's doesn't
really make sense. It only takes away some performance
due to superfluous testing.

I propose to change the default value back to 0.

The difference:

 intbv() currently has None as initial value
         would now have 0 as initial value

Objections?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Verilog blocking assignments in combinatorial logic

[Jan D. <ja...@ja...>]

Recently I found out that Verilog non-blocking assignments were
less general as I though w.r.t preventing non-determinism.

This weakens my earlier position to use non-blocking assignments
everywhere for communication, also in combinatorial logic.

I propose to give in and use blocking assignments in combinatorial
logic by default. (There is a new configuration attribute to control this.)

Objections, anybody? I guess not.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Verilator as a backend to myhdl?

[Christopher L. F. <chr...@gm...>]

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
<html>
  <head>
    <meta content="text/html; charset=ISO-8859-1"
      http-equiv="Content-Type">
  </head>
  <body bgcolor="#ffffff" text="#000000">
    On 10/8/2010 9:59 AM, Terry Chen wrote:
    <blockquote
      cite="mid:AANLkTi=25KZ7vbOoA5iyLfWUjm=iDfbbyk_NWJt=Ad...@ma..."
      type="cite">Hi Chris,<br>
      <br>
      I agree with you completely. Unfortunately, the output of
      verilator is a C++ class, so I had to wrap C++ verilated code plus
      the C golden model I already had. The good news is that I
      struggled for some time with Boost.Python last night and finally
      get a simple verilated model (of a single clock fifo) to run under
      Python. Now I just need to figure out how to shoehorn it into
      myhdl and figure out how to dump VCD properly.<br>
      <br>
      Thanks,<br>
      Terry<br>
      <br>
    </blockquote>
    <br>
    I assume the verilator doesn't support PLI/VPI?&nbsp; I am not familiar
    with verilator (sounds like it creates C++ code from a verilog
    input).&nbsp; GHDL works similiar (kinda but not really) in that it
    creates an executable.&nbsp; But that executable has a the PLI/VPI built
    in.&nbsp; <br>
    <br>
    Do you know if verilator supports (plans to) PLI/VPI.&nbsp; <br>
    <br>
    Sounds like you are making good progress and other might be
    interested as well.&nbsp; Is the following your current development flow?<br>
    <br>
    <ol>
      <li>MyHDL/Python testbench</li>
      <li>MyHDL RTL</li>
      <li>MyHDL RTL conversion to Verilog</li>
      <li>Verilog conversion to C++ (via verilator)</li>
      <li>MyHDL / Python testbench co-sim with C++</li>
    </ol>
    ??<br>
    <br>
    If you are really looking for C/C++ output one approach would be to
    create a C/C++ converter backend for MyHDL (essentially replacing
    verilator).&nbsp; Since Jan has all the Python parsing etc, it really
    might not be that hard of a task.&nbsp; Then you have the flexibility to
    add what you want to the generated C/C++<br>
    <br>
    Personally I like the original Co-simulation.&nbsp; Most of my work is
    with signal-processing (DSP) digital circuits.&nbsp; I like to have
    complex testbenches in Python/MyHDL.&nbsp; I like to reuse these
    testbenches to drive the Verilog/VHDL simulation and the final
    netlist simulation.&nbsp; The testbenches that I create in MyHDL would
    never be convertible to Verilog/VHDL, IMO.<br>
    <br>
    .chris<br>
    <br>
    <blockquote
      cite="mid:AANLkTi=25KZ7vbOoA5iyLfWUjm=iDfbbyk_NWJt=Ad...@ma..."
      type="cite"><br>
      <div class="gmail_quote">On Fri, Oct 8, 2010 at 10:18 AM,
        Christopher L. Felton <span dir="ltr">&lt;<a
            moz-do-not-send="true" href="mailto:chr...@gm...">chr...@gm...</a>&gt;</span>
        wrote:<br>
        <blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt
          0.8ex; border-left: 1px solid rgb(204, 204, 204);
          padding-left: 1ex;">
          <div class="im"> &nbsp;On 10/7/2010 5:40 PM, Terry Chen wrote:<br>
            &gt; Hello Lane,<br>
            &gt;<br>
            &gt; Thanks for the reply, actually I was just thinking
            about using<br>
            &gt; Boost.Python to wrap the C code. It is relatively easy
            for simple<br>
            &gt; blocks, but I have to explicitly list which C
            variables/function/class<br>
            &gt; I want accessible. Maybe I could get away with using
            Pyste/Py++ to<br>
            &gt; automate the C to Python layer generation. Do you (or
            anyone else),<br>
            &gt; have any experience with this? I am afraid of going
            over-the-top with<br>
            &gt; this.<br>
            <br>
          </div>
          Unless you are using C++ boost.Python is a little much. &nbsp;I
          have had much<br>
          better results just using ctypes. &nbsp;I have done projects with
          both and<br>
          usually end up abondoning boost.Python for ctypes. &nbsp;I have not
          written<br>
          the native C extension as Lane described, always have used
          ctypes.<br>
          ctypes is part of the Python distribution and numpy has good
          support for<br>
          cytpes as well.<br>
          <br>
          .chris<br>
          <div>
            <div class="h5"><br>
              <br>
              <br>
------------------------------------------------------------------------------<br>
              Beautiful is writing same markup. Internet Explorer 9
              supports<br>
              standards for HTML5, CSS3, SVG 1.1, &nbsp;ECMAScript5, and DOM
              L2 &amp; L3.<br>
              Spend less time writing and &nbsp;rewriting code and more time
              creating great<br>
              experiences on the web. Be a part of the beta today.<br>
              <a moz-do-not-send="true"
                href="http://p.sf.net/sfu/beautyoftheweb"
                target="_blank">http://p.sf.net/sfu/beautyoftheweb</a><br>
              _______________________________________________<br>
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                target="_blank">https://lists.sourceforge.net/lists/listinfo/myhdl-list</a><br>
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        </blockquote>
      </div>
      <br>
      <pre wrap="">
<fieldset class="mimeAttachmentHeader"></fieldset>
------------------------------------------------------------------------------
Beautiful is writing same markup. Internet Explorer 9 supports
standards for HTML5, CSS3, SVG 1.1,  ECMAScript5, and DOM L2 &amp; L3.
Spend less time writing and  rewriting code and more time creating great
experiences on the web. Be a part of the beta today.
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</pre>
    </blockquote>
    <br>
  </body>
</html>

Re: [myhdl-list] Verilator as a backend to myhdl?

[Terry C. <ter...@gm...>]

Hi Chris,

I agree with you completely. Unfortunately, the output of verilator is a C++
class, so I had to wrap C++ verilated code plus the C golden model I already
had. The good news is that I struggled for some time with Boost.Python last
night and finally get a simple verilated model (of a single clock fifo) to
run under Python. Now I just need to figure out how to shoehorn it into
myhdl and figure out how to dump VCD properly.

Thanks,
Terry


On Fri, Oct 8, 2010 at 10:18 AM, Christopher L. Felton <
chr...@gm...> wrote:

>  On 10/7/2010 5:40 PM, Terry Chen wrote:
> > Hello Lane,
> >
> > Thanks for the reply, actually I was just thinking about using
> > Boost.Python to wrap the C code. It is relatively easy for simple
> > blocks, but I have to explicitly list which C variables/function/class
> > I want accessible. Maybe I could get away with using Pyste/Py++ to
> > automate the C to Python layer generation. Do you (or anyone else),
> > have any experience with this? I am afraid of going over-the-top with
> > this.
>
> Unless you are using C++ boost.Python is a little much.  I have had much
> better results just using ctypes.  I have done projects with both and
> usually end up abondoning boost.Python for ctypes.  I have not written
> the native C extension as Lane described, always have used ctypes.
> ctypes is part of the Python distribution and numpy has good support for
> cytpes as well.
>
> .chris
>
>
>
>
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