myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] [ANNOUNCE] MyHDL 0.7

[Jan D. <ja...@ja...>]

I'm happy to announce MyHDL 0.7.

MyHDL is Python used as a Hardware Description Language.

Overview:
   http://www.myhdl.org/doku.php/overview

What's new in this release:
   http://www.myhdl.org/doc/0.7/whatsnew/0.7.html

Download:
   http://sourceforge.net/project/showfiles.php?group_id=91207

Best regards,

Jan Decaluwe

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] 0.7 release plan

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> So, Dec 21st came and past.  Sorry for not delivering any useful 
> feedback.  Weather and other unexpected events contributed to my failure 
> to allocate enough time to thoroughly review (excuses, excuses I have :) ).

No worries, we'll make it a white christmas release :-)

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] 0.7 release plan

[Christopher F. <chr...@gm...>]

So, Dec 21st came and past.  Sorry for not delivering any useful feedback.
 Weather and other unexpected events contributed to my failure to allocate
enough time to thoroughly review (excuses, excuses I have :) ).

I have done a first pass on the docs (skimmed) and it looks very useful.

Thanks again for all you work on this project!  I know the effort required
to design, implemented, test and document.

I will continue to look at the documents and send questions / suggestions
when I get them.  Can't promise a timely response but will do my best.

.chris


On Thu, Dec 23, 2010 at 3:41 AM, Jan Decaluwe <ja...@ja...> wrote:

> Christopher Felton wrote:
> >
> >
> > On Sun, Dec 19, 2010 at 2:37 PM, Jan Decaluwe <ja...@ja...
> > <mailto:ja...@ja...>> wrote:
> >
> >     I am planning to get 0.7 out of the door next Tuesday, Dec 21.
> >
> >     I have updated the documentation and already uploaded it to
> >     the website. The online repos are up to date also, with
> >     version number 0.7. Basically, only tagging and uploading
> >     to SourceForge remains to be done.
> >
> >     I am planning a final selective documentation proofread
> >     for typo's and to check whether anything critical is
> >     missing. If you are willing to review and find anything,
> >     let me know.
> >
> >     Jan
> >
> >
> > I will have a little time before the 21st that I can donate.  I will
> > start reviewing the online documentation,
>
> Any feedback?
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
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Re: [myhdl-list] 0.7 release plan

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> 
> 
> On Sun, Dec 19, 2010 at 2:37 PM, Jan Decaluwe <ja...@ja... 
> <mailto:ja...@ja...>> wrote:
> 
>     I am planning to get 0.7 out of the door next Tuesday, Dec 21.
> 
>     I have updated the documentation and already uploaded it to
>     the website. The online repos are up to date also, with
>     version number 0.7. Basically, only tagging and uploading
>     to SourceForge remains to be done.
> 
>     I am planning a final selective documentation proofread
>     for typo's and to check whether anything critical is
>     missing. If you are willing to review and find anything,
>     let me know.
> 
>     Jan
> 
> 
> I will have a little time before the 21st that I can donate.  I will 
> start reviewing the online documentation, 

Any feedback?

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Time for reflection

[Jan D. <ja...@ja...>]

http://www.sigasi.com/content/time-reflection

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] 0.7 release plan

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> 
> 
> On Sun, Dec 19, 2010 at 2:37 PM, Jan Decaluwe <ja...@ja... 
> <mailto:ja...@ja...>> wrote:
> 
>     I am planning to get 0.7 out of the door next Tuesday, Dec 21.
> 
>     I have updated the documentation and already uploaded it to
>     the website. The online repos are up to date also, with
>     version number 0.7. Basically, only tagging and uploading
>     to SourceForge remains to be done.
> 
>     I am planning a final selective documentation proofread
>     for typo's and to check whether anything critical is
>     missing. If you are willing to review and find anything,
>     let me know.
> 
>     Jan
> 
> 
> I will have a little time before the 21st that I can donate.  I will 
> start reviewing the online documentation, let me know if there is 
> specific selections you would like feedback.

Starting point is the what's new document with some small rewordings:

    http://www.myhdl.org/doc/current/whatsnew/0.7.html

When applicable, new features/changes are documented in the manual.

In the first place in the reference chapter:

    http://www.myhdl.org/doc/current/manual/reference.html

Shadow signals in the user manual:

    http://www.myhdl.org/doc/current/manual/modeling.html#converting-between-lists-of-signals-and-bit-vectors

New way for user-defined code:

    http://www.myhdl.org/doc/current/manual/conversion.html#user-defined-code
    http://www.myhdl.org/doc/current/manual/conversion_examples.html#user-defined-code

Docstring conversion:

http://www.myhdl.org/doc/current/manual/conversion.html#docstrings

I have made some more smaller edits, the easiest way to check these is probably
via the mercurial repo.

Jan

Re: [myhdl-list] 0.7 release plan

[Christopher F. <chr...@gm...>]

On Sun, Dec 19, 2010 at 2:37 PM, Jan Decaluwe <ja...@ja...> wrote:

> I am planning to get 0.7 out of the door next Tuesday, Dec 21.
>
> I have updated the documentation and already uploaded it to
> the website. The online repos are up to date also, with
> version number 0.7. Basically, only tagging and uploading
> to SourceForge remains to be done.
>
> I am planning a final selective documentation proofread
> for typo's and to check whether anything critical is
> missing. If you are willing to review and find anything,
> let me know.
>
> Jan
>
>
I will have a little time before the 21st that I can donate.  I will start
reviewing the online documentation, let me know if there is specific
selections you would like feedback.

.chris


>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Lotusphere 2011
> Register now for Lotusphere 2011 and learn how
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>

Re: [myhdl-list] 0.7 release plan

[Christopher F. <chr...@gm...>]

On Sun, Dec 19, 2010 at 2:37 PM, Jan Decaluwe <ja...@ja...> wrote:

> I am planning to get 0.7 out of the door next Tuesday, Dec 21.
>
> I have updated the documentation and already uploaded it to
> the website. The online repos are up to date also, with
> version number 0.7. Basically, only tagging and uploading
> to SourceForge remains to be done.
>
> I am planning a final selective documentation proofread
> for typo's and to check whether anything critical is
> missing. If you are willing to review and find anything,
> let me know.
>
> Jan
>
>
I will have a little time before the 21st that I can donate.  I will start
reviewing the online documentation, let me know if there is specific
selections you would like feedback.

.chris


>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Lotusphere 2011
> Register now for Lotusphere 2011 and learn how
> to connect the dots, take your collaborative environment
> to the next level, and enter the era of Social Business.
> http://p.sf.net/sfu/lotusphere-d2d
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] 0.7 release plan

[Jan D. <ja...@ja...>]

I am planning to get 0.7 out of the door next Tuesday, Dec 21.

I have updated the documentation and already uploaded it to
the website. The online repos are up to date also, with
version number 0.7. Basically, only tagging and uploading
to SourceForge remains to be done.

I am planning a final selective documentation proofread
for typo's and to check whether anything critical is
missing. If you are willing to review and find anything,
let me know.

Jan



-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Another MyHDL powered Soft Processor and some bugs in MyHDL

[Jian L. <jia...@go...>]

Hi List,

I've uploaded my recent Soft Processor Project on opencores. It's a
synthesizable clone of MicroBlaze called myBlaze.
The Hello world and fibonacci tests runs well on the spartan3e starter kit
with uart as the default output.

Here is the project homepage: http://opencores.org/project,myblaze
I'll write some instructions when I get time. However, I believe, the code
mostly explains itself.

And during the coding, I might just find two bugs in MyHDL conversion:
1. Name of a ram type won't be convert correctly in user defined verilog
(and might be in vhdl too).
  A dirty workaround is to subclass list like this:

  .def RAMInitial(ram, filename, clock):
  .    __verilog__ = """
  .    initial $readmemh("%(filename)s", %(ram)s);
  .    """
  .    __vhdl__ = """
  .    """
  .    @instance
  .    def initial():
  .        vals = open(filename).readlines()
  .        for i,v in enumerate(vals):
  .            ram[i].next = int(v, 16)
  .        yield clock.negedge
  .    return instances()
  .
  .# XXX: Hacked to make $readmemh work
  .class RAM(list):
  .    # representation
  .    def __str__(self):
  .        from myhdl._extractHierarchy import _memInfoMap
  .        if id(self) in _memInfoMap:
  .            return _memInfoMap[id(self)].name
  .        else:
  .            return list.__str__(self)

  and use RAM, RAMInitial to define and initialize a ram.

  So far, it works for me both in Xilinx ISE and Altera Quartus II. But I
think it would be nice if myhdl supports initial value by default.
  Any plan, Jan?

2. if __debug__: instructions seems broken in top level hierarchy. Code like
following doesn't work as expected:

  . def ExampleDummy(x, y):
  .    ...
  .    if __debug__:
  .        return z
  .    return z, debug_logic

  but if I wrap it as a instance in some higher modules, it works again. My
guess is: analyze process just overlooks such situation.


Gruss

Jian

Re: [myhdl-list] project finished

[Jan D. <ja...@ja...>]

I would wait on the response of your teachers, and if they are
positive about it, write something about your project so that
others can learn from your example.

I would do it in English to have the broadest possible audience.
I doesn't have to be on the MyHDL wiki itself, but if you
want that is available of course.

Jan


Martín Gaitán wrote:
> I've just finished my project (the DLX/MIPS processor) and its report.  
> I have no feedback from the lab teacher yet (of course, I've just sent 
> it ... and it's saturday) but I think it's working fine.
> 
> The experience with MyHDL was very successfully . At the beginning the 
> learning curve was a bit steep , because more than one, really: MyHDL 
> itself, HDL's in general and the DLX architecture in particular. But, 
> clearly, was nothing impossible.  I don't know if a comparison is valid 
> because I was specially rushed to get it done, but everybody else at the 
> course are still fighting with testbenchs in VHDL and the abusive 
> consumption of RAM of the Xilinx's IDE. 
> 
> I don't know if I'll use MyHDL again sometime in the future (never say 
> never) but I would like to contribute to the project in some way. For 
> example, translating or writing an article about it. I found this 
> article in portuguese,
> 
> http://www.cin.ufpe.br/~cinlug/wiki/index.php/Hardware_myhdl_python
> 
> what do you think about translate it to spanish ? Are the the author, 
> Rodrigo Peixoto, in this list?  May be something more updated ?
> 
> 
> Cheers
> Martin
> 
> 
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] project finished

[Martín G. <ga...@gm...>]

I've just finished my project (the DLX/MIPS processor) and its report.  I
have no feedback from the lab teacher yet (of course, I've just sent it ...
and it's saturday) but I think it's working fine.

The experience with MyHDL was very successfully . At the beginning the
learning curve was a bit steep , because more than one, really: MyHDL
itself, HDL's in general and the DLX architecture in particular. But,
clearly, was nothing impossible.  I don't know if a comparison is valid
because I was specially rushed to get it done, but everybody else at the
course are still fighting with testbenchs in VHDL and the abusive
consumption of RAM of the Xilinx's IDE.

I don't know if I'll use MyHDL again sometime in the future (never say
never) but I would like to contribute to the project in some way. For
example, translating or writing an article about it. I found this article in
portuguese,

http://www.cin.ufpe.br/~cinlug/wiki/index.php/Hardware_myhdl_python

what do you think about translate it to spanish ? Are the the author,
Rodrigo Peixoto, in this list?  May be something more updated ?


Cheers
Martin

Re: [myhdl-list] understanding Signal and intbv

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> Am 12.11.2010 11:18, schrieb Jan Decaluwe:
>> Thomas Heller wrote:
>>> I cannot find out how to split the bus into single bits (or parts)
>>> so that I can connect them to instances.
> [...]
>> Short answer: in 0.7, you can use the Signal call interface
>> to construct implicit signals that work as expected in structure.
>>
>> Longer answer:
>>
>> This is what I consider to be MyHDL's most important gotcha.
>> In MyHDL 0.7, I introduce a solution called ShadowSignals - however
>> be warned that it's not as intuitive as with compiled HDLs, where
>> the meaning of slicing can be derived from the code context
>> by a compiler.
>>
>> Background info starting point:
>>
>>      http://www.myhdl.org/doc/dev/whatsnew/0.7.html#shadow-signals
>>
> Thanks, Jan, for this answer.  0.7 seems to work as expected.
> I have to believe you that it is a good decision to make ShadowSignals
> readonly, but let me ask one question:

It's not really a decision - it's more that I can't figure out how
"writing" should work. Note that shadow signals really "follow" their
parents with one delta cycle. That is easy to do. But the inverse?
All kinds of issues pop up. Reading and writing are not symmetric.

Fortunately, I think, "following" is what we normally need. And
ConcatSignal's can sort of emulate the inverse of slicing.

> Why can't you use slicing/indexing notation to create a shadow signal?
> Performance?  Backwards compatibility?  Education of the programmer?
> Or is it simply not possible?

Suppose I would return a _SliceSignal shadow signal whenever a signal
is sliced. Now consider the case of slicing inside a generator. The only
thing you need (in traditional HDL design) is the current value of the slice.
But to obtain that, you would go through the whole process of creating
a Signal, which means all kinds of datastructures that will never be
used. And this everytime you slice, typically over and over again
during a simulation. I haven't run actual tests, but it seems obvious
this is simply unacceptable performance-wise.

You can create Signals on the fly during simulation if you want to
(unlike compiled HDLs), but creating them without using any of the
services that they are designed for is really not the intention.

> It seems a little error-prone having to use the call interface in one
> case and the indexing notation in the other case.

I agree again that it's awkward to have the two notations.

On the other hand:
With my VHDL-influenced HDL hat on, signals are really "static" things
created once before the simulation starts and that then live on "forever".
Outside generators, I think structure and signals. Inside them
I think variables and values. ShadowSignals are part of the structure,
regular slicing of generator behavior. The call interface suggest
that something new is "constructed" which is what really happens
with this workaround.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] understanding Signal and intbv

[Thomas H. <th...@ct...>]

Am 12.11.2010 11:18, schrieb Jan Decaluwe:
> Thomas Heller wrote:
>> I cannot find out how to split the bus into single bits (or parts)
>> so that I can connect them to instances.
[...]
>
> Short answer: in 0.7, you can use the Signal call interface
> to construct implicit signals that work as expected in structure.
>
> Longer answer:
>
> This is what I consider to be MyHDL's most important gotcha.
> In MyHDL 0.7, I introduce a solution called ShadowSignals - however
> be warned that it's not as intuitive as with compiled HDLs, where
> the meaning of slicing can be derived from the code context
> by a compiler.
>
> Background info starting point:
>
>      http://www.myhdl.org/doc/dev/whatsnew/0.7.html#shadow-signals
>
Thanks, Jan, for this answer.  0.7 seems to work as expected.
I have to believe you that it is a good decision to make ShadowSignals
readonly, but let me ask one question:

Why can't you use slicing/indexing notation to create a shadow signal?
Performance?  Backwards compatibility?  Education of the programmer?
Or is it simply not possible?

It seems a little error-prone having to use the call interface in one
case and the indexing notation in the other case.

Thanks,
Thomas

Re: [myhdl-list] understanding Signal and intbv

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have a 4-bit wide bus:
> 
>    bus = Signal(intbv(0)[4:])
> 
> I cannot find out how to split the bus into single bits (or parts)
> so that I can connect them to instances.  For example:
> 
>    def xor(a, b, q):
>        @always_comb
>        def inst():
>            q.next = a ^ b
>        return inst
> 
>    output = Signal(False)
> 
>    gate = xor(bus[1:0], bus[2:0], output)
> 
> bus[0] returns the current value of bit 0 and not the bus signal itself, 
> bus[1:0] returns a completely _new_ intbv object.
> 
> How would I do this?

Short answer: in 0.7, you can use the Signal call interface
to construct implicit signals that work as expected in structure.

Longer answer:

This is what I consider to be MyHDL's most important gotcha.
In MyHDL 0.7, I introduce a solution called ShadowSignals - however
be warned that it's not as intuitive as with compiled HDLs, where
the meaning of slicing can be derived from the code context
by a compiler.

Background info starting point:

    http://www.myhdl.org/doc/dev/whatsnew/0.7.html#shadow-signals


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] How does traceSignals find its signals?

[Jan D. <ja...@ja...>]

Signal lookup is done by a function that "extracts the
hierarchy" of a design. The concept of "hierarchy" is currently
understood in a traditional HDL way, with a module containing
signals, processes and submodule instantiations. In MyHDL this is
modeled by a top-level functions containing signals, specific generators,
and sub-level function calls.

Signal lookup in namespaces such as classes is currently not
understood in this definition of hierarchy, and therefore not
supported by hierarchy extraction.

One option is to write "simpler" test benches without classes,
such as supported by py.test.

Jan


as...@gm... wrote:
> I'm an experienced Python programmer but a novice with modern HDLs.
> I'm trying MyHDL because of its potential to make very sophisticated
> test benches.  But I'm having difficulty using traceSignals.  My
> circuit simulates fine, but the resulting .vcd file contains no
> signals at all.  Is the unittest framework somehow confusing
> traceSignals?
> 
> #! /usr/bin/python
> 
> import unittest
> 
> from myhdl import *
> 
> def dff(D, Q, CLK):
>   """A D flip flop"""
>   @always(CLK.posedge)
>   def process():
>     Q.next = D
>   return process
> 
> 
> class TestDFF(unittest.TestCase):
>   def setUp(self):
>     self.D = Signal(False)
>     self.Q = Signal(False)
>     self.CLK = Signal(False)
>     self.inst = dff(self.D, self.Q, self.CLK)
> 
>   def testDff(self):
>     @instance
>     def dff_tb():
>       yield delay(1)
>       self.CLK.next = True
>       yield delay(1)
>       self.assertEqual(self.Q, False)
>       self.CLK.next = False
>       yield delay(1)
>       self.D.next = True
>       yield delay(1)
>       self.CLK.next = True
>       yield delay(1)
>       self.assertEqual(self.Q, True)
>     def foo():
>       return dff_tb, self.inst
>     foo_tb = traceSignals(foo)
>     sim = Simulation(foo_tb)
>     sim.run(quiet=True)
> 
> unittest.main()
> 
> ------------------------------------------------------------------------------
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
   Python as a HDL: http://www.myhdl.org
   VHDL development, the modern way: http://www.sigasi.com
   Analog design automation: http://www.mephisto-da.com
   World-class digital design: http://www.easics.com

[myhdl-list] understanding Signal and intbv

[Thomas H. <th...@ct...>]

I have a 4-bit wide bus:

   bus = Signal(intbv(0)[4:])

I cannot find out how to split the bus into single bits (or parts)
so that I can connect them to instances.  For example:

   def xor(a, b, q):
       @always_comb
       def inst():
           q.next = a ^ b
       return inst

   output = Signal(False)

   gate = xor(bus[1:0], bus[2:0], output)

bus[0] returns the current value of bit 0 and not the bus signal itself, 
bus[1:0] returns a completely _new_ intbv object.

How would I do this?

Thanks,
Thomas

[myhdl-list] How does traceSignals find its signals?

[<as...@gm...>]

I'm an experienced Python programmer but a novice with modern HDLs.
I'm trying MyHDL because of its potential to make very sophisticated
test benches.  But I'm having difficulty using traceSignals.  My
circuit simulates fine, but the resulting .vcd file contains no
signals at all.  Is the unittest framework somehow confusing
traceSignals?

#! /usr/bin/python

import unittest

from myhdl import *

def dff(D, Q, CLK):
  """A D flip flop"""
  @always(CLK.posedge)
  def process():
    Q.next = D
  return process


class TestDFF(unittest.TestCase):
  def setUp(self):
    self.D = Signal(False)
    self.Q = Signal(False)
    self.CLK = Signal(False)
    self.inst = dff(self.D, self.Q, self.CLK)

  def testDff(self):
    @instance
    def dff_tb():
      yield delay(1)
      self.CLK.next = True
      yield delay(1)
      self.assertEqual(self.Q, False)
      self.CLK.next = False
      yield delay(1)
      self.D.next = True
      yield delay(1)
      self.CLK.next = True
      yield delay(1)
      self.assertEqual(self.Q, True)
    def foo():
      return dff_tb, self.inst
    foo_tb = traceSignals(foo)
    sim = Simulation(foo_tb)
    sim.run(quiet=True)

unittest.main()

Re: [myhdl-list] beginning with unittests

[Andrew L. <bs...@al...>]

On 11/7/10 5:51 AM, Jan Decaluwe wrote:

> More importantly, unit tests work best if you write the test
> before the implementation. A unit that has never failed
> is not very useful. The idea is to start with something
> that fails, and then starts working as the implemenation
> progresses.

I don't find 'test-first' all that useful, personally.  This is my 
opinion for both HDL's and normal programming languages.

The reason for this is that 'test-first' spends too much time testing 
modules that work and too little time testing modules that don't.

I will write maybe a very basic test or two, and then start coding a module.

I tend to bulk up my tests during the debugging phase.  When debugging, 
I'm testing *anyway*.  I'm hunting for what's wrong: did the algorithm 
fail, did the preconditions fail, did an edge case get missed?  All of 
these require some form of "test".  Rather than it just being a human 
feeding in data and looking at results, formalizing this into a testcase 
is way more reliable and serves as communication to the next poor slob 
who has to look over the same code.

This has the advantage that your testing effort is focused as well as 
serving as a signal.  A module that has very few tests is either very 
reliable (I can write most forms of adders in my sleep and probably need 
fewer tests than my junior guys) or tests aren't that useful (a crossbar 
module probably either works completely or fails completely--there's not 
a lot of subtlety).  A module that has a ton of tests is either too 
complicated or too unreliable.  It probably needs to be rewritten and 
*now* you have the tests to verify your rewrite.

There's nothing quite as restraining to "This code sucks.  I need to 
rewrite it cleanly." as looking at a set of tests and realizing "Oh, I 
didn't think of all *those* cases.  Ewwwww."

Sometimes you'll still rewrite that module because it really is that 
bad, but at least with the tests you have realistic assessment of what 
you have to do.

-a

Re: [myhdl-list] Structures of signals as ports

[Jan D. <ja...@ja...>]

Oscar Daniel Diaz wrote:
> Hi
> 
> Recently I'm working in a class structure that helps me to design by
> blocks and automatic signal connection, among other possible features
> (graphic representation, document generation, etc.). 
> 
> I've been following MyHDL since 0.5, and I found troublesome being
> unable to use structures of signals as ports (I tried list of signals,
> dictionaries and objects with signals as members) when generating VHDL
> code. My reason to use structures are to avoid to write large list of
> signals that can easily be grouped.
> 
> So, I did a small workaround by writing a small VHDL generator that
> only supports component instantiations and portmaps. My idea is to
> define MyHDL blocks that can work standalone and generate its VHDL
> output, then using my object representation to generate VHDL code that
> glue all blocks together. However the code generator output is a file,
> so I'm forced to read again the generated file in order to extract
> useful information like entity section to components. 
> 
> So, basically I have two questions:
> 
> 1. How can I use a structure (tuple, list, dict or object) of signals
> like a port, either for simulation or code generation? 

For simulation, you can do anything you want, it should all work.

For conversion you have a lot of freedom in code outside generators.
For example, for modules with large interfaces I typically don't
use explicit name association in instantiations. I look up signals
in some signal name space by name and construct an association list
automatically.

However, inside generator code there simply isn't any support for
this type of thing whatsoever. It's a common question, and I plan
to address it in 0.8, but currently it's not supported.

> 2. Is there an actual way to get the toVHDL output to a string object?

Not currently, but probably this can be done as follows. If you think
this is useful, and want to write a patch, I'll consider adding it.

Create a new attribute to toVHDL called toVHDL.file, with default None.

You can assign a file object open for writing or a stringIO object
to that attribute. If so, toVHDL could use this instead of the
file it currently opens and closes itself. After running toVHDL, the
output should be in the file-like object under your control.
(toVHDL should not close this object.)


Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] beginning with unittests

[Jan D. <ja...@ja...>]

Martín Gaitán wrote:
> On Thu, Nov 4, 2010 at 6:26 PM, Jan Decaluwe <ja...@ja... 
> <mailto:ja...@ja...>> wrote:
> 
>     Perhaps because 0b0010 != 3 ?
> 
>     If this is the reason, why use all these different representations
>     for the same thing?
> 
>     Python 2.6 has bit representation for integer values. Any representation
>     should work with intbv's and in conversion.
> 
>     Jan
> 
> 
> right, and the best example of usefulness of unit test ;-)

Yes, interesting isn't it :-) Your original test bench that "worked"
also revealed the bug, but you overlooked it. It's the formal test
that revealed it.

Let me add a few comments here.

Your example demonstrates one feature of unit tests: use a formal
check instead of "inspection" to verify correctness.

This works best if there is some high-level way to specify the
expected result. In your case I would probably set up a dict
with operators from module operator, or your own function
if required:

spec = {0b0001 : operator.add,
        0b0110 : operator.sub,

       }

and then randomly generate operands and operator control sequences.

The alu operation would come down do: spec[op](*operands).

More importantly, unit tests work best if you write the test
before the implementation. A unit that has never failed
is not very useful. The idea is to start with something
that fails, and then starts working as the implemenation
progresses.

When your are done, you know that your design works according
to the unit test spec, but also that it can fail when you
change the implementation and introduce a bug!

Personally, I find unittest way too heavy. I simply
write regular python tests that use assert statements to
verify results. You can run this with a regular python
interpreter, but it is more useful to use a framework
like py.test (there are others) for this: this looks
up all your tests automatically, runs them, and uses
some magic to report issues in a clearer way.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Structures of signals as ports

[Oscar D. D. <osc...@gm...>]

Hi

Recently I'm working in a class structure that helps me to design by
blocks and automatic signal connection, among other possible features
(graphic representation, document generation, etc.). 

I've been following MyHDL since 0.5, and I found troublesome being
unable to use structures of signals as ports (I tried list of signals,
dictionaries and objects with signals as members) when generating VHDL
code. My reason to use structures are to avoid to write large list of
signals that can easily be grouped.

So, I did a small workaround by writing a small VHDL generator that
only supports component instantiations and portmaps. My idea is to
define MyHDL blocks that can work standalone and generate its VHDL
output, then using my object representation to generate VHDL code that
glue all blocks together. However the code generator output is a file,
so I'm forced to read again the generated file in order to extract
useful information like entity section to components. 

So, basically I have two questions:

1. How can I use a structure (tuple, list, dict or object) of signals
like a port, either for simulation or code generation? 

2. Is there an actual way to get the toVHDL output to a string object?

Right now I'm not a big expert of MyHDL or its internals, but I think I
can help writing patches to support this features that I desperately
need.

Thanks in advance.

-- 
Oscar Díaz
Key fingerprint = 904B 306C C3C2 7487 650B  BFAC EDA2 B702 90E9 9964
gpg --keyserver subkeys.pgp.net --recv-keys 90E99964

Re: [myhdl-list] beginning with unittests

[Martín G. <ga...@gm...>]

On Thu, Nov 4, 2010 at 6:26 PM, Jan Decaluwe <ja...@ja...> wrote:

> Perhaps because 0b0010 != 3 ?
>
> If this is the reason, why use all these different representations
> for the same thing?
>
> Python 2.6 has bit representation for integer values. Any representation
> should work with intbv's and in conversion.
>
> Jan
>
>
right, and the best example of usefulness of unit test ;-)

and, btw, thanks for the advice.

Re: [myhdl-list] beginning with unittests

[Jan D. <ja...@ja...>]

Perhaps because 0b0010 != 3 ?

If this is the reason, why use all these different representations
for the same thing?

Python 2.6 has bit representation for integer values. Any representation
should work with intbv's and in conversion.

Jan

Martín Gaitán wrote:
> Hi everybody.
> 
> I'm very happy because my project is progressing and, not a minor point, 
> I'm learning a lot in the way. My teachers are also very interested in 
> my heteredoxy (and myhdl, of course).
> 
> because I want to do the right things, I'm trying to begin write/use 
> unit tests.  my first attempt  fails :(
> 
> here it is:
> https://github.com/nqnwebs/pymips/blob/unittest/alu.py
> 
> I'm very newbie to unittesting field in general, so I'm not sure if it's 
> fails because the design or the test is wrong. What I want to do is very 
> simple: set up the control lines of 'alu' to the operation 'add' and 
> check if it effectively add the input signals.  Instead it, control 
> lines never changes (it keeps in 0) doing another operation ( AND 
> function) on the ALU.
> 
> The mystery (for me) is that my original testbenchs seems to work
> 
> https://github.com/nqnwebs/pymips/blob/master/alu.py
> 
> in this testbench I iterate over every valid 'control' value and set 
> inputs signals with random values. The outputs are right.
> 
> Control: 0000 | 156 AND 118 | 20 | z=0
> Control: 0001 | 55 OR 196 | 247 | z=0
> Control: 0010 | 248 add 195 | 247 | z=0
> Control: 0110 | 108 substract 19 | 89 | z=0
> Control: 0111 | 88 set on < 220 | 0 | z=1
> Control: 1100 | 232 NOR 115 | -252 | z=0
> 
> so, has  anybody a clue?
> 
> thanks for the patience.
> Martín
> 
> 
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] VHDL's crown jewel

[Jan D. <ja...@ja...>]

I have written a blog post about VHDL's delta cycle
algorithm - more specifically, the way it preserves determinism.

I also discuss Verilog - it doesn't have something
similar and is therefore conceptually nondeterministic.

I'll let you guess how MyHDL does it :-)

http://www.sigasi.com/content/vhdls-crown-jewel

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com