myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] FW: Floating-point support

[Jan C. <jan...@mu...>]

On 09/03/11 14:14, Christopher Felton wrote:

> You lost me a little, I think you might have mispoken.  You stated
> "request that interest me ... provision of synthesizable modules to perform
> basic FP ..."
> but then later said
> "... automatically string these modules together based on a higher level
> description is probably beyond my interest..."
>
> These are conflicting statements?  I am not sure what you are looking for
> but lets take an example, a simple floating-point expression in MyHDL

Sorry that my cautiousness to reply and provide explanation has 
cost you so much writing. Your 3 cents is much appreciated, but I 
only have a 1 cent answer.

Your design sketch would be appropriate where maximum processing 
rate is required, otherwise it would not be ideal.  Implementation 
efficiency can be increased by using a serial data format, and 
abandoning the IEEE float representation formats.

There is a clear processing speed penalty here.  There are also 
less obvious benefits: The chip area used is reduced by a greater 
proportion than the loss in performance.  When using streamed data 
with many values close to zero the number of bits pulled from 
memory is reduced by a large factor.

Because the proposed data representation is not IEEE compliant, any 
modelling requiring equivalent methods must use a suitable 
equivalent data type in python.  Two unconstrained integers may  be 
used to represent an unconstrained float.

For modelling purposes unconstrained integers can be represented in 
python as a list of packets of bits. This can be synthesized as a 
stream of packets of bits.  I now have tested models of an adder, 
multiplier, and barrel shifter, so with this, and a little extra 
sequencing glue I am ready to start testing python models of FP 
adder and multiplier.

The data representation and methods used are suitable for 
synthesis, and I do not expect further problems ,apart from having 
to learn to use MyHDL effectively.


> fp_in  = Signal(0.0)
> fp_out = Signal(0.0)
>
> def fp_expr1(clk, fp_in, fp_out):
>      a = Signal(0.125)
>      b = Signal(0.00344)
>      c = Signal(0.01)
>
>     @always (clk.posedge)
>     def rtl_fp():
>         fp_out.next = a*fp_in**2 + b*fp_in + c
>
>     return rtl_fp

Ok, so I need two adders for the final sum, one multiplier for the 
square, one constant multiplier for the *0.344, and a barrel 
shifters for the *0.125

My diagram would be much the same as yours, but I would want a 
separate component for multiplication by a constant to allow 
suitable optimisation.

Surplus logic in the barrel shifter would be optimised away because 
the shift value is a constant. Because power of two removal would 
be part of a constant multiplier this would be a better component 
choice than the barrel shifter.

The proposed system might require twice the number of clock cycles 
to process the signal, but would likely consume 50-90% less chip 
area.  The number of clock cycles is also dependant on required 
signal resolution, and the chosen signal buss width.  Therefore, if 
more clock cycles are available, these can be traded for further 
chip area reductions.

<snipped sim, synth, diagram, MyHDL code & dire warnings>

> Good luck, hope you guys are enthusiastic about this project and make some
> great progress!  Any questions please post to the group.
>
> my 3 cents
Thanks Chris, very much appreciated.  I could never have imagined 
just how much excitement I am planning to miss out on.

BTW, another interesting feature of unbounded floats is that they 
can declare their own resolution.

Jan Coombs
-- 

Re: [myhdl-list] FW: Floating-point support

[Christopher F. <cf...@uc...>]

>
> <snip>
>
> > Because MyHDL exists in the Python eco you get a ton of power with your
> > RTL but not high-level synthesis.  This could be a separate project that
> > works with MyHDL but it is a considerable effort (see other high-level
> > synthesis research).
>
> Starting to learn Python itself has been a major leap forward for
> me, only having previous experience of logic design and low level
> languages. Features new to me, and particularly useful to this
> project are unbounded ints and lists.
>
> The parts of David Bluebaugh's request that interested me are the
> provision of synthesizable modules to perform basic FP
> calculations, and pipeline components to connect them. (I'm
> probably taking a little liberty with his words here)
>
> Some sort of front end to automatically string these modules
> together based on a higher level description is probably beyond my
> interest and capability. I'm struggling to get up to speed with
> MyHDL. The low level components interest me as they are needed for
> another project.
>
> Jan Coombs
>
> <snip>


You lost me a little, I think you might have mispoken.  You stated
"request that interest me ... provision of synthesizable modules to perform
basic FP ..."
but then later said
"... automatically string these modules together based on a higher level
description is probably beyond my interest..."

These are conflicting statements?  I am not sure what you are looking for
but lets take an example, a simple floating-point expression in MyHDL

fp_in  = Signal(0.0)
fp_out = Signal(0.0)

def fp_expr1(clk, fp_in, fp_out):
    a = Signal(0.125)
    b = Signal(0.00344)
    c = Signal(0.01)

   @always (clk.posedge)
   def rtl_fp():
       fp_out.next = a*fp_in**2 + b*fp_in + c

   return rtl_fp

If you take the above and use it in MyHDL 0.7 it will simulate fine.  You
can build an RTL model of floating-point and model / simulate it (which is
very powerful in itself).  Now, if you try to take the above and convert it
to to Verilog/VHDL the conversion will fail.  Currently it will fail because
it will identify the Signals are not bool or intbv and raise an error.

To make the above convertible, in the form Jan C. and Dave B. have
mentioned, you would need to decompose the floating-point expression.  No
main-stream HDL synthesis (behavioral to netlist) will accept
floating-point, so the converter would need create synthesizable HDL.  In
other words direct conversion is not possible.  The converter would involve
breaking the floating-point expression down to basic parts and possibly
utilizing a pre-configured floating-point library.

The above example, the expression requires two floating-point additions, two
floating-point multiplications, and one floating-point square (exponential).
 The floating-point converter would need create something like the following
...

                *fp_in*
     *a*         /    -------\         *b*
      \    |fp_square|      \       /
       \     /               \     /
     |fp_lib_mult|         |fp_lib_mult|
          \                     /
           \                   /
            \                 /
             ------  +--------
                     |
                     \                 c
                      \               /
                       \             /
                        -----  + ----
                               |
                             *fp_out*

The above doesn't show any pipeline insertions or the user options to
control the pipeline insertions.  This representation could be converted to
a MyHDL expressions

(note the conversion of the Signal types, depend on single or double
precision, below example would be single precision)

fp_in  = Signal(intbv(0)[32:])
fp_out = Signal(intbv(0)[32:])

def fp_conversion(clk, fp_in, fp_out):
     fp_in2  = Signal(intbv(0)[32:])
     fp_in_a = Signal(intbv(0)[32:])
     fp_in_b = Signal(intbv(0)[32:])
     fp_sum1 = Signal(intbv(0)[32:])
     fp_sum2 = Signal(intbv(0)[32:])

     # Break the FP expression to instances from the FP lib
     fp1 = fp_lib_square(fp_in, fp_in2)
     fp2 = fp_lib_mult(fp_in2, a, fp_in_a)
     fp3 = fp_lib_mult(fp_in, b, fp_in_b)
     fp4 = fp_lib_add(fp_in_a, fp_in_b, fp_sum1)
     fp5 = fp_lib_add(fp_sum1, c, fp_sum2)

     @always (clk.posedge)
     def rtl_fp_conv():
         fp_out.next = fp_sum2

    return instances()


The above is probably an over simplification of the problem.  This is a huge
task to undertake, unless you really limit the scope, IMO.  To even get
started on such I project I believe the developers involved would need good
understanding of the following (and I am probably missing a bunch)

   - The Python parser and AST
   - Floating-point representation and floating-point digital libraries
   - MyHDL RTL conversion
   - Concurrent decompositions
   - Hardware inference

And that is for a simple case, the converter would need to support any
(most) Python expression.  Many other issues would arise, how would you
handle list of signals, arrays, etc.  As mentioned, this could be a good
thesis/dissertation project.  You probably could get funding to take on a
project of this scope.

I believe one of the huge issues with an approach like this is; How many FP
mults can an FPGA (or ASIC) reasonably use?  For an FPGA you might want to
limit the number of FP mults to 4 (as an example).  For the converter to be
useful it needs these constraints to be configurable and then build
state-machine (control logic) to multiplex the FP resources.

My guess, is that you guys are looking for something that can take a complex
expression, based on arrays and matrices and have that converted.  The above
example is a simple case of taking FP RTL, adding floating-point type to RTL
description.  This is not decomposing an algorithm consisting of for loops
and creating an RTL description.

Good luck, hope you guys are enthusiastic about this project and make some
great progress!  Any questions please post to the group.

my 3 cents
.chris

Re: [myhdl-list] FW: Floating-point support

[David B. <dav...@ya...>]

Jan,
 
What you are thinking regarding my words are exactly as to what I was thinking.  How would you like to proceed??
 
David Blubaugh
 
 


--- On Sun, 3/6/11, Jan Coombs <jan...@mu...> wrote:


From: Jan Coombs <jan...@mu...>
Subject: Re: [myhdl-list] FW: Floating-point support
To: myh...@li...
Date: Sunday, March 6, 2011, 2:40 PM


On 22/02/11 21:43, Christopher Felton wrote:
    . . .
> MyHDL is an RTL similar to VHDL and Verilog.  It has the same level support.
>   It does not do higher level synthesis.

Yes, thanks, but it seems much more friendly than the VHDL 
synthesis and simulation tools I've used for prototyping to date.

> Because MyHDL is exists in the Python eco you get a tone of power with your
> RTL but not high-level synthesis.  This could be a separate project that
> works with MyHDL but it is a considerable effort (see other high-level
> synthesis research).

Starting to learn Python itself has been a major leap forward for 
me, only having previous experience of logic design and low level 
languages. Features new to me, and particularly useful to this 
project are unbounded ints and lists.

The parts of David Bluebaugh's request that interested me are the 
provision of synthesizable modules to perform basic FP 
calculations, and pipeline components to connect them. (I'm 
probably taking a little liberty with his words here)

Some sort of front end to automatically string these modules 
together based on a higher level description is probably beyond my 
interest and capability. I'm struggling to get up to speed with 
MyHDL. The low level components interest me as they are needed for 
another project.

Jan Coombs

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Re: [myhdl-list] FW: Floating-point support

[Jan C. <jan...@mu...>]

On 22/02/11 21:43, Christopher Felton wrote:
    . . .
> MyHDL is an RTL similar to VHDL and Verilog.  It has the same level support.
>   It does not do higher level synthesis.

Yes, thanks, but it seems much more friendly than the VHDL 
synthesis and simulation tools I've used for prototyping to date.

> Because MyHDL is exists in the Python eco you get a tone of power with your
> RTL but not high-level synthesis.  This could be a separate project that
> works with MyHDL but it is a considerable effort (see other high-level
> synthesis research).

Starting to learn Python itself has been a major leap forward for 
me, only having previous experience of logic design and low level 
languages. Features new to me, and particularly useful to this 
project are unbounded ints and lists.

The parts of David Bluebaugh's request that interested me are the 
provision of synthesizable modules to perform basic FP 
calculations, and pipeline components to connect them. (I'm 
probably taking a little liberty with his words here)

Some sort of front end to automatically string these modules 
together based on a higher level description is probably beyond my 
interest and capability. I'm struggling to get up to speed with 
MyHDL. The low level components interest me as they are needed for 
another project.

Jan Coombs

Re: [myhdl-list] FW: Floating-point support --> Fixed-point

[Christopher F. <chr...@gm...>]

>
> <snip>
> On a related sidenote, the situation is completely different for
> fixed point. I have little experience with it, but great interest
> in enhancing MyHDL support for this. It seems this could be a
> "killing feature", as Verilog doesn't have it and I think the VHDL
> approach can be improved. I have been following Chris Felton's
> work with great interest. As it happens, I am now doing a project
> involving fixed point and after that I hope to have time
> to work on it in MyHDL.
>

I do agree, Fixed-point will always be a popular topic in HDLs (ASIC/FPGA).
 Tom Dillon has done some work in this area in the past as well.  Both VHDL
and SystemC have been working on standardizing fixed-point notation (
http://www.vhdl.org/fphdl/,
http://standards.ieee.org/getieee/1666/download/1666-2005.pdf).  They are
both good starts for what is currently supported.  But I believe with
MyHDL/Python you will have much more power than the VHDL/SystemC approaches.

One mistake I made with my approach was using the "Q" notation.  We had a
sub-thread on this in comp.dsp (
http://www.dsprelated.com/showmessage/133353/2.php), which notation makes
sense for fixed-point.  The "Q" (sometimes "S", etc) has some limitation.
 The notation used in the SystemC LRM (or VHDL?) is a better notation
because you can move the "point" outside of the actual word size.  I have
wanted to update my write-up and examples with a better notation and
examples of the "point" outside the word size.  I will keep you posted.

As for the floating-point, I think most inquires, on this topic, have to do
with more than simple floating-point support.  I believe they would like a
panacea; take a sequential algorithm, in double precision, and convert it to
hardware.  As mentioned and I agree with Jan D., this is a large task, and a
task that is not in the boundaries of the MyHDL scope.  Someone with
experience in this area (doctoral topic?) could build support on top of
MyHDL (Algorithm translator --> MyHDL --> RTL) or something.

.chris

Re: [myhdl-list] FW: Floating-point support

[Jan D. <ja...@ja...>]

As always, if your interest is purely modeling, you can do
anything you want today with MyHDL.

If your interest is conversion or synthesis to an implementation
in silicon: I have personally no plans nor experience for
floating-point support.

On a related sidenote, the situation is completely different for
fixed point. I have little experience with it, but great interest
in enhancing MyHDL support for this. It seems this could be a
"killing feature", as Verilog doesn't have it and I think the VHDL
approach can be improved. I have been following Chris Felton's
work with great interest. As it happens, I am now doing a project
involving fixed point and after that I hope to have time
to work on it in MyHDL.

Jan


On 02/22/2011 09:21 PM, Jan Coombs wrote:
> On 20/03/08 22:12, Blubaugh, David A. wrote:
>      . . .
>> I was wondering that floating-point algorithms, like the FFT,  could be
>> eventually supported by MyHDL, with a direct conversion of
>> floating-point python to VHDL or verilog?  I believe one way to handle
>> this would be to develop a module which handles the floating-point
>> procedure for addition, subtraction, multiplication, and division, which
>> has been defined by IEEE and then import this module to handle the
>> computational tasks within MyHDL.  Is that possible?   I definitely hope
>> so!!!!
>>
>> Also, is there a method to automatically generate pipeline architectures
>> with MyHDL?   Thanks for all of the help and answers!!!!
>
> Hi David&  Jan,
>
> I've just been trawling the archives to try to get up to speed, and
> saw this post. It interests me greatly, as I have practical
> implementations in mind.
>
> Is it still of current interest to you or anyone else?
>
> Jan Coombs
> --
> (there should be no kisses in my mail address)
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] FW: Floating-point support

[Christopher F. <chr...@gm...>]

>
> <snip float ...>
>
> Hi David & Jan,
>
> I've just been trawling the archives to try to get up to speed, and
> saw this post. It interests me greatly, as I have practical
> implementations in mind.
>
> Is it still of current interest to you or anyone else?
>
> Jan Coombs
> --
>

Jan C,

MyHDL is an RTL similar to VHDL and Verilog.  It has the same level support.
 It does not do higher level synthesis.

Because MyHDL is exists in the Python eco you get a tone of power with your
RTL but not high-level synthesis.  This could be a separate project that
works with MyHDL but it is a considerable effort (see other high-level
synthesis research).

Hope that helps,
Chris Felton

Re: [myhdl-list] FW: Floating-point support

[Jan C. <jan...@mu...>]

On 20/03/08 22:12, Blubaugh, David A. wrote:
    . . .
> I was wondering that floating-point algorithms, like the FFT,  could be
> eventually supported by MyHDL, with a direct conversion of
> floating-point python to VHDL or verilog?  I believe one way to handle
> this would be to develop a module which handles the floating-point
> procedure for addition, subtraction, multiplication, and division, which
> has been defined by IEEE and then import this module to handle the
> computational tasks within MyHDL.  Is that possible?   I definitely hope
> so!!!!
>
> Also, is there a method to automatically generate pipeline architectures
> with MyHDL?   Thanks for all of the help and answers!!!!

Hi David & Jan,

I've just been trawling the archives to try to get up to speed, and 
saw this post. It interests me greatly, as I have practical 
implementations in mind.

Is it still of current interest to you or anyone else?

Jan Coombs
--
(there should be no kisses in my mail address)

Re: [myhdl-list] toVerilog keys

[Jan D. <ja...@ja...>]

On 02/17/2011 07:37 PM, Billy Rond wrote:
> the '__verilog__' variable in a function allows for replacement
> of signals with something like %(var)s
> is there a way to reference the function/instance that is being called
> something like %(instance_name)s that would return something like
> GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC

Any variable in the scope with a string representation can be interpolated.
So you could generate an instance name yourself in python and interpolate
it in the user-defined code.

Note that in 0.7, the __verilog__ hook for user-defined code is deprecated
in favour of a new method. Look here for the reasons:

http://www.myhdl.org/doc/current/whatsnew/0.7.html#new-method-to-specify-user-defined-code

Also documented in the manual.

>
> basically I would like to write these modules/functions in myhdl for testing.
> But I want to have the modules wired together in verilog without the actual
> module definitions. So basically my 'Top' verilog would just be a wiring of
> these
> modules.
>
> My reasoning is that I have designed these modules in CMOS but would
> prefer to wire them together and test them in MyHDL for obvious reasons.
> Cadence has a verilog in feature that would allow me to create a schematic
> that is wired up based on the verilog.
>
> what I am currently getting is something like..
>
>
> Half_Adder unitname (A,B,adder_tree_Sum_block_P,adder_tree_Sum_block_G);
>
> Half_Adder unitname (A,B,adder_tree_HA_block2_PO,adder_tree_HA_block2_GO);
>
> where Half_Adder is my CMOS module and unitname would be the instance of it.
> It is easy enough go back and change each 'unitname' but if
> there is a way to have this generated then it could be used immediately.
>
> any ideas?
>
> thanks
> --Billy
>
>
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-- 
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     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

[myhdl-list] toVerilog keys

[Billy R. <bil...@gm...>]

the '__verilog__' variable in a function allows for replacement 
of signals with something like %(var)s
is there a way to reference the function/instance that is being called 
something like %(instance_name)s that would return something like
GRAYINCREG_GRAY_INC_1_INC_1_INCLOGIC 

basically I would like to write these modules/functions in myhdl for testing.
But I want to have the modules wired together in verilog without the actual
module definitions. So basically my 'Top' verilog would just be a wiring of 
these
modules.

My reasoning is that I have designed these modules in CMOS but would
prefer to wire them together and test them in MyHDL for obvious reasons. 
Cadence has a verilog in feature that would allow me to create a schematic
that is wired up based on the verilog. 

what I am currently getting is something like..


Half_Adder unitname (A,B,adder_tree_Sum_block_P,adder_tree_Sum_block_G);

Half_Adder unitname (A,B,adder_tree_HA_block2_PO,adder_tree_HA_block2_GO);

where Half_Adder is my CMOS module and unitname would be the instance of it.
It is easy enough go back and change each 'unitname' but if
there is a way to have this generated then it could be used immediately.

any ideas?

thanks
--Billy

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Kevin S. <sta...@gm...>]

>signed is not a subtype of std_logic_vector. However, type
>conversions between the two are trivial because they are
>closely related, meaning that you can cast using the
>target type name as a conversion function.

Ah yes, but both are types made up of arrays of std_logic.

On Mon, Jan 10, 2011 at 2:19 AM, Jan Decaluwe <ja...@ja...> wrote:

> Kevin Stanton wrote:
> > The signed type is a subtype of std_logic_vector (see the
> > ieee.numeric_std package). Assuming you can used a signed binary word
> > throughout, there should be no need to convert to std_logic_vector,
> > unless you need to do arithmetic elsewhere that is unsigned and you wish
> > to convert it to unsigned format.
>
> signed is not a subtype of std_logic_vector. However, type
> conversions between the two are trivial because they are
> closely related, meaning that you can cast using the
> target type name as a conversion function.
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
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Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Kevin Stanton wrote:
> The signed type is a subtype of std_logic_vector (see the 
> ieee.numeric_std package). Assuming you can used a signed binary word 
> throughout, there should be no need to convert to std_logic_vector, 
> unless you need to do arithmetic elsewhere that is unsigned and you wish 
> to convert it to unsigned format.

signed is not a subtype of std_logic_vector. However, type
conversions between the two are trivial because they are
closely related, meaning that you can cast using the
target type name as a conversion function.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?

signed, unsigned, and std_logic_vector are in VHDL terminology
"closely related". This implies that you can directly convert
them to each other using the target type name as a casting function.

For minimal overhead, the type conversions can be done right
in the instantiation. They work at both sides of a named
association, i.e. for both formal and actual.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Jan D. <ja...@ja...>]

Thomas Heller wrote:
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?

signed, unsigned, and std_logic_vector are in VHDL terminology
"closely related". This implies that you can directly convert
them to each other using the target type name as a casting function.

For minimal overhead, the type conversions can be done right
in the instantiation. They work at both sides of a named
association, i.e. for both formal and actual.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Kevin S. <sta...@gm...>]

I don't have time to test this right now and I can't recall for sure, but
this is from http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#vec_conversion

Note that the types std_logic_vector, std_ulogic_vector, signed and unsigned
are all closely related to each other (see FAQ Part 4 -
B.40<http://www.vhdl.org/comp.lang.vhdl/FAQ4.html#closely related
types>
 and Section 4.2.18<http://www.vhdl.org/comp.lang.vhdl/FAQ1.html#ambiguous_expressions>).
Hence, the explicit conversion can be used to transform the types as
needed--no conversion functions are, in fact required (although they are
provided by the packages std_logic_1164 and numeric_std). An example showing
the use of explicit conversion is:


        variable slv_vec  : std_logic_vector(0 to 7);
        variable sulv_vec : std_ulogic_vector(0 to 7);
        variable uns_vec  : unsigned(0 to 7);
        variable sgn_vec  : signed(0 to 7);
        ...
        slv_vec  := std_logic_vector(sulv_vec);
        sulv_vec := std_ulogic_vector(slv_vec);
        slv_vec  := std_logic_vector(uns_vec);
        slv_vec  := std_logic_vector(sgn_vec);
        uns_vec  := unsigned(slv_vec);
        sgn_vec  := signed(sulv_vec);
        uns_vec  := unsigned(sgn_vec);




I don't believe any conversion needs to take place, you can simply cast it
as a std_logic_vector.

Let me know if you need more help,

Kevin

On Fri, Jan 7, 2011 at 2:11 PM, Thomas Heller <th...@ct...> wrote:

>  >> entity DSP is
>  >>      port (
>  >>          clock: in std_logic;
>  >>          x: in signed (15 downto 0);
>  >>          y: in signed (15 downto 0);
>  >>          amplitude: in signed (15 downto 0);
>  >>          offset: in signed (15 downto 0);
>  >>          xout: out signed (15 downto 0);
>  >>          yout: out signed (15 downto 0)
>  >>      );
>  >> end entity DSP;
>
>
> Am 07.01.2011 20:28, schrieb Kevin Stanton:
> > The signed type is a subtype of std_logic_vector (see the
> ieee.numeric_std
> > package). Assuming you can used a signed binary word throughout, there
> > should be no need to convert to std_logic_vector, unless you need to do
> > arithmetic elsewhere that is unsigned and you wish to convert it to
> unsigned
> > format.
>
> Kevin,
>
> what does this mean?  If I create a VHDL instantiation template for the
> DSP then xilinx ISE creates this component declaration:
>
>        COMPONENT DSP
>        PORT(
>                clock : IN std_logic;
>                x : IN std_logic_vector(15 downto 0);
>                y : IN std_logic_vector(15 downto 0);
>                amplitude : IN std_logic_vector(15 downto 0);
>                offset : IN std_logic_vector(15 downto 0);
>                xout : OUT std_logic_vector(15 downto 0);
>                yout : OUT std_logic_vector(15 downto 0)
>                );
>        END COMPONENT;
>
> I thought it is a bug that ISE generates std_logic_vector types instead
> of signed; do you mean that this is ok?
>
> Thomas
>
>
>
> ------------------------------------------------------------------------------
> Gaining the trust of online customers is vital for the success of any
> company
> that requires sensitive data to be transmitted over the Web.   Learn how to
> best implement a security strategy that keeps consumers' information secure
> and instills the confidence they need to proceed with transactions.
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Thomas H. <th...@ct...>]

 >> entity DSP is
 >>      port (
 >>          clock: in std_logic;
 >>          x: in signed (15 downto 0);
 >>          y: in signed (15 downto 0);
 >>          amplitude: in signed (15 downto 0);
 >>          offset: in signed (15 downto 0);
 >>          xout: out signed (15 downto 0);
 >>          yout: out signed (15 downto 0)
 >>      );
 >> end entity DSP;


Am 07.01.2011 20:28, schrieb Kevin Stanton:
> The signed type is a subtype of std_logic_vector (see the ieee.numeric_std
> package). Assuming you can used a signed binary word throughout, there
> should be no need to convert to std_logic_vector, unless you need to do
> arithmetic elsewhere that is unsigned and you wish to convert it to unsigned
> format.

Kevin,

what does this mean?  If I create a VHDL instantiation template for the
DSP then xilinx ISE creates this component declaration:

	COMPONENT DSP
	PORT(
		clock : IN std_logic;
		x : IN std_logic_vector(15 downto 0);
		y : IN std_logic_vector(15 downto 0);
		amplitude : IN std_logic_vector(15 downto 0);
		offset : IN std_logic_vector(15 downto 0);
		xout : OUT std_logic_vector(15 downto 0);
		yout : OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;

I thought it is a bug that ISE generates std_logic_vector types instead
of signed; do you mean that this is ok?

Thomas

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Kevin S. <sta...@gm...>]

The signed type is a subtype of std_logic_vector (see the ieee.numeric_std
package). Assuming you can used a signed binary word throughout, there
should be no need to convert to std_logic_vector, unless you need to do
arithmetic elsewhere that is unsigned and you wish to convert it to unsigned
format.

Kevin

On Fri, Jan 7, 2011 at 12:52 PM, Thomas Heller <th...@ct...> wrote:

> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
>
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
>
> entity DSP is
>     port (
>         clock: in std_logic;
>         x: in signed (15 downto 0);
>         y: in signed (15 downto 0);
>         amplitude: in signed (15 downto 0);
>         offset: in signed (15 downto 0);
>         xout: out signed (15 downto 0);
>         yout: out signed (15 downto 0)
>     );
> end entity DSP;
>
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?
>
> Thanks,
> Thomas
>
>
>
> ------------------------------------------------------------------------------
> Gaining the trust of online customers is vital for the success of any
> company
> that requires sensitive data to be transmitted over the Web.   Learn how to
> best implement a security strategy that keeps consumers' information secure
> and instills the confidence they need to proceed with transactions.
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Kevin R. Stanton
c | 734•846•3915
e | sta...@gm...

Re: [myhdl-list] Converting std_logic_vector to signed and vice versa

[Alain P. <ala...@sp...>]

Hi Thomas,

to_integer() converts unsigned or signed values to natural or integer values, respectively.
Then convert with

function conv_std_logic_vector(i : integer; w : integer) return std_logic_vector is
variable tmp : std_logic_vector(w-1 downto 0);
begin
  tmp := std_logic_vector(to_unsigned(i, w));
  return(tmp);
end;

for instance to a the std_logic_vector (refer to gaisler lib grlib).

Hope that helps.

Cheers
Alain

> -----Original Message-----
> From: Thomas Heller [mailto:th...@ct...]
> Sent: Friday, January 07, 2011 7:52 PM
> To: myh...@li...
> Subject: [myhdl-list] Converting std_logic_vector to signed and vice
> versa
> 
> I have written a small module in MyHDL which takes
> incoming waveforms x and y, multiplies them with an
> amplitude value and adds an offset tho them.
> 
> The VHDL code that MyHDL generates uses signed(15 downto 0)
> for the values:
> 
> entity DSP is
>      port (
>          clock: in std_logic;
>          x: in signed (15 downto 0);
>          y: in signed (15 downto 0);
>          amplitude: in signed (15 downto 0);
>          offset: in signed (15 downto 0);
>          xout: out signed (15 downto 0);
>          yout: out signed (15 downto 0)
>      );
> end entity DSP;
> 
> Now, my top level module uses std_logic_vector(15 downto 0)
> for these signals.  How can I use the generated module?
> 
> Thanks,
> Thomas
> 
> 
> -----------------------------------------------------------------------
> -------
> Gaining the trust of online customers is vital for the success of any
> company
> that requires sensitive data to be transmitted over the Web.   Learn
> how to
> best implement a security strategy that keeps consumers' information
> secure
> and instills the confidence they need to proceed with transactions.
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

[myhdl-list] Converting std_logic_vector to signed and vice versa

[Thomas H. <th...@ct...>]

I have written a small module in MyHDL which takes
incoming waveforms x and y, multiplies them with an
amplitude value and adds an offset tho them.

The VHDL code that MyHDL generates uses signed(15 downto 0)
for the values:

entity DSP is
     port (
         clock: in std_logic;
         x: in signed (15 downto 0);
         y: in signed (15 downto 0);
         amplitude: in signed (15 downto 0);
         offset: in signed (15 downto 0);
         xout: out signed (15 downto 0);
         yout: out signed (15 downto 0)
     );
end entity DSP;

Now, my top level module uses std_logic_vector(15 downto 0)
for these signals.  How can I use the generated module?

Thanks,
Thomas

[myhdl-list] 0.7 package for Ubuntu Maverick

[Balau <ba...@us...>]

Hello,
I packaged MyHDL 0.7 for Ubuntu (Maverick Meerkat), and published it
on my Launchpad package archive
(https://launchpad.net/~balau82/+archive/ppa). It may be more
comfortable for users to install and remove.

To install:
$ sudo apt-add-repository ppa:balau82/ppa
$ sudo apt-get update
$ sudo apt-get install myhdl

To remove:
$ sudo apt-get remove myhdl

Regards,

Francesco

[myhdl-list] Helper Class for HWModule

[<ala...@sp...>]

Dear all,

Here is a Helper Class to harness HWModule. It parsed the __doc__  
string to gather the actual entity definition.

It allows me to code stuff like:

if __name__ == '__main__':
     unittest.main()
     args = [PicAlu.arch]
     ports = PicAlu._ports                       # port definition,  
parsed from __doc__
     for i in ports._fields:
         args.append(getattr(ports, i))

     toVHDL.name = 'pic_alu'
     toVHDL(*args)

The __doc__ string shall contain the entity like this:

"""
op_i: in enum.initstate
dat_i:  in 8
dat_o: out 8
"""

Is this actually the right place to post stuff like this?

Kind regards,
Alain

Re: [myhdl-list] Unittest failure

[<ala...@sp...>]

Thanks a lot for the suggestions, I worked around the issue, as I  
suspected there was no event created, so I set the init state to  
another one and it worked like a charm.
The new version uses myhdl.enum.
Please find the working example and the missing module attached.

Merry Xmas
Alain

Quoting Jan Decaluwe <ja...@ja...>:

> Reading all this I guess this is an initialization problem:
> if the first value assigned is the same as the initial value,
> that doesn't create an event that could trigger something.
>
> Jan
>
> Günter Dannoritzer wrote:
>> Hi Alain,
>>
>> I tried to run your code, replacing the HWEntity and Bunch by empty
>> classes, but unfortunately did not succeed getting the example to go.
>>
>> Maybe you could reduce the problem to a workable example?
>>
>> See some comments further down.
>>
>>
>> Am 25.12.2010 03:09, schrieb ala...@sp...:
>>> Dear all,
>>>
>>> As I played around with MyHDL a strange (at least to me) behaviour of
>>> the simulator appeared (unittest).
>>> Here is the snippet which behaves unexpected:
>>>
>>> This works:
>>> ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS =
>>> range(1, 14)
>>>
>>>                                                               ^^^^^^
>>> this doesn't work
>>> ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS = range(13)
>>>
>>
>>> From that description it sounds like it does not work when ADD gets
>> assigned 0?
>>
>> Did it help to add some debug output to trace it down?
>>
>> Sounds fairly strange that it does not accept 0 for the opcode.
>>
>>
>>>
>>> This is the part which fails (never invoked):
>>>
>>>             if op == ADD:
>>>                 print("OPCODE ADD")
>>>                 v_dat[:] = w_reg + dat
>>>
>>
>> I think it would be interesting to run the test with range(13) and print
>> out what op has for a value for the ADD test. Sounds like it should
>> never get assigned the value 0. Then trace back from this point why it
>> never gets 0 assigned?
>>
>> Cheers,
>>
>> Guenter
>>
>> ------------------------------------------------------------------------------
>> Learn how Oracle Real Application Clusters (RAC) One Node allows customers
>> to consolidate database storage, standardize their database  
>> environment, and,
>> should the need arise, upgrade to a full multi-node Oracle RAC database
>> without downtime or disruption
>> http://p.sf.net/sfu/oracle-sfdevnl
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     Python as a HDL: http://www.myhdl.org
>     VHDL development, the modern way: http://www.sigasi.com
>     Analog design automation: http://www.mephisto-da.com
>     World-class digital design: http://www.easics.com
>
> ------------------------------------------------------------------------------
> Learn how Oracle Real Application Clusters (RAC) One Node allows customers
> to consolidate database storage, standardize their database environment, and,
> should the need arise, upgrade to a full multi-node Oracle RAC database
> without downtime or disruption
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

Re: [myhdl-list] Unittest failure

[Jan D. <ja...@ja...>]

Reading all this I guess this is an initialization problem:
if the first value assigned is the same as the initial value,
that doesn't create an event that could trigger something.

Jan

Günter Dannoritzer wrote:
> Hi Alain,
> 
> I tried to run your code, replacing the HWEntity and Bunch by empty
> classes, but unfortunately did not succeed getting the example to go.
> 
> Maybe you could reduce the problem to a workable example?
> 
> See some comments further down.
> 
> 
> Am 25.12.2010 03:09, schrieb ala...@sp...:
>> Dear all,
>>
>> As I played around with MyHDL a strange (at least to me) behaviour of
>> the simulator appeared (unittest).
>> Here is the snippet which behaves unexpected:
>>
>> This works:
>> ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS =
>> range(1, 14)
>>                                                                      
>>                                                               ^^^^^^
>> this doesn't work
>> ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS = range(13)
>>            
> 
>>From that description it sounds like it does not work when ADD gets
> assigned 0?
> 
> Did it help to add some debug output to trace it down?
> 
> Sounds fairly strange that it does not accept 0 for the opcode.
> 
> 
>>                                                               
>> This is the part which fails (never invoked):
>>
>>             if op == ADD:
>>                 print("OPCODE ADD")
>>                 v_dat[:] = w_reg + dat
>>
> 
> I think it would be interesting to run the test with range(13) and print
> out what op has for a value for the ADD test. Sounds like it should
> never get assigned the value 0. Then trace back from this point why it
> never gets 0 assigned?
> 
> Cheers,
> 
> Guenter
> 
> ------------------------------------------------------------------------------
> Learn how Oracle Real Application Clusters (RAC) One Node allows customers
> to consolidate database storage, standardize their database environment, and, 
> should the need arise, upgrade to a full multi-node Oracle RAC database 
> without downtime or disruption
> http://p.sf.net/sfu/oracle-sfdevnl
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
> 


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Unittest failure

[Günter D. <dan...@we...>]

Hi Alain,

I tried to run your code, replacing the HWEntity and Bunch by empty
classes, but unfortunately did not succeed getting the example to go.

Maybe you could reduce the problem to a workable example?

See some comments further down.


Am 25.12.2010 03:09, schrieb ala...@sp...:
> Dear all,
> 
> As I played around with MyHDL a strange (at least to me) behaviour of
> the simulator appeared (unittest).
> Here is the snippet which behaves unexpected:
> 
> This works:
> ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS =
> range(1, 14)
>                                                                      
>                                                               ^^^^^^
> this doesn't work
> ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS = range(13)
>            

>From that description it sounds like it does not work when ADD gets
assigned 0?

Did it help to add some debug output to trace it down?

Sounds fairly strange that it does not accept 0 for the opcode.


>                                                               
> This is the part which fails (never invoked):
> 
>             if op == ADD:
>                 print("OPCODE ADD")
>                 v_dat[:] = w_reg + dat
> 

I think it would be interesting to run the test with range(13) and print
out what op has for a value for the ADD test. Sounds like it should
never get assigned the value 0. Then trace back from this point why it
never gets 0 assigned?

Cheers,

Guenter

[myhdl-list] Unittest failure

[<ala...@sp...>]

Dear all,

As I played around with MyHDL a strange (at least to me) behaviour of  
the simulator appeared (unittest).
Here is the snippet which behaves unexpected:

This works:
ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS = range(1, 14)
                                                                        
                                                               ^^^^^^
this doesn't work
ADD, AND, COM, IOR, RL, RR, SUB, SWAP, XOR, BC, BS, BTSC, BTSS = range(13)
                                                                        
                                                                ^^
This is the part which fails (never invoked):

             if op == ADD:
                 print("OPCODE ADD")
                 v_dat[:] = w_reg + dat

Please find the module attached. Thanks in advance for any suggestions.

Kind regards,
Alain