myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Verilator as a backend to myhdl?

[Christopher L. F. <chr...@gm...>]

  On 10/7/2010 5:40 PM, Terry Chen wrote:
> Hello Lane,
>
> Thanks for the reply, actually I was just thinking about using 
> Boost.Python to wrap the C code. It is relatively easy for simple 
> blocks, but I have to explicitly list which C variables/function/class 
> I want accessible. Maybe I could get away with using Pyste/Py++ to 
> automate the C to Python layer generation. Do you (or anyone else), 
> have any experience with this? I am afraid of going over-the-top with 
> this.

Unless you are using C++ boost.Python is a little much.  I have had much 
better results just using ctypes.  I have done projects with both and 
usually end up abondoning boost.Python for ctypes.  I have not written 
the native C extension as Lane described, always have used ctypes.  
ctypes is part of the Python distribution and numpy has good support for 
cytpes as well.

.chris

Re: [myhdl-list] Verilator as a backend to myhdl?

[Chris H. <chi...@gm...>]

>> My normal flow these days has become to wrap verilated code up as a python
>> C extension module so that I can use python to generate stimulus and
>> control the flow. It is quite nice, especially when used with numpy and
>> nose. With numpy you can get fast numerical analysis and with nose you get
>> a nice test framework.

>> It is quite easy to do once you know how to write a python extension
>> module. It takes a little bit of time to understand how to write an
>> extension module, but knowing how to write C extension modules for python
>> is well worth the effort beyond just wrapping verilated code. I wrap
>> things all the time when I need access in python something written in C.

> Thanks for the reply, actually I was just thinking about using Boost.Python to wrap the C code


Regarding interfacing between C and python, we use two approaches:

1. SWIG (http://www.swig.org/)
By writing an interface file (which can be incredibly simple) SWIG can
generate all the required interface code, creating an importable
python module.

2. ctypes (http://docs.python.org/library/ctypes.html)
Included in the python standard library, allows you to directly call
into C from python, register python functions as callbacks etc. Very
useful and very quick (very little interface code, or even none at all
is required).

I can recommend both methods, though recently ctypes has overtaken
SWIG in usefulness and simplicity for our use cases.

Thanks,

Chris

Re: [myhdl-list] Verilator as a backend to myhdl?

[Terry C. <ter...@gm...>]

Hello Lane,

Thanks for the reply, actually I was just thinking about using Boost.Python
to wrap the C code. It is relatively easy for simple blocks, but I have to
explicitly list which C variables/function/class I want accessible. Maybe I
could get away with using Pyste/Py++ to automate the C to Python layer
generation. Do you (or anyone else), have any experience with this? I am
afraid of going over-the-top with this.

Also, I was just pondering whether to use pure python as the high-level
testbench or attempt to hack myhdl's _Simulation.py->Simulation.run to
instead redirect its calls to python-wrapped verilated model. Pure Python
might be easier for me, but myhdl's similarity with verilog and its use of
decorators is really elegant and clean.

I will admit that it is taking me quite a bit of time to wrap my head around
the myhdl code as some of the usages of myhdl generators is sending me back
to my Python textbooks. So my abilities as a python programmer may actually
be too limited to get this too work.

I guess I will keep shaking this Boost.Python idea and see what falls out.

Thanks,
Terry

On Thu, Oct 7, 2010 at 5:37 PM, Lane Brooks <la...@ub...> wrote:

> > Hi myhdl developers,
> >
> > I am new to the mailing list. So I am not sure if this issue has already
> > been discussed. I tried searching the mailing list archive, but didn't
> > find
> > anything similar.
> >
> > My question is: has anyone attempted to use a verilated C model (from
> > wilson
> > snyder's verilator) as the backend simulator for myhdl through some sort
> > of
> > python-to-C foreign language interface?
> >
> > The motivation behind this is that I would like to combine the high-level
> > programming power of python (and myhdl) with the speed of verilator. I
> > could
> > use co-sim w/ icarus or cver, but I find that cosimulation time is
> > prohibitively slow. Commercial simulator (we use modelsim) are acceptably
> > fast, but we have a limited number of licenses, and we can't afford to
> use
> > them to run regressions.
> >
> > Any thoughts / comments would be much appreciated.
> >
> > Thanks,
> > Terry
> >
>
> My normal flow these days has become to wrap verilated code up as a python
> C extension module so that I can use python to generate stimulus and
> control the flow. It is quite nice, especially when used with numpy and
> nose. With numpy you can get fast numerical analysis and with nose you get
> a nice test framework.
>
> It is quite easy to do once you know how to write a python extension
> module. It takes a little bit of time to understand how to write an
> extension module, but knowing how to write C extension modules for python
> is well worth the effort beyond just wrapping verilated code. I wrap
> things all the time when I need access in python something written in C.
>
> Furthermore, using this approach, you can develop high level stuff in
> python and then if it is too slow, push whatever makes sense down into the
> C extension module to speed it up as necessary. Flow control, checking a
> bit for pass or fail, etc. is typically not a bottle neck and is quite
> nice to do it python. Even things like generating sin waves, comparing
> memory buffers for equality, etc, is not a bottle neck in python
> (especially if you use numpy).
>
>
> ------------------------------------------------------------------------------
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>

Re: [myhdl-list] Verilator as a backend to myhdl?

[Lane B. <la...@ub...>]

> Hi myhdl developers,
>
> I am new to the mailing list. So I am not sure if this issue has already
> been discussed. I tried searching the mailing list archive, but didn't
> find
> anything similar.
>
> My question is: has anyone attempted to use a verilated C model (from
> wilson
> snyder's verilator) as the backend simulator for myhdl through some sort
> of
> python-to-C foreign language interface?
>
> The motivation behind this is that I would like to combine the high-level
> programming power of python (and myhdl) with the speed of verilator. I
> could
> use co-sim w/ icarus or cver, but I find that cosimulation time is
> prohibitively slow. Commercial simulator (we use modelsim) are acceptably
> fast, but we have a limited number of licenses, and we can't afford to use
> them to run regressions.
>
> Any thoughts / comments would be much appreciated.
>
> Thanks,
> Terry
>

My normal flow these days has become to wrap verilated code up as a python
C extension module so that I can use python to generate stimulus and
control the flow. It is quite nice, especially when used with numpy and
nose. With numpy you can get fast numerical analysis and with nose you get
a nice test framework.

It is quite easy to do once you know how to write a python extension
module. It takes a little bit of time to understand how to write an
extension module, but knowing how to write C extension modules for python
is well worth the effort beyond just wrapping verilated code. I wrap
things all the time when I need access in python something written in C.

Furthermore, using this approach, you can develop high level stuff in
python and then if it is too slow, push whatever makes sense down into the
C extension module to speed it up as necessary. Flow control, checking a
bit for pass or fail, etc. is typically not a bottle neck and is quite
nice to do it python. Even things like generating sin waves, comparing
memory buffers for equality, etc, is not a bottle neck in python
(especially if you use numpy).

Re: [myhdl-list] Blog post about Verilog

[Jan D. <ja...@ja...>]

Christopher Felton wrote:
> Thanks for posting this to the MyHDL group.  I thought it was a good read!

Thanks. The next few blog entries will continue about the same
subject, so I'll keep you posted!

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Verilator as a backend to myhdl?

[Jan D. <ja...@ja...>]

Terry Chen wrote:
> Hi myhdl developers,
> 
> I am new to the mailing list. So I am not sure if this issue has already 
> been discussed. I tried searching the mailing list archive, but didn't 
> find anything similar.
> 
> My question is: has anyone attempted to use a verilated C model (from 
> wilson snyder's verilator) as the backend simulator for myhdl through 
> some sort of python-to-C foreign language interface? 
> 
> The motivation behind this is that I would like to combine the 
> high-level programming power of python (and myhdl) with the speed of 
> verilator. I could use co-sim w/ icarus or cver, but I find that 
> cosimulation time is prohibitively slow. Commercial simulator (we use 
> modelsim) are acceptably fast, but we have a limited number of licenses, 
> and we can't afford to use them to run regressions.
> 
> Any thoughts / comments would be much appreciated.

I fear that as long a you would have Python somewhere in the loop,
it will quickly be the limiting factor in your simulation. Ultra-fast
regression type simulation just doesn't match very well with
super high-level programming power.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Verilator as a backend to myhdl?

[Terry C. <ter...@gm...>]

Hi myhdl developers,

I am new to the mailing list. So I am not sure if this issue has already
been discussed. I tried searching the mailing list archive, but didn't find
anything similar.

My question is: has anyone attempted to use a verilated C model (from wilson
snyder's verilator) as the backend simulator for myhdl through some sort of
python-to-C foreign language interface?

The motivation behind this is that I would like to combine the high-level
programming power of python (and myhdl) with the speed of verilator. I could
use co-sim w/ icarus or cver, but I find that cosimulation time is
prohibitively slow. Commercial simulator (we use modelsim) are acceptably
fast, but we have a limited number of licenses, and we can't afford to use
them to run regressions.

Any thoughts / comments would be much appreciated.

Thanks,
Terry

Re: [myhdl-list] Blog post about Verilog

[Christopher F. <chr...@gm...>]

Thanks for posting this to the MyHDL group.  I thought it was a good read!

On Wed, Oct 6, 2010 at 10:13 AM, Jan Decaluwe <ja...@ja...> wrote:

> For those interested, I have blogged about my
> experiences with Verilog. They explain some design
> decision in MyHDL.
>
> http://www.sigasi.com/content/verilogs-major-flaw
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Beautiful is writing same markup. Internet Explorer 9 supports
> standards for HTML5, CSS3, SVG 1.1,  ECMAScript5, and DOM L2 & L3.
> Spend less time writing and  rewriting code and more time creating great
> experiences on the web. Be a part of the beta today.
> http://p.sf.net/sfu/beautyoftheweb
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] Blog post about Verilog

[Jan D. <ja...@ja...>]

For those interested, I have blogged about my
experiences with Verilog. They explain some design
decision in MyHDL.

http://www.sigasi.com/content/verilogs-major-flaw

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Signals only read and written from custom __vhdl__

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
> Hi everybody,
> I have problems with myhdl not generating all the needed signal 
> declarations in VHDL. What I have found so far, is that if a signal is 
> written from a custom 
> __vhdl__ block and only read from custom __vhdl__ blocks, I need to call
> 
> _markUsed() on the signal to have the signal declaration generated in VHDL.
> 
> and
> _markRead() to suppress the myhdl warning on signal not being read 
> anywhere in the design.
> 
> Is this the correct way to do this? I feel a bit bad when using private 
> functions on objects, is there a official way to achieve something similar?

Yes, the 'driven' attribute.

http://www.myhdl.org/doc/current/manual/conversion.html#user-defined-code

Note that for VHDL it only counts whether the attribute is true or not,
for Verilog it also specifies the type of object being driven.

There is also a currently undocumented public 'read' attribute, with
the expected effect.

Let me know how it goes. I'm not entirely happy with this. Ideally
I think these attributes should work as a hint, but not be used in
error detection as currently is the case. For example, it you set the
'driven' attribute redundantly, and the convertor can also infer that
the signal is in fact driven, you currently will get a 'multiple driven'
error now. 

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Signals only read and written from custom __vhdl__

[Sigve T. <pu...@tj...>]

Hi everybody,
I have problems with myhdl not generating all the needed signal declarations
in VHDL. What I have found so far, is that if a signal is written from a
custom
__vhdl__ block and only read from custom __vhdl__ blocks, I need to call

_markUsed() on the signal to have the signal declaration generated in VHDL.

and
_markRead() to suppress the myhdl warning on signal not being read anywhere
in the design.

Is this the correct way to do this? I feel a bit bad when using private
functions on objects, is there a official way to achieve something similar?

Regards,
Sigve

[myhdl-list] MIPS32 single cycle in MyHDL

[Günter D. <dan...@we...>]

Hi,

seeing this question about a MIPS32 code in MyHDL I want to contribute
some code I created a while ago. It is from the book "Digital Design and
Computer Architecture" from David Money Harris & Sarah L. Harris.

I started converting their Verilog Code from the book for a single cycle
processor into MyHDL. However, I have to say, it is not tested and I
believe it was either not fully converted or testing showed some errors.
But maybe a starting point for something more.

I also started simple assembler, added as well.

I probably should added the code to the wiki. However I am not sure
whether there would be some conflict because it is a conversion of the
Verilog code from the book?

Cheers,

Guenter

Re: [myhdl-list] Development status update

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Patricio Kaplan wrote:
>> Jan,
>>
>> have you tried verilator for verilog? it is actively maintained and as 
>> far as I can tell doing a very good job.
> 
> No, from their overview info I concluded that is was not a
> solution for my purposes.
> 
> I just checked the website again. Apparently their value proposition
> is to make synthesizable code run very fast. But that's not what
> I need. I need full, trustworthy language support and for the unit
> tests I really don't care about performance.
> 
> MyHDL can now convert much, much more than synthesizable logic.
> I use it to convert reasonably complex python unit tests,
> thereby bypassing simulation.
                    ^
            I meant CO-simulation


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Saying Hi from Argentina

[Jan D. <ja...@ja...>]

Martín Gaitán wrote:
> On Thu, Sep 30, 2010 at 6:25 AM, Jan Decaluwe <ja...@ja... 
> <mailto:ja...@ja...>> wrote:
> 
>     ...
> 
> 
>     Main problem is the specs and testing strategy probably.
> 
>     For example - what if you just download VHDL or Verilog code
>     that is apparently easy to find, and submit it?
>     I assume that your teachers expect some amount of originality
>     from you, but how do they define that?
> 
> 
> hi Jan,
> 
> really I lied because it's not just implement the project but write a 
> short paper about "what I do" and defend it orally. Take some code from 
> somewhere is fine, but I should be able to explain it and, of course, 
> can't be a whole plagiarism.
>  
> Obviously this is the first time somebody will make this kind of project 
> with a language different to VHDL (which is the language that they 
> "teach" - cough, cough -) or Verilog (few) and probably they mock or 
> complain a bit because are old-fashioned electronic-background people. 
> But my arguments are that I must solve the problem with the best tool 
> for me ("think like an engineer", teachers say, and I doubt if are words 
> of wisdom) and it guarantees the originality of the work.

Ok, why don't you teach your teachers something :-) 
For inspiration, look at:

    http://www.myhdl.org/doku.php/why

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Development status update

[Jan D. <ja...@ja...>]

Patricio Kaplan wrote:
> Jan,
> 
> have you tried verilator for verilog? it is actively maintained and as 
> far as I can tell doing a very good job.

No, from their overview info I concluded that is was not a
solution for my purposes.

I just checked the website again. Apparently their value proposition
is to make synthesiable code run very fast. But that's not what
I need. I need full, trustworthy language support and for the unit
tests I really don't care about performance.

MyHDL can now convert much, much more than synthesizable logic.
I use it to convert reasonably complex python unit tests,
thereby bypassing simulation.

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Saying Hi from Argentina

[Martín G. <ga...@gm...>]

On Thu, Sep 30, 2010 at 6:25 AM, Jan Decaluwe <ja...@ja...> wrote:

> ...


> Main problem is the specs and testing strategy probably.
>
> For example - what if you just download VHDL or Verilog code
> that is apparently easy to find, and submit it?
> I assume that your teachers expect some amount of originality
> from you, but how do they define that?
>

hi Jan,

really I lied because it's not just implement the project but write a short
paper about "what I do" and defend it orally. Take some code from somewhere
is fine, but I should be able to explain it and, of course, can't be a whole
plagiarism.

Obviously this is the first time somebody will make this kind of project
with a language different to VHDL (which is the language that they "teach" -
cough, cough -) or Verilog (few) and probably they mock or complain a bit
because are old-fashioned electronic-background people. But my arguments are
that I must solve the problem with the best tool for me ("think like an
engineer", teachers say, and I doubt if are words of wisdom) and it
guarantees the originality of the work.

regards

Martin

Re: [myhdl-list] Development status update

[Patricio K. <pat...@gm...>]

Jan,

have you tried verilator for verilog? it is actively maintained and as far
as I can tell doing a very good job.

-patricio

On Thu, Sep 30, 2010 at 6:10 AM, Jan Decaluwe <ja...@ja...> wrote:

> Hi all:
>
> In the previous months, I have completed another industrial
> project with MyHDL. As usual, I have made a number of
> enhancements to MyHDL, driven by the project needs.
>
> There is more than enough material for a new release, and
> I will start to work towards that now. As usual, the main work
> will be to bring the documentation in sync. I am working
> on a What's New document first.
>
> MyHDL has come to a point were the open-source simulators for
> Verilog and VHDL are becoming a bottleneck, because they
> are no longer being developed (cver), or because it's sometimes
> not clear whether a discrepancy comes from MyHDL onversion, or
> from the simulator. As an alternative, I have now been able
> to run the unit tests (that don't depend on cosimuluation) with
> the free Modelsim simulator packaged with the Altera suite
> for Linux. This gives me much more confidence, and I hope
> this option will remain available in the future.
>
> Jan
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>    Python as a HDL: http://www.myhdl.org
>    VHDL development, the modern way: http://www.sigasi.com
>    Analog design automation: http://www.mephisto-da.com
>    World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Start uncovering the many advantages of virtual appliances
> and start using them to simplify application deployment and
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> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] Development status update

[Jan D. <ja...@ja...>]

Hi all:

In the previous months, I have completed another industrial
project with MyHDL. As usual, I have made a number of
enhancements to MyHDL, driven by the project needs.

There is more than enough material for a new release, and
I will start to work towards that now. As usual, the main work
will be to bring the documentation in sync. I am working
on a What's New document first.

MyHDL has come to a point were the open-source simulators for
Verilog and VHDL are becoming a bottleneck, because they
are no longer being developed (cver), or because it's sometimes
not clear whether a discrepancy comes from MyHDL onversion, or
from the simulator. As an alternative, I have now been able
to run the unit tests (that don't depend on cosimuluation) with
the free Modelsim simulator packaged with the Altera suite
for Linux. This gives me much more confidence, and I hope
this option will remain available in the future.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] Saying Hi from Argentina

[Jan D. <ja...@ja...>]

Martín Gaitán wrote:
> Hi everybody.
> 
> this is the situation: I'm a student  with one subject left (and the 
> final project, which it's almost cooked [1])  to get a dregree Computer 
> Engineering [2] at Córdoba, Argentina. This subject is computer 
> architecture. To pass and be happy I must implement a DLX/MIPS pipelined 
> processor. I would like to get my degree someday in the rest of 2010.
> I forget what I ever knew about VHDL and I never knew Verilog. but I 
> enjoy very much programming python.
> 
> My gantt diagram says that I have a month to do this.  Do you think 
> MyHDL it's my workhorse ?

Using MyHDL for a project like this shouldn't pose any problem,
has the advantage that you can use python for testing, and that
you end up with both Verilog and VHDL for the same effort.

Main problem is the specs and testing strategy probably.

For example - what if you just download VHDL or Verilog code
that is apparently easy to find, and submit it?
I assume that your teachers expect some amount of originality
from you, but how do they define that?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

[myhdl-list] Saying Hi from Argentina

[Martín G. <ga...@gm...>]

Hi everybody.

this is the situation: I'm a student  with one subject left (and the final
project, which it's almost cooked [1])  to get a dregree Computer
Engineering [2] at Córdoba, Argentina. This subject is computer
architecture. To pass and be happy I must implement a DLX/MIPS pipelined
processor. I would like to get my degree someday in the rest of 2010.
I forget what I ever knew about VHDL and I never knew Verilog. but I enjoy
very much programming python.

My gantt diagram says that I have a month to do this.  Do you think MyHDL
it's my workhorse ?

seriously, I'll be bothering here for a while. be patience. and thanks in
advance.

BTW, any open source MIPS-like project in MyHDL over there?



[1] http://code.google.com/p/gpec2010/
[2] http://computacion.efn.uncor.edu/  (probably a 404, the net an its
admins sucks)

Re: [myhdl-list] How to give signals custom names in toVHDL

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
>> I have not yet figured out why the sigdict is empty for my case.
> 
> I found a bug in my code causing this to happen. My error triggered
> the condition described above, causing the VHDL-file generated to have
> duplicate signal names. The duplicate signal names is just a symptom
> of my underlying bug, and might not be triggered for valid/sensible
> myhdlcode. It might however be a good idea to check for duplicate
> names, as that would indicate an error condition anyway.

Thanks for letting me know!

I had been "optimizing" the hierarchical naming scheme lately,
so there might have been bugs (although it works for the
existing regression tests and my latest design work.)

As I said, name clashes are possible when constructing
instance names and signals names carefully :-) A fix that
covers all cases may not be that trivial. Checking
for duplicate names as you say may indeed be a good
idea in the mean time.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] How to give signals custom names in toVHDL

[Sigve T. <pu...@tj...>]

>
> I have not yet figured out why the sigdict is empty for my case.

I found a bug in my code causing this to happen. My error triggered
the condition described above, causing the VHDL-file generated to have
duplicate signal names. The duplicate signal names is just a symptom
of my underlying bug, and might not be triggered for valid/sensible
myhdlcode. It might however be a good idea to check for duplicate
names, as that would indicate an error condition anyway.

Sigve

Re: [myhdl-list] How to give signals custom names in toVHDL

[Sigve T. <pu...@tj...>]

2010/9/21 Jan Decaluwe <ja...@ja...>:
> Sigve Tjora wrote:
>>>> I have a problem where different signals get the same name in VHDL
>>>> when using toVHDL, caused when using two instances with identical
>>>> names according to _makeName.
>>> How can 2 different instances have the same name?
>>> (except in another part of the hierarchy, where the hierarchical
>>> name is different).
>>
>> I was thinking about recreating the bug with a simple example, but
>> found the bug in the process. As it is easier to explain the bug and a
>> possible fix, I will do that.
>>
>> The problem is in the conversion._analyze._analyzeSigs function:
>>
>>         # skip processing and prefixing in context without signals
>>         if not (sigdict or memdict):
>>             prefixes.append("")
>>             continue
>>         prefixes.append(name)
>>
>> This adds an empty prefix if the current context has no signals. If
>> the hierarchy names are the same on both sides on this context,
>> signals-names will clash. A possible fix is to replace the code above
>> with:
>>
>>         # skip processing and prefixing in context without signals
>>         prefixes.append(name)
>>         if not (sigdict or memdict):
>>             continue
>>
>> This inserts the name of all contexts in the prefixes list, even if
>> the context has no signals.
>
> This may certainly be a case of premature optimization. But I
> think I still need an example.
I am working reproducing the error in a simple example, but has not
managed to do that yet. I am not familiar enough with the inner
workings of MyHdl to easily figure out what triggers the error.

> With "both sides" I think you mean a higher and a lower level in the hierarchy.
Correct.

> The lower level should still have an additional hierarchical prefix?
This is also correct, but the problem is when returning a list of
instances, where all the instances is similar. If this list is
"my_inverters", the resulting names for a given hierarchy should be

toplevel_my_inverters_0_register_output
toplevel_my_inverters_1_register_output
toplevel_my_inverters_2_register_output

but for my case the sigdict and memdict (in _analyzeSigs) is empty for
each my_inverters-instance, causing the generated names to collapsed
to:
toplevel_register_output
toplevel_register_output
toplevel_register_output

causing the name clash.

I have not yet figured out why the sigdict is empty for my case.

Sigve

Re: [myhdl-list] How to give signals custom names in toVHDL

[Jan D. <ja...@ja...>]

Sigve Tjora wrote:
>>> I have a problem where different signals get the same name in VHDL
>>> when using toVHDL, caused when using two instances with identical
>>> names according to _makeName.
>> How can 2 different instances have the same name?
>> (except in another part of the hierarchy, where the hierarchical
>> name is different).
> 
> I was thinking about recreating the bug with a simple example, but
> found the bug in the process. As it is easier to explain the bug and a
> possible fix, I will do that.
> 
> The problem is in the conversion._analyze._analyzeSigs function:
> 
>         # skip processing and prefixing in context without signals
>         if not (sigdict or memdict):
>             prefixes.append("")
>             continue
>         prefixes.append(name)
> 
> This adds an empty prefix if the current context has no signals. If
> the hierarchy names are the same on both sides on this context,
> signals-names will clash. A possible fix is to replace the code above
> with:
> 
>         # skip processing and prefixing in context without signals
>         prefixes.append(name)
>         if not (sigdict or memdict):
>             continue
> 
> This inserts the name of all contexts in the prefixes list, even if
> the context has no signals.

This may certainly be a case of premature optimization. But I
think I still need an example. With "both sides" I think you
mean a higher and a lower level in the hierarchy. The lower
level should still have an additional hierarchical prefix?


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    Python as a HDL: http://www.myhdl.org
    VHDL development, the modern way: http://www.sigasi.com
    Analog design automation: http://www.mephisto-da.com
    World-class digital design: http://www.easics.com

Re: [myhdl-list] How to give signals custom names in toVHDL

[Sigve T. <pu...@tj...>]

>> I have a problem where different signals get the same name in VHDL
>> when using toVHDL, caused when using two instances with identical
>> names according to _makeName.
>
> How can 2 different instances have the same name?
> (except in another part of the hierarchy, where the hierarchical
> name is different).

I was thinking about recreating the bug with a simple example, but
found the bug in the process. As it is easier to explain the bug and a
possible fix, I will do that.

The problem is in the conversion._analyze._analyzeSigs function:

        # skip processing and prefixing in context without signals
        if not (sigdict or memdict):
            prefixes.append("")
            continue
        prefixes.append(name)

This adds an empty prefix if the current context has no signals. If
the hierarchy names are the same on both sides on this context,
signals-names will clash. A possible fix is to replace the code above
with:

        # skip processing and prefixing in context without signals
        prefixes.append(name)
        if not (sigdict or memdict):
            continue

This inserts the name of all contexts in the prefixes list, even if
the context has no signals.

>> What is the appropriate method to give a signal a specific name?
>> Setting only a part of a signal name (prefix or postfix) would also be
>> ok.
>
> Not supported at the moment. Supporting this would probably make
> it even more difficult to avoid name clashes.
I agree.

>> The autogenerated signal names are not always very informative.
>
> It's supposed to the hierarchical name. What is not clear about it?
It is probably my use of myhdl, and I will get back with an example if
I think it is a big problem.

Thanks for a prompt answer Jan!

Sigve