myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] CASE versus IF (MyHDL)

[Jan D. <ja...@ja...>]

On 04/15/2011 08:49 AM, Jan Coombs wrote:
> On 12/04/11 10:49, David Rodríguez wrote:
>> Dear MyHDL distribution list,
>>
>> I am going through the MyHDL traning material. I have almost completed the
>> RTL combinatorial and sequential modelling section.  I need to find some
>> time to type some code and see how good my understanding  of everything is.
>> However, there is something that bothers me. I have found in the VHDL that
>> there is a big difference when CASE statements and IF statements are used.
>>
>> I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).
>
> I'm translating a small processor design from Verilog to MyHLD, so
> this point interests me, as there are large and irregular muxes
> implied in the design.
>
> Although I am interested to see that the Verilog/VHDL translation
> is as simple as possible, perhaps with good synthesis tools there
> will be very little difference in final logic compiled?

Jan:

A "true" case, specifying disjoint conditions, can make a
difference. In such cases, the convertor should be able
to map MyHDL if-then structures to a VHDL/Verilog case.



>
> Hopefully I will have some practical answers in a few days.
>
> Jan Coombs
>
> ------------------------------------------------------------------------------
> Benefiting from Server Virtualization: Beyond Initial Workload
> Consolidation -- Increasing the use of server virtualization is a top
> priority.Virtualization can reduce costs, simplify management, and improve
> application availability and disaster protection. Learn more about boosting
> the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] CASE versus IF (MyHDL)

[Jan C. <jan...@mu...>]

On 12/04/11 10:49, David Rodríguez wrote:
> Dear MyHDL distribution list,
>
> I am going through the MyHDL traning material. I have almost completed the
> RTL combinatorial and sequential modelling section.  I need to find some
> time to type some code and see how good my understanding  of everything is.
> However, there is something that bothers me. I have found in the VHDL that
> there is a big difference when CASE statements and IF statements are used.
>
> I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).

I'm translating a small processor design from Verilog to MyHLD, so 
this point interests me, as there are large and irregular muxes 
implied in the design.

Although I am interested to see that the Verilog/VHDL translation 
is as simple as possible, perhaps with good synthesis tools there 
will be very little difference in final logic compiled?

Hopefully I will have some practical answers in a few days.

Jan Coombs

Re: [myhdl-list] New MyHDL Tutorial Available.

[Jan D. <ja...@ja...>]

On 04/13/2011 05:32 PM, Andrew Stone wrote:
> Hi Christopher,
>
> Please explain what you mean by:
>
> "So the course material is not strictly open source.  By contributing
> to it, you are allowing me to make some money off of it."
>
> Please state what the license to the course material is.
>
> There has never been any requirement that nobody make any money off
> open source!  So I think that your argument to keep it closed source
> for that reason is weak.  For example people can use OSS in their
> daily jobs, include it as part of selling products, teach courses on
> it, write books, consulting, etc.
>
> If your idea is that since this course material is closed source,
> then only you (or people who license the course material from you)
> will be able to use it to teach courses, then I shall certainly
> retract my offer to test it on the Lattice Brevia XP2.  And
> regardless of the goodness that you are currently bringing, shall
> heartily wish that you find another endeavor.
>
> However, I don't think that it would come to that.  Just open-source
> the course material.  If and when myHdl becomes popular, you'll have
> plenty of paid opportunities as the author of the course.  After all,
> who would you pay to hear a lecture about myHdl from: Jan D. or me
> :-).
>
> Frankly, if you keep it closed source, you are simply inviting a
> competitor.  Once you've created a market for training classes,
> consulting, etc, someone else will make a completely separate
> open-source course and rapidly overtake your course in popularity due
> to its somewhat "free" nature.  The value is not in the actual course
> material...the value is in the generation of the market.  Fortunately
> that cannot ever be cornered because of the OSS nature of myHdl.
> Your best strategy is to dis-invite competition by open-sourcing your
> training material.
>
> Regards, Andrew

Andrew:

Thanks for these convincing arguments in favor of open source
solutions. I fully agree, and I hope people will develop MyHDL
training material along these lines.

Jan

>
>
> On Sun, Apr 10, 2011 at 10:10 PM, Christopher Lozinski
> <loz...@fr... <mailto:loz...@fr...>>
> wrote:
>
> I am pleased to announce a MyHDL tutorial at http://MyHDLClass.com
>
> Thank you Christopher Felton for all the hard work, and more
> importantly for getting it done so quickly.
>
> I think that this demonstrates that MyHDL is evolving very rapidly.
> The conference was over just 4 days ago.  Just watch!
>
> We invite you to read and download the material, and go buy a board.
> http://www.dsptronics.com/
>
> There are some other boards that people have committed to supporting
> shortly.
>
> I particularly invite you to edit the course material.  If we all
> make a few edits, in no time at all, there will be a rich deep and
> wonderful course.
>
> Let me talk a little bit about the business model.  We had a
> business model.  Jan Decaluwe was using MyHDL and consulting.  Things
> were not moving very fast.  There was a perception of a one man show.
> We all appreciate what he did.  We now have a new business model.
> MyHDL is still open source material, but we have a class to offer,
> and charge people for.  My intention is to offer that class at the
> upcoming DAC conference, and use the proceeds to support a booth
> there.  The booth is not that expensive.  What is expensive is
> engineers time to man the booth.   And there are a lot of FPGA trade
> shows around the world to exhibit at and travel to.
>
> So the course material is not strictly open source.  By contributing
> to it, you are allowing me to make some money off of it. Basically
> that will go to pay for my time, and trade show space.  This should
> allow MyHDL to grow much faster.   It is now easy for people to
> invest in MyHDL, because they know that things are happening very
> fast, moving at light speed.
>
> So please thank Christopher Felton for all his hard work, or better
> yet, go and order one of his boards. Please order one of his boards.
> Please.
>
> And try out the course material.
>
> And if you want permission to edit the course material, just send me
> an email. Also let me know if you want to sign up for the class.
>
> -- Regards Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift. http://MyHDL.org
>
>
> ------------------------------------------------------------------------------
>
>
Xperia(TM) PLAY
> It's a major breakthrough. An authentic gaming smartphone on the
> nation's most reliable network. And it wants your games.
> http://p.sf.net/sfu/verizon-sfdev
> _______________________________________________ myhdl-list mailing
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> <mailto:myh...@li...>
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>
>
>
>
> ------------------------------------------------------------------------------
>
>
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Floating Point Libraries

[Tom D. <td...@di...>]

some comments below:

On 04/14/2011 08:32 AM, Christopher Felton wrote:
>
> At the risk of embarrassing myself but to keep this thread going I will
> start a FP interface based on Jan D and Tom D. suggestions.  Something
> like the following could be a start to an interface definition.
>
> class FloatingPoint(object):
>
>       def __init__(self):
>           pass
>
>       def Add(self, clk, reset,
> 	    a_sign, a_mant, a_exp, dva,
>               b_sign, b_mant, b_exp, dvb,
>               r_sign, r_mant, r_exp, dvr,
> 	    EXP_W=8, MAN_W=23):
>           pass
>
>       def Mul(self, clk, reset,
> 	    a_sign, a_mant, a_exp, dva,
>               b_sign, b_mant, b_exp, dvb,
>               r_sign, r_mant, r_exp, dvr,
> 	    EXP_W=8, MAN_W=23):
>           pass
>
>       def Div(self, clk, reset,
> 	    a_sign, a_mant, a_exp, dva,
>               b_sign, b_mant, b_exp, dvb,
>               r_sign, r_mant, r_exp, dvr,
> 	    EXP_W=8, MAN_W=23):
>           pass
>
I would recommend the class be the MyHDL representation of the number 
itself.

I don't think there is any real benefit to the operators being in the 
class as they will just be called like function calls returning the 
MyHDL instances.

So I see it as something like this:

class fp(object) :
   __slots__ = ['sign', 'exp', 'man', '_expW', '_manW']
   def __init__(self,initNum=0.0,expW=8,manW=23) :
     self._expW = expW
     self._manW = manW
     self.setvalue(initNum)

Note the fp object would keep all information about the structure and 
widths.

Then a Add module would look like this:

def FpAdd(x,a,b,clk=None,reset=None,pipes=0) :

x,a, and b being the required ports of type fp (could expand to other 
types (fixed point). Option ports and parameters follow. You will end up 
with more parameters before you are done.

In floating point, something like an Add will have to have the option 
for pipelines to be very useful. You may also want options for 
multi-cycle operation to optimize the logic when they don't need to run 
at the full clock rate.

The operators don't need to know the width of the operands. That will be 
determined by the i/o ports. You may want to allow mixed widths.

You will like passing only the objects and not the sign, man and exp 
separately. You may also decide that you don't store the sign internally 
if that turned out to be more efficient. Keeping the sign in the mantissa.

Now when this is done it will be cleaner to use but will present a 
problem with you get to conversion as the you won't be able to have an 
fp object in the ports list at the top level. That is where you will 
need a wrapper that breaks out and attaches the elements inside fp.

I think that is much easier than having three times the ports for all 
module connections. You also increase your cross wiring chances.

You can add a lot to the fp class that will make your life easier as well.

Anyhow, just my thoughts. Good luck.

Re: [myhdl-list] Floating Point Libraries

[Christopher F. <chr...@gm...>]

Glad to hear you got the poster and things are going good.  Hope you 
enjoy your time in Argentina!

On 4/14/2011 11:02 AM, Jan Langer wrote:
> Hi,
> just a quick comment. Wouldn´t an explicit statement which signals
> should be treated as hardware signals be better? Something like
>
> def __to_hardware__(self):
>     return self.x,self.y,self.z
>
> I really think too much magic with Python´s introspection should be avoided.

This would go back to a complex structure having many signals versus one 
signal for a complex structure.  I have to think about this a little more.

>
> On a sidenote: the poster (unfortunately we had to scale it down a
> bit) and the flyers are finally up and I will report back on the
> generated interest later.
> greetings from argentina,
> Jan
>
> Quoting Christopher Felton<chr...@gm...>:
>
>> <snip>
>>>
>>> So why not start with a workaround? We could define an
>>> interface using a_sign, a_mant, a_exp and b_sign, b_mant, b_exp.
>>> Ok, the interface is flattened, but in the code the only
>>> difference would be the underscore instead of dot notation.
>>> But it would teach us if this type of interface is really
>>> what we want to work with. And it works today. And if conversion ever
>>> gets more powerful, an upgrade may be simple.
>>
>>
>>
>> Are you thinking something like the following?  If I understand, the
>> proposal would be to have one Signal for a complex structure vs. a
>> structure with multiple Signals.
>>
>> -----------
>> from myhdl import *
>>
>> class TypeStruct(object):
>>
>> 	def __init__(self):
>> 		x = intbv(0)[8:]
>> 		y = intbv(0)[12:]
>> 		z = intbv(0)[23:]
>>
>>
>> if __name__ == '__main__':
>>       struct = Signal(TypeStruct())
>>       struct.next.x = 1
>>       struct.next.y = 2
>>       struct.next.z = 3
>>       struct._update()   # usually happens behind the scenes
>>
>>       print struct.x, struct.y, struct.z
>>
>> -----------
>>
>> This isn't specific to the FP interface proposal.  This is the general
>> method to handle grouping of types.  And then the conversion proposal
>> would be; that a Signal carrying a class type (and dict?) the internal
>> intbv types would be expanded to struct_x, struct_y, struct_z, for the
>> above example?
>>
>> I follow, that the conversion work would follow the general modeling
>> approach.
>>
>> Or when you said "code" you are referring to the MyHDL code.  And for
>> the near-term it is more important to define a working convertible FP
>> module that is support by MyHDL 0.7.  The FP unit would be built using
>> the interface you mentioned and in the future it could be replaced by
>> something like the above.
>>
>> Chris Felton
>>
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Benefiting from Server Virtualization: Beyond Initial Workload
>> Consolidation -- Increasing the use of server virtualization is a top
>> priority.Virtualization can reduce costs, simplify management, and improve
>> application availability and disaster protection. Learn more about boosting
>> the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>>
>
>
>

Re: [myhdl-list] Floating Point Libraries

[Jan L. <ja...@la...>]

Hi,
just a quick comment. Wouldn´t an explicit statement which signals  
should be treated as hardware signals be better? Something like

def __to_hardware__(self):
   return self.x,self.y,self.z

I really think too much magic with Python´s introspection should be avoided.

On a sidenote: the poster (unfortunately we had to scale it down a  
bit) and the flyers are finally up and I will report back on the  
generated interest later.
greetings from argentina,
Jan

Quoting Christopher Felton <chr...@gm...>:

> <snip>
>>
>> So why not start with a workaround? We could define an
>> interface using a_sign, a_mant, a_exp and b_sign, b_mant, b_exp.
>> Ok, the interface is flattened, but in the code the only
>> difference would be the underscore instead of dot notation.
>> But it would teach us if this type of interface is really
>> what we want to work with. And it works today. And if conversion ever
>> gets more powerful, an upgrade may be simple.
>
>
>
> Are you thinking something like the following?  If I understand, the
> proposal would be to have one Signal for a complex structure vs. a
> structure with multiple Signals.
>
> -----------
> from myhdl import *
>
> class TypeStruct(object):
>
> 	def __init__(self):
> 		x = intbv(0)[8:]
> 		y = intbv(0)[12:]
> 		z = intbv(0)[23:]
>
>
> if __name__ == '__main__':
>      struct = Signal(TypeStruct())
>      struct.next.x = 1
>      struct.next.y = 2
>      struct.next.z = 3
>      struct._update()   # usually happens behind the scenes
>
>      print struct.x, struct.y, struct.z
>
> -----------
>
> This isn't specific to the FP interface proposal.  This is the general
> method to handle grouping of types.  And then the conversion proposal
> would be; that a Signal carrying a class type (and dict?) the internal
> intbv types would be expanded to struct_x, struct_y, struct_z, for the
> above example?
>
> I follow, that the conversion work would follow the general modeling
> approach.
>
> Or when you said "code" you are referring to the MyHDL code.  And for
> the near-term it is more important to define a working convertible FP
> module that is support by MyHDL 0.7.  The FP unit would be built using
> the interface you mentioned and in the future it could be replaced by
> something like the above.
>
> Chris Felton
>
>
>
>
> ------------------------------------------------------------------------------
> Benefiting from Server Virtualization: Beyond Initial Workload
> Consolidation -- Increasing the use of server virtualization is a top
> priority.Virtualization can reduce costs, simplify management, and improve
> application availability and disaster protection. Learn more about boosting
> the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>



-- 
jan langer ... ja...@la...
"pi ist genau drei"

Re: [myhdl-list] Floating Point Libraries

[Christopher F. <chr...@gm...>]

<snip>

>
> So why not start with a workaround? We could define an
> interface using a_sign, a_mant, a_exp and b_sign, b_mant, b_exp.
> Ok, the interface is flattened, but in the code the only
> difference would be the underscore instead of dot notation.
> But it would teach us if this type of interface is really
> what we want to work with. And it works today. And if conversion ever
> gets more powerful, an upgrade may be simple.
>

At the risk of embarrassing myself but to keep this thread going I will 
start a FP interface based on Jan D and Tom D. suggestions.  Something 
like the following could be a start to an interface definition.

class FloatingPoint(object):

     def __init__(self):
         pass

     def Add(self, clk, reset,
	    a_sign, a_mant, a_exp, dva,
             b_sign, b_mant, b_exp, dvb,
             r_sign, r_mant, r_exp, dvr,
	    EXP_W=8, MAN_W=23):
         pass

     def Mul(self, clk, reset,
	    a_sign, a_mant, a_exp, dva,
             b_sign, b_mant, b_exp, dvb,
             r_sign, r_mant, r_exp, dvr,
	    EXP_W=8, MAN_W=23):
         pass

     def Div(self, clk, reset,
	    a_sign, a_mant, a_exp, dva,
             b_sign, b_mant, b_exp, dvb,
             r_sign, r_mant, r_exp, dvr,
	    EXP_W=8, MAN_W=23):
         pass


I simply added a dv* and dvo for flow control.  I did not add the error 
signals / info output signals.  Note they are all the same interface for 
each op.  Since the "sign" is explicit, it can be flipped for 
subtraction etc.

This is for modeling not conversion, yet.

Chris Felton

Re: [myhdl-list] Floating Point Libraries

[Christopher F. <chr...@gm...>]

<snip>
>
> So why not start with a workaround? We could define an
> interface using a_sign, a_mant, a_exp and b_sign, b_mant, b_exp.
> Ok, the interface is flattened, but in the code the only
> difference would be the underscore instead of dot notation.
> But it would teach us if this type of interface is really
> what we want to work with. And it works today. And if conversion ever
> gets more powerful, an upgrade may be simple.



Are you thinking something like the following?  If I understand, the 
proposal would be to have one Signal for a complex structure vs. a 
structure with multiple Signals.

-----------
from myhdl import *

class TypeStruct(object):

	def __init__(self):
		x = intbv(0)[8:]
		y = intbv(0)[12:]
		z = intbv(0)[23:]
		

if __name__ == '__main__':
     struct = Signal(TypeStruct())
     struct.next.x = 1
     struct.next.y = 2
     struct.next.z = 3
     struct._update()   # usually happens behind the scenes

     print struct.x, struct.y, struct.z

-----------

This isn't specific to the FP interface proposal.  This is the general 
method to handle grouping of types.  And then the conversion proposal 
would be; that a Signal carrying a class type (and dict?) the internal 
intbv types would be expanded to struct_x, struct_y, struct_z, for the 
above example?

I follow, that the conversion work would follow the general modeling 
approach.

Or when you said "code" you are referring to the MyHDL code.  And for 
the near-term it is more important to define a working convertible FP 
module that is support by MyHDL 0.7.  The FP unit would be built using 
the interface you mentioned and in the future it could be replaced by 
something like the above.

Chris Felton

Re: [myhdl-list] Free MyHDL class on skype

[David R. <dav...@gm...>]

Hi,

I am in for the class!

On Thu, Apr 14, 2011 at 2:01 AM, Christopher Lozinski <
loz...@fr...> wrote:

> Well only one of us has our boards so far, but what the heck, let us get
> started.
>
> We can walk through the python tutorials first, for those who are new to
> python.
>
> First we will do a basic flip flop, then display or simulate the signal
> somehow.
>
> We can all write a test script for that.
>
> Then we will do the blinking light tutorials.  Work out all the problems.
>
> And then, later, once people start getting boards, we can push the class
> out to hardware.
>
> As for boards, I should say that dsptronics had 3 of the small ones (250
> K  Gates).  Of those 2 should have shipped by now.   Reportedly they are
> making 5 more of the large ones (500K Gates).  They are supposedly
> going to be ready on the 23rd of April.
>
> There was a complaint that I am pushing dsptronics.  My apologies.    I
> am quite agnostic about boards and chip sets.  They are the only
> supported board so far.  That is why I support them.
>
> But why wait?   Let us start with an online class.   It is free.  Send
> me an email if you are interested.  And tell me what you would like
> covered?
>
> And the people at the Cordoba trade show can tell the newbies that we
> are offering a free online class in the next week or so.   If a large
> class is unwieldy online, I may limit it to the first 4 people who sign up.
>
> I should also say that this is the first time I am doing this, I have
> never done this before.  But we will figure it out as we go along.  And
> there is nothing like having a deadline for a scheduled class for
> focusing the mind.   By the time I offer the second class, it will be
> quite good.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
>
> ------------------------------------------------------------------------------
> Benefiting from Server Virtualization: Beyond Initial Workload
> Consolidation -- Increasing the use of server virtualization is a top
> priority.Virtualization can reduce costs, simplify management, and improve
> application availability and disaster protection. Learn more about boosting
> the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
David Rodríguez Martin
Cambridge,UK

[myhdl-list] Free MyHDL class on skype

[Christopher L. <loz...@fr...>]

Well only one of us has our boards so far, but what the heck, let us get 
started.

We can walk through the python tutorials first, for those who are new to 
python.

First we will do a basic flip flop, then display or simulate the signal 
somehow.

We can all write a test script for that.

Then we will do the blinking light tutorials.  Work out all the problems.

And then, later, once people start getting boards, we can push the class 
out to hardware.

As for boards, I should say that dsptronics had 3 of the small ones (250 
K  Gates).  Of those 2 should have shipped by now.   Reportedly they are 
making 5 more of the large ones (500K Gates).  They are supposedly
going to be ready on the 23rd of April.

There was a complaint that I am pushing dsptronics.  My apologies.    I 
am quite agnostic about boards and chip sets.  They are the only 
supported board so far.  That is why I support them.

But why wait?   Let us start with an online class.   It is free.  Send 
me an email if you are interested.  And tell me what you would like 
covered?

And the people at the Cordoba trade show can tell the newbies that we 
are offering a free online class in the next week or so.   If a large 
class is unwieldy online, I may limit it to the first 4 people who sign up.

I should also say that this is the first time I am doing this, I have 
never done this before.  But we will figure it out as we go along.  And 
there is nothing like having a deadline for a scheduled class for 
focusing the mind.   By the time I offer the second class, it will be 
quite good.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] MyHDLClass

[Jan D. <ja...@ja...>]

On 04/13/2011 11:05 PM, Christopher Lozinski wrote:
> Home page is massively updated.
>
> http://MyHDLClass.com
>
> That provides links to the course material, still on Chris Felton's Hg
> server.  Next I start editing the course material.
>
> We are releasing this material under a creative commons non-commercial
> license, same as MyHDL.org.

This may be the appropriate license for your purposes,
but for myhdl.org it really is a (my) mistake.

Given the evolutions, I have done some quick research.
Some comments about myhdl.org.

The original license was GDFL. If you look carefully, it
it is still there. This shows that something is wrong,
because this is not compatible with CC BY-NC-SA.
GDFL permits commercial use.

The problem is that the dokuwiki templates add the
CC BY-NC-SA license as a default, and I forgot to
remove/modify it.

Just as with MyHDL, my intention is not to prevent
commercial use. All I want to ensure is that derivative
works are licensed under the same terms, so that
everyone, include the original authors, can benefit
from the work they started.

To make matters confusing, the appropriate license is
no longer the GDFL. As the example of wikipedia has
shown, things have evolved and the GDFL is not the best
choice for wiki's. The right license is the wikipedia
one: CC BY-SA. This permits commercial use, like GDFL,
but works much better for interactive wiki's with
manycontributors.

In addition, there should be terms of use so that
contributors and users know how they should operate.
Again wikipedia can serve as an example.

I will soon take an iniative to clean this up - it
will require the approval of all contributors of
significant content.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDLClass

[Christopher L. <loz...@fr...>]

That url now works.

http://MyHDLClass.com

Prettiest web site I have done in my life.

And probably fastest.

Sorry about that.  The templates I used were index.html, zope expects 
index_html, the redirect I did correctly, so I did not see the problem.

thanks again Ben.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] MyHDLClass

[Jan D. <ja...@ja...>]

On 04/13/2011 11:05 PM, Christopher Lozinski wrote:
> Home page is massively updated.
>
> http://MyHDLClass.com
>
> That provides links to the course material, still on Chris Felton's Hg
> server.  Next I start editing the course material.
>
> We are releasing this material under a creative commons non-commercial
> license, same as MyHDL.org.
>
> We are going with Sphinx for editing the manual.  That is what
> python.org and MyHDL.org use.  I am new to it.  I would love your help
> with this work.

myhdl.org - the web site - uses dokuwiki.

The MyHDL manual is developed using sphinx,
like the Python manuals. Sphinx is good for large
technical manuals.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDLClass

[Christopher L. <loz...@fr...>]

In the meantime this URL should work.

  http://208.86.225.44/Localizer/MyHDLClass/index.html

What is happening is I just updated the DNS for this site.  So if you 
get the old dns entry it redirects correctly, if you get the new entry, 
there is trouble.  I am fixing it.  In the meantime the above should work.

Thanks ben.  Pleasure to work with a group that gives me feedback.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] MyHDLClass

[Christopher L. <loz...@fr...>]

Well I have reports from Ben that the url breaks under

Mac OS X Chrome, Firefox, and Mozilla.  Of course it works for me on 
those platforms.

I am off to test on some more computers.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

[myhdl-list] MyHDLClass

[Christopher L. <loz...@fr...>]

Home page is massively updated.

http://MyHDLClass.com

That provides links to the course material, still on Chris Felton's Hg 
server.  Next I start editing the course material.

We are releasing this material under a creative commons non-commercial 
license, same as MyHDL.org.

We are going with Sphinx for editing the manual.  That is what 
python.org and MyHDL.org use.  I am new to it.  I would love your help 
with this work.

Now my attention turns to supporting this class.   We will do what we 
can to help you work through the course materials.   With the caveat 
that we are waiting for our first board to arrive, but we will probably 
get it before you get your board!

And the page has a nice photo from the recent FPGACentral conference.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Floating Point Libraries

[Tom D. <td...@di...>]

> Actually I believe there are many good applications for
> "hierarchy" in signals, but I don't think this particular
> case is one.
>
> Before continuing, let me stress once more a point which
> is missed all the time. Everything that is being talked
> about, no matter how complex, can being done in MyHDL -
> the modeling language today. That is not the problem.
>
> The problem is conversion. We need it for the things
> that have to get implemented, but I'm finding it hard.
> For other parts in MyHDL, we can reuse the python
> interpreter. For conversion, we write a compiler
> ourselves. The biggest problem is that for anything
> that we want to support, we have to find and implement
> a meaningful mapping in a much less capable language
> such as Verilog.
>
> Once again: in MyHDL modeling you can do anything you
> want. There is nothing that prevents us from experimenting
> with the type of interface we would like to have,
> and then see if and how we could support it in
> the conversion.
>

I agree that this is only an issue with conversion. And I would also 
add, it is only an issue at the top module level.

The simple solution I use is make a wrapper for the top level I/O. 
Honestly a couple of lines of python code. Like this:

     C = cordic.cordic(type=cordic.MAG)

     # must have intbv at top to make Verilog, so need wrapper
     def cordic_top(mag,in_r,in_i,ov,clk,r,iv) :
       inC = cplx.cplx(in_r,in_i)

       CM0 = C.logic(mag,inC,ov,clk,r,iv)
       return CM0

cplx is just a class that maintains the real and imaginary of whatever 
type you are using. Typically I would have two of some other data type, 
fixed, float or int.

cordic is a class that contains the logic and models for the module.

Now I don't know how conversion works and frankly it is like magic to 
me. I was just saying if we wanted to fix this, my idea (for what it's 
worth) would be to allow a class to inherit a base set of methods that 
conversion knew about. Then change the ones needed to simplify your life.

My assumption is that the Signal class contains some conversion 
information.

Re: [myhdl-list] New MyHDL Tutorial Available.

[Andrew S. <g.a...@gm...>]

Hi Christopher,

Please explain what you mean by:

"So the course material is not strictly open source.  By contributing to
it, you are allowing me to make some money off of it."

Please state what the license to the course material is.

There has never been any requirement that nobody make any money off open
source!  So I think that your argument to keep it closed source for that
reason is weak.  For example people can use OSS in their daily jobs, include
it as part of selling products, teach courses on it, write books,
consulting, etc.

If your idea is that since this course material is closed source, then only
you (or people who license the course material from you) will be able to use
it to teach courses, then I shall certainly retract my offer to test it on
the Lattice Brevia XP2.  And regardless of the goodness that you are
currently bringing, shall heartily wish that you find another endeavor.

However, I don't think that it would come to that.  Just open-source the
course material.  If and when myHdl becomes popular, you'll have plenty of
paid opportunities as the author of the course.  After all, who would you
pay to hear a lecture about myHdl from: Jan D. or me :-).

Frankly, if you keep it closed source, you are simply inviting a
competitor.  Once you've created a market for training classes, consulting,
etc, someone else will make a completely separate open-source course and
rapidly overtake your course in popularity due to its somewhat "free"
nature.  The value is not in the actual course material...the value is in
the generation of the market.  Fortunately that cannot ever be cornered
because of the OSS nature of myHdl.  Your best strategy is to dis-invite
competition by open-sourcing your training material.

Regards,
Andrew


On Sun, Apr 10, 2011 at 10:10 PM, Christopher Lozinski <
loz...@fr...> wrote:

> I am pleased to announce a MyHDL tutorial at
> http://MyHDLClass.com
>
> Thank you Christopher Felton for all the hard work, and more importantly
> for getting it done so quickly.
>
> I think that this demonstrates that MyHDL is evolving very rapidly.  The
> conference was over just 4 days ago.  Just watch!
>
> We invite you to read and download the material, and go buy a board.
> http://www.dsptronics.com/
>
> There are some other boards that people have committed to supporting
> shortly.
>
> I particularly invite you to edit the course material.  If we all make a
> few edits, in no time at all, there will be a rich deep and wonderful
> course.
>
> Let me talk a little bit about the business model.  We had a business
> model.  Jan Decaluwe was using MyHDL and consulting.  Things were not
> moving very fast.  There was a perception of a one man show.  We all
> appreciate what he did.  We now have a new business model.  MyHDL is
> still open source material, but we have a class to offer, and charge
> people for.  My intention is to offer that class at the upcoming DAC
> conference, and use the proceeds to support a booth there.  The booth is
> not that expensive.  What is expensive is engineers time to man the
> booth.   And there are a lot of FPGA trade shows around the world to
> exhibit at and travel to.
>
> So the course material is not strictly open source.  By contributing to
> it, you are allowing me to make some money off of it. Basically that
> will go to pay for my time, and trade show space.  This should allow
> MyHDL to grow much faster.   It is now easy for people to invest in
> MyHDL, because they know that things are happening very fast, moving at
> light speed.
>
> So please thank Christopher Felton for all his hard work, or better yet,
> go and order one of his boards.
> Please order one of his boards.   Please.
>
> And try out the course material.
>
> And if you want permission to edit the course material, just send me an
> email.
> Also let me know if you want to sign up for the class.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
>
> ------------------------------------------------------------------------------
> Xperia(TM) PLAY
> It's a major breakthrough. An authentic gaming
> smartphone on the nation's most reliable network.
> And it wants your games.
> http://p.sf.net/sfu/verizon-sfdev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>

[myhdl-list] myhdl direction/strategy recap?

[Andrew S. <g.a...@gm...>]

Hi all,

I am pretty excited to see some evangelical interest in myHdl!  But just to
satisfy my/our curiosity can the list get some of the back story?

Why this sudden change?  Why now?  What is the future?  Who is involved?

Regards,
Andrew

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

On 4/13/2011 7:51 AM, Ben wrote:
> On Wed, Apr 13, 2011 at 05:00, Christopher Felton
> <chr...@gm...>  wrote:
>> The code can be retrieved from :
>> hg clone https://bitbucket.org/dsptronics/myhdl_tutorials
>>
>
> I was willing to put the doc from google docs to restructuredText
> format there also, I just cannot find the link to the google doc
> anymore ...
>
> Does anyone raise any objection ?
>
> Does anyone has that link ?

I don't object and it was mentioned by others that reST would be a good 
format.  I don't know what happened to the original google doc?

Chris Felton

Re: [myhdl-list] New MyHDL Tutorial Available.

[Ben <ben...@gm...>]

On Wed, Apr 13, 2011 at 05:00, Christopher Felton
<chr...@gm...> wrote:
> The code can be retrieved from :
> hg clone https://bitbucket.org/dsptronics/myhdl_tutorials
>

I was willing to put the doc from google docs to restructuredText
format there also, I just cannot find the link to the google doc
anymore ...

Does anyone raise any objection ?

Does anyone has that link ?

Regards,
Benoît

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

On 4/13/2011 7:34 AM, David Rodríguez wrote:
> Yes it does. As I said, I was being "picky".

Picky is fine and encourage!

>
> Regarding the reset signal. Do you have a power_up pin on that FPGA that
> shows you when power has been enable? The reset signal could be hooked
> up to that pin.

Yes, you can use an unused PIN and configure it with a pullup and use it 
as an active low reset to some flip-flops to create a sync-reset.  This 
covers, voltage, clock, and config.  I explained a little why I did not 
use a reset in this circuit.  If most feel more comfortable with a reset 
I can add one.

>
> Do we have to explain how to pin assignment in the document?

I don't think so for this tutorial, I think we want it to be as much 
MyHDL focused as possible.  I am hoping to completely automate the 
bit-file creation.

>
> Chris, are you using a Mac for this...I have a couple of questions that
> would be a good idea to ask off the MyHDL list for Mac user...obviously
> regarding MyHDL.

I use a Mac and widoze and linux (ugh).  I have an older Mac (PPC) so I 
cannot run an emulated Win/Lin to run the Xilinx tools.  I have not 
tried Wine to run the P&R tools (I would be willing to give it a shot). 
  I can try and answer Mac-MyHDL questions.

>
>
>
> On Wed, Apr 13, 2011 at 1:21 PM, Christopher Felton
> <chr...@gm... <mailto:chr...@gm...>> wrote:
>
>     On 4/13/2011 2:55 AM, David Rodríguez wrote:
>      > Hi,
>      >
>      > I'm being "picky" but it will be a good idea to change variable
>     CLK_RATE
>      > to CLK_48Mhz. It makes more sense when reading the code as the
>     LED rate
>      > of change is also named LED_RATE. In doing so, it is easier to
>      > understand things like Nloops=CLK_48Mhz*LED_RATE.
>      >
>
>     Does CLK_FREQ work for you?  I don't want to explicitly state 48MHz
>     because we are targeting multiple boards, all which have different
>     frequencies.
>
>     Chris Felton
>
>     (I also noticed I can't do math in comments :), I will fix if someone
>     already hasn't )
>
>     <snip>
>
>
>     ------------------------------------------------------------------------------
>     Forrester Wave Report - Recovery time is now measured in hours and
>     minutes
>     not days. Key insights are discussed in the 2010 Forrester Wave
>     Report as
>     part of an in-depth evaluation of disaster recovery service providers.
>     Forrester found the best-in-class provider in terms of services and
>     vision.
>     Read this report now! http://p.sf.net/sfu/ibm-webcastpromo
>     _______________________________________________
>     myhdl-list mailing list
>     myh...@li...
>     <mailto:myh...@li...>
>     https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>
>
>
> --
> David Rodríguez Martin
> Cambridge,UK
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

On 4/13/2011 7:09 AM, Jan Decaluwe wrote:
> On 04/13/2011 05:00 AM, Christopher Felton wrote:
>
>>
>> The code can be retrieved from :
>> hg clone https://bitbucket.org/dsptronics/myhdl_tutorials
>
> Ok, great, I got access and made some text edits.
> (The code still runs :-))
>
> There is a remark I forgot previously: why no reset signals?
> I guess fpga software does the "right" thing
> at initialization, but as a matter of policy,
> isn't adding a reset a good idea?
>

Yes and no, I was not trying to exploit the fact that the FPGA has a POR 
and the state of the FF is known at power on (config release).  But 
rather, when possible not to use resets.  At least I have been 
encouraged in the past.  In this case, the >= handles the "unknown" 
cases.  If the counter comes up either the >= will get the value back in 
range or the first LED cycle will be short.  Both acceptable behavior.

If most feel more comfortable with a reset I am not against it.

Note, not using resets only makes sense in a small subset of circuits. 
When I was in CO. there were a lineage of folks that worked on fibre 
controller chip-sets.  This was their policy, never to use resets (crazy 
huh).  This flowed over to other companies and work in the area, 
including the SigProc-FPGA work I was doing at the time.  And best of my 
knowledge they have shipping chip-sets with limited use of resets (not 
FPGA).  As mentioned, for most I don't think this is practical, you have 
to be very careful that you understand all the possible init states and 
know that each is handled correctly.

Chris Felton

Re: [myhdl-list] New MyHDL Tutorial Available.

[David R. <dav...@gm...>]

Yes it does. As I said, I was being "picky".

Regarding the reset signal. Do you have a power_up pin on that FPGA that
shows you when power has been enable? The reset signal could be hooked up to
that pin.

Do we have to explain how to pin assignment in the document?

Chris, are you using a Mac for this...I have a couple of questions that
would be a good idea to ask off the MyHDL list for Mac user...obviously
regarding MyHDL.



On Wed, Apr 13, 2011 at 1:21 PM, Christopher Felton
<chr...@gm...>wrote:

> On 4/13/2011 2:55 AM, David Rodríguez wrote:
> > Hi,
> >
> > I'm being "picky" but it will be a good idea to change variable CLK_RATE
> > to CLK_48Mhz. It makes more sense when reading the code as the LED rate
> > of change is also named LED_RATE. In doing so, it is easier to
> > understand things like Nloops=CLK_48Mhz*LED_RATE.
> >
>
> Does CLK_FREQ work for you?  I don't want to explicitly state 48MHz
> because we are targeting multiple boards, all which have different
> frequencies.
>
> Chris Felton
>
> (I also noticed I can't do math in comments :), I will fix if someone
> already hasn't )
>
> <snip>
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
David Rodríguez Martin
Cambridge,UK

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

On 4/13/2011 2:55 AM, David Rodríguez wrote:
> Hi,
>
> I'm being "picky" but it will be a good idea to change variable CLK_RATE
> to CLK_48Mhz. It makes more sense when reading the code as the LED rate
> of change is also named LED_RATE. In doing so, it is easier to
> understand things like Nloops=CLK_48Mhz*LED_RATE.
>

Does CLK_FREQ work for you?  I don't want to explicitly state 48MHz 
because we are targeting multiple boards, all which have different 
frequencies.

Chris Felton

(I also noticed I can't do math in comments :), I will fix if someone 
already hasn't )

<snip>