myhdl-list — Mailing list for discussions on MyHDL

[myhdl-list] wrap function

[Christopher F. <chr...@gm...>]

I created a small write-up here, 
http://www.myhdl.org/doku.php/user:cfelton:projects:wrap, for a proposed 
intbv.wrap() function.

I wrote this quick and probably needs a second look.  I will look at the 
implementation details later.

Any comments welcome.

Thanks
Chris Felton

Re: [myhdl-list] spislave code

[Christopher F. <chr...@gm...>]

I believe traceSignals is looking for at least one "@instance".  But the 
@instance can (should) be in your testbench.  You should create 
something like:

def test():
     SPISlave_inst = ...

     @instance
     def test_stimulus():
         ...

     return SPISalve_inst, test_stimulus

if __name__ == '__main__':
    tb = test()
    Simulation(tb).run()


The above is an example, you can define your clocks, reset, etc in the 
testbench.  Then when the simulation runs it will create the VCD file.

Hope that helps,
Chris Felton

On 4/12/11 6:00 AM, Thomas Heller wrote:
> I found some confusing behaviour when I tried he code published
> in this article: http://www.linuxjournal.com/node/7542/print
> (The article is the first link that google finds when searching
> for "myhdl spislave").
>
> Apparently myhdl isn't able to handle this code:
>
> def SPISlave(miso, mosi, sclk, ss_n,
>                txdata, txrdy, rxdata, rxrdy,
>                rst_n, n=8):
>       ...
>       def RX():
>           ...
>
>       def TX():
>           ...
>       return RX(), TX()
>
> when it is instantiated with traceSignals:
>
>       SPISlave_inst = traceSignals(SPISlave,
>           miso, mosi, sclk, ss_n,
>           txdata, txrdy, rxdata, rxrdy, rst_n, n=n)
>
> However, using it in this way works fine:
>
>       SPISlave_inst = SPISlave(
>           miso, mosi, sclk, ss_n,
>           txdata, txrdy, rxdata, rxrdy, rst_n, n=n)
>
> Is this a bug?
>
> The code works in both cases, however, if is is rewritten
> in this way:
>
> def SPISlave(miso, mosi, sclk, ss_n,
>                txdata, txrdy, rxdata, rxrdy,
>                rst_n, n=8):
>       ...
>       @instance
>       def RX():
>           ...
>       @instance
>       def TX():
>           ...
>       return RX, TX
>
>
> Thanks,
> Thomas
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo

Re: [myhdl-list] spislave code

[Christopher F. <chr...@gm...>]

What signal definitions did you use?

Re: [myhdl-list] spislave code

[Christopher F. <chr...@gm...>]

I have not tried the code (yet) but as you noticed the version in the 
LinuxJournal was before the decorators (@always, @always_comb, @instance).

Maybe LinuxJournal would run another article with updated features?

Something might have been lost/broke.  But I believe, it is the intent 
that this should still work.  Both RX and TX are still iterators.  I can 
try and see what error it produces.

Chris Felton

On 4/12/11 6:00 AM, Thomas Heller wrote:
> I found some confusing behaviour when I tried he code published
> in this article: http://www.linuxjournal.com/node/7542/print
> (The article is the first link that google finds when searching
> for "myhdl spislave").
>
> Apparently myhdl isn't able to handle this code:
>
> def SPISlave(miso, mosi, sclk, ss_n,
>                txdata, txrdy, rxdata, rxrdy,
>                rst_n, n=8):
>       ...
>       def RX():
>           ...
>
>       def TX():
>           ...
>       return RX(), TX()
>
> when it is instantiated with traceSignals:
>
>       SPISlave_inst = traceSignals(SPISlave,
>           miso, mosi, sclk, ss_n,
>           txdata, txrdy, rxdata, rxrdy, rst_n, n=n)
>
> However, using it in this way works fine:
>
>       SPISlave_inst = SPISlave(
>           miso, mosi, sclk, ss_n,
>           txdata, txrdy, rxdata, rxrdy, rst_n, n=n)
>
> Is this a bug?
>
> The code works in both cases, however, if is is rewritten
> in this way:
>
> def SPISlave(miso, mosi, sclk, ss_n,
>                txdata, txrdy, rxdata, rxrdy,
>                rst_n, n=8):
>       ...
>       @instance
>       def RX():
>           ...
>       @instance
>       def TX():
>           ...
>       return RX, TX
>
>
> Thanks,
> Thomas
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo

[myhdl-list] spislave code

[Thomas H. <th...@ct...>]

I found some confusing behaviour when I tried he code published
in this article: http://www.linuxjournal.com/node/7542/print
(The article is the first link that google finds when searching
for "myhdl spislave").

Apparently myhdl isn't able to handle this code:

def SPISlave(miso, mosi, sclk, ss_n,
              txdata, txrdy, rxdata, rxrdy,
              rst_n, n=8):
     ...
     def RX():
         ...

     def TX():
         ...
     return RX(), TX()

when it is instantiated with traceSignals:

     SPISlave_inst = traceSignals(SPISlave,
         miso, mosi, sclk, ss_n,
         txdata, txrdy, rxdata, rxrdy, rst_n, n=n)

However, using it in this way works fine:

     SPISlave_inst = SPISlave(
         miso, mosi, sclk, ss_n,
         txdata, txrdy, rxdata, rxrdy, rst_n, n=n)

Is this a bug?

The code works in both cases, however, if is is rewritten
in this way:

def SPISlave(miso, mosi, sclk, ss_n,
              txdata, txrdy, rxdata, rxrdy,
              rst_n, n=8):
     ...
     @instance
     def RX():
         ...
     @instance
     def TX():
         ...
     return RX, TX


Thanks,
Thomas

Re: [myhdl-list] 2's compliment wrap (long post)

[Christopher F. <chr...@gm...>]

While I slept the wrap() function seemed liked it had been discussed 
before.  And yes, it had.  There was a long thread on this topic back in 
June 2007 (crazy, 3 years ago).

I will review this thread and I will propose a method to handle the wrap.

Thanks
Chris Felton

On 4/11/11 5:14 PM, Christopher Felton wrote:
> The signed 2's compliment wrap has come up before but it was embedded in
> other threads.  I thought I would bring the topic up again.
>
> In many digital filters take advantage of the 2's compliment wrap
> property.  One such example is the CIC filter
> (http://www.myhdl.org/doku.php/projects:gcicexample).  Standard FIR and
> IIR filter implementations might exploit this property as well.
>
> The "wrap" behavior in this context is similar to an unsigned wrap.  The
> "bits" behave the same but the "value" is signed.  When the bit-vector
> wraps it goes from negative to positive.  And there is an intermediate
> wrap as well, that half-way point, when we go one past the max positive
> value the value changes positive to negative.  Example for a signed
> 3-bit word the following are the signed values for the range 3,-4.
>
> bin   signed
> ----+--------
> 000    0
> 001    1
> 010    2
> 011    3
> 100    -4
> 101    -3
> 110    -2
> 111    -1
> 000    0
> 001    1
>
> To declare a Signal of signed type in MyHDL
>     x = Signal(intbv(0, min=-4, max=4))
>
> This type has all the desired features of an Int (as described in Jan
> D's "These Ints are made ...").  But I have not found a good way to do
> handle the 2's compliment wrap in MyHDL, yet.
>
> The unsinged wrap has been discussed before and there are a couple
> solutions, one being to explicitly use the mod operator, example.
>
>     x = Signal(intbv(0)[16:])
>     ...
>         x.next = (x + 1) % 2**16
>
> For unsigned integers this works great.  And it is has the benefit of
> being explicit and efficient.  Someone looking at the code knows what is
> happening and the resulting hardware will be as expected, i.e. no
> additional hardware to handle the wrap inherent to a register word.
>
> For the signed case, I have thought of only two options:
>
> 1. "Cast" to an unsigned then cast back
>
> 2. Explicitly define the logic to describe the behavior.
>
> Option 1, produces the desired circuit but seems like there should be a
> better option?  Option 2 is complicated and doesn't automatically
> simplify (addition hardware is generated).  Option 2 I incorrectly
> posted on the wiki as an example (will fix soon).
>
> Any hints or ideas?
>
> Maybe one method would be to have a wrap() function (or whatever might
> be a good name).  Similar to the concat() function.  The wrap() function
> can work for signed and unsigned.  And can automatically handle the
> "values" of the types.  For conversion, nothing has to happen, just
> identified that the user wants the behavior of the wrap.  A user has to
> explicitly use a wrap the default boundary checks are still used but can
> be overridden by a user.
>
> Thanks
> Chris Felton
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo

Re: [myhdl-list] CASE versus IF (MyHDL)

[Jan D. <ja...@ja...>]

David:

The convertor detects commonly used if-then-else patterns
that can be mapped to VHDL/Verilog case statements, and
does so when possible.

http://www.myhdl.org/doc/current/manual/conversion_examples.html#optimizations-for-finite-state-machines
http://www.myhdl.org/doc/current/whatsnew/0.7.html#more-powerful-mapping-to-case-statements

On 04/12/2011 11:49 AM, David Rodríguez wrote:
> Dear MyHDL distribution list,
>
> I am going through the MyHDL traning material. I have almost completed the RTL combinatorial and sequential modelling section.  I need to find some time to type some code and see how good my understanding  of everything is. However, there is something that bothers me. I have found in the VHDL that there is a big difference when CASE statements and IF statements are used.
>
> I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).
>
> IF will be used if you want to a sequence of events to happens (synthesis tools would infer a "daisy-chain" of MUXs).
>
> It is important to say that what I've observed probably is an outcome of something I am doing wrong or some lack of experience. But I would like to know what the opinion about the no CASE statement in Python is and if that can limit MyHDL capability to model digital systems.
>
>   regards,
>
> --
> David Rodríguez Martin
> Cambridge,UK
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

[myhdl-list] CASE versus IF (MyHDL)

[David R. <dav...@gm...>]

Dear MyHDL distribution list,

I am going through the MyHDL traning material. I have almost completed the
RTL combinatorial and sequential modelling section.  I need to find some
time to type some code and see how good my understanding  of everything is.
However, there is something that bothers me. I have found in the VHDL that
there is a big difference when CASE statements and IF statements are used.

I tend to use CASE when I want a given MUX to be inferred (e.g. MUX 4-to-1).

IF will be used if you want to a sequence of events to happens (synthesis
tools would infer a "daisy-chain" of MUXs).

It is important to say that what I've observed probably is an outcome of
something I am doing wrong or some lack of experience. But I would like to
know what the opinion about the no CASE statement in Python is and if that
can limit MyHDL capability to model digital systems.

 regards,

-- 
David Rodríguez Martin
Cambridge,UK

Re: [myhdl-list] Boards

[Karl K. <kk...@be...>]

Just a clarification on the DE2 boards. According to Altera's web site
http://www.altera.com/education/univ/materials/boards/de2/unv-de2-board.htmlthe
boards start around $500 or $270 for academics.

BTW: DE2 is a really great board for classes and demos.

--Karl

On Mon, Apr 11, 2011 at 1:22 PM, Christopher Lozinski <
loz...@sp...> wrote:

> I spoke to Christopher Felton, he has 2 DSPTronics boards in inventory,
> and an unsupported prototype board he could sell to a poor person for
> less money. He sent one to England, but reportedly that has not arrived.
>   His boards go for $200 or $230.
>
> I spoke to his manufacturer, they are producing 5 more boards.  So I am
> confident in a supply of Xilinx boards.
>
> I had a long talk with Wayne Radohonski this morning.  He has committed
> to supporting the
> Altera Terasic DE2 board.   They are more expensive boards, he said
> thousands of dollars.
> We talked extensively about integrating MyHDL with the large stack of
> proprietary libraries from Altera.
>
> Andrew Stone committed to supporting the entry-level Lattice board, and
> Chris Felton offered to support that effort.  In fact Chris went ahead
> and ordered that board for himself.
>
> Hope that helps.  Let me know if I missed anything.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Best regards,

Karl Kaiser | 408 306 1755

[myhdl-list] 2's compliment wrap (long post)

[Christopher F. <chr...@gm...>]

The signed 2's compliment wrap has come up before but it was embedded in 
other threads.  I thought I would bring the topic up again.

In many digital filters take advantage of the 2's compliment wrap 
property.  One such example is the CIC filter 
(http://www.myhdl.org/doku.php/projects:gcicexample).  Standard FIR and 
IIR filter implementations might exploit this property as well.

The "wrap" behavior in this context is similar to an unsigned wrap.  The 
"bits" behave the same but the "value" is signed.  When the bit-vector 
wraps it goes from negative to positive.  And there is an intermediate 
wrap as well, that half-way point, when we go one past the max positive 
value the value changes positive to negative.  Example for a signed 
3-bit word the following are the signed values for the range 3,-4.

bin   signed
----+--------
000    0
001    1
010    2
011    3
100    -4
101    -3
110    -2
111    -1
000    0
001    1

To declare a Signal of signed type in MyHDL
   x = Signal(intbv(0, min=-4, max=4))

This type has all the desired features of an Int (as described in Jan 
D's "These Ints are made ...").  But I have not found a good way to do 
handle the 2's compliment wrap in MyHDL, yet.

The unsinged wrap has been discussed before and there are a couple 
solutions, one being to explicitly use the mod operator, example.

   x = Signal(intbv(0)[16:])
   ...
       x.next = (x + 1) % 2**16

For unsigned integers this works great.  And it is has the benefit of 
being explicit and efficient.  Someone looking at the code knows what is 
happening and the resulting hardware will be as expected, i.e. no 
additional hardware to handle the wrap inherent to a register word.

For the signed case, I have thought of only two options:

1. "Cast" to an unsigned then cast back

2. Explicitly define the logic to describe the behavior.

Option 1, produces the desired circuit but seems like there should be a 
better option?  Option 2 is complicated and doesn't automatically 
simplify (addition hardware is generated).  Option 2 I incorrectly 
posted on the wiki as an example (will fix soon).

Any hints or ideas?

Maybe one method would be to have a wrap() function (or whatever might 
be a good name).  Similar to the concat() function.  The wrap() function 
can work for signed and unsigned.  And can automatically handle the 
"values" of the types.  For conversion, nothing has to happen, just 
identified that the user wants the behavior of the wrap.  A user has to 
explicitly use a wrap the default boundary checks are still used but can 
be overridden by a user.

Thanks
Chris Felton

Re: [myhdl-list] Floating Point Libraries

[Christopher F. <chr...@gm...>]

On 4/11/2011 3:35 PM, Christopher Lozinski wrote:
> Christopher Felton and I have been having a discussion about libraries.
> I am moving it to the mailing list, because I think many people would be
> interested.
>
> We have been talking about how to represent floating point in MyHDL, and
> how to work with it in Verilog.  Basically the plan is to implement a
> multiply in MyHDL as a python * operator.   Then export it by calling
> some library.  The question is which library.

Note, this approach will take some work and it will be a module on-top 
of MyHDL.  It will be faster to first implement the fp libraries in 
MyHDL or decide how to interface with external fp libs.

>
> So Wayne  Radohonski is quite committed to supporting his Altera board.
>
> The libraries he wants to use are the Altera libraries.  Phase lock
> loop, and then floating point multiply.
> His point is that building phase lock loops is even more important than
> the floating point multiplier.

Do you mean, to instantiate the PLLs that are in the Altera FPGA or to 
design an ADLL (all digital lock loop)?

Do you know which Altera fp libraries are targeted?  They might cost $$ 
and not many people might have access to them.

>
> Both because supporting an Altera board is important, and because of the
> policy of one engineer at a time, I want to support the boards Wayne
> wants in this endeavor.  So the plan is to create two MyHDL classes, one
> for a floating point signal, and one for a floating point multiplier.
> When exporting it will generate the right Verilog code to call the
> Altera libraries.  Later it will call other libraries.  One at a time.
>
> How does that sound?
>

This is a similar approach Andrew L, just need to be careful which mixed 
approach to take.  The DE2 boards are mid-size Cyclone FPGAs, he 
probably has the 70k DE2 board?

Chris Felton

[myhdl-list] Unsubscribe

[Kanchan D. <kan...@gm...>]

Please remove this email id from your mailing list.
Thanks,
Kanchan

[myhdl-list] DAC Conference update

[Christopher L. <loz...@fr...>]

Well plan B was to offer a tutorial, but we are too late for that I just 
found out.

And as far as I can tell, no one has tried out the tutorial!

So we will see if someone makes up T-shirts or not.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

[myhdl-list] Floating Point Libraries

[Christopher L. <loz...@fr...>]

Christopher Felton and I have been having a discussion about libraries.  
I am moving it to the mailing list, because I think many people would be 
interested.

We have been talking about how to represent floating point in MyHDL, and 
how to work with it in Verilog.  Basically the plan is to implement a 
multiply in MyHDL as a python * operator.   Then export it by calling 
some library.  The question is which library.

So Wayne  Radohonski is quite committed to supporting his Altera board.

The libraries he wants to use are the Altera libraries.  Phase lock 
loop, and then floating point multiply.
His point is that building phase lock loops is even more important than 
the floating point multiplier.

Both because supporting an Altera board is important, and because of the 
policy of one engineer at a time, I want to support the boards Wayne 
wants in this endeavor.  So the plan is to create two MyHDL classes, one 
for a floating point signal, and one for a floating point multiplier.  
When exporting it will generate the right Verilog code to call the 
Altera libraries.  Later it will call other libraries.  One at a time.

How does that sound?

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

[myhdl-list] Boards

[Christopher L. <loz...@sp...>]

I spoke to Christopher Felton, he has 2 DSPTronics boards in inventory, 
and an unsupported prototype board he could sell to a poor person for 
less money. He sent one to England, but reportedly that has not arrived. 
   His boards go for $200 or $230.

I spoke to his manufacturer, they are producing 5 more boards.  So I am 
confident in a supply of Xilinx boards.

I had a long talk with Wayne Radohonski this morning.  He has committed 
to supporting the
Altera Terasic DE2 board.   They are more expensive boards, he said 
thousands of dollars.
We talked extensively about integrating MyHDL with the large stack of 
proprietary libraries from Altera.

Andrew Stone committed to supporting the entry-level Lattice board, and 
Chris Felton offered to support that effort.  In fact Chris went ahead 
and ordered that board for himself.

Hope that helps.  Let me know if I missed anything.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] DA Conference $4300

[Christopher F. <chr...@gm...>]

<snip>
>
> Last year, one of the start-ups I'm coaching (Sigasi)
> "attended" DAC, but not in a booth. They were all over
> place, dressed in eye-catching T-shirts with their
> twitter name, talking to people, giving informal demo's...
> and I think they did get some visibility out of it.
>
I believe it is free to attend on certain days, at least I don't recall 
paying when I went.

> In addition to selling boards, perhaps we can consider selling
> merchandise such as "Expect a paradigm shift" T-shirts :-)?
> Perhaps simply being at DAC with such mystery message
> is a cheap but effective initial step?
>

T-shirts are cool!

Re: [myhdl-list] DA Conference $4300

[Christopher L. <loz...@fr...>]

They were all over the
> place, dressed in eye-catching T-shirts with their
> twitter name, talking to people, giving informal demo's...
> and I think they did get some visibility out of it.
I love Guerrilla Marketing.  Totally appropriate for open source.  Can 
someone make up T-Shirts?

We have the flyers.  Some say too wordy, I think since we are targeting 
engineers they are great.

Regards
Chris

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

<snip>
>
> Let me talk a little bit about the business model.  We had a business
> model.  Jan Decaluwe was using MyHDL and consulting.  Things were not
> moving very fast.  There was a perception of a one man show.  We all
> appreciate what he did.  We now have a new business model.  MyHDL is
> still open source material, but we have a class to offer, and charge
> people for.  My intention is to offer that class at the upcoming DAC
> conference, and use the proceeds to support a booth there.  The booth is
> not that expensive.  What is expensive is engineers time to man the
> booth.   And there are a lot of FPGA trade shows around the world to
> exhibit at and travel to.

In my opinion this is good.  I have enjoyed seeing the increased 
activity on the MyHDL mailing-list this last week.  For me, MyHDL has 
been an invaluable tool.  I have been using it in my professional work 
as well my free time.  Seeing the user base grow should mostly be 
positive.  From some of the feedback it sounds like MyHDL could benefit 
from an increased user base and hopefully more contributors.

<< I realize this  is a late reply and that DAC has been determined too 
expensive. >>

>
> So the course material is not strictly open source.  By contributing to
> it, you are allowing me to make some money off of it. Basically that
> will go to pay for my time, and trade show space.  This should allow
> MyHDL to grow much faster.   It is now easy for people to invest in
> MyHDL, because they know that things are happening very fast, moving at
> light speed.
>

Thanks for providing information to the group how this might evolve and 
benefit the group.

To echo your sentiments, Jan D. has done a terrific job with MyHDL and 
hopefully others will see the value.  And if not, oh well, we will 
continue on using MyHDL.

<snip>

Thanks for lighting a fire under MyHDL!

Chris Felton

Re: [myhdl-list] DA Conference $4300

[Jan D. <ja...@ja...>]

On 04/11/2011 08:13 PM, Christopher Lozinski wrote:
> I heard back about getting a booth at the Design Automation Conference.
>
>> The cost for a 10x10 booth is $4,300. You would need to order the
>> carpeting, etc. after that.
>
> Ouch.  Too expensive for me.
>
> Next attempt, see if I can offer a tutorial before the conference.

I already thought that earlier pricing mentioned sounded
rather cheap ...

I realized this is a chicken and egg problem, but I fear
DAC attendance is really for well-funded companies.

Last year, one of the start-ups I'm coaching (Sigasi)
"attended" DAC, but not in a booth. They were all over
place, dressed in eye-catching T-shirts with their
twitter name, talking to people, giving informal demo's...
and I think they did get some visibility out of it.

In addition to selling boards, perhaps we can consider selling
merchandise such as "Expect a paradigm shift" T-shirts :-)?
Perhaps simply being at DAC with such mystery message
is a cheap but effective initial step?

Jan


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Updated Flyer

[Angel E. <ang...@gm...>]

This is very good and very clear! The only criticism that I can think
of is that it is perhaps too wordy for a flyer, but the explanation
and the exposition of the many advantages of MyHDL is really good.

Nice!

Angel


On Mon, Apr 11, 2011 at 9:21 PM, Christopher Lozinski
<loz...@fr...> wrote:
> You can see the flyer at
> http:/MyHDLClass.com/Flyer.pdf
>
> And the source code at:
> http:/MyHDLClass.com/Flyer.pdf
>
> I just added an introduction and a conclusion to the excellent technical
> material in the middle.
>
> MyHDL is an open source Python package that lets you go from Python to
> silicon. With MyHDL, you create a Python model of the hardware system, which
> you can then simulate, and validate, or export to Verilog or VHDL, and take
> it to a silicon implementation from there.
>
> Paradigm Shift. MyHDL represents a paradigm shift in digital circuit design.
> We used to talk about design, simulation, synthesis, validation and
> verification. In this new object-oriented world we talk about object-models,
> class libraries, and interfaces to boards. You need to learn and understand
> this new way of thinking.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

[myhdl-list] Updated Flyer

[Christopher L. <loz...@fr...>]

You can see the flyer at
http:/MyHDLClass.com/Flyer.pdf

And the source code at:
http:/MyHDLClass.com/Flyer.pdf

I just added an introduction and a conclusion to the excellent technical 
material in the middle.

*MyHDL*is an open source Python package that lets you go from Python to 
silicon. With MyHDL, you create a Python model of the hardware system, 
which you can then simulate, and validate, or export to Verilog or VHDL, 
and take it to a silicon implementation from there.

*Paradigm Shift. *MyHDL represents a paradigm shift in digital circuit 
design. We used to talk about design, simulation, synthesis, validation 
and verification. In this new object-oriented world we talk about 
object-models, class libraries, and interfaces to boards. You need to 
learn and understand this new way of thinking.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] DA Conference $4300

[Jan Langer<jan...@et...>]

Hi from argentina,
I dont know about the dac, but its european sister conference date offers a shared university booth that is for free. Maybe dac has something similar.
Jan

Durch MOTOBLUR™ verbunden

-----Ursprüngliche Nachricht-----
Von: Christopher Lozinski <loz...@fr...>
An: General discussions on MyHDL <myh...@li...>
Gesendet: Mo, 11 Apr 2011, 15:13:45 GMT-03:00
Betreff: [myhdl-list] DA Conference $4300

I heard back about getting a booth at the Design Automation Conference.

>The cost for a 10x10 booth is $4,300. You would need to order the
>carpeting, etc. after that.

Ouch.  Too expensive for me.

Next attempt, see if I can offer a tutorial before the conference.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org


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[myhdl-list] DA Conference $4300

[Christopher L. <loz...@fr...>]

I heard back about getting a booth at the Design Automation Conference.

>The cost for a 10x10 booth is $4,300. You would need to order the
>carpeting, etc. after that.

Ouch.  Too expensive for me.

Next attempt, see if I can offer a tutorial before the conference.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] New MyHDL Tutorial Available.

[David R. <dav...@gm...>]

Hi All,
I'm still waiting

Sent from my iPod

On 11 Apr 2011, at 05:09, Christopher Lozinski <loz...@fr... 
 > wrote:

> Okay, so I read through the tutorial.  Looks fine. I cleaned up some
> formatting.
> It is very important in python to get the indents correct.  They may
> have been messed up.
> The files are posted on my website, there is a link to them from the
> tutorial.
>
> You should all be able to work through the python part of the  
> exercise.
> Please post to the list when someone has done that successfully.  In
> this internet era, I am hoping that someone does that by the time I  
> wake
> up.  Of course getting it to work with a board will take longer,  
> because
> I do not know anyone who has this board.  The one guy ordered it from
> England, I do not think he has received it yet.
>
> I have contacted the board manufacturer to find out how many they have
> in stock, and when more will be available.
>
> And again my thanks, all of our thanks, to Christopher Felton for  
> doing
> this so rapidly.
>
> -- 
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
> --- 
> --- 
> --- 
> ---------------------------------------------------------------------
> Xperia(TM) PLAY
> It's a major breakthrough. An authentic gaming
> smartphone on the nation's most reliable network.
> And it wants your games.
> http://p.sf.net/sfu/verizon-sfdev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher L. <loz...@fr...>]

Okay, so I read through the tutorial.  Looks fine. I cleaned up some 
formatting.
It is very important in python to get the indents correct.  They may 
have been messed up.
The files are posted on my website, there is a link to them from the 
tutorial.

You should all be able to work through the python part of the exercise.  
Please post to the list when someone has done that successfully.  In 
this internet era, I am hoping that someone does that by the time I wake 
up.  Of course getting it to work with a board will take longer, because 
I do not know anyone who has this board.  The one guy ordered it from 
England, I do not think he has received it yet.

I have contacted the board manufacturer to find out how many they have 
in stock, and when more will be available.

And again my thanks, all of our thanks, to Christopher Felton for doing 
this so rapidly.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org