myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] New MyHDL Tutorial Available.

[Jan D. <ja...@ja...>]

On 04/13/2011 05:00 AM, Christopher Felton wrote:

>
> The code can be retrieved from :
> hg clone https://bitbucket.org/dsptronics/myhdl_tutorials

Ok, great, I got access and made some text edits.
(The code still runs :-))

There is a remark I forgot previously: why no reset signals?
I guess fpga software does the "right" thing
at initialization, but as a matter of policy,
isn't adding a reset a good idea?

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Floating Point Libraries

[Jan D. <ja...@ja...>]

On 04/13/2011 01:40 AM, Christopher Lozinski wrote:
> First thank you for all the excellent discussions about Floating point.
> I am learning rapidly.
>
> I really liked Tom Dillons example of signals being hierarchical.  Take
> the case of the complex number.  It is made up of two floating point
> numbers.  They are made up of a sign bit, mantissa and exponent.
> Data structures of dictionaries are not enough, hierarchies of objects
> are much more flexible.
>
> MyHDL has hierarchy in hardware modules, I guess it also needs them in
> signals.  Then it is easy to explictely operate on a Mantissa.  Or to
> assemble other signals from sub-signals.  Does anyone else have some
> good examples?

Actually I believe there are many good applications for
"hierarchy" in signals, but I don't think this particular
case is one.

Before continuing, let me stress once more a point which
is missed all the time. Everything that is being talked
about, no matter how complex, can being done in MyHDL -
the modeling language today. That is not the problem.

The problem is conversion. We need it for the things
that have to get implemented, but I'm finding it hard.
For other parts in MyHDL, we can reuse the python
interpreter. For conversion, we write a compiler
ourselves. The biggest problem is that for anything
that we want to support, we have to find and implement
a meaningful mapping in a much less capable language
such as Verilog.

Once again: in MyHDL modeling you can do anything you
want. There is nothing that prevents us from experimenting
with the type of interface we would like to have,
and then see if and how we could support it in
the conversion.

> So building floating points in MyHDL is really about managing
> hierarchies of signals.

I don't think so. I think that when we get to the (floating) point,
we will want a native type such as the intbv, that can be used
both as a variable and a signal. In other words, we will
want the "hierarchy" in the type itself, not through
signals.

> Now we get to the vendor libraries.   Wayne wants to connect to the
> Altera libraries.  In a private communication Jan D. checked, and they
> are of course built up of arrays of bits.  Trouble!  No hierarchy
> there.  What do we do?  Well we could do a module that maps from the
> object-model to the vendor model.
> That preserves vendor neutrality, which sounds like a good thing to me.

Yes. We should define our own interface and map it to
other interfaces locally if required.

Now let's get practical. If you think "hierarchy" in types is
a good idea, the problem is not that the altera libraries
don't have it. The problem is that MyHDL *conversion* doesn't
support it at the moment. And before doing so, I would want
to be absolutely sure about what we want - concepts and interfaces
should be proven. Conversion is the trickiest and hardest
part in the project.

So why not start with a workaround? We could define an
interface using a_sign, a_mant, a_exp and b_sign, b_mant, b_exp.
Ok, the interface is flattened, but in the code the only
difference would be the underscore instead of dot notation.
But it would teach us if this type of interface is really
what we want to work with. And it works today. And if conversion ever
gets more powerful, an upgrade may be simple.

> The other solution, I would prefer to find a floating point Verilog
> library that matches our representation.   At least i hope this will be
> our representation.  That allows MyHDL to preserve its flexible in the
> long run.   Better impedance matching.

Verilog doesn't have the slightest support for the kind of
"signal hierarchy" that is being talked about.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] list admin news

[David R. <dav...@gm...>]

Forget about point 2. There is already a background note!!

On Wed, Apr 13, 2011 at 9:26 AM, David Rodríguez <
dav...@gm...> wrote:

> Hi,
>
> First of all, I would like to congratulate Jan for the manual notes at
> myHDL.org. I am still going through the notes. I would like to suggest a
> couple of things:
>
>
>    1. Add numbering to the sections. It will help a lot because cross
>    reference will be made easier. As the manual becomes bigger, it woul be
>    necessary to reference different parts of the manuals
>    2. Add a link or Appendix to explain what decorators, iterators and
>    generators are from pure Pythonic point of view. Everything made sense when
>    I decided to clarify what those objects are
>    3. Create a table of decorators for quick reference.
>    4. Talk more about the object signal. For instance, in the section
>    (Signals, Ports and Concurrency) the example program starts defining a clock
>    (ClkDriver); within the function CLKDriver, clk shows an attribute named
>    clk.next. It makes more sense to me (as a newby) to define clk first,
>    explain that it is a signal with attributes... I have found that not having
>    to define the type of the objects in Python make very hard to fallow a
>    program. Although, I believe this is just due to my lack of experience.
>
> Regards,
> David
>
> On Wed, Apr 13, 2011 at 7:21 AM, Jan Decaluwe <ja...@ja...> wrote:
>
>> On 04/12/2011 09:42 PM, Martín Gaitán wrote:
>> > 2011/4/12 Jan Decaluwe <ja...@ja... <mailto:ja...@ja...
>> >>
>> >
>> >     One definite result of the increased activity
>> >     is a significantly higher rate of unsubscriptions :-)
>> >
>> >
>> > :-(
>>
>> Martin:
>>
>> I wouldn't make to much of it, I meant it more as a joke :-)
>>
>> It is normal that some people loose interest over time, and
>> of course it's only when the activity increases that they
>> get at wake-up call about it :-)
>>
>> > I was thinking about this earlier (when somebody asked for
>> unsubscription) and I'll try to explain it in my rough english
>> >
>> > I think the list is turning very mixed between the business efforts and
>>  the technical support
>> > I was very surprised about how fast people works to get things done and
>> that's pretty cool and, of course.  I'm happy helping the project with my
>> talk but the point is that I'm not really interested in being a "Myhdl's
>> agent".
>> >
>> > Maybe for many subscriptors there is too much "bussines talk" which is
>> very uncommon in a public list of an open source project. More over, if we
>> are expecting new users, it would be a bit annoying for them and feel like
>> they are just the selling target  of courses and boards.
>> >
>> > So, wouldn't be a better idea to have a separated "bussiness" myhdl list
>> ?
>> >
>> > hope you've understood me
>>
>> I think I have.
>>
>> Everything has always two sides. Thanks to the increased
>> activity, many people such as you have expressed their
>> enthousiasm, which is really good to know for all. I
>> believe you have made a potentially interesting contact
>> as a byproduct.
>>
>> I wouldn't want to create separate lists. As far as I'm
>> concerned, we are still at the early stages of a more
>> "structured" effort to move MyHDL ahead and we are
>> experimenting with ideas on how to do that. As you
>> have noticed, the ideas/experiences/suggestions are
>> jumping around very quickly, and we'll see how it
>> crystallizes. For example, what I hope to see when
>> to project accellerates, is increased technical
>> support for the software itself, something which
>> is not being discussed currently.
>>
>> At this point, this is still an effort driven by
>> volunteers. Any positive contribution is welcomed -
>> just keep the positive energy and ingnore what
>> doesn't fit you.
>>
>> Jan
>>
>>
>>
>> --
>> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>>     Python as a HDL: http://www.myhdl.org
>>     VHDL development, the modern way: http://www.sigasi.com
>>     Analog design automation: http://www.mephisto-da.com
>>     World-class digital design: http://www.easics.com
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Forrester Wave Report - Recovery time is now measured in hours and minutes
>> not days. Key insights are discussed in the 2010 Forrester Wave Report as
>> part of an in-depth evaluation of disaster recovery service providers.
>> Forrester found the best-in-class provider in terms of services and
>> vision.
>> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> David Rodríguez Martin
> Cambridge,UK
>



-- 
David Rodríguez Martin
Cambridge,UK

Re: [myhdl-list] list admin news

[David R. <dav...@gm...>]

Hi,

First of all, I would like to congratulate Jan for the manual notes at
myHDL.org. I am still going through the notes. I would like to suggest a
couple of things:


   1. Add numbering to the sections. It will help a lot because cross
   reference will be made easier. As the manual becomes bigger, it woul be
   necessary to reference different parts of the manuals
   2. Add a link or Appendix to explain what decorators, iterators and
   generators are from pure Pythonic point of view. Everything made sense when
   I decided to clarify what those objects are
   3. Create a table of decorators for quick reference.
   4. Talk more about the object signal. For instance, in the section
   (Signals, Ports and Concurrency) the example program starts defining a clock
   (ClkDriver); within the function CLKDriver, clk shows an attribute named
   clk.next. It makes more sense to me (as a newby) to define clk first,
   explain that it is a signal with attributes... I have found that not having
   to define the type of the objects in Python make very hard to fallow a
   program. Although, I believe this is just due to my lack of experience.

Regards,
David

On Wed, Apr 13, 2011 at 7:21 AM, Jan Decaluwe <ja...@ja...> wrote:

> On 04/12/2011 09:42 PM, Martín Gaitán wrote:
> > 2011/4/12 Jan Decaluwe <ja...@ja... <mailto:ja...@ja...
> >>
> >
> >     One definite result of the increased activity
> >     is a significantly higher rate of unsubscriptions :-)
> >
> >
> > :-(
>
> Martin:
>
> I wouldn't make to much of it, I meant it more as a joke :-)
>
> It is normal that some people loose interest over time, and
> of course it's only when the activity increases that they
> get at wake-up call about it :-)
>
> > I was thinking about this earlier (when somebody asked for
> unsubscription) and I'll try to explain it in my rough english
> >
> > I think the list is turning very mixed between the business efforts and
>  the technical support
> > I was very surprised about how fast people works to get things done and
> that's pretty cool and, of course.  I'm happy helping the project with my
> talk but the point is that I'm not really interested in being a "Myhdl's
> agent".
> >
> > Maybe for many subscriptors there is too much "bussines talk" which is
> very uncommon in a public list of an open source project. More over, if we
> are expecting new users, it would be a bit annoying for them and feel like
> they are just the selling target  of courses and boards.
> >
> > So, wouldn't be a better idea to have a separated "bussiness" myhdl list
> ?
> >
> > hope you've understood me
>
> I think I have.
>
> Everything has always two sides. Thanks to the increased
> activity, many people such as you have expressed their
> enthousiasm, which is really good to know for all. I
> believe you have made a potentially interesting contact
> as a byproduct.
>
> I wouldn't want to create separate lists. As far as I'm
> concerned, we are still at the early stages of a more
> "structured" effort to move MyHDL ahead and we are
> experimenting with ideas on how to do that. As you
> have noticed, the ideas/experiences/suggestions are
> jumping around very quickly, and we'll see how it
> crystallizes. For example, what I hope to see when
> to project accellerates, is increased technical
> support for the software itself, something which
> is not being discussed currently.
>
> At this point, this is still an effort driven by
> volunteers. Any positive contribution is welcomed -
> just keep the positive energy and ingnore what
> doesn't fit you.
>
> Jan
>
>
>
> --
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
>     Python as a HDL: http://www.myhdl.org
>     VHDL development, the modern way: http://www.sigasi.com
>     Analog design automation: http://www.mephisto-da.com
>     World-class digital design: http://www.easics.com
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
David Rodríguez Martin
Cambridge,UK

Re: [myhdl-list] New MyHDL Tutorial Available.

[David R. <dav...@gm...>]

Hi,

I'm being "picky" but it will be a good idea to change variable CLK_RATE to
CLK_48Mhz. It makes more sense when reading the code as the LED rate of
change is also named LED_RATE. In doing so, it is easier to understand
things like Nloops=CLK_48Mhz*LED_RATE.

On Wed, Apr 13, 2011 at 4:00 AM, Christopher Felton
<chr...@gm...>wrote:

> <snip>
> >
> > I have done an initial review. This is only about the .py source
> > file. As mentioned before, the indentation in the tutorial
> > text itself has to be cleaned up to make the code readable.
> >
> > 1) good idea to add educational info in comments.
> >
> > There are a number of small typo's - I prefer to fix them directly
> > instead of reporting them, when there's an agreed way to edit.
>
> The code can be retrieved from :
> hg clone https://bitbucket.org/dsptronics/myhdl_tutorials
>
> I know we wanted to keep everything in one spot but I didn't want to
> loose momentum.  I have no preference where the code is located.  If we
> want it some where else I can destroy this repo.  But for now this will
> allow multiple edits of the code.
>
> >
> > Instead of 'iterators' I would talk about 'generators' - technically
> > more accurate. I wouldn't use the terminology 'behavioral statements'.
> > I would talk about the "code within generators" instead.
> > Probably we cannot avoid explaining what "generators" are early on.
> > These are functions preceded by an @always, @always_comb
> > or @initial decorator. In a MyHDL model, they are the primary
> > units of concurrent behavior.
>
> Yes, thanks this was a goof by me, I have fixed the comments to say
> generators.  I haven't added more "educational" text, yet.
>
> >
> > I wouldn't mention 'return instances()' - I consider it advanced
> > knowledge. For newbies, I think it's too much magic, and potentially
> > confusing. (I never use it and sometimes regret to have added it :-))
>
> removed, doh I guess I am lazy, I use it often :)
>
> >
> > 2) conversion files
> >
> > To customize the default output file names, you can also set
> > toVerilog.name / toVHDL.name. This would be a gentle
> > introduction to the conversion function attributes that
> > can be used to customize the output, e.g. to have
> > a different header than the default. Otherwise, users may
> > start using text manipulation operations to do such things.
>
> Nice!!  How quickly I forget these things after reading them.
>
> >
> > 3) (minor issue) Why upper case for ports? This is the same
> > convention as for constants, but perhaps this has to do with
> > fpga sofware conventions for ports?
>
> Dunno, good or bad habit.  I think it is common on FPGAs that I have
> worked on, just adopted it unconsciously.  I think I have even done this
> in the couple ASICs I have done.   I changed it for this example.  Will
> review the Python coding standard (PEP??) for other coding styles.
>
> .chris
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
David Rodríguez Martin
Cambridge,UK

Re: [myhdl-list] list admin news

[Jan D. <ja...@ja...>]

On 04/12/2011 09:42 PM, Martín Gaitán wrote:
> 2011/4/12 Jan Decaluwe <ja...@ja... <mailto:ja...@ja...>>
>
>     One definite result of the increased activity
>     is a significantly higher rate of unsubscriptions :-)
>
>
> :-(

Martin:

I wouldn't make to much of it, I meant it more as a joke :-)

It is normal that some people loose interest over time, and
of course it's only when the activity increases that they
get at wake-up call about it :-)

> I was thinking about this earlier (when somebody asked for unsubscription) and I'll try to explain it in my rough english
>
> I think the list is turning very mixed between the business efforts and  the technical support
> I was very surprised about how fast people works to get things done and that's pretty cool and, of course.  I'm happy helping the project with my talk but the point is that I'm not really interested in being a "Myhdl's agent".
>
> Maybe for many subscriptors there is too much "bussines talk" which is very uncommon in a public list of an open source project. More over, if we are expecting new users, it would be a bit annoying for them and feel like they are just the selling target  of courses and boards.
>
> So, wouldn't be a better idea to have a separated "bussiness" myhdl list ?
>
> hope you've understood me

I think I have.

Everything has always two sides. Thanks to the increased
activity, many people such as you have expressed their
enthousiasm, which is really good to know for all. I
believe you have made a potentially interesting contact
as a byproduct.

I wouldn't want to create separate lists. As far as I'm
concerned, we are still at the early stages of a more
"structured" effort to move MyHDL ahead and we are
experimenting with ideas on how to do that. As you
have noticed, the ideas/experiences/suggestions are
jumping around very quickly, and we'll see how it
crystallizes. For example, what I hope to see when
to project accellerates, is increased technical
support for the software itself, something which
is not being discussed currently.

At this point, this is still an effort driven by
volunteers. Any positive contribution is welcomed -
just keep the positive energy and ingnore what
doesn't fit you.

Jan



-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] New MyHDL Tutorial Available.

[Christopher F. <chr...@gm...>]

<snip>
>
> I have done an initial review. This is only about the .py source
> file. As mentioned before, the indentation in the tutorial
> text itself has to be cleaned up to make the code readable.
>
> 1) good idea to add educational info in comments.
>
> There are a number of small typo's - I prefer to fix them directly
> instead of reporting them, when there's an agreed way to edit.

The code can be retrieved from :
hg clone https://bitbucket.org/dsptronics/myhdl_tutorials

I know we wanted to keep everything in one spot but I didn't want to 
loose momentum.  I have no preference where the code is located.  If we 
want it some where else I can destroy this repo.  But for now this will 
allow multiple edits of the code.

>
> Instead of 'iterators' I would talk about 'generators' - technically
> more accurate. I wouldn't use the terminology 'behavioral statements'.
> I would talk about the "code within generators" instead.
> Probably we cannot avoid explaining what "generators" are early on.
> These are functions preceded by an @always, @always_comb
> or @initial decorator. In a MyHDL model, they are the primary
> units of concurrent behavior.

Yes, thanks this was a goof by me, I have fixed the comments to say 
generators.  I haven't added more "educational" text, yet.

>
> I wouldn't mention 'return instances()' - I consider it advanced
> knowledge. For newbies, I think it's too much magic, and potentially
> confusing. (I never use it and sometimes regret to have added it :-))

removed, doh I guess I am lazy, I use it often :)

>
> 2) conversion files
>
> To customize the default output file names, you can also set
> toVerilog.name / toVHDL.name. This would be a gentle
> introduction to the conversion function attributes that
> can be used to customize the output, e.g. to have
> a different header than the default. Otherwise, users may
> start using text manipulation operations to do such things.

Nice!!  How quickly I forget these things after reading them.

>
> 3) (minor issue) Why upper case for ports? This is the same
> convention as for constants, but perhaps this has to do with
> fpga sofware conventions for ports?

Dunno, good or bad habit.  I think it is common on FPGAs that I have 
worked on, just adopted it unconsciously.  I think I have even done this 
in the couple ASICs I have done.   I changed it for this example.  Will 
review the Python coding standard (PEP??) for other coding styles.

.chris

Re: [myhdl-list] Cordoba Booth

[Christopher F. <chr...@gm...>]

I made the changes really quick, it looks ok.

http://www.myhdl.org/lib/exe/fetch.php/users:cfelton:fpgacamp:myhdl_fpgacamp_v4_a0.pdf


On 4/12/11 5:21 PM, Jan Langer wrote:
> Hi,
> there has been a problem with the poster at the SPL conference in
> Cordoba. Our poster is landscape format and they need a portrait A0
> format poster. Alternatively we can downscale the poster for about
> 30cm, but that would make some of the plots unreadable. I do have only
> a pdf version of the poster. Maybe someone can edit the poster for
> landscape A0 format. The printing has cost 6 euros yesterday. Maybe I
> can organize another print today.
> Thanks,
> Jan L.
>
>
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo

Re: [myhdl-list] Floating Point Libraries

[Christopher L. <loz...@fr...>]

First thank you for all the excellent discussions about Floating point.  
I am learning rapidly.

I really liked Tom Dillons example of signals being hierarchical.  Take 
the case of the complex number.  It is made up of two floating point 
numbers.  They are made up of a sign bit, mantissa and exponent.
Data structures of dictionaries are not enough, hierarchies of objects 
are much more flexible.

MyHDL has hierarchy in hardware modules, I guess it also needs them in 
signals.  Then it is easy to explictely operate on a Mantissa.  Or to 
assemble other signals from sub-signals.  Does anyone else have some 
good examples?

So building floating points in MyHDL is really about managing 
hierarchies of signals.

Now we get to the vendor libraries.   Wayne wants to connect to the 
Altera libraries.  In a private communication Jan D. checked, and they 
are of course built up of arrays of bits.  Trouble!  No hierarchy 
there.  What do we do?  Well we could do a module that maps from the 
object-model to the vendor model.
That preserves vendor neutrality, which sounds like a good thing to me.

The other solution, I would prefer to find a floating point Verilog 
library that matches our representation.   At least i hope this will be 
our representation.  That allows MyHDL to preserve its flexible in the 
long run.   Better impedance matching.

So we get to a MyHDL module.  It has these hierarchical signals in and 
out.   That should be quite manageable.     Maybe it will be even easier 
to code the internal logic given the structured inputs rather than just 
trying to operate on a vector of bits.

What else would I like to see?  I would love to see the modules 
operating on hierarchical inputs in one of two fashions.  For speed, I 
want them to call the python * operator on the top level values of the 
objects.  For detailed accuracy, I want them to operate on the signals 
represented as bit vectors.

And yes I did miss that the modules need to represent clock cycles per 
instruction and pipelining, and error flags.

I understand that I am new to all of this.  So what am I missing?

As for upgrading my wiki web servers, I am working on it.  It is always 
more complex than expected.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Cordoba Booth

[Jan L. <ja...@la...>]

Hi,
there has been a problem with the poster at the SPL conference in  
Cordoba. Our poster is landscape format and they need a portrait A0  
format poster. Alternatively we can downscale the poster for about  
30cm, but that would make some of the plots unreadable. I do have only  
a pdf version of the poster. Maybe someone can edit the poster for  
landscape A0 format. The printing has cost 6 euros yesterday. Maybe I  
can organize another print today.
Thanks,
Jan L.

Re: [myhdl-list] New MyHDL Tutorial Available.

[Jan D. <ja...@ja...>]

On 04/11/2011 04:10 AM, Christopher Lozinski wrote:
> I am pleased to announce a MyHDL tutorial at
> http://MyHDLClass.com
>
> Thank you Christopher Felton for all the hard work, and more importantly
> for getting it done so quickly.
>
> I think that this demonstrates that MyHDL is evolving very rapidly.  The
> conference was over just 4 days ago.  Just watch!
>
> We invite you to read and download the material, and go buy a board.
> http://www.dsptronics.com/
>
> There are some other boards that people have committed to supporting
> shortly.
>
> I particularly invite you to edit the course material.  If we all make a
> few edits, in no time at all, there will be a rich deep and wonderful
> course.

I have done an initial review. This is only about the .py source
file. As mentioned before, the indentation in the tutorial
text itself has to be cleaned up to make the code readable.

1) good idea to add educational info in comments.

There are a number of small typo's - I prefer to fix them directly
instead of reporting them, when there's an agreed way to edit.

Instead of 'iterators' I would talk about 'generators' - technically
more accurate. I wouldn't use the terminology 'behavioral statements'.
I would talk about the "code within generators" instead.
Probably we cannot avoid explaining what "generators" are early on.
These are functions preceded by an @always, @always_comb
or @initial decorator. In a MyHDL model, they are the primary
units of concurrent behavior.

I wouldn't mention 'return instances()' - I consider it advanced
knowledge. For newbies, I think it's too much magic, and potentially
confusing. (I never use it and sometimes regret to have added it :-))

2) conversion files

To customize the default output file names, you can also set
toVerilog.name / toVHDL.name. This would be a gentle
introduction to the conversion function attributes that
can be used to customize the output, e.g. to have
a different header than the default. Otherwise, users may
start using text manipulation operations to do such things.

3) (minor issue) Why upper case for ports? This is the same
convention as for constants, but perhaps this has to do with
fpga sofware conventions for ports?

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] list admin news

[Martín G. <ga...@gm...>]

2011/4/12 Jan Decaluwe <ja...@ja...>

> One definite result of the increased activity
> is a significantly higher rate of unsubscriptions :-)
>
>
:-(

I was thinking about this earlier (when somebody asked for unsubscription)
and I'll try to explain it in my rough english

I think the list is turning very mixed between the business efforts and  the
technical support
I was very surprised about how fast people works to get things done and
that's pretty cool and, of course.  I'm happy helping the project with my
talk but the point is that I'm not really interested in being a "Myhdl's
agent".

Maybe for many subscriptors there is too much "bussines talk" which is very
uncommon in a public list of an open source project. More over, if we are
expecting new users, it would be a bit annoying for them and feel like they
are just the selling target  of courses and boards.

So, wouldn't be a better idea to have a separated  "bussiness" myhdl list ?

hope you've understood me

cheers.

Re: [myhdl-list] Cordoba Booth

[Jose I. V. <jo...@dt...>]

Hi!
I'm sorry, but this evening I have to prepair the presentation for tomorrow.
I still don't even have the slides ready...
Maybe we can meet tomorrow or on Thursday?

About the attendance to the presentation, I'm not involved on the organizing
commitee, but if it's on my hand I'll manage to try them to allow you to
attend.

Kind regards,
Jose.




José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64



On Tue, Apr 12, 2011 at 8:38 PM, Jan Langer
<jan...@et...>wrote:

> Hi jose ignacio,
> I will be at the registration later today and talk to one of the organizers
> about the poster.
> Maybe you are there?
> Anyway i will write another email about the outcome later.
> Jan
>
> *Durch MOTOBLUR™ verbunden*
>
>
> -----Ursprüngliche Nachricht-----
>
> *Von: *"Martín Gaitán" <ga...@gm...>*
> An: *General discussions on MyHDL <myh...@li...>*
> Gesendet: *Di, 12 Apr 2011, 11:08:19 GMT-03:00*
> Betreff: *Re: [myhdl-list] Cordoba Booth
>
>

Re: [myhdl-list] Boards

[Christopher F. <chr...@gm...>]

On Tue, Apr 12, 2011 at 1:56 AM, Karl Kaiser <kk...@be...> wrote:

> Just a clarification on the DE2 boards. According to Altera's web site
> http://www.altera.com/education/univ/materials/boards/de2/unv-de2-board.htmlthe boards start around $500 or $270 for academics.
>
> BTW: DE2 is a really great board for classes and demos.
>


I am completely biased here but I disagree that the DE2 is a "great" board
for classes and demos, I think it is just ok.  Having taught classes I have
worked with a bunch of different boards.  We have used DE2 and similar
boards (and I have a couple).  For students starting out they like the large
buttons buttons and displays.  But after they blink some lights then the
boards aren't used for much.

I know the board has tons of peripherals but even the larger student
projects not many students finished projects with boards like the DE2, which
inspired me to help DSPtronics generate their board.  The DSPtronics board
is small in size and helps students stay focused.  It is this in-between
board, not too simple, but too complicated either.

Boards like the DSPtronics signa-x fills an intermediate step.  After the
blinking lights demos students can continue interfacing with the real
world.  From my experience I have seen this much more effective, and it
holds students interest much longer.  They can simply interface the board to
the PC with the USB.  And the boards size and cost lets student easily
integrate into a project.  The larger size of the DE2 makes it difficult.

I realize the DE2 has some of the features mentioned as well.  But either
all the interfaces need to be generated or the students were unable to find
the support for the interfaces.  Also note, there are 3 versions of the DE2
board.  We might not be thinking about the same boards.

Chris Felton


>
> --Karl
>
>
> On Mon, Apr 11, 2011 at 1:22 PM, Christopher Lozinski <
> loz...@sp...> wrote:
>
>> I spoke to Christopher Felton, he has 2 DSPTronics boards in inventory,
>> and an unsupported prototype board he could sell to a poor person for
>> less money. He sent one to England, but reportedly that has not arrived.
>>   His boards go for $200 or $230.
>>
>> I spoke to his manufacturer, they are producing 5 more boards.  So I am
>> confident in a supply of Xilinx boards.
>>
>> I had a long talk with Wayne Radohonski this morning.  He has committed
>> to supporting the
>> Altera Terasic DE2 board.   They are more expensive boards, he said
>> thousands of dollars.
>> We talked extensively about integrating MyHDL with the large stack of
>> proprietary libraries from Altera.
>>
>> Andrew Stone committed to supporting the entry-level Lattice board, and
>> Chris Felton offered to support that effort.  In fact Chris went ahead
>> and ordered that board for himself.
>>
>> Hope that helps.  Let me know if I missed anything.
>>
>> --
>> Regards
>> Christopher Lozinski
>>
>> Check out my iPhone apps TextFaster and EmailFaster
>> http://textfaster.com
>>
>> Expect a paradigm shift.
>> http://MyHDL.org
>>
>>
>>
>> ------------------------------------------------------------------------------
>> Forrester Wave Report - Recovery time is now measured in hours and minutes
>> not days. Key insights are discussed in the 2010 Forrester Wave Report as
>> part of an in-depth evaluation of disaster recovery service providers.
>> Forrester found the best-in-class provider in terms of services and
>> vision.
>> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
>> _______________________________________________
>> myhdl-list mailing list
>> myh...@li...
>> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>>
>
>
>
> --
> Best regards,
>
> Karl Kaiser | 408 306 1755
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

[myhdl-list] list admin news

[Jan D. <ja...@ja...>]

One definite result of the increased activity
is a significantly higher rate of unsubscriptions :-)

(Note that there's actually no need to subscribe/unsubscribe
to the mailing list, if you access as a newsgroup.)

One more thing: some of you submit posts with
large attachments - if it's higher than 400K it
requires admin (my) permission which can be delayed.
So it may seem "not to work". So think twice
before adding large attachments, the website
may be a better choice.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Floating Point Libraries

[Tom D. <td...@di...>]

see below:

> How did you handled the RTL in a class?  For example, if you have
>
> class FloatingPoint(object):
>      ...
>      def Model(self):
>           ...
>
>      def RTL(self):
>           ...
>
>           return instances()
>
> When I have done this like the above example, the conversion fails
> because it uses self as one of the ports?  My RTL ends up being a
> separate function outside of the class.

You are right about that. In your example if the FloatingPoint.RTL()  
was to be the top level, you would have to add a wrapper level that just 
had the I/O.

>
>> float0 = {'sign':Signal(bool(0)), 'exp':Signal(0), 'man':Signal(0)}
> This would probably fall under a general "structure" usage in MyHDL.
> Today modeling supports this.  A potentially straight-forward approach
> for conversion, might be, let the converter expand the names, e.g. the
> converted HDL could be float0_sign, float0_exp, float0_man in
> Verilog/VHDL.
>
> But I imagine this would be a considerable effort to test and implement.
>    The MyHDL analyzer would need to identify things like classes and
> dicts and drill down till it finds a Signal type and generate the
> primitive name.  I think there are a lot of error cases and special
> cases.  This topic has come up a couple times on the wiki.  I think it
> is a good idea to support a class of signals and dict.  This might be a
> good starting point for a floating-point implementation.  I don't know
> if anyone is available to propose, create a test plan, and implement.
>

I like the idea of letting the user make a class for the group of 
signals with a requirement that they provide MyHDL the information 
needed to simply handle the things like top level I/O.  Not sure if that 
is even possible, but...

>> Right now, I don't think you can use a list of signals or a dict of
>> signals as I/O so you would have to cat together the sign, mantissa and
>> exponent at the top level. It would be nice if MyHDL would do this for
>> other cases to, like complex numbers.
> A list of signals can be used but it has to be homogeneous, all the
> signals in the list have to be the same type.  The list of signals (LOS)
> will be converted to array types in Verilog and VHDL.

That is good to know, I forgot about that.

Re: [myhdl-list] Cordoba Booth

[Christopher L. <loz...@fr...>]

My advice on Cordoba

I learned a few things when exhibiting at the FPGACentral conference.

Here is my advice.

There are several things you are trying to do.  One is build brand 
awareness.  The lecture, and the poster session are all great.  If you 
hand out flyers in front of the poster, and also at the lecture, people 
get more information.  That is all good.   In the long run it will 
attract people.   I think it is really good to have people at the door 
of the lecture, handing out flyers, as many as possible, to show a 
strong support group.

But I also really like Karl Kaiser's advice: "one Engineer at a time".  
Most people will be just curious, a few will look like they are really 
interested, and might use it.  Ask them for their business card.  Offer 
to mentor them.  We are in good shape.  There is a shipping supported 
board.  There is a tutorial.  MyHDL is now real.   What they need is to 
be invited, to be welcomed, to have a person they can call if they have 
questions, and are embarrassed to post to the mailing list.

If you get their business card, then call them in a week.  Ask them if 
they downloaded it.  Ask them if they ordered the board.  Just help make 
it happen.

Take some photographs of the poster and lecture.  I did.  I will post 
them when I get around to it.

And the other piece, is that you will get a lot of engineers with blank 
stares.  Try to get a photo or two of this if you can.  The way to 
connect to them, is to ask if this is difficult to put in context.  The 
blank stares are because it makes no sense.  Let them know that there is 
a paradigm shift happening.  How do you tell it is a paradigm shift, 
because the language we use, is different from the language they use.   
We talk about class libraries, and object models, they talk about 
design, simulations, verification.   Tell them that this is the 
direction the design world is going, and that they need to be educated 
about this.  That MyHDL is not just about designing circuits.  They may 
not want to use it for that.  It is also about educating them about the 
paradigm shift, so that they can understand what this is all about.   
Everyone wants to be educated and understand.

Oh and if they ask you about C language tools, tell them the language 
does not really matter.  What matters are the concepts.  Python supports 
object-oriented models, so that you get different concepts than you do 
with traditional C language functional decomposition approaches.

Hope that helps.

The other thing we should do, is to offer a class in Cordoba about a 
month after the conference.   Assuming enough people sign up.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Floating Point Libraries

[Christopher F. <chr...@gm...>]

<snip>
>
> The way I have done this and I think is best, is to make a class that
> would contain the model and logic. You always want a bit accurate model.
> In this case if your logic matches true floating point it could be just
> two python floats as in a * b. But you may end up making some
> compromises for logic usage or speed sake that make your math slightly
> different than the IEEE standard, you would then have a model to match it.

How did you handled the RTL in a class?  For example, if you have

class FloatingPoint(object):
    ...
    def Model(self):
         ...

    def RTL(self):
         ...

         return instances()

When I have done this like the above example, the conversion fails 
because it uses self as one of the ports?  My RTL ends up being a 
separate function outside of the class.

>
> I too started thinking that it would be nice to use an operator and then
> just change the operand types to switch to making logic. This works
> great when only modeling and I do that all the time. Say changing from
> floating point to fixed point or changing the width of the fixed point
> data. But when it come to generating the logic a function call returning
> an instance is much better in MyHDL. You can make the same function call
> easily work for any data types, that is just easy with python.
>
> I don't think you need a new signal type. I would prefer something like
> a dictionary of signals that MyHDL would allow to be I/O of a top level
> module. For the floating point case, something like:
>
> float0 = {'sign':Signal(bool(0)), 'exp':Signal(0), 'man':Signal(0)}

This would probably fall under a general "structure" usage in MyHDL. 
Today modeling supports this.  A potentially straight-forward approach 
for conversion, might be, let the converter expand the names, e.g. the 
converted HDL could be float0_sign, float0_exp, float0_man in 
Verilog/VHDL.

But I imagine this would be a considerable effort to test and implement. 
  The MyHDL analyzer would need to identify things like classes and 
dicts and drill down till it finds a Signal type and generate the 
primitive name.  I think there are a lot of error cases and special 
cases.  This topic has come up a couple times on the wiki.  I think it 
is a good idea to support a class of signals and dict.  This might be a 
good starting point for a floating-point implementation.  I don't know 
if anyone is available to propose, create a test plan, and implement.

>
> Right now, I don't think you can use a list of signals or a dict of
> signals as I/O so you would have to cat together the sign, mantissa and
> exponent at the top level. It would be nice if MyHDL would do this for
> other cases to, like complex numbers.

A list of signals can be used but it has to be homogeneous, all the 
signals in the list have to be the same type.  The list of signals (LOS) 
will be converted to array types in Verilog and VHDL.

>
> An even better way might be to allow a class that would have methods to
> tell MyHDL what to do for I/O. Like the cat and uncat that will have to
> done often. That actually sounds better to me.
>
> On the Altera topic, there is no reason that floating point operators
> can't be coded in a generic sense and any synthesis tool will take care
> of the rest. The only time would be if you wanted to make a call to an
> Altera floating point IP module. But synthesis would not care about that
> and you could easily do that in your function call that implemented the
> floating point multiply.
>
> Anyhow, MyHDL is a great tool for something like floating point
> operators and I will try to kick in some ideas if asked.
>
> Good luck.
>
>

Thanks for the input!

<snip>

Re: [myhdl-list] Floating Point Libraries

[Tom D. <td...@di...>]

Hi,

I  thought I would throw in my two cents worth on the floating point 
discussion.

I don't think the best way is to infer say a floating point mult from 
the * operator. Instead you will want a function call that returns an 
instance.

It only really works in a pure modeling sense to use an operator. Once 
you need clock, reset, and other connection information, you really need 
to pass those. Also, you will likely want to pass parameter type 
information, like the number of pipeline stages and other special 
behavior information.

The way I have done this and I think is best, is to make a class that 
would contain the model and logic. You always want a bit accurate model. 
In this case if your logic matches true floating point it could be just 
two python floats as in a * b. But you may end up making some 
compromises for logic usage or speed sake that make your math slightly 
different than the IEEE standard, you would then have a model to match it.

I too started thinking that it would be nice to use an operator and then 
just change the operand types to switch to making logic. This works 
great when only modeling and I do that all the time. Say changing from 
floating point to fixed point or changing the width of the fixed point 
data. But when it come to generating the logic a function call returning 
an instance is much better in MyHDL. You can make the same function call 
easily work for any data types, that is just easy with python.

I don't think you need a new signal type. I would prefer something like 
a dictionary of signals that MyHDL would allow to be I/O of a top level 
module. For the floating point case, something like:

float0 = {'sign':Signal(bool(0)), 'exp':Signal(0), 'man':Signal(0)}

Right now, I don't think you can use a list of signals or a dict of 
signals as I/O so you would have to cat together the sign, mantissa and 
exponent at the top level.  It would be nice if MyHDL would do this for 
other cases to, like complex numbers.

An even better way might be to allow a class that would have methods to 
tell MyHDL what to do for I/O. Like the cat and uncat that will have to 
done often. That actually sounds better to me.

On the Altera topic, there is no reason that floating point operators 
can't be coded in a generic sense and any synthesis tool will take care 
of the rest. The only time would be if you wanted to make a call to an 
Altera floating point IP module. But synthesis would not care about that 
and you could easily do that in your function call that implemented the 
floating point multiply.

Anyhow, MyHDL is a great tool for something like floating point 
operators and I will try to kick in some ideas if asked.

Good luck.



On 04/12/2011 07:52 AM, Jan Decaluwe wrote:
> On 04/11/2011 10:35 PM, Christopher Lozinski wrote:
>> Christopher Felton and I have been having a discussion about libraries.
>> I am moving it to the mailing list, because I think many people would be
>> interested.
>>
>> We have been talking about how to represent floating point in MyHDL, and
>> how to work with it in Verilog.  Basically the plan is to implement a
>> multiply in MyHDL as a python * operator.   Then export it by calling
>> some library.  The question is which library.
> I assume you mean inferring a floating point mult from '*'. Assuming
> we are talking about RTL coding and synthesis, I don't see how that
> would work, as I expect such a block to have clock cycle latency.
>
>> So Wayne  Radohonski is quite committed to supporting his Altera board.
>>
>> The libraries he wants to use are the Altera libraries.  Phase lock
>> loop, and then floating point multiply.
>> His point is that building phase lock loops is even more important than
>> the floating point multiplier.
>>
>> Both because supporting an Altera board is important, and because of the
>> policy of one engineer at a time, I want to support the boards Wayne
>> wants in this endeavor.  So the plan is to create two MyHDL classes, one
>> for a floating point signal, and one for a floating point multiplier.
> There should not be a need to define a new Signal class. It is intended
> to work with any underlying type. Of course, there may be a need to
> define such types.
>
>> When exporting it will generate the right Verilog code to call the
>> Altera libraries.  Later it will call other libraries.  One at a time.
>>
>> How does that sound?
> That depends. If you mean inference, I don't immediately see how
> this would work as explained earlier.
>
> If you mean instantiation, there is a good and a bad way, as I
> explained recently in my reply to Angel Ezquerra.
>
> The bad way is to look into the Altera catalog and redo that
> same interface in MyHDL. Now you can use their core "direcly"
> but all your other code will be infected, even if doesn't
> contain technology-dependent code itself. Supporting
> others targets later with the same code has become impossible.
>
> The good way is to define the interface that you would like to use
> in your RTL, taking into account RTL characterstics of course.
> For example, I guess you will want to add a simple
> start/ready protocol. And you will have to define how to
> map floating point numbers to RTL-friendly types.
> I looked at the altera way, I don't think I would like
> to do it like that.
>
> Then define an extensive test suite, including boundary
> conditions, that specify and test the behavior of your
> new core - in one pass demonstrating to people like Andrew Lentvorski
> how we do things differently over here. Your new core
> has empty placeholder code and all tests will (should) fail.
>
> Then start implementing a generic RTL implementation.
> Here you can e.g. use '*' to infer integer multipliers.
> It will not necessarily be hard. Your tests will start
> working.
>
> When all tests work, you are done. Now you have a floating
> point core that will work on any target, but not necessarily
> in the most efficient way. So now is the time for
> optimization.
>
> If you are interested in altera,
> you now look into the altera catalog to see how you can use
> their cores, and perhaps some additional logic, for a
> more efficient implementation. You add a parameter to
> specify targets, and you can use the verilog/vhdl hooks
> to add parameterizable verilog/vhdl instantiations.
>
> All of this works perfectly with MyHDL as it stands today.
>
> Jan
>

Re: [myhdl-list] Cordoba Booth

[Martín G. <ga...@gm...>]

2011/4/12 Jose Ignacio Villar <jo...@dt...>

> Hi all,
> sorry for being  out of touch with the list for the last two weeks.
> I'm who is going to present the paper about MyHDL and I'm glad to see that
> it has generated some expectation, now I know I'm not the only fan of MyHDL
> at SPL 2011 :)
>
> I've read that there is going to be a poster presentation during the
> conference and a booth in the next weeks. If I can help you with anything,
> just let me know. I would like to meet other list members in person. I'm
> already at Cordoba and will depart on saturday morning.
>

Hi Ignacio.

I'm Martin from Córdoba. I really would like yo attend your presentation
tomorrow but I asked a teacher about get attendee permission to that
specific presentation and the answer was "we'll see". Do you think you could
help me?

Btw, yesterday I met Jan Larger who is also at Córdoba participating at SPL
conference. We drinked a few "mates" and printed the Myhdl's poster
yesterday (was cheaper than we thought) . Jan gives the poster today to the
organizers and maybe we get together to "answer" (really I just could tell
my little experience) questions at the poster show (I'm not sure when it
is).
Of course, you could join us and maybe take some beers enjoying Córdoba.

Re: [myhdl-list] Cordoba Booth

[Jose I. V. <jo...@dt...>]

Hi all,
sorry for being  out of touch with the list for the last two weeks.
I'm who is going to present the paper about MyHDL and I'm glad to see that
it has generated some expectation, now I know I'm not the only fan of MyHDL
at SPL 2011 :)

I've read that there is going to be a poster presentation during the
conference and a booth in the next weeks. If I can help you with anything,
just let me know. I would like to meet other list members in person. I'm
already at Cordoba and will depart on saturday morning.

Kind regards!
Jose Ignacio Vilar

José Ignacio Villar <jo...@dt...>
Departamento de Tecnología Electrónica
Escuela Técnica Superior de Ingeniería Informática
Universidad de Sevilla
Avda. Reina Mercedes, s/n
41012 - Sevilla (Spain)

Tlf: 954 55 99 62
Fax: 954 55 27 64



On Sat, Apr 9, 2011 at 5:59 PM, Martín Gaitán <ga...@gm...> wrote:

> 2011/4/9 Christopher Lozinski <loz...@fr...>
>
>> Jan Langer has offered to help man a booth at the Cordoba trade show.
>>
>> Could someone who writes Spanish well please inquire about an open
>> source booth for MyHDL?
>>
>> Would anyone else like to help run the booth?  Jan does not speak Spanish.
>>
>> We have flyers here.  We can do an improved version.  Would anyone be
>> willing to translate them into Spanish?
>>
>> Should we print a Spanish language banner?  First let us find out if we
>> can get a booth.
>>
>
>
> Of course I could help, but I have no idea how to inquire a booth and if
> there is time to do that. Should I contact organizers ?
>
> I also could translate what be needed (my English isn't so good -- sorry
> --, but I could write in Spanish well)  but I think due this conference is
> international it's a better idea to keep flyers and banners in english.
>
> BTW,  what about the people who presents the paper about MyHDL ? Does
> somebody knows them? And is the paper available somewhere?
>
>
>
>
> ------------------------------------------------------------------------------
> Xperia(TM) PLAY
> It's a major breakthrough. An authentic gaming
> smartphone on the nation's most reliable network.
> And it wants your games.
> http://p.sf.net/sfu/verizon-sfdev
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>

Re: [myhdl-list] Floating Point Libraries

[Jan D. <ja...@ja...>]

On 04/11/2011 10:35 PM, Christopher Lozinski wrote:
> Christopher Felton and I have been having a discussion about libraries.
> I am moving it to the mailing list, because I think many people would be
> interested.
>
> We have been talking about how to represent floating point in MyHDL, and
> how to work with it in Verilog.  Basically the plan is to implement a
> multiply in MyHDL as a python * operator.   Then export it by calling
> some library.  The question is which library.

I assume you mean inferring a floating point mult from '*'. Assuming
we are talking about RTL coding and synthesis, I don't see how that
would work, as I expect such a block to have clock cycle latency.

> So Wayne  Radohonski is quite committed to supporting his Altera board.
>
> The libraries he wants to use are the Altera libraries.  Phase lock
> loop, and then floating point multiply.
> His point is that building phase lock loops is even more important than
> the floating point multiplier.
>
> Both because supporting an Altera board is important, and because of the
> policy of one engineer at a time, I want to support the boards Wayne
> wants in this endeavor.  So the plan is to create two MyHDL classes, one
> for a floating point signal, and one for a floating point multiplier.

There should not be a need to define a new Signal class. It is intended
to work with any underlying type. Of course, there may be a need to
define such types.

> When exporting it will generate the right Verilog code to call the
> Altera libraries.  Later it will call other libraries.  One at a time.
>
> How does that sound?

That depends. If you mean inference, I don't immediately see how
this would work as explained earlier.

If you mean instantiation, there is a good and a bad way, as I
explained recently in my reply to Angel Ezquerra.

The bad way is to look into the Altera catalog and redo that
same interface in MyHDL. Now you can use their core "direcly"
but all your other code will be infected, even if doesn't
contain technology-dependent code itself. Supporting
others targets later with the same code has become impossible.

The good way is to define the interface that you would like to use
in your RTL, taking into account RTL characterstics of course.
For example, I guess you will want to add a simple
start/ready protocol. And you will have to define how to
map floating point numbers to RTL-friendly types.
I looked at the altera way, I don't think I would like
to do it like that.

Then define an extensive test suite, including boundary
conditions, that specify and test the behavior of your
new core - in one pass demonstrating to people like Andrew Lentvorski
how we do things differently over here. Your new core
has empty placeholder code and all tests will (should) fail.

Then start implementing a generic RTL implementation.
Here you can e.g. use '*' to infer integer multipliers.
It will not necessarily be hard. Your tests will start
working.

When all tests work, you are done. Now you have a floating
point core that will work on any target, but not necessarily
in the most efficient way. So now is the time for
optimization.

If you are interested in altera,
you now look into the altera catalog to see how you can use
their cores, and perhaps some additional logic, for a
more efficient implementation. You add a parameter to
specify targets, and you can use the verilog/vhdl hooks
to add parameterizable verilog/vhdl instantiations.

All of this works perfectly with MyHDL as it stands today.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] wrap function

[Christopher F. <chr...@gm...>]

On 4/12/11 7:11 AM, Thomas Heller wrote:
> Am 12.04.2011 13:52, schrieb Christopher Felton:
>> I created a small write-up here,
>> http://www.myhdl.org/doku.php/user:cfelton:projects:wrap, for a proposed
>> intbv.wrap() function.
>>
>> I wrote this quick and probably needs a second look.  I will look at the
>> implementation details later.
>
> Hm, if we have a wrap() function, why not add a saturated() function
> additionally?  Saturated arithmetic sounds like a useful feature,
> sometimes...
>

I will start with the wrap.  My rational for not adding the saturate() 
is that the saturate adds some additional logic, although small, it 
would require additional logic.  Where as, the bound checking and wrap() 
work in the realm of a binary words behaviors.

Chris Felton

> Thomas
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo

Re: [myhdl-list] spislave code

[Jan D. <ja...@ja...>]

http://www.myhdl.org/doc/current/whatsnew/0.6.html#decorator-usage


On 04/12/2011 01:00 PM, Thomas Heller wrote:
> I found some confusing behaviour when I tried he code published
> in this article: http://www.linuxjournal.com/node/7542/print
> (The article is the first link that google finds when searching
> for "myhdl spislave").
>
> Apparently myhdl isn't able to handle this code:
>
> def SPISlave(miso, mosi, sclk, ss_n,
>                txdata, txrdy, rxdata, rxrdy,
>                rst_n, n=8):
>       ...
>       def RX():
>           ...
>
>       def TX():
>           ...
>       return RX(), TX()
>
> when it is instantiated with traceSignals:
>
>       SPISlave_inst = traceSignals(SPISlave,
>           miso, mosi, sclk, ss_n,
>           txdata, txrdy, rxdata, rxrdy, rst_n, n=n)
>
> However, using it in this way works fine:
>
>       SPISlave_inst = SPISlave(
>           miso, mosi, sclk, ss_n,
>           txdata, txrdy, rxdata, rxrdy, rst_n, n=n)
>
> Is this a bug?
>
> The code works in both cases, however, if is is rewritten
> in this way:
>
> def SPISlave(miso, mosi, sclk, ss_n,
>                txdata, txrdy, rxdata, rxrdy,
>                rst_n, n=8):
>       ...
>       @instance
>       def RX():
>           ...
>       @instance
>       def TX():
>           ...
>       return RX, TX
>
>
> Thanks,
> Thomas
>
>
> ------------------------------------------------------------------------------
> Forrester Wave Report - Recovery time is now measured in hours and minutes
> not days. Key insights are discussed in the 2010 Forrester Wave Report as
> part of an in-depth evaluation of disaster recovery service providers.
> Forrester found the best-in-class provider in terms of services and vision.
> Read this report now!  http://p.sf.net/sfu/ibm-webcastpromo


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] wrap function

[Thomas H. <th...@ct...>]

Am 12.04.2011 13:52, schrieb Christopher Felton:
> I created a small write-up here,
> http://www.myhdl.org/doku.php/user:cfelton:projects:wrap, for a proposed
> intbv.wrap() function.
>
> I wrote this quick and probably needs a second look.  I will look at the
> implementation details later.

Hm, if we have a wrap() function, why not add a saturated() function 
additionally?  Saturated arithmetic sounds like a useful feature, 
sometimes...

Thomas