myhdl-list — Mailing list for discussions on MyHDL

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Christopher L. <loz...@fr...>]

>
> Jan L wrote:
>
>   I am a little reluctant to send this to the list as I dont really 
> want to offend you, but rather give you my opinion why some things are 
> not working as expected. If you are comfortable with it, you can 
> forward it to the list.
>


I think the letter is excellent advise, so,  I am publishing it to help 
move this conversation forward.

On 5/2/11 8:17 AM, Jan Langer wrote:
> Am 02.05.2011 um 16:45 schrieb Christopher Lozinski:
>> But in this case, we have a problem, that MyHDL is not growing as fast
>> as we would like, and furthermore, the class libraries and test
>> harnesses are barely there.   They certainly do not meet my needs.
>
>
> Hi Christopher,
> it seems there are only two ways to solve this problem. First, you sit 
> down and implement what you need. Or second, you find other people 
> doing it for whatever reasons. Somehow, the second is unlikely to 
> happen. People like spending time and effort for a good cause, but you 
> got to convince them that what you need is such a good cause. The best 
> way of doing this is going forward yourself. Work on solving your 
> problem and eventually people will help you if they can see this is 
> going somewhere.


>
> Maybe you can just write down your future plan in some detail and 
> outline what your part in it will be. Then you can ask if someone is 
> willing to join the effort. For my part, I dont really get your 
> overall concept. You say you want to offer a commercial class and I 
> personally doubt that enough people will buy the class to 
> significantly grow the MyHDL community or to earn a living for the 
> teacher. Another point is that a class is best taught by an expert of 
> that topic. So the best way for you is to become an expert by 
> implementing stuff.

All excellent advise.  So let me proceed.

I believe that there are a significant number of software hackers who 
would like to build things using FPGA's.   People like myself.  We take 
a look at current microprocessors, and they use 2 billion gates (and one 
Bill Gates)  to execuate 10 instructions per clock cycle.  That is 200 
million gates per instruction per clock cycle.  Surely we can do 
better.  And they hear that FPGA's can do 100 times better, and they are 
hooked.  What do they do?  They can use MyHDL, or Verilog, or VHDL.  I 
tell you, the only option for me is python and MyHDL.   Because I am not 
only building a FPGA, I have to build a considerable software stack on 
top of it.

These are not necessarily hard-core Python developers.  They are the 
guys who hang out in Silicon Valley at places like Hacker's Dojo.   They 
may know a little python, they have heard good things about it, and are 
happy to use a python toolkit, MyHDL.

The class will cost $50, the board another $50.   I think a lot of these 
guys will have no problem to check it out.  Some will stay.

Will I make much money on this?  No.  But I will have a great time, and 
I am learning so much in this process.   I am finding my path. I am 
getting educated.   Thank you for all the help.  My apologies if I often 
get it wrong.

And I think that the guys who agree to teach these classes may be able 
to land some more lucrative MyHDL consulting gigs.

So what is to be done?    The next big task is to put together a slide 
show. Just like the Spanish introductory presentation that arrived this 
morning.   I am sure other things will need to be done.   Booking 
venues, answering questions, buying boards.  Processing credit cards.  
Refunding cancellations.  And dealing with the unexpected.

And then we need to take this show on the road.  I am happy to go up to 
Silicon Valley from time to time.  I had so much fun on the bus back 
yesterday.  Started learning Korean.  Their sentence structure is like 
Japanese!

> I think the best way to help MyHDL is to use it and during doing that 
> improve MyHDL itself and its online documentation. As I see it thats 
> exactly the way Jan D and others are successful.

I understand this point of view.  There is a huge difference between 
doing something for me, and doing it for someone else.  If I were to 
work on MyHDL for myself, I would focus my attention, on the floating 
point class libraries, and the different ways to export them.  If I am 
to work on this for someone else, I would teach them about FPGA's, and 
python and other such introductory things.    Those are different 
focuses.   So as a group, we need to facilitate the entry of new 
members, and reach out to them, by offering such a class, in a location 
where they are going to be, with an inexpensive circuit board, or better 
yet, a borrowed circuit board.

So that is my plan.  I invite people to help make this happen.  Many 
hands make light work.  I am happy to divide up the small amounts of 
money we make however people feel comfortable.  I do not want to do it 
all myself.  I think each of us can do what we most enjoy.  And if there 
is one part that does not get done this way, if several of us do it 
together it will be quite easy.


-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Cheap USB FPGA board needed

[Christopher L. <loz...@fr...>]

Thanks for the suggestions.  It is now time to move forward, so here is 
my reply.

I like this circuit board.

http://www.arrownac.com/offers/altera-corporation/bemicro/



Small, cheap, it is not a board, but a usb stick with some blinking 
lights. It has the right form factor, I was told altera tools are a 
little easier to use.

Regards
Chris
>
>
> --Karl
>
> On Mon, Apr 25, 2011 at 8:53 AM, Christopher Lozinski
> <loz...@fr...>  wrote:
>> I applied to Techshop
>> http://TechShop.ws
>>
>> to teach a MyHDL class.  They charge about $60 per class, so charging
>> $200 plus for the board seemed a bit high to me, and a potential show
>> stopper to them.  Basically we need a $50 board, so that people can try
>> it out.  A $20 board would be even better.   If they like it, then they
>> can upgrade to a $200 board.   Or I could give the students a choice of
>> board.
>>
>> So can anyone recommend a cheap board? There was talk of the Lattice
>> Semiconductor Brevia board for $49.  But it turns out that it only has a
>> parallel port connection, not a USB port,  so that if your computer only
>> has USB, then it requires a $150 connector.   Useless!
>>
>> The required board does not need a lot of LUTs, or transistors or I/O.
>> Just a blinking light, enough transistors to implement a blinking light
>> tutorial, and a USB connection.  The goal is to minimize the barrier to
>> entry to the MyHDL community.
>>
>> Conceptually what I have done is moved from targeting the FPGA
>> community, to the Python community, to the larger software developer
>> community in Silicon Valley.  Lots of people will want to play with
>> FPGAs.  The code for a flip flop in MyHDL is so much simpler than in
>> Verilog.  Python has a great reputation.
>>
>> So if anyone can recommend a board, that would be most appreciated.
>>
>> --
>> Regards
>> Christopher Lozinski
>>
>> Check out my iPhone apps TextFaster and EmailFaster
>> http://textfaster.com
>>
>> Expect a paradigm shift.
>> http://MyHDL.org
>>
>>
>> ------------------------------------------------------------------------------
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>> Lean software platforms are now widely adopted and the benefits have been
>> demonstrated beyond question. Learn why your peers are replacing JEE
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>>
>
>


-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Christopher L. <loz...@fr...>]

> Let's see, what problem could that be?
MyHDL is not going anywhere fast.  Of course just this morning that 
lovely Spanish introductory python material showed up, as if to disprove 
my beliefs.  But the larger issues is still there.  The class libraries, 
the board interfaces, the test cases are just not there.    To be 
specific, it does not have the functionality I need to build my 
project.  And nothing visible is happening on the mailing list.

> Right from the start, you made it very clear that you were looking
> for a closed-source project.
That is not entirely correct.  I rather like the idea of the core being 
LGPL, meaning you are not allowed to make money reselling it.  I like 
the idea of the class libraries and content being more open, like Zope 
public libraries, meaning you are allowed to resell them.
> Actually, some went to work
> immediately with considerable efforts.
>
Let me correct you.  Chris Felton and Jan Coombs, did brilliant work, 
but we later learned we were working under different assumptions.

> There must be something in your approach
> that they dislike very much.
That is very clear to me.  There are those, Richard Stallman included, 
who do not like companies making money off their software, and so 
despite the good marketing name, "open source",  they close the source 
to commercial use.   Coming from the Zope community, I had not 
understood how strong those sentiments were.

But in this case, we have a problem, that MyHDL is not growing as fast 
as we would like, and furthermore, the class libraries and test 
harnesses are barely there.   They certainly do not meet my needs.

I am just pointing out a problem.  Please do not shoot the messenger.  I 
would appreciate it if those who agreed with my position would also 
speak up.

> The real question is how it is
> even possible to waste so much goodwill in such a small
> period of time.
I like the saying, "Hard on issues, soft on people".  Please let us stay 
focused on what it takes to build MyHDL into the thriving community that 
it deserves to be.  Let us figure out what strong medicine this weak 
patient needs.  I am sorry if strong medicine tastes bad.

Anyhow thanks for engaging in this discussion, and allowing me to 
express a different point of view.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Jan D. <ja...@ja...>]

On 05/01/2011 10:35 AM, loz...@fr... wrote:
>
>
>> The intent is that any content can be freely re-used and modified,
>> including for commercial purposes, provided that any derived work
>> is licensed under the same conditions.
>
> (Note: This is independent of the proposed license change.)
>
>
> Then we all have a problem.  To make MyHDL vibrant, we need a
> commercial class that goes to places like Hacker's Dojo in Silicon
> Valley and teaches newbies the material, and rapidly grows the
> community.
>
> I am not willing to put together such a class, if I have to do it all
> from scratch.  And I am not willing to do it using existing
> materials, if it means I have to open source the whole class.  Nor do
> I see anyone else even interested in creating the teaching materials.
> Sure Chris Felton did a great job in creating the basic tutorials,
> but there is so much other work to create and market such a class.
> And I do not see anyone doing it.
>
> So we all have a problem here.

Let's see, what problem could that be?

Right from the start, you made it very clear that you were looking
for a closed-source project. For the record, I personally think
that's absolute fine. Certainly it didn't prevent several people
to offer help, myself included. Actually, some went to work
immediately with considerable efforts.

Now you're telling us that all those people have run away. Even   
the "great team" on your class website has apparently already
been dissolved. There must be something in your approach
that they dislike very much.

There is no scapegoat to be found in closed source or the
absence of potential help. The real question is how it is
even possible to waste so much goodwill in such a small
period of time.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

[myhdl-list] MyHDL at PyDay in Córdoba

[Martín G. <ga...@gm...>]

Yesterday was the PyDay and I gave my talk about MyHDL. It's very
short and basic, oriented to people who knows about python but not
hardware design (not so far from myself!)

here are the slides
http://nqnwebs.github.com/myhdl-talk/

and here all  sources
https://github.com/nqnwebs/myhdl-talk

I think it was fine :-)

cheers
Martin

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[<loz...@fr...>]

 

>The intent is that any content can be freely re-used
>and modified, including for commercial purposes, provided
>that any derived work is licensed under the same conditions.

(Note: This is independent of the proposed license change.)


Then we all have a problem.  To make MyHDL vibrant, we need a commercial class that goes to places like Hacker's Dojo in Silicon Valley and teaches newbies the material, and rapidly grows the community. 

I am not willing to put together such a class, if I have to do it all from scratch.  And I am not willing to do it using existing materials, if it means I have to open source the whole class.  Nor do I see anyone else even interested in creating the teaching materials.  Sure Chris Felton did a great job in creating the basic tutorials, but there is so much other work to create and market such a class.  And I do not see anyone doing it. 

So we all have a problem here. 

>The answer is yes, quite obviously. I'll let you know my
>current consultancy rate if you're interested. 

Of course if someone shows up with lots of money great.  But the question is how do we harness the meager resources of this community to more rapidly build what is needed.  And frankly the current approach is not doing it, the conflict over the issues has been disastrous.   

So back to building my iPhone apps till all this gets sorted out. 

Regards
Chris

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Jan D. <ja...@ja...>]

On 04/30/2011 03:49 PM, Christopher Felton wrote:
> Sounds like a good plan.  No objections here.

Thanks, Chris.

>
> Chris Felton
>
> On 4/30/11 2:11 AM, Jan Decaluwe wrote:
>> Currently, content on the www.myhdl.org is licensed under
>> the GFDL (Gnu Free Documentation License).
>>
>> The intent is that any content can be freely re-used
>> and modified, including for commercial purposes, provided
>> that any derived work is licensed under the same conditions.
>>
>> The GFDL was originally created for software documentation
>> texts with a few authors. In practice, it is very hard if
>> not impossible to comply with its requirements for on-line
>> resources with many authors, such as wiki's. For these
>> reasons, major projects like wikipedia have moved from
>> the GFDL to the Creative Commons Attribution Share-Alike
>> license (CC BY-SA).
>>
>> The CC BY-SA implements the same intent as the GFDL, but
>> in a way better suited to online resources with many.
>> contributors. For example, it makes it possible to
>> attribute the work by simply including an URL to the
>> original content. The CC BY-SA is becoming the de facto
>> standard for this type of resources, making it easier to
>> create derived works by combining content from different
>> sources.
>>
>> For more information and details, see:
>>
>> http://meta.wikimedia.org/wiki/Licensing_update/Questions_and_Answers
>>
>> In light of the above, I am proposing to change the license
>> for www.myhdl.org to CC BY-SA. Upfront, I cannot see a reason why
>> any contributor would object to this: as said, it implements the
>> same intent as the GFDL in a way that is workable in practice.
>> Therefore, I am essentially looking for a consensus.
>>
>> I have prepared a draft Terms of Use that explains how www.myhdl.org
>> would have to be used with the proposed license, based on the
>> corresponding text from wikipedia:
>>
>> http://www.myhdl.org/doku.php/terms_of_use
>>
>> I will wait a few days to see if there are any major or
>> fundemental objections. I will treat absence of feedback
>> as silent agreement, but I will not go ahead if there
>> are major contributors who disagree.
>>
>> Jan
>>
>
>
>
> ------------------------------------------------------------------------------
> WhatsUp Gold - Download Free Network Management Software
> The most intuitive, comprehensive, and cost-effective network
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-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Jan D. <ja...@ja...>]

On 04/30/2011 04:54 PM, Christopher Lozinski wrote:
> First of all, I think it is great that you are upgrading the licensing.
>
> My question is, if someone were to offer a commercial class, can that
> person grab your flip flop examples, and use them.

Of course. As I said in my post:

The intent is that any content can be freely re-used
and modified, including for commercial purposes, provided
that any derived work is licensed under the same conditions.

(Note: This is independent of the proposed license change.)

> And the bigger question is do you want to support commercial activities,
> on top of MyHDL or not.

The answer is yes, quite obviously. I'll let you know my
current consultancy rate if you're interested.

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Christopher L. <loz...@fr...>]

First of all, I think it is great that you are upgrading the licensing.

My question is, if someone were to offer a commercial class, can that 
person grab your flip flop examples, and use them.  If not, what would 
it take to enable that use of the material.  A commercial class is so 
needed.

And the bigger question is do you want to support commercial activities, 
on top of MyHDL or not.

I am heading out for the weekend.  Please give me until Tuesday to get 
back to you.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Proposal to change license of wwww.myhdl.org

[Christopher F. <chr...@gm...>]

Sounds like a good plan.  No objections here.

Chris Felton

On 4/30/11 2:11 AM, Jan Decaluwe wrote:
> Currently, content on the www.myhdl.org is licensed under
> the GFDL (Gnu Free Documentation License).
>
> The intent is that any content can be freely re-used
> and modified, including for commercial purposes, provided
> that any derived work is licensed under the same conditions.
>
> The GFDL was originally created for software documentation
> texts with a few authors. In practice, it is very hard if
> not impossible to comply with its requirements for on-line
> resources with many authors, such as wiki's. For these
> reasons, major projects like wikipedia have moved from
> the GFDL to the Creative Commons Attribution Share-Alike
> license (CC BY-SA).
>
> The CC BY-SA implements the same intent as the GFDL, but
> in a way better suited to online resources with many.
> contributors. For example, it makes it possible to
> attribute the work by simply including an URL to the
> original content. The CC BY-SA is becoming the de facto
> standard for this type of resources, making it easier to
> create derived works by combining content from different
> sources.
>
> For more information and details, see:
>
> http://meta.wikimedia.org/wiki/Licensing_update/Questions_and_Answers
>
> In light of the above, I am proposing to change the license
> for www.myhdl.org to CC BY-SA. Upfront, I cannot see a reason why
> any contributor would object to this: as said, it implements the
> same intent as the GFDL in a way that is workable in practice.
> Therefore, I am essentially looking for a consensus.
>
> I have prepared a draft Terms of Use that explains how www.myhdl.org
> would have to be used with the proposed license, based on the
> corresponding text from wikipedia:
>
> http://www.myhdl.org/doku.php/terms_of_use
>
> I will wait a few days to see if there are any major or
> fundemental objections. I will treat absence of feedback
> as silent agreement, but I will not go ahead if there
> are major contributors who disagree.
>
> Jan
>

[myhdl-list] Proposal to change license of wwww.myhdl.org

[Jan D. <ja...@ja...>]

Currently, content on the www.myhdl.org is licensed under
the GFDL (Gnu Free Documentation License).

The intent is that any content can be freely re-used
and modified, including for commercial purposes, provided
that any derived work is licensed under the same conditions.

The GFDL was originally created for software documentation
texts with a few authors. In practice, it is very hard if
not impossible to comply with its requirements for on-line
resources with many authors, such as wiki's. For these
reasons, major projects like wikipedia have moved from
the GFDL to the Creative Commons Attribution Share-Alike
license (CC BY-SA).

The CC BY-SA implements the same intent as the GFDL, but
in a way better suited to online resources with many.
contributors. For example, it makes it possible to
attribute the work by simply including an URL to the
original content. The CC BY-SA is becoming the de facto
standard for this type of resources, making it easier to
create derived works by combining content from different
sources.

For more information and details, see:

http://meta.wikimedia.org/wiki/Licensing_update/Questions_and_Answers

In light of the above, I am proposing to change the license
for www.myhdl.org to CC BY-SA. Upfront, I cannot see a reason why
any contributor would object to this: as said, it implements the
same intent as the GFDL in a way that is workable in practice.
Therefore, I am essentially looking for a consensus.

I have prepared a draft Terms of Use that explains how www.myhdl.org
would have to be used with the proposed license, based on the
corresponding text from wikipedia:

http://www.myhdl.org/doku.php/terms_of_use

I will wait a few days to see if there are any major or
fundemental objections. I will treat absence of feedback
as silent agreement, but I will not go ahead if there
are major contributors who disagree.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL project debriefing

[Jan D. <ja...@ja...>]

On 04/27/2011 11:47 AM, Angel Ezquerra wrote:
> On Tue, Apr 26, 2011 at 10:13 PM, Jan Decaluwe<ja...@ja...>  wrote:
>> I just finished a MyHDL project that was lot of fun,
>> and I thought some of you might be interested in a few highlights.
>> You will understand that I cannot go in too much detail.
>>
>> The starting point for this image processing algorithm
>> was a spec in words. The deliverable was RTL VHDL code
>> and a regression test suite.
>>
>> To have a verification reference, the customer agreed
>> that I developed a high-level untimed model of the
>> algorithm in pure Python. This have been a great help,
>> and the customer actually agreed to sign of on it.
>
> Jan,
>
> did this high-level untimed python model use MyHDL at all?

No. plain python for algorithmic development.

In other projects, I can imagine that the intbv type
might be useful in such models, for its bound-checking capabilities.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL project debriefing

[Angel E. <ang...@gm...>]

On Tue, Apr 26, 2011 at 10:13 PM, Jan Decaluwe <ja...@ja...> wrote:
> I just finished a MyHDL project that was lot of fun,
> and I thought some of you might be interested in a few highlights.
> You will understand that I cannot go in too much detail.
>
> The starting point for this image processing algorithm
> was a spec in words. The deliverable was RTL VHDL code
> and a regression test suite.
>
> To have a verification reference, the customer agreed
> that I developed a high-level untimed model of the
> algorithm in pure Python. This have been a great help,
> and the customer actually agreed to sign of on it.

Jan,

did this high-level untimed python model use MyHDL at all?

Angel

Re: [myhdl-list] MyHDL project debriefing

[Jan D. <ja...@ja...>]

On 04/27/2011 05:25 AM, Tom Dillon wrote:
> Some comments:
>
>
> On 04/26/2011 03:13 PM, Jan Decaluwe wrote:
>> I just finished a MyHDL project that was lot of fun,
>> and I thought some of you might be interested in a few highlights.
>> You will understand that I cannot go in too much detail.
>>
>> The starting point for this image processing algorithm
>> was a spec in words. The deliverable was RTL VHDL code
>> and a regression test suite.
>>
>> To have a verification reference, the customer agreed
>> that I developed a high-level untimed model of the
>> algorithm in pure Python. This have been a great help,
>> and the customer actually agreed to sign of on it.
>
> I too have found Python great for this.
>
>> I developed all functional modules in MyHDL. There were
>> a number of arithmetic modules (multipliers, dividers) and
>> algorithmic modules (e.g. sorting). In some cases, pipelining
>> was needed (to meet timing), in others iterative
>> implementations (to save area.) A unit-based test-driven
>> development approach worked great in such cases.
>>
>> All MyHDL modules were individually converted to VHDL. The
>> convertor's ability to add all the resizing/conversion
>> details proved again a great help. (I also discovered
>> some bugs in the process.
>> The modules were stitched together in VHDL using Sigasi HDT,
>> a VHDL IDE from Sigasi, a company that I am coaching
>> (as a consultant, director and shareholder.) Sigasi HDT was
>> also used to develop the test bench code. Recommended for
>> anyone who (also) uses VHDL :-)
>>
> Was there a reason not to covert at a higher level and get rid of the
> need for Sigasi HDT?

As per customer requirements, the final deliverable was VHDL RTL
code for synthesis, and a VHDL-based regression suite.
The customer has to be able to use the deliverable directly in his
VHDL-only design flow.

The test bench involves file IO, input and output, in a
way not supported by conversion. So for the top-level
test bench I used a direct VHDL approach, including
VHDL configurations to set up different scenario's.

For the top-level, I could have used conversion, however I
wanted to keep some hierarchy (for clarity for the customer),
and as you know this takes some work. As I didn't use  the
MyHDL top-level itself, there was little value in this,
especially because Sigasi HDT makes stitching things
together structurally very easy

>
>> The high-level Python model generated input data as well
>> as expected output. A single (configurable) VHDL test bench
>> takes the input and dumps the output. The regression
>> test suite simply runs all test scenarios and diffs
>> actual and expected output.
>
> Was a MyHDL test bench too slow to run the top level test? Or why use VHDL?

See above - VHDL handoff was a customer requirement.

MyHDL would have been slower, but that would not have been a major issue.

In the ideal world, I would of course prefer to use a MyHDL only
design flow and only use VHDL/Verilog as a backend format. But in
this first engagement with this customer I'm happy that I have
been able to show the value of Python as a first step.


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL project debriefing

[Tom D. <td...@di...>]

Some comments:


On 04/26/2011 03:13 PM, Jan Decaluwe wrote:
> I just finished a MyHDL project that was lot of fun,
> and I thought some of you might be interested in a few highlights.
> You will understand that I cannot go in too much detail.
>
> The starting point for this image processing algorithm
> was a spec in words. The deliverable was RTL VHDL code
> and a regression test suite.
>
> To have a verification reference, the customer agreed
> that I developed a high-level untimed model of the
> algorithm in pure Python. This have been a great help,
> and the customer actually agreed to sign of on it.

I too have found Python great for this.

> I developed all functional modules in MyHDL. There were
> a number of arithmetic modules (multipliers, dividers) and
> algorithmic modules (e.g. sorting). In some cases, pipelining
> was needed (to meet timing), in others iterative
> implementations (to save area.) A unit-based test-driven
> development approach worked great in such cases.
>
> All MyHDL modules were individually converted to VHDL. The
> convertor's ability to add all the resizing/conversion
> details proved again a great help. (I also discovered
> some bugs in the process.
> The modules were stitched together in VHDL using Sigasi HDT,
> a VHDL IDE from Sigasi, a company that I am coaching
> (as a consultant, director and shareholder.) Sigasi HDT was
> also used to develop the test bench code. Recommended for
> anyone who (also) uses VHDL :-)
>
Was there a reason not to covert at a higher level and get rid of the 
need for Sigasi HDT?

> The high-level Python model generated input data as well
> as expected output. A single (configurable) VHDL test bench
> takes the input and dumps the output. The regression
> test suite simply runs all test scenarios and diffs
> actual and expected output.

Was a MyHDL test bench too slow to run the top level test? Or why use VHDL?

[myhdl-list] MyHDL project debriefing

[Jan D. <ja...@ja...>]

I just finished a MyHDL project that was lot of fun,
and I thought some of you might be interested in a few highlights.
You will understand that I cannot go in too much detail.

The starting point for this image processing algorithm
was a spec in words. The deliverable was RTL VHDL code
and a regression test suite.

To have a verification reference, the customer agreed
that I developed a high-level untimed model of the
algorithm in pure Python. This have been a great help,
and the customer actually agreed to sign of on it.

I developed all functional modules in MyHDL. There were
a number of arithmetic modules (multipliers, dividers) and
algorithmic modules (e.g. sorting). In some cases, pipelining
was needed (to meet timing), in others iterative
implementations (to save area.) A unit-based test-driven
development approach worked great in such cases.

All MyHDL modules were individually converted to VHDL. The
convertor's ability to add all the resizing/conversion
details proved again a great help. (I also discovered
some bugs in the process.)

The modules were stitched together in VHDL using Sigasi HDT,
a VHDL IDE from Sigasi, a company that I am coaching
(as a consultant, director and shareholder.) Sigasi HDT was
also used to develop the test bench code. Recommended for
anyone who (also) uses VHDL :-)

The high-level Python model generated input data as well
as expected output. A single (configurable) VHDL test bench
takes the input and dumps the output. The regression
test suite simply runs all test scenarios and diffs
actual and expected output.

Timing was not trival to meet. However, using this methodology
it was possible to run trial synthesis early on and get
feedback from trial place&route, so that meaningful
optimizations (in some case large) to the RTL could be
made, integrated in the RTL development flow.

A pity it's over :-)

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] Cheap USB FPGA board needed

[Iain C. <iai...@at...>]

It appears that the Digilent interface software is now available for Linux as 
well but I have not verified the functionality.

http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2




________________________________
From: Iain Clark <iai...@at...>
To: General discussions on MyHDL <myh...@li...>
Sent: Mon, April 25, 2011 12:35:37 PM
Subject: Re: [myhdl-list] Cheap USB FPGA board needed


Hi:

I have used Digilent Inc's boards professionally and bought their Nexys-2 for 
personal hacking. Their Basys-2 may meet your needs and is in your price range 
using their student pricing. Qualifications for student pricing  seem to be 
stringent and they claim to verify them. 


http://www.digilentinc.com/nav1index.cfm?NavTop=82#academicpricing

They provide FPGA programming through USB (supports JTAG but not required) and 
have a pretty decent set of interface tools that allow software control of 
registers and loading/dumping of memory. I found the reference design they 
provided for my board to be a great starting point. I believe their tools only 
run under windows  at present.

Lots of docs, schematics etc at:
http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=BASYS2

Do let me know what you decide on.

Iain





________________________________
From: Karl Kaiser <kk...@be...>
To: General discussions on MyHDL <myh...@li...>
Sent: Mon, April 25, 2011 9:46:55 AM
Subject: Re: [myhdl-list] Cheap USB FPGA board needed

Christopher,

This may work for you and fits the $49.

http://papilio.cc

or this one may be particular handy for a class full of python geeks ;-).

http://www.arrownac.com/offers/altera-corporation/bemicro/

--Karl

On Mon, Apr 25, 2011 at 8:53 AM, Christopher Lozinski
<loz...@fr...> wrote:
> I applied to Techshop
> http://TechShop.ws
>
> to teach a MyHDL class.  They charge about $60 per class, so charging
> $200 plus for the board seemed a bit high to me, and a potential show
> stopper to them.  Basically we need a $50 board, so that  people can try
> it out.  A $20 board would be even better.   If they like it, then they
> can upgrade to a $200 board.   Or I could give the students a choice of
> board.
>
> So can anyone recommend a cheap board? There was talk of the Lattice
> Semiconductor Brevia board for $49.  But it turns out that it only has a
> parallel port connection, not a USB port,  so that if your computer only
> has USB, then it requires a $150 connector.   Useless!
>
> The required board does not need a lot of LUTs, or transistors or I/O.
> Just a blinking light, enough transistors to implement a blinking light
> tutorial, and a USB connection.  The goal is to minimize the barrier to
> entry to the MyHDL community.
>
> Conceptually what I have done is moved from targeting the FPGA
> community, to the Python community, to the larger software  developer
> community in Silicon Valley.  Lots of people will want to play with
> FPGAs.  The code for a flip flop in MyHDL is so much simpler than in
> Verilog.  Python has a great reputation.
>
> So if anyone can recommend a board, that would be most appreciated.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
> ------------------------------------------------------------------------------
> Fulfilling the Lean Software Promise
> Lean software platforms are now widely adopted and the benefits have been
> demonstrated beyond question. Learn why your peers are replacing  JEE
> containers with lightweight application servers - and what you can gain
> from the move. http://p.sf.net/sfu/vmware-sfemails
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Best regards,

Karl Kaiser | 408 306 1755

------------------------------------------------------------------------------
WhatsUp Gold - Download Free Network Management Software
The most intuitive, comprehensive, and cost-effective network 
management toolset available today.  Delivers lowest initial 
acquisition cost and overall TCO of any competing solution.
http://p.sf.net/sfu/whatsupgold-sd
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] Cheap USB FPGA board needed

[Iain C. <iai...@at...>]

Hi:

I have used Digilent Inc's boards professionally and bought their Nexys-2 for 
personal hacking. Their Basys-2 may meet your needs and is in your price range 
using their student pricing. Qualifications for student pricing  seem to be 
stringent and they claim to verify them. 


http://www.digilentinc.com/nav1index.cfm?NavTop=82#academicpricing

They provide FPGA programming through USB (supports JTAG but not required) and 
have a pretty decent set of interface tools that allow software control of 
registers and loading/dumping of memory. I found the reference design they 
provided for my board to be a great starting point. I believe their tools only 
run under windows at present.

Lots of docs, schematics etc at:
http://digilentinc.com/Products/Detail.cfm?NavPath=2,400,790&Prod=BASYS2

Do let me know what you decide on.

Iain





________________________________
From: Karl Kaiser <kk...@be...>
To: General discussions on MyHDL <myh...@li...>
Sent: Mon, April 25, 2011 9:46:55 AM
Subject: Re: [myhdl-list] Cheap USB FPGA board needed

Christopher,

This may work for you and fits the $49.

http://papilio.cc

or this one may be particular handy for a class full of python geeks ;-).

http://www.arrownac.com/offers/altera-corporation/bemicro/

--Karl

On Mon, Apr 25, 2011 at 8:53 AM, Christopher Lozinski
<loz...@fr...> wrote:
> I applied to Techshop
> http://TechShop.ws
>
> to teach a MyHDL class.  They charge about $60 per class, so charging
> $200 plus for the board seemed a bit high to me, and a potential show
> stopper to them.  Basically we need a $50 board, so that people can try
> it out.  A $20 board would be even better.   If they like it, then they
> can upgrade to a $200 board.   Or I could give the students a choice of
> board.
>
> So can anyone recommend a cheap board? There was talk of the Lattice
> Semiconductor Brevia board for $49.  But it turns out that it only has a
> parallel port connection, not a USB port,  so that if your computer only
> has USB, then it requires a $150 connector.   Useless!
>
> The required board does not need a lot of LUTs, or transistors or I/O.
> Just a blinking light, enough transistors to implement a blinking light
> tutorial, and a USB connection.  The goal is to minimize the barrier to
> entry to the MyHDL community.
>
> Conceptually what I have done is moved from targeting the FPGA
> community, to the Python community, to the larger software developer
> community in Silicon Valley.  Lots of people will want to play with
> FPGAs.  The code for a flip flop in MyHDL is so much simpler than in
> Verilog.  Python has a great reputation.
>
> So if anyone can recommend a board, that would be most appreciated.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
> ------------------------------------------------------------------------------
> Fulfilling the Lean Software Promise
> Lean software platforms are now widely adopted and the benefits have been
> demonstrated beyond question. Learn why your peers are replacing JEE
> containers with lightweight application servers - and what you can gain
> from the move. http://p.sf.net/sfu/vmware-sfemails
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Best regards,

Karl Kaiser | 408 306 1755

------------------------------------------------------------------------------
WhatsUp Gold - Download Free Network Management Software
The most intuitive, comprehensive, and cost-effective network 
management toolset available today.  Delivers lowest initial 
acquisition cost and overall TCO of any competing solution.
http://p.sf.net/sfu/whatsupgold-sd
_______________________________________________
myhdl-list mailing list
myh...@li...
https://lists.sourceforge.net/lists/listinfo/myhdl-list

Re: [myhdl-list] Cheap USB FPGA board needed

[Karl K. <kk...@be...>]

Christopher,

This may work for you and fits the $49.

http://papilio.cc

or this one may be particular handy for a class full of python geeks ;-).

http://www.arrownac.com/offers/altera-corporation/bemicro/

--Karl

On Mon, Apr 25, 2011 at 8:53 AM, Christopher Lozinski
<loz...@fr...> wrote:
> I applied to Techshop
> http://TechShop.ws
>
> to teach a MyHDL class.  They charge about $60 per class, so charging
> $200 plus for the board seemed a bit high to me, and a potential show
> stopper to them.  Basically we need a $50 board, so that people can try
> it out.  A $20 board would be even better.   If they like it, then they
> can upgrade to a $200 board.   Or I could give the students a choice of
> board.
>
> So can anyone recommend a cheap board? There was talk of the Lattice
> Semiconductor Brevia board for $49.  But it turns out that it only has a
> parallel port connection, not a USB port,  so that if your computer only
> has USB, then it requires a $150 connector.   Useless!
>
> The required board does not need a lot of LUTs, or transistors or I/O.
> Just a blinking light, enough transistors to implement a blinking light
> tutorial, and a USB connection.  The goal is to minimize the barrier to
> entry to the MyHDL community.
>
> Conceptually what I have done is moved from targeting the FPGA
> community, to the Python community, to the larger software developer
> community in Silicon Valley.  Lots of people will want to play with
> FPGAs.  The code for a flip flop in MyHDL is so much simpler than in
> Verilog.  Python has a great reputation.
>
> So if anyone can recommend a board, that would be most appreciated.
>
> --
> Regards
> Christopher Lozinski
>
> Check out my iPhone apps TextFaster and EmailFaster
> http://textfaster.com
>
> Expect a paradigm shift.
> http://MyHDL.org
>
>
> ------------------------------------------------------------------------------
> Fulfilling the Lean Software Promise
> Lean software platforms are now widely adopted and the benefits have been
> demonstrated beyond question. Learn why your peers are replacing JEE
> containers with lightweight application servers - and what you can gain
> from the move. http://p.sf.net/sfu/vmware-sfemails
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list
>



-- 
Best regards,

Karl Kaiser | 408 306 1755

[myhdl-list] Cheap USB FPGA board needed

[Christopher L. <loz...@fr...>]

I applied to Techshop
http://TechShop.ws

to teach a MyHDL class.  They charge about $60 per class, so charging 
$200 plus for the board seemed a bit high to me, and a potential show 
stopper to them.  Basically we need a $50 board, so that people can try 
it out.  A $20 board would be even better.   If they like it, then they 
can upgrade to a $200 board.   Or I could give the students a choice of 
board.

So can anyone recommend a cheap board? There was talk of the Lattice 
Semiconductor Brevia board for $49.  But it turns out that it only has a 
parallel port connection, not a USB port,  so that if your computer only 
has USB, then it requires a $150 connector.   Useless!

The required board does not need a lot of LUTs, or transistors or I/O.  
Just a blinking light, enough transistors to implement a blinking light 
tutorial, and a USB connection.  The goal is to minimize the barrier to 
entry to the MyHDL community.

Conceptually what I have done is moved from targeting the FPGA 
community, to the Python community, to the larger software developer 
community in Silicon Valley.  Lots of people will want to play with 
FPGAs.  The code for a flip flop in MyHDL is so much simpler than in 
Verilog.  Python has a great reputation.

So if anyone can recommend a board, that would be most appreciated.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] help - hot bit encoder

[Jan D. <ja...@ja...>]

Jan:

Sorry for the delay in responding - I'm not very motivated
to make things more complex than needed :-)

Anyway, I understand you want to investigate and learn,
but in that case, please read the manual. I wrote it
for you :-)

http://www.myhdl.org/doc/current/manual/conversion.html#supported-types

It clearly states that the kind of thing your are doing
with object 'map' is just not supported by the converter.
As I keep repeating, conversion is really very restricted.
We really should be discussing anything you don't understand
or is unclear in the manual. Your starting assumption should
be that almost nothing inside a generator is convertible :-)
Don't just keep on trying and be frustrated - first read
about the restrictions in the manual.

Of course, it remains a software bug to let assertions
escape to the user, and I have now added a clearer error
message in development.

Jan


On 04/10/2011 02:17 AM, Jan Coombs wrote:
> On 08/04/11 08:31, Jan Coombs wrote:
>> On 03/04/11 12:02, Jan Decaluwe wrote:
>> > Jan:
>> >
>> > You struggle . . .
>>
>> Yes. . . .
>
> I now have simulation working correctly, though I'm not sure if this is the simplest way to write the code I want.
>
> Conversion to VHDL or Verilog is a problem. I get the error:
>
> Traceback (most recent call last):
> File "./encodeHotBit_map11.py", line 83, in <module>
> test_ehb()
> File "./encodeHotBit_map11.py", line 81, in test_ehb
> toVHDL(hotBit2binary, iv, ov, Width)
> File "/usr/local/lib/python2.6/dist-packages/myhdl/conversion/_toVHDL.py", line 145, in __call__
> genlist = _analyzeGens(arglist, h.absnames)
> File "/usr/local/lib/python2.6/dist-packages/myhdl/conversion/_analyze.py", line 165, in _analyzeGens
> _isMem(obj) or _isTupleOfInts(obj)
> AssertionError
>
>
> Any suggestions? Jan Coombs
>
>
>
> ------------------------------------------------------------------------------
> Xperia(TM) PLAY
> It's a major breakthrough. An authentic gaming
> smartphone on the nation's most reliable network.
> And it wants your games.
> http://p.sf.net/sfu/verizon-sfdev
>
>
>
> _______________________________________________
> myhdl-list mailing list
> myh...@li...
> https://lists.sourceforge.net/lists/listinfo/myhdl-list


-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
     Python as a HDL: http://www.myhdl.org
     VHDL development, the modern way: http://www.sigasi.com
     Analog design automation: http://www.mephisto-da.com
     World-class digital design: http://www.easics.com

Re: [myhdl-list] MyHDL marketing at Python Conferences

[Jan C. <jan...@mu...>]

On 21/04/11 18:02, Christopher Lozinski wrote:
    . . .
> I had thought that we should be exhibiting at FPGA shows.   Those are
> the guys who need better tools.  But the results are underwhelming.  It
> is better than nothing, But I now believe that does not lead to a big
> jump in users.   MyHDL is really ready for the python conferences.  I
> assume that there are way more python developers than FPGA developers.
> And I believe that MyHDL makes them comfortable doing hardware, whereas
> it makes the hard core FPGA engineers uncomfortable.    So big benefit
> to python developers, a risk is perceived to FPGA engineers.  So perhaps
> our efforts should go into the python conferences rather than  into the
> FPGA conferences.  Live and learn.
Most of this seems to be unsupported by evidence, speculative, and 
wrong.

    . . .
> It has been suggested I am just a marketing person.
    . . .
> It has been said that I do not understand hardware development.  That is
> true.  I am learning.  I will get it.  I always get my software to
> work.   I am comfortable making mistakes.   Please be patient.
Ok, so please send me your first go at changing that simple adder 
demo into a subtracter.

> I will get to being a MyHDL developer, but there are other more
> important things to do first.  Like build the community.   This is a
> long term project for me.
What community? How can you build the new new community of python 
hardware developers if you do not understand the methods they will 
need to use yourself?
    . . .
>
> Comments appreciated.
Who are the "we"?  Sounds like a right royal wee to me.  Now who's 
taking the piss?

Jam Coombs

[myhdl-list] MyHDL marketing at Python Conferences

[Christopher L. <loz...@fr...>]

Thanks to Jan L, and friends for the presence in Cordoba.  And for the 
wonderful report and marketing advice.

I had thought that we should be exhibiting at FPGA shows.   Those are 
the guys who need better tools.  But the results are underwhelming.  It 
is better than nothing, But I now believe that does not lead to a big 
jump in users.   MyHDL is really ready for the python conferences.  I 
assume that there are way more python developers than FPGA developers.  
And I believe that MyHDL makes them comfortable doing hardware, whereas 
it makes the hard core FPGA engineers uncomfortable.    So big benefit 
to python developers, a risk is perceived to FPGA engineers.  So perhaps 
our efforts should go into the python conferences rather than  into the 
FPGA conferences.  Live and learn.

So here is the list of python conferences.
http://www.pycon.org/

I invite you all to present MyHDL at these conferences.  Either as free 
papers, booths, or paid tutorials.  Whatever works for you.  Whatever 
the conference allows.

It has been suggested I am just a marketing person.  Do a search on 
Google for "python resume" and my django job board shows up on the first 
page.  My Zope job board is way larger.   Or download my iPhone app 
http://TextFaster.com

It has been said that I do not understand hardware development.  That is 
true.  I am learning.  I will get it.  I always get my software to 
work.   I am comfortable making mistakes.   Please be patient.

I will get to being a MyHDL developer, but there are other more 
important things to do first.  Like build the community.   This is a 
long term project for me.

My belief in MyHDL is that the core is good, but way more classes and 
test suites for those classes are needed.   Easier and more fun, and 
more needed, to grow the community than to write them myself.   We tried 
marketing in the FPGA community, and certainly that brought this mailing 
list to life, but it is still a fragile community.  More is needed.

So my attention turns to the larger python community.

On a related note, you may know this, it turns out that for a while AMD 
has had an effort to ship FPGA's on the mother board.  Intel is now 
doing the same.  So these devices are really becoming main stream, as 
everyone starts to realize the gate inefficiency of traditional 
microprocessors.   So this stuff is going mainstream, and by marketing 
to the python community, we are on the right mainstream path.   I think 
there will be a flood of python developers getting into FPGA 
development.  But then I am always an optimist.

And if that does not work,  we will try something different.

Comments appreciated.

-- 
Regards
Christopher Lozinski

Check out my iPhone apps TextFaster and EmailFaster
http://textfaster.com

Expect a paradigm shift.
http://MyHDL.org

Re: [myhdl-list] Testbench problems

[Terry B. <tt...@gm...>]

Christopher Felton <chris.felton <at> gmail.com> writes:


> 
> Make your "tasks" generators and then use yield test_readit()
> 

> Hope that helps.
> Chris Felton
> 
>

Thank you!  I now have it working.  I am somewhat experienced with Python and
this is my first attempt to use MyHdl for production purposes.

I plan of developing modules in MyHdl, testing using the unittest framework,
then converting to verilog and using that verilog in my higher level design.

Terry Brown

[myhdl-list] Cordoba Poster

[Jan L. <jan...@et...>]

Hi everybody,
After some discussion with the conference chair I was able to put up  
the poster on the second of three days. I also put 30 flyers there,  
that were all gone by the end. The poster was much smaller in the end,  
maybe A1 and contained some printing artifacts. My spanish is way too  
bad to argue with the guys in the printing shop (they somehow imported  
it into corel draw, who knows why)

The interest in the poster was good. Of the about 100 conference  
participants (the vast majority from argentina or brazil)  maybe 15 to  
20 people were interested and I was able to explain some details. Some  
(not more than 5, mainly students) seemed really interested and might  
try MyHDL.

What I really missed was a code example on the poster and some  
explanation that MyHDL is not about High-Level-Synthesis but more or  
less normal RTL design. I wrote Chris a separate mail on that topic.  
The same applies for the flyer. People like to see code.

Currently, I brought both versions of the poster with me to germany.  
But as has already been pointed out, shipping such a thing is more  
expensive than printing a new one.

The best thing has been to meet with Martin and Jose. Jose did a great  
talk on MyHDL the first day, and I have been able to refer to that  
during the poster sessions.

So in general, this rather small effort was a good way to make MyHDL  
known in the south american hardware community in a way that maybe if  
a student like Martin wants to use MyHDL chances are good that his  
professor will have heard about it :-) Paying real money or spending  
an engineers valuable time will probably be not worth it (I would have  
just eaten more cookies without the poster, being there anyway)
Jan

-- 
Jan Langer
Professorship Circuit and System Design
Chemnitz University of Technology, Reichenhainer Str. 70, 09126 Chemnitz
Phone: +49 371 531-33158, Fax: +49 371 531-833158
http://www.tu-chemnitz.de/etit/sse