linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/include/asm-mips/vr4111 vr4111.h,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4111
In directory usw-pr-cvs1:/tmp/cvs-serv30742/include/asm-mips/vr4111

Added Files:
	vr4111.h 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.



--- NEW FILE: vr4111.h ---
/* 
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1999 by Michael Klar
 *
 * Adapted for VR4111
 * Copyright (C) 2001 Jim Paris <ji...@jt...>
 */
#ifndef __ASM_VR4111_VR4111_H 
#define __ASM_VR4111_VR4111_H 

#include <asm/addrspace.h>

#define VR41XX_CPU_IRQ_BASE  0
#define VR41XX_NUM_CPU_IRQ   8

#define VR41XX_SYS_IRQ_BASE  8
#define VR41XX_NUM_SYS_IRQ   32

#define VR41XX_GPIO_IRQ_BASE 40
#define VR41XX_NUM_GPIO_IRQ  32

/* CPU interrupts */
#define VR41XX_IRQ_SW1       0  /* IP0 - Software interrupt */
#define VR41XX_IRQ_SW2       1  /* IP1 - Software interrupt */
#define VR41XX_IRQ_INT0      2  /* IP2 - All other interrupts */
#define VR41XX_IRQ_INT1      3  /* IP3 - RTC Long1 */
#define VR41XX_IRQ_INT2      4  /* IP4 - RTC Long2 */
#define VR41XX_IRQ_INT3      5  /* IP5 - High Speed Modem */
#define VR41XX_IRQ_INT4      6  /* IP6 - Unused on VR4111 */
#define VR41XX_IRQ_TIMER     7  /* IP7 - Timer interrupt */

/* Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts) */
#define VR41XX_IRQ_BATTERY   8
#define VR41XX_IRQ_POWER     9
#define VR41XX_IRQ_RTCL1     10  /* Use VR41XX_IRQ_INT1 instead. */
#define VR41XX_IRQ_ETIMER    11
#define VR41XX_IRQ_RFU12     12
#define VR41XX_IRQ_PIU       13
#define VR41XX_IRQ_AIU       14
#define VR41XX_IRQ_KIU       15
#define VR41XX_IRQ_GIU       16  /* Cascade to GIU IRQs (40-71) */
#define VR41XX_IRQ_SIU       17
#define VR41XX_IRQ_WRBERR    18
#define VR41XX_IRQ_SOFT      19
#define VR41XX_IRQ_RFU20     20
#define VR41XX_IRQ_DOZEPIU   21
#define VR41XX_IRQ_RFU22     22
#define VR41XX_IRQ_RFU23     23
#define VR41XX_IRQ_RTCL2     24  /* Use VR41XX_IRQ_INT2 instead. */
#define VR41XX_IRQ_LED       25
#define VR41XX_IRQ_HSP       26  /* Use VR41XX_IRQ_INT3 instead. */
#define VR41XX_IRQ_TCLK      27
#define VR41XX_IRQ_FIR       28
#define VR41XX_IRQ_DSIU      29
#define VR41XX_IRQ_RFU30     30
#define VR41XX_IRQ_RFU31     31
#define VR41XX_IRQ_RFU32     32
#define VR41XX_IRQ_RFU33     33
#define VR41XX_IRQ_RFU34     34
#define VR41XX_IRQ_RFU35     35
#define VR41XX_IRQ_RFU36     36
#define VR41XX_IRQ_RFU37     37
#define VR41XX_IRQ_RFU38     38
#define VR41XX_IRQ_RFU39     39

/* Cascaded from VR41XX_IRQ_GIU */
#define VR41XX_IRQ_GPIO0     40
#define VR41XX_IRQ_GPIO1     41
#define VR41XX_IRQ_GPIO2     42
#define VR41XX_IRQ_GPIO3     43
#define VR41XX_IRQ_GPIO4     44
#define VR41XX_IRQ_GPIO5     45
#define VR41XX_IRQ_GPIO6     46
#define VR41XX_IRQ_GPIO7     47
#define VR41XX_IRQ_GPIO8     48
#define VR41XX_IRQ_GPIO9     49
#define VR41XX_IRQ_GPIO10    50
#define VR41XX_IRQ_GPIO11    51
#define VR41XX_IRQ_GPIO12    52
#define VR41XX_IRQ_GPIO13    53
#define VR41XX_IRQ_GPIO14    54
#define VR41XX_IRQ_GPIO15    55
#define VR41XX_IRQ_GPIO16    56
#define VR41XX_IRQ_GPIO17    57
#define VR41XX_IRQ_GPIO18    58
#define VR41XX_IRQ_GPIO19    59
#define VR41XX_IRQ_GPIO20    60
#define VR41XX_IRQ_GPIO21    61
#define VR41XX_IRQ_GPIO22    62
#define VR41XX_IRQ_GPIO23    63
#define VR41XX_IRQ_GPIO24    64
#define VR41XX_IRQ_GPIO25    65
#define VR41XX_IRQ_GPIO26    66
#define VR41XX_IRQ_GPIO27    67
#define VR41XX_IRQ_GPIO28    68
#define VR41XX_IRQ_GPIO29    69
#define VR41XX_IRQ_GPIO30    70
#define VR41XX_IRQ_GPIO31    71

// Alternative to above GPIO IRQ defines
#define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin))

#define VR41XX_SYSINT1_IRQ_BASE 8
#define VR41XX_SYSINT2_IRQ_BASE 24
#define VR41XX_GIUINTL_IRQ_BASE 40
#define VR41XX_GIUINTH_IRQ_BASE 56

#ifndef _LANGUAGE_ASSEMBLY
#define __preg8		(volatile unsigned char*)
#define __preg16	(volatile unsigned short*)
#define __preg32	(volatile unsigned int*)
#else
#define __preg8
#define __preg16
#define __preg32
#endif

/*
 * Embedded CPU peripheral registers
 */

/* Bus Control Unit (BCU) */
#define VR41XX_BCUCNTREG1	__preg16(KSEG1 + 0x0B000000)	/* BCU Control Register 1 (R/W) */
#define VR41XX_BCUCNTREG2	__preg16(KSEG1 + 0x0B000002)	/* BCU Control Register 2 (R/W) */
#define VR41XX_BCUSPEEDREG	__preg16(KSEG1 + 0x0B00000A)	/* BCU Access Cycle Change Register (R/W) */
#define VR41XX_BCUERRSTREG	__preg16(KSEG1 + 0x0B00000C)	/* BCU BUS ERROR Status Register (R/W) */
#define VR41XX_BCURFCNTREG	__preg16(KSEG1 + 0x0B00000E)	/* BCU Refresh Control Register (R/W) */
#define VR41XX_REVIDREG		__preg16(KSEG1 + 0x0B000010)	/* Revision ID Register (R) */
#define VR41XX_BCURFCOUNTREG	__preg16(KSEG1 + 0x0B000012)	/* BCU Refresh Count Register (R/W) */
#define VR41XX_CLKSPEEDREG	__preg16(KSEG1 + 0x0B000014)	/* Clock Speed Register (R) */
#define VR41XX_BCUCNTREG3	__preg16(KSEG1 + 0x0B000016)	/* BCU Control Register 3 (R/W) */

/* DMA Address Unit (DMAAU) */
#define VR41XX_AIUIBALREG	__preg16(KSEG1 + 0x0B000020)	/* AIU IN DMA Base Address Register Low (R/W) */
#define VR41XX_AIUIBAHREG	__preg16(KSEG1 + 0x0B000022)	/* AIU IN DMA Base Address Register High (R/W) */
#define VR41XX_AIUIALREG	__preg16(KSEG1 + 0x0B000024)	/* AIU IN DMA Address Register Low (R/W) */
#define VR41XX_AIUIAHREG	__preg16(KSEG1 + 0x0B000026)	/* AIU IN DMA Address Register High (R/W) */
#define VR41XX_AIUOBALREG	__preg16(KSEG1 + 0x0B000028)	/* AIU OUT DMA Base Address Register Low (R/W) */
#define VR41XX_AIUOBAHREG	__preg16(KSEG1 + 0x0B00002A)	/* AIU OUT DMA Base Address Register High (R/W) */
#define VR41XX_AIUOALREG	__preg16(KSEG1 + 0x0B00002C)	/* AIU OUT DMA Address Register Low (R/W) */
#define VR41XX_AIUOAHREG	__preg16(KSEG1 + 0x0B00002E)	/* AIU OUT DMA Address Register High (R/W) */
#define VR41XX_FIRBALREG	__preg16(KSEG1 + 0x0B000030)	/* FIR DMA Base Address Register Low (R/W) */
#define VR41XX_FIRBAHREG	__preg16(KSEG1 + 0x0B000032)	/* FIR DMA Base Address Register High (R/W) */
#define VR41XX_FIRALREG		__preg16(KSEG1 + 0x0B000034)	/* FIR DMA Address Register Low (R/W) */
#define VR41XX_FIRAHREG		__preg16(KSEG1 + 0x0B000036)	/* FIR DMA Address Register High (R/W) */

/* DMA Control Unit (DCU) */
#define VR41XX_DMARSTREG	__preg16(KSEG1 + 0x0B000040)	/* DMA Reset Register (R/W) */
#define VR41XX_DMAIDLEREG	__preg16(KSEG1 + 0x0B000042)	/* DMA Idle Register (R) */
#define VR41XX_DMASENREG	__preg16(KSEG1 + 0x0B000044)	/* DMA Sequencer Enable Register (R/W) */
#define VR41XX_DMAMSKREG	__preg16(KSEG1 + 0x0B000046)	/* DMA Mask Register (R/W) */
#define VR41XX_DMAREQREG	__preg16(KSEG1 + 0x0B000048)	/* DMA Request Register (R) */
#define VR41XX_TDREG		__preg16(KSEG1 + 0x0B00004A)	/* Transfer Direction Register (R/W) */

/* Clock Mask Unit (CMU) */
#define VR41XX_CMUCLKMSK	__preg16(KSEG1 + 0x0B000060)	/* CMU Clock Mask Register (R/W) */
#define VR41XX_CMUCLKMSK_MSKPIU		0x0001
#define VR41XX_CMUCLKMSK_MSKSIU		0x0002
#define VR41XX_CMUCLKMSK_MSKAIU		0x0004
#define VR41XX_CMUCLKMSK_MSKKIU		0x0008
#define VR41XX_CMUCLKMSK_MSKFIR		0x0010
#define VR41XX_CMUCLKMSK_MSKDSIU       	0x0020
#define VR41XX_CMUCLKMSK_MSKSSIU	0x0100
#define VR41XX_CMUCLKMSK_MSKSHSP	0x0200
#define VR41XX_CMUCLKMSK_MSKFFIR	0x0400

#ifndef _LANGUAGE_ASSEMBLY
extern void vr4111_clock_supply(unsigned short mask);
extern void vr4111_clock_mask(unsigned short mask);
#endif

/* Interrupt Control Unit (ICU) */
#define VR41XX_SYSINT1REG	__preg16(KSEG1 + 0x0B000080)	/* Level 1 System interrupt register 1 (R) */
#define VR41XX_PIUINTREGro	__preg16(KSEG1 + 0x0B000082)	/* Level 2 PIU interrupt register (R) */
#define VR41XX_AIUINTREG	__preg16(KSEG1 + 0x0B000084)	/* Level 2 AIU interrupt register (R) */
#define VR41XX_KIUINTREG	__preg16(KSEG1 + 0x0B000086)	/* Level 2 KIU interrupt register (R) */
#define VR41XX_GIUINTLREG	__preg16(KSEG1 + 0x0B000088)	/* Level 2 GIU interrupt register Low (R) */
#define VR41XX_DSIUINTREG	__preg16(KSEG1 + 0x0B00008A)	/* Level 2 DSIU interrupt register (R) */
#define VR41XX_MSYSINT1REG	__preg16(KSEG1 + 0x0B00008C)	/* Level 1 mask system interrupt register 1 (R/W) */
#define VR41XX_MPIUINTREG	__preg16(KSEG1 + 0x0B00008E)	/* Level 2 mask PIU interrupt register (R/W) */
#define VR41XX_MAIUINTREG	__preg16(KSEG1 + 0x0B000090)	/* Level 2 mask AIU interrupt register (R/W) */
#define VR41XX_MKIUINTREG	__preg16(KSEG1 + 0x0B000092)	/* Level 2 mask KIU interrupt register (R/W) */
#define VR41XX_MGIUINTLREG	__preg16(KSEG1 + 0x0B000094)	/* Level 2 mask GIU interrupt register Low (R/W) */
#define VR41XX_MDSIUINTREG	__preg16(KSEG1 + 0x0B000096)	/* Level 2 mask DSIU interrupt register (R/W) */
#define VR41XX_NMIREG		__preg16(KSEG1 + 0x0B000098)	/* NMI register (R/W) */
#define VR41XX_SOFTINTREG	__preg16(KSEG1 + 0x0B00009A)	/* Software interrupt register (R/W) */
#define VR41XX_SYSINT2REG	__preg16(KSEG1 + 0x0B000200)	/* Level 1 System interrupt register 2 (R) */
#define VR41XX_GIUINTHREG	__preg16(KSEG1 + 0x0B000202)	/* Level 2 GIU interrupt register High (R) */
#define VR41XX_FIRINTREG	__preg16(KSEG1 + 0x0B000204)	/* Level 2 FIR interrupt register (R) */
#define VR41XX_MSYSINT2REG	__preg16(KSEG1 + 0x0B000206)	/* Level 1 mask system interrupt register 2 (R/W) */
#define VR41XX_MGIUINTHREG	__preg16(KSEG1 + 0x0B000208)	/* Level 2 mask GIU interrupt register High (R/W) */
#define VR41XX_MFIRINTREG	__preg16(KSEG1 + 0x0B00020A)	/* Level 2 mask FIR interrupt register (R/W) */

/* Power Management Unit (PMU) */
#define VR41XX_PMUINTREG	__preg16(KSEG1 + 0x0B0000A0)	/* PMU Status Register (R/W) */
#define VR41XX_PMUCNTREG	__preg16(KSEG1 + 0x0B0000A2)	/* PMU Control Register (R/W) */
#define VR41XX_PMUINT2REG	__preg16(KSEG1 + 0x0B0000A4)	/* PMU Interrupt/Status 2 Register (R/W) */
#define VR41XX_PMUCNT2REG	__preg16(KSEG1 + 0x0B0000A6)	/* PMU Control 2 Resister (R/W) */
#define VR41XX_PMUWAITREG	__preg16(KSEG1 + 0x0B0000A8)	/* PMU Wait Counter Register (R/W) */

#define VR41XX_PMUINT_POWERSW  0x1	/* Power switch */
#define VR41XX_PMUINT_BATT     0x2	/* Low batt during normal operation */
#define VR41XX_PMUINT_DEADMAN  0x4	/* Deadman's switch */
#define VR41XX_PMUINT_RESET    0x8	/* Reset switch */
#define VR41XX_PMUINT_RTCRESET 0x10	/* RTC Reset */
#define VR41XX_PMUINT_TIMEOUT  0x20	/* HAL Timer Reset */
#define VR41XX_PMUINT_BATTLOW  0x100	/* Battery low */
#define VR41XX_PMUINT_RTC      0x200	/* RTC Alarm */
#define VR41XX_PMUINT_DCD      0x400	/* DCD# */
#define VR41XX_PMUINT_GPIO0    0x1000	/* GPIO0 */
#define VR41XX_PMUINT_GPIO1    0x2000	/* GPIO1 */
#define VR41XX_PMUINT_GPIO2    0x4000	/* GPIO2 */
#define VR41XX_PMUINT_GPIO3    0x8000	/* GPIO3 */

/* Real Time Clock Unit (RTC) */
#define VR41XX_ETIMELREG	__preg16(KSEG1 + 0x0B0000C0)	/* Elapsed Time L Register (R/W) */
#define VR41XX_ETIMEMREG	__preg16(KSEG1 + 0x0B0000C2)	/* Elapsed Time M Register (R/W) */
#define VR41XX_ETIMEHREG	__preg16(KSEG1 + 0x0B0000C4)	/* Elapsed Time H Register (R/W) */
#define VR41XX_ECMPLREG		__preg16(KSEG1 + 0x0B0000C8)	/* Elapsed Compare L Register (R/W) */
#define VR41XX_ECMPMREG		__preg16(KSEG1 + 0x0B0000CA)	/* Elapsed Compare M Register (R/W) */
#define VR41XX_ECMPHREG		__preg16(KSEG1 + 0x0B0000CC)	/* Elapsed Compare H Register (R/W) */
#define VR41XX_RTCL1LREG	__preg16(KSEG1 + 0x0B0000D0)	/* RTC Long 1 L Register (R/W) */
#define VR41XX_RTCL1HREG	__preg16(KSEG1 + 0x0B0000D2)	/* RTC Long 1 H Register (R/W) */
#define VR41XX_RTCL1CNTLREG	__preg16(KSEG1 + 0x0B0000D4)	/* RTC Long 1 Count L Register (R) */
#define VR41XX_RTCL1CNTHREG	__preg16(KSEG1 + 0x0B0000D6)	/* RTC Long 1 Count H Register (R) */
#define VR41XX_RTCL2LREG	__preg16(KSEG1 + 0x0B0000D8)	/* RTC Long 2 L Register (R/W) */
#define VR41XX_RTCL2HREG	__preg16(KSEG1 + 0x0B0000DA)	/* RTC Long 2 H Register (R/W) */
#define VR41XX_RTCL2CNTLREG	__preg16(KSEG1 + 0x0B0000DC)	/* RTC Long 2 Count L Register (R) */
#define VR41XX_RTCL2CNTHREG	__preg16(KSEG1 + 0x0B0000DE)	/* RTC Long 2 Count H Register (R) */
#define VR41XX_TCLKLREG		__preg16(KSEG1 + 0x0B0001C0)	/* TCLK L Register (R/W) */
#define VR41XX_TCLKHREG		__preg16(KSEG1 + 0x0B0001C2)	/* TCLK H Register (R/W) */
#define VR41XX_TCLKCNTLREG	__preg16(KSEG1 + 0x0B0001C4)	/* TCLK Count L Register (R) */
#define VR41XX_TCLKCNTHREG	__preg16(KSEG1 + 0x0B0001C6)	/* TCLK Count H Register (R) */
#define VR41XX_RTCINTREG	__preg16(KSEG1 + 0x0B0001DE)	/* RTC Interrupt Register (R/W) */

/* Deadman's Switch Unit (DSU) */
#define VR41XX_DSUCNTREG	__preg16(KSEG1 + 0x0B0000E0)	/* DSU Control Register (R/W) */
#define VR41XX_DSUSETREG	__preg16(KSEG1 + 0x0B0000E2)	/* DSU Dead Time Set Register (R/W) */
#define VR41XX_DSUCLRREG	__preg16(KSEG1 + 0x0B0000E4)	/* DSU Clear Register (W) */
#define VR41XX_DSUTIMREG	__preg16(KSEG1 + 0x0B0000E6)	/* DSU Elapsed Time Register (R/W) */

/* General Purpose I/O Unit (GIU) */
#define VR41XX_GIUIOSELL	__preg16(KSEG1 + 0x0B000100)	/* GPIO Input/Output Select Register L (R/W) */
#define VR41XX_GIUIOSELH	__preg16(KSEG1 + 0x0B000102)	/* GPIO Input/Output Select Register H (R/W) */
#define VR41XX_GIUPIODL		__preg16(KSEG1 + 0x0B000104)	/* GPIO Port Input/Output Data Register L (R/W) */
#define VR41XX_GIUPIODL_GPIO15  0x8000
#define VR41XX_GIUPIODL_GPIO14  0x4000
#define VR41XX_GIUPIODL_GPIO13  0x2000
#define VR41XX_GIUPIODL_GPIO12  0x1000
#define VR41XX_GIUPIODL_GPIO11  0x0800
#define VR41XX_GIUPIODL_GPIO10  0x0400
#define VR41XX_GIUPIODL_GPIO9  0x0200
#define VR41XX_GIUPIODL_GPIO8  0x0100
#define VR41XX_GIUPIODL_GPIO7  0x0080
#define VR41XX_GIUPIODL_GPIO6  0x0040
#define VR41XX_GIUPIODL_GPIO5  0x0020
#define VR41XX_GIUPIODL_GPIO4  0x0010
#define VR41XX_GIUPIODL_GPIO3  0x0008
#define VR41XX_GIUPIODL_GPIO2  0x0004
#define VR41XX_GIUPIODL_GPIO1  0x0002
#define VR41XX_GIUPIODL_GPIO0  0x0001
#define VR41XX_GIUPIODH		__preg16(KSEG1 + 0x0B000106)	/* GPIO Port Input/Output Data Register H (R/W) */
#define VR41XX_GIUPIODH_GPIO31  0x8000
#define VR41XX_GIUPIODH_GPIO30  0x4000
#define VR41XX_GIUPIODH_GPIO29  0x2000
#define VR41XX_GIUPIODH_GPIO28  0x1000
#define VR41XX_GIUPIODH_GPIO27  0x0800
#define VR41XX_GIUPIODH_GPIO26  0x0400
#define VR41XX_GIUPIODH_GPIO25  0x0200
#define VR41XX_GIUPIODH_GPIO24  0x0100
#define VR41XX_GIUPIODH_GPIO23  0x0080
#define VR41XX_GIUPIODH_GPIO22  0x0040
#define VR41XX_GIUPIODH_GPIO21  0x0020
#define VR41XX_GIUPIODH_GPIO20  0x0010
#define VR41XX_GIUPIODH_GPIO19  0x0008
#define VR41XX_GIUPIODH_GPIO18  0x0004
#define VR41XX_GIUPIODH_GPIO17  0x0002
#define VR41XX_GIUPIODH_GPIO16  0x0001
#define VR41XX_GIUINTSTATL	__preg16(KSEG1 + 0x0B000108)	/* GPIO Interrupt Status Register L (R/W) */
#define VR41XX_GIUINTSTATH	__preg16(KSEG1 + 0x0B00010A)	/* GPIO Interrupt Status Register H (R/W) */
#define VR41XX_GIUINTENL	__preg16(KSEG1 + 0x0B00010C)	/* GPIO Interrupt Enable Register L (R/W) */
#define VR41XX_GIUINTENH	__preg16(KSEG1 + 0x0B00010E)	/* GPIO Interrupt Enable Register H (R/W) */
#define VR41XX_GIUINTTYPL	__preg16(KSEG1 + 0x0B000110)	/* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */
#define VR41XX_GIUINTTYPH	__preg16(KSEG1 + 0x0B000112)	/* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */
#define VR41XX_GIUINTALSELL	__preg16(KSEG1 + 0x0B000114)	/* GPIO Interrupt Active Level Select Register L (R/W) */
#define VR41XX_GIUINTALSELH	__preg16(KSEG1 + 0x0B000116)	/* GPIO Interrupt Active Level Select Register H (R/W) */
#define VR41XX_GIUINTHTSELL	__preg16(KSEG1 + 0x0B000118)	/* GPIO Interrupt Hold/Through Select Register L (R/W) */
#define VR41XX_GIUINTHTSELH	__preg16(KSEG1 + 0x0B00011A)	/* GPIO Interrupt Hold/Through Select Register H (R/W) */

#define VR41XX_GIUPODATL	__preg16(KSEG1 + 0x0B00011C)	/* GPIO Port Output Data Register L (R/W) */
#define VR41XX_GIUPODATL_GPIO47  0x8000
#define VR41XX_GIUPODATL_GPIO46  0x4000
#define VR41XX_GIUPODATL_GPIO45  0x2000
#define VR41XX_GIUPODATL_GPIO44  0x1000
#define VR41XX_GIUPODATL_GPIO43  0x0800
#define VR41XX_GIUPODATL_GPIO42  0x0400
#define VR41XX_GIUPODATL_GPIO41  0x0200
#define VR41XX_GIUPODATL_GPIO40  0x0100
#define VR41XX_GIUPODATL_GPIO39  0x0080
#define VR41XX_GIUPODATL_GPIO38  0x0040
#define VR41XX_GIUPODATL_GPIO37  0x0020
#define VR41XX_GIUPODATL_GPIO36  0x0010
#define VR41XX_GIUPODATL_GPIO35  0x0008
#define VR41XX_GIUPODATL_GPIO34  0x0004
#define VR41XX_GIUPODATL_GPIO33  0x0002
#define VR41XX_GIUPODATL_GPIO32  0x0001
#define VR41XX_GIUPODATL_PODAT15  0x8000
#define VR41XX_GIUPODATL_PODAT14  0x4000
#define VR41XX_GIUPODATL_PODAT13  0x2000
#define VR41XX_GIUPODATL_PODAT12  0x1000
#define VR41XX_GIUPODATL_PODAT11  0x0800
#define VR41XX_GIUPODATL_PODAT10  0x0400
#define VR41XX_GIUPODATL_PODAT9  0x0200
#define VR41XX_GIUPODATL_PODAT8  0x0100
#define VR41XX_GIUPODATL_PODAT7  0x0080
#define VR41XX_GIUPODATL_PODAT6  0x0040
#define VR41XX_GIUPODATL_PODAT5  0x0020
#define VR41XX_GIUPODATL_PODAT4  0x0010
#define VR41XX_GIUPODATL_PODAT3  0x0008
#define VR41XX_GIUPODATL_PODAT2  0x0004
#define VR41XX_GIUPODATL_PODAT1  0x0002
#define VR41XX_GIUPODATL_PODAT0  0x0001
#define VR41XX_GIUPODATH	__preg16(KSEG1 + 0x0B00011E)	/* GPIO Port Output Data Register H (R/W) */
#define VR41XX_GIUPODATH_GPIO51  0x0008
#define VR41XX_GIUPODATH_GPIO50  0x0004
#define VR41XX_GIUPODATH_GPIO49  0x0002
#define VR41XX_GIUPODATH_GPIO48  0x0001
#define VR41XX_GIUPODATH_PODAT3  0x0008
#define VR41XX_GIUPODATH_PODAT2  0x0004
#define VR41XX_GIUPODATH_PODAT1  0x0002
#define VR41XX_GIUPODATH_PODAT0  0x0001
#define VR41XX_GIUUSEUPDN	__preg16(KSEG1 + 0x0B0002E0)	/* GPIO Pullup/Down User Register (R/W) */
#define VR41XX_GIUTERMUPDN	__preg16(KSEG1 + 0x0B0002E2)	/* GPIO Terminal Pullup/Down Register (R/W) */
#define VR41XX_SECIRQMASKL	VR41XX_GIUINTENL
#define VR41XX_SECIRQMASKH	VR41XX_GIUINTENH

/* Touch Panel Interface Unit (PIU) */
#define VR41XX_PIUCNTREG	__preg16(KSEG1 + 0x0B000122)	/* PIU Control register (R/W) */
#define VR41XX_PIUCNTREG_PIUSEQEN	0x0004
#define VR41XX_PIUCNTREG_PIUPWR		0x0002
#define VR41XX_PIUCNTREG_PADRST		0x0001

#define VR41XX_PIUINTREG	__preg16(KSEG1 + 0x0B000124)	/* PIU Interrupt cause register (R/W) */
#define VR41XX_PIUINTREG_OVP		0x8000
#define VR41XX_PIUINTREG_PADCMD		0x0040
#define VR41XX_PIUINTREG_PADADP		0x0020
#define VR41XX_PIUINTREG_PADPAGE1	0x0010
#define VR41XX_PIUINTREG_PADPAGE0	0x0008
#define VR41XX_PIUINTREG_PADDLOST	0x0004
#define VR41XX_PIUINTREG_PENCHG		0x0001

#define VR41XX_PIUSIVLREG	__preg16(KSEG1 + 0x0B000126)	/* PIU Data sampling interval register (R/W) */
#define VR41XX_PIUSTBLREG	__preg16(KSEG1 + 0x0B000128)	/* PIU A/D converter start delay register (R/W) */
#define VR41XX_PIUCMDREG	__preg16(KSEG1 + 0x0B00012A)	/* PIU A/D command register (R/W) */
#define VR41XX_PIUASCNREG	__preg16(KSEG1 + 0x0B000130)	/* PIU A/D port scan register (R/W) */
#define VR41XX_PIUAMSKREG	__preg16(KSEG1 + 0x0B000132)	/* PIU A/D scan mask register (R/W) */
#define VR41XX_PIUCIVLREG	__preg16(KSEG1 + 0x0B00013E)	/* PIU Check interval register (R) */
#define VR41XX_PIUPB00REG	__preg16(KSEG1 + 0x0B0002A0)	/* PIU Page 0 Buffer 0 register (R/W) */
#define VR41XX_PIUPB01REG	__preg16(KSEG1 + 0x0B0002A2)	/* PIU Page 0 Buffer 1 register (R/W) */
#define VR41XX_PIUPB02REG	__preg16(KSEG1 + 0x0B0002A4)	/* PIU Page 0 Buffer 2 register (R/W) */
#define VR41XX_PIUPB03REG	__preg16(KSEG1 + 0x0B0002A6)	/* PIU Page 0 Buffer 3 register (R/W) */
#define VR41XX_PIUPB10REG	__preg16(KSEG1 + 0x0B0002A8)	/* PIU Page 1 Buffer 0 register (R/W) */
#define VR41XX_PIUPB11REG	__preg16(KSEG1 + 0x0B0002AA)	/* PIU Page 1 Buffer 1 register (R/W) */
#define VR41XX_PIUPB12REG	__preg16(KSEG1 + 0x0B0002AC)	/* PIU Page 1 Buffer 2 register (R/W) */
#define VR41XX_PIUPB13REG	__preg16(KSEG1 + 0x0B0002AE)	/* PIU Page 1 Buffer 3 register (R/W) */
#define VR41XX_PIUAB0REG	__preg16(KSEG1 + 0x0B0002B0)	/* PIU A/D scan Buffer 0 register (R/W) */
#define VR41XX_PIUAB1REG	__preg16(KSEG1 + 0x0B0002B2)	/* PIU A/D scan Buffer 1 register (R/W) */
#define VR41XX_PIUAB2REG	__preg16(KSEG1 + 0x0B0002B4)	/* PIU A/D scan Buffer 2 register (R/W) */
#define VR41XX_PIUAB3REG	__preg16(KSEG1 + 0x0B0002B6)	/* PIU A/D scan Buffer 3 register (R/W) */
#define VR41XX_PIUPB04REG	__preg16(KSEG1 + 0x0B0002BC)	/* PIU Page 0 Buffer 4 register (R/W) */
#define VR41XX_PIUPB14REG	__preg16(KSEG1 + 0x0B0002BE)	/* PIU Page 1 Buffer 4 register (R/W) */

/* Audio Interface Unit (AIU) */
#define VR41XX_MDMADATREG	__preg16(KSEG1 + 0x0B000160)	/* Mike DMA Data Register (R/W) */
#define VR41XX_SDMADATREG	__preg16(KSEG1 + 0x0B000162)	/* Speaker DMA Data Register (R/W) */
#define VR41XX_SODATREG		__preg16(KSEG1 + 0x0B000166)	/* Speaker Output Data Register (R/W) */
#define VR41XX_SCNTREG		__preg16(KSEG1 + 0x0B000168)	/* Speaker Output Control Register (R/W) */
#define VR41XX_SCNVRREG		__preg16(KSEG1 + 0x0B00016A)	/* Speaker Conversion Rate Register (R/W) */
#define VR41XX_MIDATREG		__preg16(KSEG1 + 0x0B000170)	/* Mike Input Data Register (R/W) */
#define VR41XX_MCNTREG		__preg16(KSEG1 + 0x0B000172)	/* Mike Input Control Register (R/W) */
#define VR41XX_MCNVRREG		__preg16(KSEG1 + 0x0B000174)	/* Mike Conversion Rate Register (R/W) */
#define VR41XX_DVALIDREG	__preg16(KSEG1 + 0x0B000178)	/* Data Valid Register (R/W) */
#define VR41XX_SEQREG		__preg16(KSEG1 + 0x0B00017A)	/* Sequential Register (R/W) */
#define VR41XX_INTREG		__preg16(KSEG1 + 0x0B00017C)	/* Interrupt Register (R/W) */

/* Keyboard Interface Unit (KIU) */
#define VR41XX_KIUDAT0		__preg16(KSEG1 + 0x0B000180)	/* KIU Data0 Register (R/W) */
#define VR41XX_KIUDAT1		__preg16(KSEG1 + 0x0B000182)	/* KIU Data1 Register (R/W) */
#define VR41XX_KIUDAT2		__preg16(KSEG1 + 0x0B000184)	/* KIU Data2 Register (R/W) */
#define VR41XX_KIUDAT3		__preg16(KSEG1 + 0x0B000186)	/* KIU Data3 Register (R/W) */
#define VR41XX_KIUDAT4		__preg16(KSEG1 + 0x0B000188)	/* KIU Data4 Register (R/W) */
#define VR41XX_KIUDAT5		__preg16(KSEG1 + 0x0B00018A)	/* KIU Data5 Register (R/W) */
#define VR41XX_KIUSCANREP	__preg16(KSEG1 + 0x0B000190)	/* KIU Scan/Repeat Register (R/W) */
#define VR41XX_KIUSCANREP_KEYEN      0x8000
#define VR41XX_KIUSCANREP_SCANSTP    0x0008
#define VR41XX_KIUSCANREP_SCANSTART  0x0004
#define VR41XX_KIUSCANREP_ATSTP      0x0002
#define VR41XX_KIUSCANREP_ATSCAN     0x0001
#define VR41XX_KIUSCANS		__preg16(KSEG1 + 0x0B000192)	/* KIU Scan Status Register (R) */
#define VR41XX_KIUWKS		__preg16(KSEG1 + 0x0B000194)	/* KIU Wait Keyscan Stable Register (R/W) */
#define VR41XX_KIUWKI		__preg16(KSEG1 + 0x0B000196)	/* KIU Wait Keyscan Interval Register (R/W) */
#define VR41XX_KIUINT		__preg16(KSEG1 + 0x0B000198)	/* KIU Interrupt Register (R/W) */
#define VR41XX_KIUINT_KDATLOST       0x0004
#define VR41XX_KIUINT_KDATRDY        0x0002
#define VR41XX_KIUINT_SCANINT        0x0001
#define VR41XX_KIURST		__preg16(KSEG1 + 0x0B00019A)	/* KIU Reset Register (W) */
#define VR41XX_KIUGPEN		__preg16(KSEG1 + 0x0B00019C)	/* KIU General Purpose Output Enable (R/W) */
#define VR41XX_SCANLINE		__preg16(KSEG1 + 0x0B00019E)	/* KIU Scan Line Register (R/W) */

/* Debug Serial Interface Unit (DSIU) */
#define VR41XX_PORTREG		__preg16(KSEG1 + 0x0B0001A0)	/* Port Change Register (R/W) */
#define VR41XX_MODEMREG		__preg16(KSEG1 + 0x0B0001A2)	/* Modem Control Register (R) */
#define VR41XX_ASIM00REG	__preg16(KSEG1 + 0x0B0001A4)	/* Asynchronous Mode 0 Register (R/W) */
#define VR41XX_ASIM01REG	__preg16(KSEG1 + 0x0B0001A6)	/* Asynchronous Mode 1 Register (R/W) */
#define VR41XX_RXB0RREG		__preg16(KSEG1 + 0x0B0001A8)	/* Receive Buffer Register (Extended) (R) */
#define VR41XX_RXB0LREG		__preg16(KSEG1 + 0x0B0001AA)	/* Receive Buffer Register (R) */
#define VR41XX_TXS0RREG		__preg16(KSEG1 + 0x0B0001AC)	/* Transmit Data Register (Extended) (R/W) */
#define VR41XX_TXS0LREG		__preg16(KSEG1 + 0x0B0001AE)	/* Transmit Data Register (R/W) */
#define VR41XX_ASIS0REG		__preg16(KSEG1 + 0x0B0001B0)	/* Status Register (R) */
#define VR41XX_INTR0REG		__preg16(KSEG1 + 0x0B0001B2)	/* Debug SIU Interrupt Register (R/W) */
#define VR41XX_BPRM0REG		__preg16(KSEG1 + 0x0B0001B6)	/* Baud rate Generator Prescaler Mode Register (R/W) */
#define VR41XX_DSIURESETREG	__preg16(KSEG1 + 0x0B0001B8)	/* Debug SIU Reset Register (R/W) */

/* LED Control Unit (LED) */
#define VR41XX_LEDHTSREG	__preg16(KSEG1 + 0x0B000240)	/* LED H Time Set register (R/W) */
#define VR41XX_LEDLTSREG	__preg16(KSEG1 + 0x0B000242)	/* LED L Time Set register (R/W) */
#define VR41XX_LEDCNTREG	__preg16(KSEG1 + 0x0B000248)	/* LED Control register (R/W) */
#define VR41XX_LEDASTCREG	__preg16(KSEG1 + 0x0B00024A)	/* LED Auto Stop Time Count register (R/W) */
#define VR41XX_LEDINTREG	__preg16(KSEG1 + 0x0B00024C)	/* LED Interrupt register (R/W) */

/* Serial Interface Unit (SIU) */
#define VR41XX_SIURB		__preg8(KSEG1 + 0x0C000000)	/* Receiver Buffer Register (Read) DLAB = 0 (R) */
#define VR41XX_SIUTH		__preg8(KSEG1 + 0x0C000000)	/* Transmitter Holding Register (Write) DLAB = 0 (W) */
#define VR41XX_SIUDLL		__preg8(KSEG1 + 0x0C000000)	/* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */
#define VR41XX_SIUIE		__preg8(KSEG1 + 0x0C000001)	/* Interrupt Enable DLAB = 0 (R/W) */
#define VR41XX_SIUDLM		__preg8(KSEG1 + 0x0C000001)	/* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */
#define VR41XX_SIUIID		__preg8(KSEG1 + 0x0C000002)	/* Interrupt Identification Register (Read) (R) */
#define VR41XX_SIUFC		__preg8(KSEG1 + 0x0C000002)	/* FIFO Control Register (Write) (W) */
#define VR41XX_SIULC		__preg8(KSEG1 + 0x0C000003)	/* Line Control Register (R/W) */
#define VR41XX_SIUMC		__preg8(KSEG1 + 0x0C000004)	/* MODEM Control Register (R/W) */
#define VR41XX_SIULS		__preg8(KSEG1 + 0x0C000005)	/* Line Status Register (R/W) */
#define VR41XX_SIUMS		__preg8(KSEG1 + 0x0C000006)	/* MODEM Status Register (R/W) */
#define VR41XX_SIUSC		__preg8(KSEG1 + 0x0C000007)	/* Scratch Register (R/W) */
#define VR41XX_SIUIRSEL		__preg8(KSEG1 + 0x0C000008)	/* SIU/FIR IrDA Selector (R/W) */
#define VR41XX_SIUIRSEL_SIRSEL   0x1
#define VR41XX_SIUIRSEL_IRUSESEL 0x2
#define VR41XX_SIURESET		__preg8(KSEG1 + 0x0C000009)	/* SIU Reset Register (R/W) */
#define VR41XX_SIUCSEL		__preg8(KSEG1 + 0x0C00000A)	/* SIU Echo-Back Control Register (R/W) */

/* Modem Interface Unit (HSP) (NEC56K core) */
#define VR41XX_HSPINIT		__preg16(KSEG1 + 0x0C000020)	/* HSP Initialize Register (R/W) */
#define VR41XX_HSPDATAL		__preg8(KSEG1 + 0x0C000022)	/* HSP Data Register L (R/W) */
#define VR41XX_HSPDATAH		__preg8(KSEG1 + 0x0C000023)	/* HSP Data Register H (R/W) */
#define VR41XX_HSPINDEX		__preg16(KSEG1 + 0x0C000024)	/* HSP Index Register (W) */
#define VR41XX_HSPID		__preg8(KSEG1 + 0x0C000028)	/* HSP ID Register (R) */
#define VR41XX_HSPPCS		__preg8(KSEG1 + 0x0C000029)	/* HSP I/O Address Program Confirmation Register (R) */
#define VR41XX_HSPPCTEL		__preg8(KSEG1 + 0x0C000029)	/* HSP Signature Checking Port (W) */

/* Fast IrDA Interface Unit (FIR) */
#define VR41XX_FRSTR		__preg16(KSEG1 + 0x0C000040)	/* FIR Reset register (R/W) */
#define VR41XX_DPINTR		__preg16(KSEG1 + 0x0C000042)	/* DMA Page Interrupt register (R/W) */
#define VR41XX_DPCNTR		__preg16(KSEG1 + 0x0C000044)	/* DMA Control register (R/W) */
#define VR41XX_TDR		__preg16(KSEG1 + 0x0C000050)	/* Transmit Data register (W) */
#define VR41XX_RDR		__preg16(KSEG1 + 0x0C000052)	/* Receive Data register (R) */
#define VR41XX_IMR		__preg16(KSEG1 + 0x0C000054)	/* Interrupt Mask register (R/W) */
#define VR41XX_FSR		__preg16(KSEG1 + 0x0C000056)	/* FIFO Setup register (R/W) */
#define VR41XX_IRSR1		__preg16(KSEG1 + 0x0C000058)	/* Infrared Setup register 1 (R/W) */
#define VR41XX_CRCSR		__preg16(KSEG1 + 0x0C00005C)	/* CRC Setup register (R/W) */
#define VR41XX_FIRCR		__preg16(KSEG1 + 0x0C00005E)	/* FIR Control register (R/W) */
#define VR41XX_MIRCR		__preg16(KSEG1 + 0x0C000060)	/* MIR Control register (R/W) */
#define VR41XX_DMACR		__preg16(KSEG1 + 0x0C000062)	/* DMA Control register (R/W) */
#define VR41XX_DMAER		__preg16(KSEG1 + 0x0C000064)	/* DMA Enable register (R/W) */
#define VR41XX_TXIR		__preg16(KSEG1 + 0x0C000066)	/* Transmit Indication register (R) */
#define VR41XX_RXIR		__preg16(KSEG1 + 0x0C000068)	/* Receive Indication register (R) */
#define VR41XX_IFR		__preg16(KSEG1 + 0x0C00006A)	/* Interrupt Flag register (R) */
#define VR41XX_RXSTS		__preg16(KSEG1 + 0x0C00006C)	/* Receive Status (R) */
#define VR41XX_TXFL		__preg16(KSEG1 + 0x0C00006E)	/* Transmit Frame Length (R/W) */
#define VR41XX_MRXF		__preg16(KSEG1 + 0x0C000070)	/* Maximum Receive Frame Length (R/W) */
#define VR41XX_RXFL		__preg16(KSEG1 + 0x0C000074)	/* Receive Frame Length (R) */

/* Is the rest of this file Clio-specific?  I think maybe, but I'm not sure. */

/* physical address spaces */
#define VR41XX_LCD             0x0a000000
#define VR41XX_INTERNAL_IO_2   0x0b000000
#define VR41XX_INTERNAL_IO_1   0x0c000000
#define VR41XX_ISA_MEM         0x10000000
#define VR41XX_ISA_IO          0x14000000
#define VR41XX_ROM             0x18000000

/* This is the base address for IO port decoding to which the 16 bit
 * IO port address is added.  Defining it to 0 will usually cause a
 * kernel oops any time port IO is attempted, which can be handy for
 * turning up parts of the kernel that make incorrect architecture
 * assumptions (by assuming that everything acts like a PC), but we
 * need it correctly defined to use the PCMCIA/CF controller: 
 */
#define VR41XX_PORT_BASE	(KSEG1 + VR41XX_ISA_IO)
#define VR41XX_ISAMEM_BASE	(KSEG1 + VR41XX_ISA_MEM)

#endif /* __ASM_VR41XX_VR41XX_H */

[Linux-mips-commits]CVS: linux/include/asm-mips bootinfo.h,1.9,1.10 irq.h,1.3,1.4

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv30742/include/asm-mips

Modified Files:
	bootinfo.h irq.h 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.



Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- bootinfo.h	2001/10/24 23:32:54	1.9
+++ bootinfo.h	2001/10/28 23:04:19	1.10
@@ -203,8 +203,9 @@
 #define MACH_NEC_OSPREY                0       /* Osprey eval board */
 #define MACH_NEC_EAGLE                 1       /* NEC Eagle board */
 #define MACH_NEC_KORVA                 2       /* NEC korva board */
+#define MACH_VADEM_CLIO_1000           3       /* Vadem Clio 1000 */
 
-#define GROUP_NEC_VR41XX_NAMES { "Osprey", "Eagle", "Korva" }
+#define GROUP_NEC_VR41XX_NAMES { "Osprey", "Eagle", "Korva", "Clio 1000" }
 
 /*
  * Valid machtype for group EE

Index: irq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/irq.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq.h	2001/08/25 02:19:28	1.3
+++ irq.h	2001/10/28 23:04:19	1.4
@@ -11,7 +11,7 @@
 
 #include <linux/config.h>
 
-#define NR_IRQS 64		/* Largest number of ints of all machines.  */
+#define NR_IRQS 128		/* Largest number of ints of all machines.  */
 
 #define TIMER_IRQ 0
 

[Linux-mips-commits]CVS: linux/arch/mips/vr4111/common Makefile,NONE,1.1 cmu.c,NONE,1.1 icu.c,NONE,1.1 int-handler.S,NONE,1.1 irq.c,NONE,1.1 power.c,NONE,1.1 serial.c,NONE,1.1 time.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4111/common
In directory usw-pr-cvs1:/tmp/cvs-serv30742/arch/mips/vr4111/common

Added Files:
	Makefile cmu.c icu.c int-handler.S irq.c power.c serial.c 
	time.c 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.



--- NEW FILE: Makefile ---
#
# Makefile for common code of NEC vr4111 based boards
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET:= vr4111.o

obj-y	 := irq.o int-handler.o icu.o serial.o time.o power.o cmu.o

include $(TOPDIR)/Rules.make

--- NEW FILE: cmu.c ---
/*
 * BRIEF MODULE DESCRIPTION
 *	NEC Vr4111 Clock Mask Unit routines.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 * Adapted to VR4111 from arch/mips/vr4122/common/cmu.c
 * by Jim Paris <ji...@jt...>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/config.h>
#include <asm/vr41xx.h>

void vr4111_clock_supply(unsigned short mask)
{
	*VR41XX_CMUCLKMSK |= mask;
}

void vr4111_clock_mask(unsigned short mask)
{
	*VR41XX_CMUCLKMSK &= ~mask;
}

--- NEW FILE: icu.c ---
/*
 * Interrupt dispatcher for VR4111 ICU.
 *
 * Based on arch/mips/vr4122/common/icu.c
 * Copyright 2001 MontaVista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 * Copyright 2001 Jim Paris <ji...@jt...>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/config.h>
#include <asm/io.h>
#include <asm/types.h>
#include <asm/vr41xx.h>

/*
 * Determine whether it's a SYSINT1, SYSINT2, GIUINTL, or GIUINTH
 * interrupt, set the base IRQ to the appropriate value and read the
 * status of the corresponding interrupt register, and then do a
 * binary search to find which actual IRQ occurred.  
 */

asmlinkage void int0_icu_irqdispatch(struct pt_regs *regs)
{
	u16 pend1, pend2;
	int irq;
	u16 search;

	pend1 = *VR41XX_SYSINT1REG & *VR41XX_MSYSINT1REG;
	pend2 = *VR41XX_SYSINT2REG & *VR41XX_MSYSINT2REG;

	if (pend1) {
		if ((pend1 & 0x01ff) == 0x0100) {
			/* Handle the GIU interrupt */
			pend1 = *VR41XX_GIUINTLREG & *VR41XX_MGIUINTLREG;
			pend2 = *VR41XX_GIUINTHREG & *VR41XX_MGIUINTHREG;
			if (pend1) {
				irq = VR41XX_GIUINTL_IRQ_BASE;
				search = pend1;
				/* ... fall through to search */
			} else if (pend2) {
				irq = VR41XX_GIUINTH_IRQ_BASE;
				search = pend2;
				/* ... fall through to search */
			} else {
				return;
			}
		}
		else {
			/* Not a GIU interrupt */
			irq = VR41XX_SYSINT1_IRQ_BASE;
			search = pend1;
			/* ... fall through to search */
		}
	} else if (pend2) {
		irq = VR41XX_SYSINT2_IRQ_BASE;
		search = pend2;
	   	/* ... fall through to search */
	} else {
		return;
	}

	if(search & 0xFF00) {
		search >>= 8;
		irq += 8;
   	}

	if(search & 0xF0) {
		search >>= 4;
		irq += 4;
   	}

	if(search & 0xC) {
		search >>= 2;
		irq += 2;
   	}

	if(search & 2) {
		irq += 1;
	}

	do_IRQ(irq, regs);
}





--- NEW FILE: int-handler.S ---
/*
 * BRIEF MODULE DESCRIPTION
 *	Interrupt dispatcher for NEC Vr4111 CPU core.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 * Adapted for VR4111 from arch/mips/vr4122/common/int-handler.S
 * by Jim Paris <ji...@jt...>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/stackframe.h>

#include <asm/vr41xx.h>
	
	.text
	.set	noreorder

	.align	5
	NESTED(vr4111_handle_int, PT_SIZE, ra)
	.set	noat
	SAVE_ALL
	CLI
	.set	at
	.set	noreorder

	/* Get a list of pending interrupts that are not disabled */
	mfc0	t0, CP0_CAUSE
	mfc0	t1, CP0_STATUS
	and	t0, t0, t1

	andi	t1, t0, CAUSEF_IP7	# timer interrupt
	beqz	t1, 1f
	li	a0, 7
	jal	ll_timer_interrupt
	move	a1, sp
	j	ret_from_irq

1:
	andi	t1, t0, 0x7800		# check for IP3-6
	beqz	t1, 2f

		andi	t1, t0, CAUSEF_IP3	# check for IP3 (rtc_long1)
		bnez	t1, handle_it
		li	a0, 3

		andi	t1, t0, CAUSEF_IP4	# check for IP4 (rtc_long2)
		bnez	t1, handle_it
		li	a0, 4

		andi	t1, t0, CAUSEF_IP5	# check for IP5 (hsp)
		bnez	t1, handle_it
		li	a0, 5

/* Int4 will never occur on the VR4111 (user manual, 7.3.6)
 *		andi	t1, t0, CAUSEF_IP6	# check for IP6 (Int4)
 *		bnez	t1, handle_it
 *		li	a0, 6
 */

2:
	andi	t1, t0, CAUSEF_IP2	# check for IP2 (all other interrupts)
	beqz	t1, 3f
	move	a0, sp
	jal	int0_icu_irqdispatch	# in C for implementation ease
	nop
	j	ret_from_irq
	nop

3:
	andi	t1, t0, CAUSEF_IP0	# check for IP0 (software 0)
	bnez	t1, handle_it
	li	a0, 0

	andi	t1, t0, CAUSEF_IP1	# check for IP1 (software 1)
	bnez	t1, handle_it
	li	a0, 1

	j	spurious_interrupt
	nop

handle_it:
	jal	do_IRQ
	move	a1, sp
	j	ret_from_irq

	END(vr4111_handle_int)

--- NEW FILE: irq.c ---
/*
 * arch/mips/vr4111/common/irq.c
 *
 * Copyright (C) 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * Copyright (C) 2001 Jim Paris <ji...@jt...>
 *
 * Credits to Bradley D. LaRonde and Michael Klar for writing the original
 * irq.c file which was derived from the common irq.c file.
 *	
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */
#include <linux/types.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/malloc.h>
#include <linux/random.h>

#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/gdb-stub.h>

#include <asm/vr41xx.h>

/*
 * Strategy:
 *
 * We essentially have three irq controllers, CPU, system, and gpio.
 *
 * CPU irq controller is taken care by arch/mips/kernel/irq_cpu.c and
 * CONFIG_IRQ_CPU config option.
 *
 * We here provide sys_irq and gpio_irq controller code.
 */

static int sys_irq_base;
static int gpio_irq_base;

/* ---------------------- sys irq ------------------------ */
static void
sys_irq_enable(unsigned int irq)
{
	if(irq==VR41XX_IRQ_DSIU)
		*VR41XX_MDSIUINTREG |= 0x0800;
	irq -= sys_irq_base;
	if (irq < 16) {
		*VR41XX_MSYSINT1REG |= (u16)(1 << irq);
	} else {
		irq -= 16;
		*VR41XX_MSYSINT2REG |= (u16)(1 << irq);
	}
}

static void
sys_irq_disable(unsigned int irq)
{
	if(irq==VR41XX_IRQ_DSIU)
		*VR41XX_MDSIUINTREG = 0;
	irq -= sys_irq_base;
	if (irq < 16) {
		*VR41XX_MSYSINT1REG &= ~((u16)(1 << irq));
	} else {
		irq -= 16;
		*VR41XX_MSYSINT2REG &= ~((u16)(1 << irq));
	}

}

static unsigned int
sys_irq_startup(unsigned int irq)
{
	sys_irq_enable(irq);
	return 0;
}

#define sys_irq_shutdown	sys_irq_disable
#define sys_irq_ack		sys_irq_disable
#define sys_irq_end		sys_irq_enable

static hw_irq_controller sys_irq_controller = {
	"vr4111_sys_irq",
	sys_irq_startup,
	sys_irq_shutdown,
	sys_irq_enable,
	sys_irq_disable,
	sys_irq_ack,
	sys_irq_end,
	NULL			/* no affinity stuff for UP */
};

/* ---------------------- gpio irq ------------------------ */
static void
gpio_irq_clear(unsigned int irq)
{
	/* clear interrupt if edge triggered; write a 1 to clear */
	irq -= gpio_irq_base;
	if (irq < 16) {
		if(*VR41XX_GIUINTTYPL & ((u16)1 << irq))
			*VR41XX_GIUINTSTATL = ((u16)1 << irq);
	} else {
		irq -= 16;
		if(*VR41XX_GIUINTTYPH & ((u16)1 << irq))
			*VR41XX_GIUINTSTATH = ((u16)1 << irq);
	}
}

static void
gpio_irq_enable(unsigned int irq)
{
	gpio_irq_clear(irq);

	irq -= gpio_irq_base;
	if (irq < 16) {
		*VR41XX_MGIUINTLREG |= (u16)(1 << irq);
	} else {
		irq -= 16;
		*VR41XX_MGIUINTHREG |= (u16)(1 << irq);
	}
}

static void
gpio_irq_disable(unsigned int irq)
{
	irq -= gpio_irq_base;
	if (irq < 16) {
		*VR41XX_MGIUINTLREG &= ~((u16)(1 << irq));
	} else {
		irq -= 16;
		*VR41XX_MGIUINTHREG &= ~((u16)(1 << irq));
	}
}

static unsigned int
gpio_irq_startup(unsigned int irq)
{
	gpio_irq_enable(irq);

	irq -= gpio_irq_base;
	if (irq < 16) {
		*VR41XX_GIUINTENL |= (u16)(1 << irq);
	} else {
		irq -= 16;
		*VR41XX_GIUINTENH |= (u16)(1 << irq);
	}

	return 0;
}

static void
gpio_irq_shutdown(unsigned int irq)
{
	gpio_irq_disable(irq);

	irq -= gpio_irq_base;
	if (irq < 16) {
		*VR41XX_GIUINTENL &= ~((u16)(1 << irq));
	} else {
		irq -= 16;
		*VR41XX_GIUINTENH &= ~((u16)(1 << irq));
	}
}

static void
gpio_irq_ack(unsigned int irq)
{
	gpio_irq_disable(irq);
	gpio_irq_clear(irq);
}

#define gpio_irq_end		gpio_irq_enable

static hw_irq_controller gpio_irq_controller = {
	"vr4111_gpio_irq",
	gpio_irq_startup,
	gpio_irq_shutdown,
	gpio_irq_enable,
	gpio_irq_disable,
	gpio_irq_ack,
	gpio_irq_end,
	NULL			/* no affinity stuff for UP */
};

/* ---------------------  IRQ init stuff ---------------------- */

extern asmlinkage void vr4111_handle_int(void);
extern void breakpoint(void);
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern void mips_cpu_irq_init(u32 irq_base);

static struct irqaction cascade = 
	{ no_action, SA_INTERRUPT, 0, "cascade", NULL, NULL };
static struct irqaction reserved = 
	{ no_action, SA_INTERRUPT, 0, "reserved", NULL, NULL };

void __init init_IRQ(void)
{
	int i;
	extern irq_desc_t irq_desc[];

	init_generic_irq();
	mips_cpu_irq_init(VR41XX_CPU_IRQ_BASE);

	/* init sys irqs */
	sys_irq_base = VR41XX_SYS_IRQ_BASE;
	for (i=sys_irq_base; i < sys_irq_base + VR41XX_NUM_SYS_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &sys_irq_controller;
	}

	/* init gpio irqs */
	gpio_irq_base = VR41XX_GPIO_IRQ_BASE;
	for (i=gpio_irq_base; i < gpio_irq_base + VR41XX_NUM_GPIO_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &gpio_irq_controller;
	}

	/* Default all ICU IRQs to off ... */
	*VR41XX_MSYSINT1REG = 0;
	*VR41XX_MSYSINT2REG = 0;
 
	/* We initialize the level 2 ICU registers to all bits disabled. */
	*VR41XX_MPIUINTREG = 0;
	*VR41XX_MAIUINTREG = 0;
	*VR41XX_MKIUINTREG = 0;
	*VR41XX_MDSIUINTREG = 0;
	*VR41XX_MFIRINTREG = 0;
	*VR41XX_MGIUINTLREG = 0;
	*VR41XX_MGIUINTHREG = 0;

	/* Disable and clear all GPIO interrupts */
	*VR41XX_GIUINTENL = 0;
	*VR41XX_GIUINTENH = 0;
	*VR41XX_GIUINTSTATL = 0xffff;
	*VR41XX_GIUINTSTATH = 0xffff;

	setup_irq(VR41XX_IRQ_INT0, &cascade);
	setup_irq(VR41XX_IRQ_GIU, &cascade);
	setup_irq(VR41XX_IRQ_RTCL1, &reserved);
	setup_irq(VR41XX_IRQ_RTCL2, &reserved);

	set_except_vector(0, vr4111_handle_int);

#ifdef CONFIG_REMOTE_DEBUG
	printk("Setting debug traps - please connect the remote debugger.\n");
	set_debug_traps();
	breakpoint();
#endif
}

--- NEW FILE: power.c ---
/*
 * VR4111 reset and power management type stuff
 *
 * Copyright (C) 2000 Michael Klar
 *
 * Copyright (C) 2001 Jim Paris <ji...@jt...>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/sysctl.h>
#include <linux/pm.h>
#include <linux/acpi.h>
#include <linux/irq.h>	/* for disable_irq, enable_irq, to be removed */
#include <asm/vr41xx.h>
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#include <asm/pgalloc.h>
#include <asm/power.h>

/*
 * vr4111_dma_sem is needed because we cannot suspend while a DMA transfer
 * is in progress, otherwise the CPU will be left in an undefined state.
 */
extern struct semaphore vr4111_dma_sem;

void vr4111_wait(void)
{
	/* Use "standby" instead of "wait" on VR4111. */
	asm volatile (
		".set noreorder\n"
		"standby\n"
		"nop\n"
		"nop\n"
		"nop\n"
		".set reorder\n"
	);
}

void vr4111_hibernate(void)
{
	asm volatile (
		" .set noreorder\n"
		" .align 4\n"
		" hibernate\n"
		" nop\n"
		" nop\n"
		" nop\n"
		" .set reorder\n"
	);
}

static inline void vr4111_suspend(void)
{
	asm volatile (
		" .set noreorder\n"
		" .align 4\n"
		" suspend\n"
		" nop\n"
		" nop\n"
		" nop\n"
		" .set reorder\n"
	);
}

static inline void vr4111_standby(void)
{
	asm volatile (
		" .set noreorder\n"
		" .align 4\n"
		" standby\n"
		" nop\n"
		" nop\n"
		" nop\n"
		" .set reorder\n"
	);
}

--- NEW FILE: serial.c ---
/*
 * Copyright 2001 MontaVista Software Inc.
 * Author: Jun Sun, js...@mv... or js...@ju...
 *
 * arch/mips/vr4111/common/serial.c
 *     initialize serial port on vr4111.
 *
 * Adapted to the VR4111 from arch/mips/vr4181/common/serial.c
 * Copyright (C) 2001 Jim Paris <ji...@jt...>
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 */

/*
 * [jsun, 010925]
 * You need to make sure rs_table has at least one element in 
 * drivers/char/serial.c file.	There is no good way to do it right
 * now.	 A workaround is to include CONFIG_SERIAL_MANY_PORTS in your
 * configure file, which would gives you 64 ports and wastes 11K ram.
 */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <asm/string.h>
#include <asm/io.h>
#include <asm/vr41xx.h>

void __init vr4111_init_serial(void)
{
	struct serial_struct s;
	unsigned short val;

	/* Ensure that serial is set to RS-232C (not IrDA) */
	*VR41XX_SIUIRSEL &= ~VR41XX_SIUIRSEL_SIRSEL;

	/* Supply clocks to all serial units */
	vr4111_clock_supply(VR41XX_CMUCLKMSK_MSKSIU);
	vr4111_clock_supply(VR41XX_CMUCLKMSK_MSKDSIU);
	vr4111_clock_supply(VR41XX_CMUCLKMSK_MSKSSIU);

	memset(&s, 0, sizeof(s));
	s.line = 0;
	s.baud_base = 1152000;
	s.irq = VR41XX_IRQ_SIU;
	s.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; /* STD_COM_FLAGS */
	s.iomem_base = (u8*)VR41XX_SIURB;
	s.iomem_reg_shift = 0;
	s.io_type = SERIAL_IO_MEM;
	if (early_serial_setup(&s) != 0) {
		panic("vr4111_init_serial() failed!\n");
	}
}


--- NEW FILE: time.c ---
/*
 * BRIEF MODULE DESCRIPTION
 *	NEC Vr4111 RTC Unit routines.
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 * Adapted to the VR4111 from arch/mips/vr4122/common/time.c
 * by Jim Paris <ji...@jt...>
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/spinlock.h>
#include <linux/config.h>
#include <linux/irq.h>
#include <asm/io.h>
#include <asm/time.h>
#include <asm/vr41xx.h>

spinlock_t vr4111_rtc_lock = SPIN_LOCK_UNLOCKED;

static inline unsigned short read_etime_register(volatile unsigned short *addr)
{
	unsigned short val;

	do {
		val = *addr;
	} while (val != *addr);

	return val;
}

static unsigned long vr4111_rtc_get_time(void)
{
	unsigned short etimel, etimem, etimeh;

	do {
		etimem = read_etime_register(VR41XX_ETIMEMREG);
		etimeh = read_etime_register(VR41XX_ETIMEHREG);
		etimel = read_etime_register(VR41XX_ETIMELREG);
	} while (etimem != read_etime_register(VR41XX_ETIMEMREG));

	return ((etimeh << 17) | (etimem << 1) | (etimel >> 15));
}

static int vr4111_rtc_set_time(unsigned long sec)
{
	unsigned long flags;

	spin_lock_irqsave(&vr4111_rtc_lock, flags);
	*VR41XX_ETIMELREG = sec << 15;
	*VR41XX_ETIMEMREG = sec >> 1;
	*VR41XX_ETIMEHREG = sec >> 17;
	spin_unlock_irqrestore(&vr4111_rtc_lock, flags);

	return 0;
}

void vr4111_time_init(void)
{
	unsigned long clock;
	unsigned short val;

	rtc_get_time = vr4111_rtc_get_time;
	rtc_set_time = vr4111_rtc_set_time;
	
	/* If it's not already set (by board-specific code),
	   figure out the counter frequency from the clock speed
	   register */
	if(mips_counter_frequency) return;

	val = *VR41XX_CLKSPEEDREG;
	if((val & 0x1f)==0)
		panic("can't determine core clock clock: divide by zero!\n");
	clock = (18432000 * 64) / (val & 0x1f);
	printk("CPU core clock: %ldHz\n",clock);

	switch((~val) & 0xE000) {
	case 0x8000:
		clock = clock / 2;
		break;
	case 0x4000:
		clock = clock / 3;
		break;
	case 0x2000:
		clock = clock / 4;
		break;
	default:
		panic("can't determine peripheral clock: unknown divisor!\n");
	}
	printk("Peripheral unit clock: %ldHz\n",clock);

	mips_counter_frequency = clock / 4;
}

void vr4111_timer_setup(struct irqaction *irq)
{
	unsigned int count;

	count = read_32bit_cp0_register(CP0_COUNT);
	write_32bit_cp0_register (CP0_COMPARE, 
				  count + (mips_counter_frequency / HZ));
	setup_irq(VR41XX_IRQ_TIMER, irq);
}

[Linux-mips-commits]CVS: linux/arch/mips/vr41xx/common Makefile,1.2,1.3 reset.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/common
In directory usw-pr-cvs1:/tmp/cvs-serv30742/arch/mips/vr41xx/common

Added Files:
	Makefile reset.c 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.




--- NEW FILE: reset.c ---
/*
 * VR41xx reset
 *
 * Copyright (C) 2000 Michael Klar
 * Copyright (C) 2001 Jim Paris <ji...@jt...>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/config.h>
#include <linux/delay.h>
#include <linux/mm.h>
#include <linux/sysctl.h>
#include <linux/pm.h>
#include <linux/acpi.h>
#include <asm/vr41xx.h>
#include <asm/cacheops.h>
#include <asm/mipsregs.h>
#include <asm/pgalloc.h>
#include <asm/power.h>

void vr41xx_restart(char *c)
{
	void *reset_addr = (void *)0xbfc00000;

	/*
	 * Try deadman's reset: set it to 1 second and wait for 2
	 */
	*(volatile int *)VR41XX_DSUCLRREG = 1;  /* clear last one */
	*(volatile int *)VR41XX_DSUSETREG = 1;  /* 1sec */
	*(volatile int *)VR41XX_DSUCNTREG = 1;  /* enable deadman switch */
	mdelay(2000);                           /* wait 2 second */

	/*
	 * That didn't work, so try jumping to the start address 
	 */
	goto *reset_addr;
}

[Linux-mips-commits]CVS: linux/arch/mips/vr4111/clio-1000 Makefile,NONE,1.1 prom.c,NONE,1.1 setup.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4111/clio-1000
In directory usw-pr-cvs1:/tmp/cvs-serv30742/arch/mips/vr4111/clio-1000

Added Files:
	Makefile prom.c setup.c 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.



--- NEW FILE: Makefile ---
#
# Makefile for the Vadem Clio 1000 / Sharp Mobilon Tripad PV-6000
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(AFLAGS) $< -o $@
.S.o:
	$(CC) $(AFLAGS) -c $< -o $@

O_TARGET := clio-1000.o

all: clio-1000.o

obj-y	 := setup.o prom.o

include $(TOPDIR)/Rules.make

--- NEW FILE: prom.c ---
/*
 * arch/mips/vr4111/clio-1000/prom.c
 *
 * Copyright (C) 1999 Bradley D. LaRonde and Michael Klar
 *
 * Copyright (C) 2001 Jim Paris <ji...@jt...>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */

#include <linux/init.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/page.h>
#include <asm/vr41xx.h>

char arcs_cmdline[COMMAND_LINE_SIZE];
extern int _end;

#define min(a,b)  (((a)<(b))?(a):(b))

unsigned long __init probe_ram_size(void)
{
	unsigned long ramsize;
	unsigned int *p1, *p2;
	unsigned int d1, d2;

	/* Begin probe starting with the first 1MB past the global data */
	ramsize = ((unsigned long)&_end + 0x000fffff) & 0x1ff00000;

	/* Probe sequential 1MB areas, looking for a lack of RAM */
	while (ramsize < 0x04000000) {
		/* Save the data and replace with a pattern */
		p1 = (unsigned int *)(KSEG1 + ramsize + 0x000ffff0);
		d1 = *p1;
		*p1 = 0x1234a5a5;
		barrier();

		/* Do it again to ensure it's not an empty bus */
		p2 = (unsigned int *)(KSEG1 + ramsize + 0x000fffe0);
		d2 = *p2;
		*p2 = 0x00ff5a5a;
		barrier();

		/* Is the first pattern there? */
		if (*p1 != 0x1234a5a5)
			break;

		/* Put the old data back */
		*p1 = d1;
		*p2 = d2;

		ramsize += 0x00100000;
	}
	return ramsize;
}

void __init prom_init(int argc, char **argv, char **envp)
{
	unsigned long mem_detected;
	int i;

	/*
         * Clear ERL and EXL in case the bootloader got us here
	 * through an exception 
	 */
	write_32bit_cp0_register(CP0_STATUS, 0);

	/* 
	 * Collect args and prepare cmd_line
	 */
	strcpy(arcs_cmdline, "");
	for (i = 1; i < argc; i++) {
		strcat(arcs_cmdline, argv[i]);
		if (i < (argc - 1))
			strcat(arcs_cmdline, " ");
	}

	mips_machgroup = MACH_GROUP_NEC_VR41XX;
	mips_machtype = MACH_VADEM_CLIO_1000;

	mem_detected = probe_ram_size();
	printk("Detected %dMB of memory.\n",(int)mem_detected >> 20);

	add_memory_region(0, mem_detected, BOOT_MEM_RAM);
}

void __init prom_free_prom_memory(void)
{
}


--- NEW FILE: setup.c ---
/*
 * linux/arch/mips/vr4111/setup.c
 *
 * VR41xx setup routines
 *
 * Copyright (C) 1999 Bradley D. LaRonde
 * Copyright (C) 1999, 2000 Michael Klar
 *
 * Copyright 2001 MontaVista Software Inc.
 * Author: js...@mv... or js...@ju...
 *
 * Copyright 2001 Jim Paris <ji...@jt...>
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 */

#include <linux/config.h>
#include <linux/console.h>
#include <linux/ide.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <asm/time.h>
#include <asm/reboot.h>
#include <asm/vr41xx.h>
#include <asm/io.h>

extern void vr41xx_restart(char *c);
extern void vr4111_hibernate(void);
extern void vr4111_wait(void);
extern void vr4111_time_init(void);
extern void vr4111_timer_setup(void);

extern struct ide_ops std_ide_ops;

void __init put_cf_reg(unsigned char reg, unsigned char val)
{
	/* PCMCIA controller (VG469) is mapped here */
	outb(reg, 0x3e0);
	outb(val, 0x3e1);
}

void __init clio_1000_setup(void)
{
	unsigned short val;
  
	mips_io_port_base = VR41XX_PORT_BASE;
	isa_slot_offset = VR41XX_ISAMEM_BASE;

	board_time_init = vr4111_time_init;
	board_timer_setup = vr4111_timer_setup;

	_machine_restart = vr41xx_restart;
	_machine_halt = vr4111_hibernate;
	_machine_power_off = vr4111_hibernate;
	cpu_wait = vr4111_wait;

	ide_ops = &std_ide_ops;

#ifdef CONFIG_FB
	conswitchp = &dummy_con;
#endif

	/* Reset the PCMCIA and CF and power them off */
	put_cf_reg(0x03, 0x20);   /* Socket 0 */
	put_cf_reg(0x43, 0x20);   /* Socket 1 */
	put_cf_reg(0x02, 0x00);   /* Socket 0 */
	put_cf_reg(0x42, 0x00);   /* Socket 1 */

	/* Clio-specific RS232 enable */
	*VR41XX_GIUPODATL |= VR41XX_GIUPODATL_GPIO42;

	vr4111_init_serial();

	/* Turn the green LED on (debug) */
	*VR41XX_GIUPODATH = 0;
	*VR41XX_GIUPODATH = 0x302;
	*VR41XX_GIUPODATH = 0x303;
	*VR41XX_GIUPODATH = 0;
}

[Linux-mips-commits]CVS: linux/arch/mips/kernel setup.c,1.24,1.25

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv30742/arch/mips/kernel

Modified Files:
	setup.c 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.



Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -d -r1.24 -r1.25
--- setup.c	2001/10/26 16:58:29	1.24
+++ setup.c	2001/10/28 23:04:19	1.25
@@ -599,6 +599,7 @@
 	void nec_eagle_setup(void);
 	void nec_korva_setup(void);
 	void ps2_setup(void);
+	void clio_1000_setup(void);
 
 	unsigned long bootmap_size;
 	unsigned long start_pfn, max_pfn, first_usable_pfn;
@@ -698,6 +699,11 @@
 #ifdef CONFIG_NEC_KORVA
 	case MACH_GROUP_NEC_VR41XX:
 		nec_korva_setup();
+		break;
+#endif
+#ifdef CONFIG_VADEM_CLIO_1000
+	case MACH_GROUP_NEC_VR41XX:
+		clio_1000_setup();
 		break;
 #endif
 #ifdef CONFIG_MIPS_EV96100

[Linux-mips-commits]CVS: linux/arch/mips Makefile,1.23,1.24 config.in,1.41,1.42

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv30742/arch/mips

Modified Files:
	Makefile config.in 
Log Message:
Merged Vr4111 (Clio-1000) patch from Jim Paris.



Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.23
retrieving revision 1.24
diff -u -d -r1.23 -r1.24
--- Makefile	2001/10/24 23:32:54	1.23
+++ Makefile	2001/10/28 23:04:19	1.24
@@ -62,7 +62,7 @@
 GCCFLAGS	+= -mcpu=r4300 -mips2 -Wa,--trap
 endif
 ifdef CONFIG_CPU_VR41XX
-GCCFLAGS	+= -mcpu=r4600 -mips2 -Wa,--trap
+GCCFLAGS	+= -mips2 -Wa,-m4100,--trap
 endif
 ifdef CONFIG_CPU_R4X00
 GCCFLAGS	+= -mcpu=r4600 -mips2 -Wa,--trap
@@ -325,6 +325,19 @@
 CORE_FILES    += arch/mips/ps2/ps2.o
 SUBDIRS       += arch/mips/ps2
 LOADADDR      += 0x80010000
+endif
+
+# 
+# Vadem Clio-1000 (aka Sharp Mobilon Tripad PV-6000)
+#
+ifdef CONFIG_VADEM_CLIO_1000
+SUBDIRS       += arch/mips/vr41xx/common \
+		 arch/mips/vr4111/common \
+		 arch/mips/vr4111/clio-1000
+LIBS          += arch/mips/vr41xx/common/vr41xx.o \
+		 arch/mips/vr4111/common/vr4111.o \
+                 arch/mips/vr4111/clio-1000/clio-1000.o
+LOADADDR      += 0x80001000
 endif
 
 #

Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.41
retrieving revision 1.42
diff -u -d -r1.41 -r1.42
--- config.in	2001/10/28 09:19:07	1.41
+++ config.in	2001/10/28 23:04:19	1.42
@@ -46,6 +46,7 @@
    fi
    bool 'Support for Sony PlayStation 2' CONFIG_PS2
    bool 'Support for Casio Cassiopeia BE-300 (EXPERIMENTAL)' CONFIG_CASIO_BE300	
+   bool 'Support for Vadem Clio 1000 (EXPERIMENTAL)' CONFIG_VADEM_CLIO_1000
 fi
 bool 'Support for Mips Magnum 4000' CONFIG_MIPS_MAGNUM_4000
 bool 'Support for Momentum Ocelot board' CONFIG_MOMENCO_OCELOT
@@ -248,6 +249,18 @@
    define_bool CONFIG_NEW_PCI y
    define_bool CONFIG_OLD_TIME_C y
 fi
+if [ "$CONFIG_VADEM_CLIO_1000" = "y" ]; then
+   define_bool CONFIG_CPU_VR41XX y
+   define_bool CONFIG_VR4111 y
+   define_bool CONFIG_SERIAL y
+   define_bool CONFIG_SERIAL_MANY_PORTS y
+   define_bool CONFIG_NEW_IRQ y
+   define_bool CONFIG_IRQ_CPU y
+   define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_ISA y
+   define_bool CONFIG_DUMMY_KEYB y
+fi
+
 if [ "$CONFIG_NINO" = "y" ]; then
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_PC_KEYB y
@@ -355,6 +368,7 @@
 if [ "$CONFIG_DECSTATION" = "y" -o \
      "$CONFIG_DDB5074" = "y" -o    \
      "$CONFIG_NINO" = "y" -o      \
+     "$CONFIG_VR4111" = "y"   -o  \
      "$CONFIG_NEC_KORVA" = "y" ]; then
    define_bool CONFIG_CPU_LITTLE_ENDIAN y
 else

[Linux-mips-commits]CVS: linux/include/asm-mips/vr4111 - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4111
In directory usw-pr-cvs1:/tmp/cvs-serv29309/include/asm-mips/vr4111

Log Message:
Directory /cvsroot/linux-mips/linux/include/asm-mips/vr4111 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr4111/clio-1000 - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4111/clio-1000
In directory usw-pr-cvs1:/tmp/cvs-serv28847/arch/mips/vr4111/clio-1000

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr4111/clio-1000 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr4111/common - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4111/common
In directory usw-pr-cvs1:/tmp/cvs-serv28824/arch/mips/vr4111/common

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr4111/common added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr4111 - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4111
In directory usw-pr-cvs1:/tmp/cvs-serv28797/arch/mips/vr4111

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr4111 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/kernel irq.c,1.5,1.6

[Bradley D. L. <br...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv5854/arch/mips/kernel

Modified Files:
	irq.c 
Log Message:
Require dev_id for shared irqs.


Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq.c	2001/10/12 17:33:56	1.5
+++ irq.c	2001/10/28 21:09:09	1.6
@@ -350,18 +350,12 @@
 	int retval;
 	struct irqaction * action;
 
-#if 1
 	/*
-	 * Sanity-check: shared interrupts should REALLY pass in
-	 * a real dev-ID, otherwise we'll have trouble later trying
-	 * to figure out which interrupt is which (messes up the
-	 * interrupt freeing logic etc).
+	 * Shared interrupts require a dev_id, otherwise we can't
+	 * later figure out which interrupt to free.
 	 */
-	if (irqflags & SA_SHIRQ) {
-		if (!dev_id)
-			printk("Bad boy: %s (at 0x%x) called us without a dev_id!\n", devname, (&irq)[-1]);
-	}
-#endif
+	if ((irqflags & SA_SHIRQ) && !dev_id)
+		return -EINVAL;
 
 	if (irq >= NR_IRQS)
 		return -EINVAL;

[Linux-mips-commits]CVS: linux/include/asm-mips/ps2 irq.h,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/ps2
In directory usw-pr-cvs1:/tmp/cvs-serv9292

Added Files:
	irq.h 
Log Message:
Add interrupt definitions.



--- NEW FILE: irq.h ---
/*
 * linux/include/asm-mips/ps2/irq.h
 *
 *        Copyright (C) 2000  Sony Computer Entertainment Inc.
 *
 * This file is subject to the terms and conditions of the GNU General
 * Public License Version 2. See the file "COPYING" in the main
 * directory of this archive for more details.
 *
 * $Id: irq.h,v 1.1 2001/10/28 09:20:31 lethal Exp $
 */

#ifndef __ASM_PS2_IRQ_H
#define __ASM_PS2_IRQ_H

/*
 * PlayStation 2 interrupts
 */

/* INTC */
#define IRQ_INTC	0
#define IRQ_INTC_GS	0
#define IRQ_INTC_SBUS	1
#define IRQ_INTC_VB_ON	2
#define IRQ_INTC_VB_OFF	3
#define IRQ_INTC_VIF0	4
#define IRQ_INTC_VIF1	5
#define IRQ_INTC_VU0	6
#define IRQ_INTC_VU1	7
#define IRQ_INTC_IPU	8
#define IRQ_INTC_TIMER0	9
#define IRQ_INTC_TIMER1	10
#define IRQ_INTC_TIMER2	11
#define IRQ_INTC_TIMER3	12
#define IRQ_INTC_SFIFO	13
#define IRQ_INTC_VU0WD	14
#define IRQ_INTC_PGPU	15

/* DMAC */
#define IRQ_DMAC	16
#define IRQ_DMAC_0	16
#define IRQ_DMAC_1	17
#define IRQ_DMAC_2	18
#define IRQ_DMAC_3	19
#define IRQ_DMAC_4	20
#define IRQ_DMAC_5	21
#define IRQ_DMAC_6	22
#define IRQ_DMAC_7	23
#define IRQ_DMAC_8	24
#define IRQ_DMAC_9	25
#define IRQ_DMAC_S	29
#define IRQ_DMAC_ME	30
#define IRQ_DMAC_BE	31

/* GS */
#define IRQ_GS		32
#define IRQ_GS_SIGNAL	32
#define IRQ_GS_FINISH	33
#define IRQ_GS_HSYNC	34
#define IRQ_GS_VSYNC	35
#define IRQ_GS_EDW	36
#define IRQ_GS_EXHSYNC	37
#define IRQ_GS_EXVSYNC	38

/* SBUS */
#define IRQ_SBUS	40
#define IRQ_SBUS_AIF	40
#define IRQ_SBUS_PCIC	41
#define IRQ_SBUS_USB	42

#endif /* __ASM_PS2_IRQ_H */

[Linux-mips-commits]CVS: linux/include/asm-mips/ps2 - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/ps2
In directory usw-pr-cvs1:/tmp/cvs-serv9254/ps2

Log Message:
Directory /cvsroot/linux-mips/linux/include/asm-mips/ps2 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/ps2 time.c,NONE,1.1 Makefile,1.2,1.3

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ps2
In directory usw-pr-cvs1:/tmp/cvs-serv8980/ps2

Modified Files:
	Makefile 
Added Files:
	time.c 
Log Message:
Add the PS2 time code, after rewriting it for the new format and cleaning up
unused/generic garbage.



--- NEW FILE: time.c ---
/* $Id: time.c,v 1.1 2001/10/28 09:19:07 lethal Exp $
 *
 *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
 *  Copyright (C) 1996, 1997, 1998  Ralf Baechle
 *  Copyright (C) 2000  Sony Computer Entertainment Inc.
 *  Copyright (C) 2001  Paul Mundt <le...@ch...>
 *
 * This file contains the time handling details for PC-style clocks as
 * found in some MIPS systems.
 */
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>

#include <asm/bootinfo.h>
#include <asm/mipsregs.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/ps2/irq.h>

#include <linux/mc146818rtc.h>
#include <linux/timex.h>

#define CPU_FREQ  294912000		/* CPU clock frequency (Hz) */
#define BUS_CLOCK (CPU_FREQ/2)		/* bus clock frequency (Hz) */
#define TM0_COMP  (BUS_CLOCK/256/HZ)	/* to generate 100Hz */

static volatile int *tm0_count = (volatile int *)0xb0000000;
static volatile int *tm0_mode  = (volatile int *)0xb0000010;
static volatile int *tm0_comp  = (volatile int *)0xb0000020;

static unsigned int last_cycle_count;
static int timer_intr_delay;

struct ps2_rtc {
	u_char padding_1;
	u_char sec;
	u_char min;
	u_char hour;
	u_char padding_2;
	u_char day;
	u_char mon;
	u_char year;
} *prtc = (struct ps2_rtc *)0x81fff010;

/**
 * 	ps2_do_gettimeoffset - Get Time Offset
 *
 * 	Returns the time duration since the last timer
 * 	interrupt in usecs.
 */
static unsigned long ps2_do_gettimeoffset(void)
{
	unsigned int count;
	int delay;

	count = read_32bit_cp0_register(CP0_COUNT);
	count -= last_cycle_count;
	count = (count * 1000 + (CPU_FREQ / 1000 / 2)) / (CPU_FREQ / 1000);
	delay = (timer_intr_delay * 10000 + (TM0_COMP / 2)) / TM0_COMP;

	return delay + count;
}

/**
 *	ps2_rtc_set_time - Set RTC Time
 *
 *	@nowtime: Time to set
 *
 *	Sets the RTC to the given time @nowtime.
 *
 *	In order to set the CMOS clock precisely, this routine has
 *	to be called 500 ms after the second @nowtime has started,
 *	because when @nowtime is written into the registers of
 *	the CMOS clock, it will jump to the next second precisely
 *	500 ms later. Check the Motorola MC146818A or Dallas
 *	DS12887 data sheet for details.
 *
 *	BUG: This routine does not handle hour overflow properly;
 *	     it just sets the minutes. Usually you won't notice
 *	     until after reboot!
 */
static int ps2_rtc_set_time(unsigned long nowtime)
{
	int retval = 0;
	int real_seconds, real_minutes, cmos_minutes;
	unsigned char save_control, save_freq_select;

	/* tell the clock it's being set */
	save_control = CMOS_READ(RTC_CONTROL);
	CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);

	/* stop and reset prescaler */
	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
	CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);

	cmos_minutes = CMOS_READ(RTC_MINUTES);

	if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
		BCD_TO_BIN(cmos_minutes);

	/*
	 * Since we're only adjusting minutes and seconds,
	 * don't interfere with hour overflow. This avoids
	 * messing with unknown time zones but requires your
	 * RTC not to be off by more than 15 minutes
	 */
	real_seconds = nowtime % 60;
	real_minutes = nowtime / 60;

	if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
		/* correct for half hour time zone */
		real_minutes += 30;

	real_minutes %= 60;

	if (abs(real_minutes - cmos_minutes) < 30) {
		if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
			BIN_TO_BCD(real_seconds);
			BIN_TO_BCD(real_minutes);
		}
		CMOS_WRITE(real_seconds,RTC_SECONDS);
		CMOS_WRITE(real_minutes,RTC_MINUTES);
	} else {
		printk(KERN_WARNING
		       "ps2_rtc_set_time: can't update from %d to %d\n",
		       cmos_minutes, real_minutes);
 		retval = -1;
	}

	/* 
	 * The following flags have to be released exactly in this order,
	 * otherwise the DS12887 (popular MC146818A clone with integrated
	 * battery and quartz) will not reset the oscillator and will not
	 * update precisely 500 ms later. You won't find this mentioned in
	 * the Dallas Semiconductor data sheets, but who believes data
	 * sheets anyway ...                           -- Markus Kuhn
	 */
	CMOS_WRITE(save_control, RTC_CONTROL);
	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);

	return retval;
}

/**
 * 	ps2_timer_interrupt - Timer Interrupt Routine
 *
 * 	@irq:    interrupt
 * 	@dev_id: device ID
 * 	@regs:   registers as they appear on the stack
 *	         during a syscall/exception.
 * 	
 * 	Timer interrupt routine, wraps the generic timer_interrupt() but
 * 	sets the timer interrupt delay and clears interrupts first.
 */
static void ps2_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	int cpu = smp_processor_id();

        irq_enter(cpu, IRQ_INTC_TIMER0);
        kstat.irqs[0][IRQ_INTC_TIMER0]++;

	/* Set the timer interrupt delay */
	timer_intr_delay = *tm0_count;

	/* Clear the interrupt */
	*tm0_mode = *tm0_mode;

	timer_interrupt(irq, dev_id, regs);
	irq_exit(cpu, IRQ_INTC_TIMER0);
}

/**
 * 	ps2_timer_setup - Timer Setup Routine
 *
 * 	@irq: Structure defining interrupt.
 *
 * 	Registers timer interrupt routine with appropriate
 * 	interrupt.
 */
static void ps2_timer_setup(struct irqaction *irq)
{
	/* Setup our handler */
	irq->handler = ps2_timer_interrupt;

	/* Setup interrupt */
	setup_irq(IRQ_INTC_TIMER0, irq);
}

/**
 * 	ps2_init_time - Initialize Clock
 *
 * 	Loads up the RTC with an almost useful default value
 * 	and registers our callbacks.
 */
void __init ps2_init_time(void)
{
	rtc_set_time      = ps2_rtc_set_time;
	do_gettimeoffset  = ps2_do_gettimeoffset;
	board_timer_setup = ps2_timer_setup;

	/*
	 * FIXME: This is really dependant on what the timezone is set to,
	 * contrary to popular belief, not everyone hacking PS2 code is in a
	 * JST timezone .. Anyone have any clues on how to probe the timezone
	 * information from the thing so this can be done dynamically? Static
	 * timezone configuration needs to be drug out and shot. -Lethal
	 */

	/* convert JST(UTC-9) to UTC */
	ps2_rtc_set_time(mktime(BCD_TO_BIN(prtc->year) + 2000,
				BCD_TO_BIN(prtc->mon),
				BCD_TO_BIN(prtc->day),
				BCD_TO_BIN(prtc->hour),
				BCD_TO_BIN(prtc->min),
				BCD_TO_BIN(prtc->sec) - 60 * 60 * 9));

	/* setup 100Hz interval timer */
	*tm0_count = 0;
	*tm0_comp = TM0_COMP;

	/* busclk / 256, zret, cue, cmpe, equf */
	*tm0_mode = 2 | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 10);

	clear_cp0_status(ST0_IM);
	set_cp0_status(IE_IRQ0 | IE_IRQ1);
}


Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ps2/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile	2001/10/28 07:43:57	1.2
+++ Makefile	2001/10/28 09:19:07	1.3
@@ -13,7 +13,7 @@
 
 O_TARGET := ps2.o
 
-obj-y    := setup.o reset.o prom.o
+obj-y    := setup.o reset.o prom.o time.o
 
 include $(TOPDIR)/Rules.make
 

[Linux-mips-commits]CVS: linux/arch/mips config.in,1.40,1.41

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv8980

Modified Files:
	config.in 
Log Message:
Add the PS2 time code, after rewriting it for the new format and cleaning up
unused/generic garbage.



Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.40
retrieving revision 1.41
diff -u -d -r1.40 -r1.41
--- config.in	2001/10/26 22:30:51	1.40
+++ config.in	2001/10/28 09:19:07	1.41
@@ -255,6 +255,7 @@
 if [ "$CONFIG_PS2" = "y" ]; then
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_BOARD_SCACHE y
+   define_bool CONFIG_NEW_TIME_C y
 fi
 if [ "$CONFIG_CASIO_BE300" = "y" ]; then
    define_bool CONFIG_CPU_VR41XX y

[Linux-mips-commits]CVS: linux/arch/mips/ps2 prom.c,NONE,1.1 Makefile,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/ps2
In directory usw-pr-cvs1:/tmp/cvs-serv17595

Modified Files:
	Makefile 
Added Files:
	prom.c 
Log Message:
PROM init routines for the PS2.. one step closer to generic r5900 support..



--- NEW FILE: prom.c ---
/*
 * arch/mips/ps2/prom.c
 *
 * PlayStation 2 PROM Library Initialization Routines
 *
 * Copyright (C) 2001 Paul Mundt <le...@ch...>
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */
#include <linux/init.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/bootmem.h>
#include <asm/bootinfo.h>
#include <asm/addrspace.h>

char arcs_cmdline[COMMAND_LINE_SIZE];

void __init prom_init(int argc, char **argv, char **envp)
{
	int i;

	for (i = 1; i < argc; i++) {
		strcat(arcs_cmdline, argv[i]);

		if (i < (argc - 1))
			strcat(arcs_cmdline, " ");
	}

	/*
	 * Only deals with the PS2 right now.. worry about the DTL-10000
	 * later..
	 */
	mips_machgroup = MACH_GROUP_EE;
	mips_machtype  = MACH_PS2;

	add_memory_region(0, PAGE_ALIGN((32 << 20) - PAGE_SIZE), BOOT_MEM_RAM);
}

void __init prom_free_prom_memory(void)
{
}

void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}


Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ps2/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile	2001/08/25 11:20:20	1.1
+++ Makefile	2001/10/28 07:43:57	1.2
@@ -13,7 +13,7 @@
 
 O_TARGET := ps2.o
 
-obj-y    := setup.o reset.o
+obj-y    := setup.o reset.o prom.o
 
 include $(TOPDIR)/Rules.make
 

[Linux-mips-commits]CVS: linux/drivers/char vr41xxwdt.c,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv20026

Modified Files:
	vr41xxwdt.c 
Log Message:
WDT updates.. use the new VR41XX_MACRO naming scheme. Get rid of ugly ifdef
nonsense.



Index: vr41xxwdt.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/vr41xxwdt.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- vr41xxwdt.c	2001/10/24 05:28:03	1.1
+++ vr41xxwdt.c	2001/10/28 03:49:14	1.2
@@ -25,20 +25,9 @@
 
 #include <asm/io.h>
 #include <asm/uaccess.h>
-
-#define __preg16(addr)	(volatile unsigned short *)(KSEG1 + addr)
+#include <asm/vr41xx.h>
 
-#if defined(CONFIG_VR4111) || defined(CONFIG_VR4121) || defined(CONFIG_VR4181)
-  #define DSUCNTREG	__preg16(0x0b0000e0)	/* DSU Control Register */
-  #define DSUSETREG	__preg16(0x0b0000e2)	/* DSU Dead Time Set Register */
-  #define DSUCLRREG	__preg16(0x0b0000e4)	/* DSU Clear Register */
-  #define DSUTIMREG	__preg16(0x0b0000e6)	/* DSU Elapsed Time Register */
-#elif defined(CONFIG_VR4122)
-  #define DSUCNTREG	__preg16(0x0f0000e0)	/* DSU Control Register */
-  #define DSUSETREG	__preg16(0x0f0000e2)	/* DSU Dead Time Set Register */
-  #define DSUCLRREG	__preg16(0x0f0000e4)	/* DSU Clear Register */
-  #define DSUTIMREG	__preg16(0x0f0000e6)	/* DSU Elapsed Time Register */
-#else
+#ifndef CONFIG_CPU_VR41XX
   #error "Can't use VR41xx watchdog on non-VR41xx processor."
 #endif
 
@@ -79,13 +68,13 @@
 	add_timer(&timer);
 
 	/* Clear the counter */
-	writew(0x01, DSUCLRREG);
+	writew(0x01, VR41XX_DSUCLRREG);
 
 	/* Set the overflow period (in seconds) */
-	writew(nsecs, DSUSETREG);
+	writew(nsecs, VR41XX_DSUSETREG);
 
 	/* Turn on the watchdog */
-	writew(0x01, DSUCNTREG);
+	writew(0x01, VR41XX_DSUCNTREG);
 }
 
 /**
@@ -98,10 +87,10 @@
 	del_timer(&timer);
 
 	/* Clear the counter */
-	writew(0x01, DSUCLRREG);
+	writew(0x01, VR41XX_DSUCLRREG);
 
 	/* Turn off the watchdog */
-	writew(0x00, DSUCNTREG);
+	writew(0x00, VR41XX_DSUCNTREG);
 }
 
 /**
@@ -115,7 +104,7 @@
 {
 	if (time_before(jiffies, next_heartbeat)) {
 		/* Clear overflow counter */
-		writew(0x01, DSUCLRREG);
+		writew(0x01, VR41XX_DSUCLRREG);
 
 		/* Update timer */
 		timer.expires = DSUTMRINTRVL;
@@ -307,7 +296,7 @@
 		return -EINVAL;
 	}
 
-	if (!request_region((unsigned long)DSUCNTREG, 8, "vr41xxwdt")) {
+	if (!request_region((unsigned long)VR41XX_DSUCNTREG, 8, "vr41xxwdt")) {
 		printk(KERN_ERR "vr41xx wdt: Can't request DSU register region\n");
 		misc_deregister(&vr41xx_wdt_miscdev);
 		return -ENXIO;
@@ -315,7 +304,7 @@
 
 	if (register_reboot_notifier(&vr41xx_wdt_notifier)) {
 		printk(KERN_ERR "vr41xx wdt: Can't register reboot notifier\n");
-		release_region((unsigned long)DSUCNTREG, 8);
+		release_region((unsigned long)VR41XX_DSUCNTREG, 8);
 		misc_deregister(&vr41xx_wdt_miscdev);
 		return -EINVAL;
 	}
@@ -337,7 +326,7 @@
 static void __exit vr41xx_wdt_exit(void)
 {
 	unregister_reboot_notifier(&vr41xx_wdt_notifier);
-	release_region((unsigned long)DSUCNTREG, 8);
+	release_region((unsigned long)VR41XX_DSUCNTREG, 8);
 	misc_deregister(&vr41xx_wdt_miscdev);
 }
 

[Linux-mips-commits]CVS: linux/include/asm-mips/vr4181 vr4181.h,1.3,1.4

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4181
In directory usw-pr-cvs1:/tmp/cvs-serv19649/asm-mips/vr4181

Modified Files:
	vr4181.h 
Log Message:
Add DSU definitions.



Index: vr4181.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4181/vr4181.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- vr4181.h	2001/10/07 16:57:20	1.3
+++ vr4181.h	2001/10/28 03:48:46	1.4
@@ -156,10 +156,10 @@
 #define VR4181_RTCINTREG	__preg16(KSEG1 + 0x0B0001DE)	/* RTC Interrupt Register (R/W) */
 
 // Deadman's Switch Unit (DSU)
-#define VR4181_DSUCNTREG	__preg16(KSEG1 + 0x0B0000E0)	/* DSU Control Register (R/W) */
-#define VR4181_DSUSETREG	__preg16(KSEG1 + 0x0B0000E2)	/* DSU Dead Time Set Register (R/W) */
-#define VR4181_DSUCLRREG	__preg16(KSEG1 + 0x0B0000E4)	/* DSU Clear Register (W) */
-#define VR4181_DSUTIMREG	__preg16(KSEG1 + 0x0B0000E6)	/* DSU Elapsed Time Register (R/W) */
+#define VR41XX_DSUCNTREG	__preg16(KSEG1 + 0x0B0000E0)	/* DSU Control Register (R/W) */
+#define VR41XX_DSUSETREG	__preg16(KSEG1 + 0x0B0000E2)	/* DSU Dead Time Set Register (R/W) */
+#define VR41XX_DSUCLRREG	__preg16(KSEG1 + 0x0B0000E4)	/* DSU Clear Register (W) */
+#define VR41XX_DSUTIMREG	__preg16(KSEG1 + 0x0B0000E6)	/* DSU Elapsed Time Register (R/W) */
 
 // General Purpose I/O Unit (GIU)
 #define VR4181_GPMD0REG		__preg16(KSEG1 + 0x0B000300)	/* GPIO Mode 0 Register (R/W) */

[Linux-mips-commits]CVS: linux/include/asm-mips/vr4122 vr4122.h,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4122
In directory usw-pr-cvs1:/tmp/cvs-serv19649/asm-mips/vr4122

Modified Files:
	vr4122.h 
Log Message:
Add DSU definitions.



Index: vr4122.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4122/vr4122.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- vr4122.h	2001/09/22 04:27:16	1.1
+++ vr4122.h	2001/10/28 03:48:46	1.2
@@ -219,6 +219,13 @@
 #define VR4122_PMUCLKRUNREG	KSEG1ADDR(0x0F0000D6)	/* PMU CLKRUN control register */
 
 
+/* Deadman's Switch Unit (DSU) */
+#define VR41XX_DSUCNTREG	KSEG1ADDR(0x0f0000e0)	/* DSU Control Register */
+#define VR41XX_DSUSETREG	KSEG1ADDR(0x0f0000e2)	/* DSU Dead Time Set Register */
+#define VR41XX_DSUCLRREG	KSEG1ADDR(0x0f0000e4)	/* DSU Clear Register */
+#define VR41XX_DSUTIMREG	KSEG1ADDR(0x0f0000e6)	/* DSU Elapsed Time Register */
+
+
 /* Real Time Clock Unit (RTC) */
 #define VR4122_ETIMELREG	KSEG1ADDR(0x0F000100)	/* Elapsed Time L Register */
 #define VR4122_ETIMEMREG	KSEG1ADDR(0x0F000102)	/* Elapsed Time M Register */

[Linux-mips-commits]CVS: linux/include/asm-mips vr41xx.h,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv11215/include/asm-mips

Added Files:
	vr41xx.h 
Log Message:
Add a generic vr41xx.h for people to use.



--- NEW FILE: vr41xx.h ---
/*
 * include/asm-mips/vr41xx.h
 *
 * Primary header for NEC VR41xx processors.
 *
 * Copyright (C) 1999 Michael Klar
 * Copyright (C) 2001 Paul Mundt <le...@ch...>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */
#ifndef __ASM_MIPS_VR41XX_H
#define __ASM_MIPS_VR41XX_H

#include <linux/config.h>

/*
 * Any code being written for a VR41xx device should be including this
 * header.. especially if it's a driver. Directly including a header for a
 * specific member of the family should be avoided, as should any
 * CONFIG_VR41XX checks in drivers when its something as simple as the
 * location of a certain register not being consistent across all members of
 * the family (such as in the case of the DSU).
 *
 * The headers that are included by this header are to have the naming
 * convention of VR41XX_MACRO at all times, and should _never_ under _any_
 * circumstances be referencing VR4181_MACRO (in the case of the vr4181). Any
 * member specific macros need to go somewhere else.
 */
#if defined(CONFIG_VR4111)
  #include <asm/vr4111/vr4111.h>
#elif defined(CONFIG_VR4122)
  #include <asm/vr4122/vr4122.h>
#elif defined(CONFIG_VR4181)
  #include <asm/vr4181/vr4181.h>
#endif

#endif /* __ASM_MIPS_VR41XX_H */

[Linux-mips-commits]CVS: linux/drivers/video mq200fb.c,1.1,1.2 mq2hw.h,1.1,1.2

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/video
In directory usw-pr-cvs1:/tmp/cvs-serv10548

Modified Files:
	mq200fb.c mq2hw.h 
Log Message:
Use intelligent PCI ID's instead..



Index: mq200fb.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/mq200fb.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- mq200fb.c	2001/07/23 21:04:18	1.1
+++ mq200fb.c	2001/10/28 02:43:33	1.2
@@ -608,8 +608,9 @@
     memset(p, 0, sizeof(*p));
 
 #ifdef MQ_PCI
-    pPciDev = (struct pci_dev *) pci_find_device(MQ200_VENDOR_ID, \
-                                                 MQ200_DEVICE_ID, NULL);
+    pPciDev = (struct pci_dev *) pci_find_device(PCI_VENDOR_ID_MEDIAQ,
+                                                 PCI_DEVICE_ID_MEDIAQ_MQ200,
+						 NULL);
   
 #ifdef TEST
     PDEBUG("mq200fb: pci_find_devide = 0X%08X\n", pPciDev);

Index: mq2hw.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/mq2hw.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- mq2hw.h	2001/07/23 21:04:18	1.1
+++ mq2hw.h	2001/10/28 02:43:33	1.2
@@ -10,8 +10,6 @@
 #ifndef _VIDEO_MQ200_MQ2HW_H
 #define _VIDEO_MQ200_MQ2HW_H
 
-#define MQ200_VENDOR_ID		0x4D51
-#define MQ200_DEVICE_ID		0x0200
 #define MQ200_ID		0x02004D51
 #define PM_ID_CAP		0x06210001 /* Power management ID/capability */
 

[Linux-mips-commits]CVS: linux/include/linux pci_ids.h,1.6,1.7

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/linux
In directory usw-pr-cvs1:/tmp/cvs-serv9947/linux

Modified Files:
	pci_ids.h 
Log Message:
Remove 4173 AC97 controller ID.. this already exists as the 5477 in OSS.



Index: pci_ids.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/linux/pci_ids.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pci_ids.h	2001/10/28 02:21:08	1.6
+++ pci_ids.h	2001/10/28 02:41:23	1.7
@@ -436,7 +436,6 @@
 #define PCI_DEVICE_ID_NEC_NILE4		0x005a
 #define PCI_DEVICE_ID_NEC_VRC5476       0x009b
 #define PCI_DEVICE_ID_NEC_VRC4173_BCU	0x00a5
-#define PCI_DEVICE_ID_NEC_VRC4173_AC97	0x00a6
 #define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
 
 #define PCI_VENDOR_ID_FD		0x1036

[Linux-mips-commits]CVS: linux/arch/mips/vr4122/eagle pci.c,1.3,1.4

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle
In directory usw-pr-cvs1:/tmp/cvs-serv9867/mips/vr4122/eagle

Modified Files:
	pci.c 
Log Message:
Use the Vrc5477 ID instead.. they're the same anyways..



Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle/pci.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci.c	2001/10/09 21:54:21	1.3
+++ pci.c	2001/10/28 02:40:44	1.4
@@ -215,7 +215,12 @@
 	case PCI_VENDOR_ID_NEC:
 		switch (dev->device) {
 		case PCI_DEVICE_ID_NEC_VRC4173_BCU:
-		case PCI_DEVICE_ID_NEC_VRC4173_AC97:
+		/*
+		 * The Vrc4173 and Vrc5477 AC97 controller are one and the
+		 * same, therefore it should be no surprise that they share
+		 * the same PCI ID. -Lethal
+		 */
+		case PCI_DEVICE_ID_NEC_VRC5477_AC97:
 		case PCI_DEVICE_ID_NEC_VRC4173_CARDU:
 		case PCI_DEVICE_ID_NEC_VRC4173_USB: /* all three share the same IRQ */
 			dev->irq = VR4122_IRQ_VRC4173;

[Linux-mips-commits]CVS: linux/include/linux pci_ids.h,1.5,1.6

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/linux
In directory usw-pr-cvs1:/tmp/cvs-serv6311

Modified Files:
	pci_ids.h 
Log Message:
Needed a few missing PCI id's to get eagle building.. now to figure out _why_
the hell the Vrc4173 AC97 and the Vrc5477 have the same PCI ID's..



Index: pci_ids.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/linux/pci_ids.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pci_ids.h	2001/10/19 21:19:40	1.5
+++ pci_ids.h	2001/10/28 02:21:08	1.6
@@ -430,9 +430,13 @@
 #define PCI_DEVICE_ID_MIRO_36050	0x5601
 
 #define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_VRC4173_USB	0x0035
+#define PCI_DEVICE_ID_NEC_VRC4173_CARDU	0x003e
 #define PCI_DEVICE_ID_NEC_PCX2		0x0046
 #define PCI_DEVICE_ID_NEC_NILE4		0x005a
 #define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173_BCU	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC4173_AC97	0x00a6
 #define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
 
 #define PCI_VENDOR_ID_FD		0x1036
@@ -1504,6 +1508,9 @@
 
 #define PCI_VENDOR_ID_NETVIN		0x4a14
 #define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
+
+#define PCI_VENDOR_ID_MEDIAQ		0x4d51
+#define PCI_DEVICE_ID_MEDIAQ_MQ200	0x0200
 
 #define PCI_VENDOR_ID_S3		0x5333
 #define PCI_DEVICE_ID_S3_PLATO_PXS	0x0551