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From: Bradley D. L. <br...@us...> - 2001-10-27 21:08:11
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv1317/arch/mips/kernel
Modified Files:
pci_auto.c
Log Message:
- Add a top_bus argument to the "early config" functions so that
they can set a fake parent bus pointer to convince the underlying
pci ops to use type 1 configuration for sub busses.
- Set P2P bridge base and limit registers correctly.
- Align io and memory base properly before and after P2P bridge setup.
- Don't fall through to pci_setup_bars for P2P bridge.
- Reformat the debug output to look more like lspci's output.
Index: pci_auto.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci_auto.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci_auto.c 2001/08/25 02:19:27 1.2
+++ pci_auto.c 2001/10/27 21:08:08 1.3
@@ -4,6 +4,7 @@
* Author: Matt Porter <mp...@mv...>
*
* Copyright 2000, 2001 MontaVista Software Inc.
+ * Copyright 2001 Bradley D. LaRonde <br...@lt...>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
@@ -19,6 +20,15 @@
* . change most int to u32.
*
* Further modified to include it as mips generic code, pp...@mv....
+ *
+ * 2001-10-26 Bradley D. LaRonde <br...@lt...>
+ * - Add a top_bus argument to the "early config" functions so that
+ * they can set a fake parent bus pointer to convince the underlying
+ * pci ops to use type 1 configuration for sub busses.
+ * - Set bridge base and limit registers correctly.
+ * - Align io and memory base properly before and after bridge setup.
+ * - Don't fall through to pci_setup_bars for bridge.
+ * - Reformat the debug output to look more like lspci's output.
*/
#include <linux/kernel.h>
@@ -35,14 +45,47 @@
#define DBG(x...)
#endif
-/* These are used for config access before all the PCI probing has been done. */
-int early_read_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 *val);
-int early_read_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 *val);
-int early_read_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 *val);
-int early_write_config_byte(struct pci_channel *hose, int bus, int dev_fn, int where, u8 val);
-int early_write_config_word(struct pci_channel *hose, int bus, int dev_fn, int where, u16 val);
-int early_write_config_dword(struct pci_channel *hose, int bus, int dev_fn, int where, u32 val);
+/*
+ * These functions are used early on before PCI scanning is done
+ * and all of the pci_dev and pci_bus structures have been created.
+ */
+static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
+ int top_bus, int busnr, int devfn)
+{
+ static struct pci_dev dev;
+ static struct pci_bus bus;
+ dev.bus = &bus;
+ dev.sysdata = hose;
+ dev.devfn = devfn;
+ bus.number = busnr;
+ bus.ops = hose->pci_ops;
+
+ if(busnr != top_bus)
+ /* Fake a parent bus structure. */
+ bus.parent = &bus;
+ else
+ bus.parent = NULL;
+
+ return &dev;
+}
+
+#define EARLY_PCI_OP(rw, size, type) \
+int early_##rw##_config_##size(struct pci_channel *hose, \
+ int top_bus, int bus, int devfn, int offset, type value) \
+{ \
+ return pci_##rw##_config_##size( \
+ fake_pci_dev(hose, top_bus, bus, devfn), \
+ offset, value); \
+}
+
+EARLY_PCI_OP(read, byte, u8 *)
+EARLY_PCI_OP(read, word, u16 *)
+EARLY_PCI_OP(read, dword, u32 *)
+EARLY_PCI_OP(write, byte, u8)
+EARLY_PCI_OP(write, word, u16)
+EARLY_PCI_OP(write, dword, u32)
+
static u32 pciauto_lower_iospc;
static u32 pciauto_upper_iospc;
@@ -51,6 +94,7 @@
void __init
pciauto_setup_bars(struct pci_channel *hose,
+ int top_bus,
int current_bus,
int pci_devfn)
{
@@ -60,17 +104,14 @@
u32 * lower_limit;
int found_mem64 = 0;
- DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
- current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
-
for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar+=4) {
/* Tickle the BAR and get the response */
- early_write_config_dword(hose,
+ early_write_config_dword(hose, top_bus,
current_bus,
pci_devfn,
bar,
0xffffffff);
- early_read_config_dword(hose,
+ early_read_config_dword(hose, top_bus,
current_bus,
pci_devfn,
bar,
@@ -80,12 +121,20 @@
if (!bar_response)
continue;
+ /*
+ * Workaround for a BAR that doesn't use its upper word,
+ * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
+ * bdl <br...@lt...>
+ */
+ if (!(bar_response & 0xffff0000))
+ bar_response |= 0xffff0000;
+
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
addr_mask = PCI_BASE_ADDRESS_IO_MASK;
upper_limit = &pciauto_upper_iospc;
lower_limit = &pciauto_lower_iospc;
- DBG("PCI Autoconfig: BAR %d, I/O, ", bar_nr);
+ DBG(" I/O");
} else {
if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
PCI_BASE_ADDRESS_MEM_TYPE_64)
@@ -94,7 +143,7 @@
addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
upper_limit = &pciauto_upper_memspc;
lower_limit = &pciauto_lower_memspc;
- DBG("PCI Autoconfig: BAR %d, Mem, ", bar_nr);
+ DBG(" Mem");
}
/* Calculate requested size */
@@ -104,7 +153,7 @@
bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
/* Write it out and update our limit */
- early_write_config_dword(hose, current_bus, pci_devfn,
+ early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
bar, bar_value);
*lower_limit = bar_value + bar_size;
@@ -116,97 +165,99 @@
*/
if (found_mem64) {
bar += 4;
- early_write_config_dword(hose,
+ early_write_config_dword(hose, top_bus,
current_bus,
pci_devfn,
bar,
0x00000000);
}
- bar_nr++;
+ DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
- DBG("size=0x%x, address=0x%x\n",
- bar_size, bar_value);
+ bar_nr++;
}
}
void __init
pciauto_prescan_setup_bridge(struct pci_channel *hose,
+ int top_bus,
int current_bus,
int pci_devfn,
int sub_bus)
{
- int cmdstat;
-
/* Configure bus number registers */
- early_write_config_byte(hose, current_bus, pci_devfn,
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_PRIMARY_BUS, current_bus);
- early_write_config_byte(hose, current_bus, pci_devfn,
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_SECONDARY_BUS, sub_bus + 1);
- early_write_config_byte(hose, current_bus, pci_devfn,
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_SUBORDINATE_BUS, 0xff);
- /* Round memory allocator to 1MB boundary */
- pciauto_upper_memspc &= ~(0x100000 - 1);
+ /* Align memory and I/O to 1MB and 4KB boundaries. */
+ pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
+ & ~(0x100000 - 1);
+ pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
+ & ~(0x1000 - 1);
- /* Round I/O allocator to 4KB boundary */
- pciauto_upper_iospc &= ~(0x1000 - 1);
+ /* Set base (lower limit) of address range behind bridge. */
+ early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
+ PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
+ early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
- /* Set up memory and I/O filter limits, assume 32-bit I/O space */
- early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_LIMIT,
- ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
- early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_LIMIT,
- ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
- early_write_config_word(hose, current_bus, pci_devfn,
- PCI_IO_LIMIT_UPPER16,
- ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
-
/* We don't support prefetchable memory for now, so disable */
- early_write_config_word(hose, current_bus, pci_devfn,
- PCI_PREF_MEMORY_BASE, 0x1000);
- early_write_config_word(hose, current_bus, pci_devfn,
- PCI_PREF_MEMORY_LIMIT, 0x1000);
-
- /* Enable memory and I/O accesses, enable bus master */
- early_read_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND,
- &cmdstat);
- early_write_config_dword(hose, current_bus, pci_devfn, PCI_COMMAND,
- cmdstat | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER);
+ early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_PREF_MEMORY_BASE, 0);
+ early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_PREF_MEMORY_LIMIT, 0);
}
void __init
pciauto_postscan_setup_bridge(struct pci_channel *hose,
+ int top_bus,
int current_bus,
int pci_devfn,
int sub_bus)
{
+ u32 temp;
+
/* Configure bus number registers */
- early_write_config_byte(hose, current_bus, pci_devfn,
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_SUBORDINATE_BUS, sub_bus);
- /* Round memory allocator to 1MB boundary */
- pciauto_upper_memspc &= ~(0x100000 - 1);
- early_write_config_word(hose, current_bus, pci_devfn, PCI_MEMORY_BASE,
- pciauto_upper_memspc >> 16);
+ /* Set upper limit of address range behind bridge. */
+ early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
+ PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
+ early_write_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
- /* Round I/O allocator to 4KB boundary */
- pciauto_upper_iospc &= ~(0x1000 - 1);
- early_write_config_byte(hose, current_bus, pci_devfn, PCI_IO_BASE,
- (pciauto_upper_iospc & 0x0000f000) >> 8);
- early_write_config_word(hose, current_bus, pci_devfn,
- PCI_IO_BASE_UPPER16, pciauto_upper_iospc >> 16);
+ /* Align memory and I/O to 1MB and 4KB boundaries. */
+ pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
+ & ~(0x100000 - 1);
+ pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
+ & ~(0x1000 - 1);
+
+ /* Enable memory and I/O accesses, enable bus master */
+ early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
+ PCI_COMMAND, &temp);
+ early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
+ PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
+ | PCI_COMMAND_MASTER);
}
#define PCIAUTO_IDE_MODE_MASK 0x05
int __init
-pciauto_bus_scan(struct pci_channel *hose, int current_bus)
+pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
{
int sub_bus;
u32 pci_devfn, pci_class, cmdstat, found_multi=0;
- unsigned short vid;
+ unsigned short vid, did;
unsigned char header_type;
int devfn_start = 0;
int devfn_stop = 0xff;
@@ -223,54 +274,70 @@
if (PCI_FUNC(pci_devfn) && !found_multi)
continue;
- early_read_config_byte(hose, current_bus, pci_devfn,
+ early_read_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_VENDOR_ID, &vid);
+
+ if (vid == 0xffff) continue;
+
+ early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_HEADER_TYPE, &header_type);
if (!PCI_FUNC(pci_devfn))
found_multi = header_type & 0x80;
-
- early_read_config_word(hose, current_bus, pci_devfn,
- PCI_VENDOR_ID, &vid);
- if (vid == 0xffff) continue;
+ early_read_config_word(hose, top_bus, current_bus, pci_devfn,
+ PCI_DEVICE_ID, &did);
- early_read_config_dword(hose, current_bus, pci_devfn,
+ early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_CLASS_REVISION, &pci_class);
+
+ DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
+ current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
+ pci_class >> 16, vid, did);
+ if (pci_class & 0xff)
+ DBG(" (rev %.2x)", pci_class & 0xff);
+ DBG("\n");
+
if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
- DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
- pciauto_prescan_setup_bridge(hose, current_bus,
+ DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
+ current_bus, sub_bus + 1);
+ pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
pci_devfn, sub_bus);
- sub_bus = pciauto_bus_scan(hose, sub_bus+1);
- pciauto_postscan_setup_bridge(hose, current_bus,
+ DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
+ sub_bus + 1,
+ pciauto_lower_iospc, pciauto_lower_memspc);
+ sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
+ DBG("Back to bus %.2x\n", current_bus);
+ pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
pci_devfn, sub_bus);
-
+ continue;
} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
unsigned char prg_iface;
- early_read_config_byte(hose, current_bus, pci_devfn,
- PCI_CLASS_PROG, &prg_iface);
+ early_read_config_byte(hose, top_bus, current_bus,
+ pci_devfn, PCI_CLASS_PROG, &prg_iface);
if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
- DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
+ DBG("Skipping legacy mode IDE controller\n");
continue;
}
}
- /*
+ /*
* Found a peripheral, enable some standard
* settings
*/
- early_read_config_dword(hose, current_bus, pci_devfn,
+ early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_COMMAND, &cmdstat);
- early_write_config_dword(hose, current_bus, pci_devfn,
+ early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
- early_write_config_byte(hose, current_bus, pci_devfn,
+ early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_LATENCY_TIMER, 0x80);
/* Allocate PCI I/O and/or memory space */
- pciauto_setup_bars(hose, current_bus, pci_devfn);
+ pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn);
}
return sub_bus;
}
@@ -283,41 +350,9 @@
pciauto_upper_iospc = hose->io_resource->end + 1;
pciauto_lower_memspc = hose->mem_resource->start;
pciauto_upper_memspc = hose->mem_resource->end + 1;
-
- return pciauto_bus_scan(hose, busno);
-}
-
-
-/*
- * These functions are used early on before PCI scanning is done
- * and all of the pci_dev and pci_bus structures have been created.
- */
-static struct pci_dev *fake_pci_dev(struct pci_channel *hose, int busnr,
- int devfn)
-{
- static struct pci_dev dev;
- static struct pci_bus bus;
-
- dev.bus = &bus;
- dev.sysdata = hose;
- dev.devfn = devfn;
- bus.number = busnr;
- bus.ops = hose->pci_ops;
-
- return &dev;
-}
+ DBG("Autoconfig PCI channel 0x%p\n", hose);
+ DBG("Scanning bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
+ busno, pciauto_lower_iospc, pciauto_lower_memspc);
-#define EARLY_PCI_OP(rw, size, type) \
-int early_##rw##_config_##size(struct pci_channel *hose, int bus, \
- int devfn, int offset, type value) \
-{ \
- return pci_##rw##_config_##size(fake_pci_dev(hose, bus, devfn), \
- offset, value); \
+ return pciauto_bus_scan(hose, busno, busno);
}
-
-EARLY_PCI_OP(read, byte, u8 *)
-EARLY_PCI_OP(read, word, u16 *)
-EARLY_PCI_OP(read, dword, u32 *)
-EARLY_PCI_OP(write, byte, u8)
-EARLY_PCI_OP(write, word, u16)
-EARLY_PCI_OP(write, dword, u32)
|
|
From: Paul M. <le...@us...> - 2001-10-27 20:53:07
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv31045 Removed Files: fast-sysmips.S Log Message: Don't need this anymore.. --- fast-sysmips.S DELETED --- |
|
From: Paul M. <le...@us...> - 2001-10-27 20:52:07
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv30758/mips/kernel
Modified Files:
Makefile irix5sys.h scall_o32.S syscalls.h sysmips.c
Log Message:
sysmips syncups.. works fine on ITE board.. more testing probably needed. This
brings us in sync with OSS on sysmips.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/Makefile,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- Makefile 2001/10/26 20:00:15 1.12
+++ Makefile 2001/10/27 20:52:05 1.13
@@ -15,10 +15,12 @@
O_TARGET := kernel.o
+export-objs = pci-dma.o smp.o
+
obj-y += branch.o process.o signal.o entry.o \
traps.o ptrace.o vm86.o ioport.o reset.o \
semaphore.o setup.o syscall.o sysmips.o \
- ipc.o scall_o32.o unaligned.o fast-sysmips.o
+ ipc.o scall_o32.o unaligned.o
obj-$(CONFIG_MODULES) += mips_ksyms.o
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
@@ -38,7 +40,6 @@
obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
-export-objs += smp.o
obj-$(CONFIG_SMP) += smp.o
# Old style irq support, going to die in 2.5.
@@ -57,7 +58,6 @@
obj-$(CONFIG_BINFMT_IRIX) += irixelf.o irixioctl.o irixsig.o sysirix.o \
irixinv.o
obj-$(CONFIG_REMOTE_DEBUG) += gdb-low.o gdb-stub.o
-export-objs += pci-dma.o
obj-$(CONFIG_PCI) += pci-dma.o
obj-$(CONFIG_PROC_FS) += proc.o
@@ -68,6 +68,5 @@
entry.o: entry.S
head.o: head.S
-fast-sysmips.o: fast-sysmips.S
include $(TOPDIR)/Rules.make
Index: irix5sys.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/irix5sys.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irix5sys.h 2001/09/25 03:36:35 1.3
+++ irix5sys.h 2001/10/27 20:52:05 1.4
@@ -68,7 +68,7 @@
SYS(irix_getgid, 0) /* 1047 getgid() V*/
SYS(irix_unimp, 0) /* 1048 (XXX IRIX 4 ssig) V*/
SYS(irix_msgsys, 6) /* 1049 sys_msgsys V*/
-SYS(fast_sysmips, 4) /* 1050 sysmips() HV*/
+SYS(sys_sysmips, 4) /* 1050 sysmips() HV*/
SYS(irix_unimp, 0) /* 1051 XXX sysacct() IV*/
SYS(irix_shmsys, 5) /* 1052 sys_shmsys V*/
SYS(irix_semsys, 0) /* 1053 sys_semsys V*/
Index: scall_o32.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/scall_o32.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- scall_o32.S 2001/09/04 16:43:46 1.5
+++ scall_o32.S 2001/10/27 20:52:05 1.6
@@ -3,7 +3,8 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1997, 1998, 1999, 2000 by Ralf Baechle
+ * Copyright (C) 1997, 1998, 1999, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
*/
#include <asm/asm.h>
#include <linux/errno.h>
@@ -12,6 +13,7 @@
#include <asm/regdef.h>
#include <asm/stackframe.h>
#include <asm/isadep.h>
+#include <asm/sysmips.h>
#include <asm/unistd.h>
/* This duplicates the definition from <linux/sched.h> */
@@ -192,3 +194,73 @@
sw t0, PT_R7(sp)
j ret_from_sys_call
END(handle_sys)
+
+ LEAF(mips_atomic_set)
+ lw v1, THREAD_CURDS($28)
+ addiu a0, a1, 4
+ or a0, a0, a1
+ li v0, -EFAULT
+ and a0, a0, v1
+ bltz a0, 8f
+
+#ifdef CONFIG_CPU_HAS_LLSC
+ /* Ok, this is the ll/sc case. World is sane :-) */
+1: ll v0, (a1)
+ move a0, a2
+2: sc a0, (a1)
+ beqz a0, 1b
+
+ .section __ex_table,"a"
+ PTR 1b, bad_stack
+ PTR 2b, bad_stack
+ .previous
+#else
+ sw a1, 16(sp)
+ sw a2, 20(sp)
+
+ move a0, sp
+ move a2, a1
+ li a1, 1
+ jal do_page_fault
+
+ lw a1, 16(sp)
+ lw a2, 20(sp)
+
+ /*
+ * At this point the page should be readable and writable unless
+ * there was no more memory available.
+ */
+1: lw v0, (a1)
+2: sw a2, (a1)
+
+ .section __ex_table,"a"
+ PTR 1b, no_mem
+ PTR 2b, no_mem
+ .previous
+#endif
+
+ sw v0, PT_R2(sp) # result
+1:
+
+ /* Success, so skip usual error handling garbage. */
+ lw t0, TASK_PTRACE($28) # syscall tracing enabled?
+ andi t0, PT_TRACESYS
+ bnez t0, 1f
+ b o32_ret_from_sys_call
+
+1: SAVE_STATIC
+ jal syscall_trace
+ li a3, 0 # success
+ j ret_from_sys_call
+
+no_mem: li v0, -ENOMEM
+ jr ra
+
+8: li v0, -EFAULT
+9: jr ra
+ END(mips_atomic_set)
+
+ LEAF(sys_sysmips)
+ beq a0, MIPS_ATOMIC_SET, mips_atomic_set
+ j _sys_sysmips
+ END(sys_sysmips)
Index: syscalls.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/syscalls.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- syscalls.h 2001/08/13 22:08:37 1.3
+++ syscalls.h 2001/10/27 20:52:05 1.4
@@ -163,7 +163,7 @@
SYS(sys_writev, 3)
SYS(sys_cacheflush, 3)
SYS(sys_cachectl, 3)
-SYS(fast_sysmips, 4)
+SYS(sys_sysmips, 4)
SYS(sys_ni_syscall, 0) /* 4150 */
SYS(sys_getsid, 1)
SYS(sys_fdatasync, 0)
Index: sysmips.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/sysmips.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- sysmips.c 2001/09/26 03:18:54 1.8
+++ sysmips.c 2001/10/27 20:52:05 1.9
@@ -1,11 +1,10 @@
/*
- * MIPS specific syscalls
- *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 1995, 1996, 1997, 2000 by Ralf Baechle
+ * Copyright (C) 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
*/
#include <linux/config.h>
#include <linux/errno.h>
@@ -48,7 +47,7 @@
}
asmlinkage int
-sys_sysmips(int cmd, int arg1, int arg2, int arg3)
+_sys_sysmips(int cmd, int arg1, int arg2, int arg3)
{
char *name;
int tmp, len, retval;
@@ -72,86 +71,11 @@
system_utsname.nodename[len] = '\0';
return 0;
}
-
- case MIPS_ATOMIC_SET: {
- int *ptr, val, ret, err, tmp;
- struct siginfo info;
-
- ptr = (int *)arg1;
- val = (int)arg2;
-
- /* Don't emulate unaligned accesses. */
- if ((int)ptr & 3) {
- info.si_signo = SIGBUS;
- info.si_code = BUS_ADRALN;
- goto fault;
- }
-
- /* A zero here saves us three instructions. */
- err = verify_area(VERIFY_WRITE, ptr, 0);
- if (err) {
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_ACCERR;
- goto fault;
- }
-
-#ifdef CONFIG_CPU_HAS_LLSC
- __asm__(".set mips2\n\t"
- "1:\n\t"
- "ll %0,%5\n\t"
- ".set push\n\t"
- ".set noreorder\n\t"
- "beq %0,%4,3f\n\t"
- " move %3,%4\n"
- ".set pop\n\t"
- "2:\n\t"
- "sc %3,%1\n\t"
- "beqz %3,1b\n\t"
- "3:\n\t"
- ".set mips0\n\t"
- ".section .fixup,\"ax\"\n"
- "4:\n\t"
- "li %2,%7\n\t"
- "j 3b\n\t"
- ".previous\n\t"
- ".section __ex_table,\"a\"\n\t"
- ".word 1b,4b\n\t"
- ".word 2b,4b\n\t"
- ".previous"
- : "=&r" (ret), "=m" (*ptr), "=r" (err), "=&r" (tmp)
- : "r" (val), "1" (*ptr), "2" (0), "i" (-EFAULT));
-#else
- save_and_cli(tmp);
- err = __get_user(ret, ptr);
- if (ret != val)
- err |= __put_user(val, ptr); /* No fault
- unless unwriteable. */
- restore_flags(tmp);
-#endif
- if (err) {
- info.si_signo = SIGSEGV;
- info.si_code = SEGV_MAPERR;
- goto fault;
- }
-
- if ( (ret < 0) && (ret >= -EMAXERRNO) ) {
- info.si_signo = SIGSYS;
- info.si_code = 0;
- goto fault;
- }
-
- return ret;
-
-fault:
- /* Go back to SYSCALL. */
- ((struct pt_regs *)&cmd)->cp0_epc -= 4;
-
- info.si_addr = (void *)((struct pt_regs *)&cmd)->cp0_epc;
- force_sig_info(info.si_signo, &info, current);
-
- return 0;
- }
+ case MIPS_ATOMIC_SET:
+ printk(KERN_CRIT "How did I get here?\n");
+ retval = -EINVAL;
+ goto out;
case MIPS_FIXADE:
tmp = current->thread.mflags & ~3;
|
|
From: Paul M. <le...@us...> - 2001-10-27 20:52:07
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel In directory usw-pr-cvs1:/tmp/cvs-serv30758/mips64/kernel Modified Files: scall_o32.S Log Message: sysmips syncups.. works fine on ITE board.. more testing probably needed. This brings us in sync with OSS on sysmips. Index: scall_o32.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/scall_o32.S,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- scall_o32.S 2001/09/09 20:17:15 1.8 +++ scall_o32.S 2001/10/27 20:52:05 1.9 @@ -227,8 +227,10 @@ jr ra END(mips_atomic_set) + LEAF(sys_sysmips) beq a0, MIPS_ATOMIC_SET, mips_atomic_set - j sys_sysmips + j _sys_sysmips + END(sys_sysmips) .macro syscalltable sys sys_syscall 0 /* 4000 */ |
|
From: James S. <jsi...@tr...> - 2001-10-27 20:43:17
|
We need module.h to port these functions to modules. Otherwise it will not compile. > Index: pci-dma.c > =================================================================== > RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci-dma.c,v > retrieving revision 1.3 > retrieving revision 1.4 > diff -u -d -r1.3 -r1.4 > --- pci-dma.c 2001/10/26 20:00:15 1.3 > +++ pci-dma.c 2001/10/27 17:28:54 1.4 > @@ -8,7 +8,6 @@ > * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. > */ > #include <linux/config.h> > -#include <linux/module.h> > #include <linux/types.h> > #include <linux/mm.h> > #include <linux/string.h> > > > _______________________________________________ > Linux-mips-commits mailing list > Lin...@li... > https://lists.sourceforge.net/lists/listinfo/linux-mips-commits > |
|
From: James S. <jsi...@us...> - 2001-10-27 20:40:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv27791 Modified Files: pci-dma.c Log Message: We need this to support exporting these functions to modules. Index: pci-dma.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci-dma.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- pci-dma.c 2001/10/27 17:28:54 1.4 +++ pci-dma.c 2001/10/27 20:40:12 1.5 @@ -8,6 +8,7 @@ * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. */ #include <linux/config.h> +#include <linux/module.h> #include <linux/types.h> #include <linux/mm.h> #include <linux/string.h> |
|
From: James S. <jsi...@tr...> - 2001-10-27 20:38:27
|
Be careful. This file in the OSS tree is really broken. I will send another patch to Ralph to fix this up. What we have in CVS is correct. The one in the OSS tree is broken. > Index: Config.in > =================================================================== > RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v > retrieving revision 1.15 > retrieving revision 1.16 > diff -u -d -r1.15 -r1.16 > --- Config.in 2001/10/26 17:36:56 1.15 > +++ Config.in 2001/10/27 17:28:54 1.16 > @@ -68,11 +68,6 @@ > fi > if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then > bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD > - if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then > - define_bool CONFIG_IT8172_CIR y > - else > - bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB > - fi > bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0 > bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1 > fi > @@ -87,6 +82,24 @@ > fi > bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE > fi > + if [ "$CONFIG_MIPS" = "y" ]; then > + bool ' TMPTX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912 > + dep_bool ' Console on TMPTX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912 > + bool ' Enable Au1000 UART Support' CONFIG_AU1000_UART > + if [ "$CONFIG_AU1000_UART" = "y" ]; then > + bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE > + fi > + fi > +fi > +if [ "$CONFIG_IT8712" = "y" ]; then > + bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD > + if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then > + define_bool CONFIG_IT8172_CIR y > + else > + bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB > + fi > + bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0 > + bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1 > fi > bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS > if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then > > > _______________________________________________ > Linux-mips-commits mailing list > Lin...@li... > https://lists.sourceforge.net/lists/listinfo/linux-mips-commits > |
|
From: James S. <jsi...@us...> - 2001-10-27 20:36:50
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv26764
Modified Files:
Config.in
Log Message:
More duplicated fields. Now it is fixed.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- Config.in 2001/10/27 17:40:13 1.17
+++ Config.in 2001/10/27 20:36:47 1.18
@@ -62,9 +62,9 @@
bool ' TMPTX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
dep_bool ' Console on TMPTX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
bool ' Enable Au1000 UART Support' CONFIG_AU1000_UART
- if [ "$CONFIG_AU1000_UART" = "y" ]; then
- bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
- fi
+ if [ "$CONFIG_AU1000_UART" = "y" ]; then
+ bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
+ fi
fi
if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
@@ -77,21 +77,13 @@
fi
bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
fi
- if [ "$CONFIG_MIPS" = "y" ]; then
- bool ' TMPTX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
- dep_bool ' Console on TMPTX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
- bool ' Enable Au1000 UART Support' CONFIG_AU1000_UART
- if [ "$CONFIG_AU1000_UART" = "y" ]; then
- bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
- fi
- fi
fi
-if [ "$CONFIG_IT8712" = "y" ]; then
+if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
- define_bool CONFIG_IT8172_CIR y
+ define_bool CONFIG_IT8172_CIR y
else
- bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
+ bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
fi
bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
|
|
From: James S. <jsi...@tr...> - 2001-10-27 20:30:48
|
This is not needed. It uses the universal ramdisk. Look at arch/mips/Makefile. I reversed the change. > =================================================================== > RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v > retrieving revision 1.3 > retrieving revision 1.4 > diff -u -d -r1.3 -r1.4 > --- Makefile 2001/10/26 22:30:51 1.3 > +++ Makefile 2001/10/27 17:28:54 1.4 > @@ -22,6 +22,12 @@ > > obj-$(CONFIG_REMOTE_DEBUG) += kgdb.o > > +obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o > + > +ramdisk.o: > + $(MAKE) -C ramdisk > + mv ramdisk/ramdisk.o ramdisk.o > + > clean: > rm -f *.o > > > > _______________________________________________ > Linux-mips-commits mailing list > Lin...@li... > https://lists.sourceforge.net/lists/listinfo/linux-mips-commits > |
|
From: James S. <jsi...@us...> - 2001-10-27 20:29:42
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino In directory usw-pr-cvs1:/tmp/cvs-serv25095 Modified Files: Makefile Log Message: We are using the universal ramdisk now. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- Makefile 2001/10/27 17:28:54 1.4 +++ Makefile 2001/10/27 20:29:40 1.5 @@ -22,12 +22,6 @@ obj-$(CONFIG_REMOTE_DEBUG) += kgdb.o -obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o - -ramdisk.o: - $(MAKE) -C ramdisk - mv ramdisk/ramdisk.o ramdisk.o - clean: rm -f *.o |
|
From: Paul M. <le...@us...> - 2001-10-27 17:40:16
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv22404
Modified Files:
Config.in
Log Message:
Nuke annoying duplicate entry.. die die die..
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -d -r1.16 -r1.17
--- Config.in 2001/10/27 17:28:54 1.16
+++ Config.in 2001/10/27 17:40:13 1.17
@@ -66,11 +66,6 @@
bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
fi
fi
-if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
- bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
- bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
- bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
-fi
if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
fi
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27
In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/sgi-ip27
Modified Files:
ip27-init.c ip27-timer.c
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: ip27-init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-init.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ip27-init.c 2001/10/22 19:16:45 1.2
+++ ip27-init.c 2001/10/27 17:28:54 1.3
@@ -364,7 +364,7 @@
#if 0
intr_init();
#endif
- set_cp0_status(ST0_IM, 0);
+ clear_cp0_status(ST0_IM);
per_hub_init(cnode);
cpu_time_init();
if (smp_processor_id()) /* master can't do this early, no kmalloc */
@@ -374,12 +374,12 @@
#if 0
install_tlbintr(cpu);
#endif
- set_cp0_status(SRB_DEV0 | SRB_DEV1, SRB_DEV0 | SRB_DEV1);
+ set_cp0_status(SRB_DEV0 | SRB_DEV1);
if (is_slave) {
- set_cp0_status(ST0_BEV, 0);
+ clear_cp0_status(ST0_BEV);
if (mips4_available)
- set_cp0_status(ST0_XX, ST0_XX);
- set_cp0_status(ST0_KX|ST0_SX|ST0_UX, ST0_KX|ST0_SX|ST0_UX);
+ set_cp0_status(ST0_XX);
+ set_cp0_status(ST0_KX|ST0_SX|ST0_UX);
sti();
load_mmu();
atomic_inc(&numstarted);
Index: ip27-timer.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-timer.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ip27-timer.c 2001/10/11 19:19:52 1.2
+++ ip27-timer.c 2001/10/27 17:28:54 1.3
@@ -253,7 +253,7 @@
printk("CPU %d clock is %dMHz.\n", smp_processor_id(), cpu->cpu_speed);
- set_cp0_status(SRB_TIMOCLK, SRB_TIMOCLK);
+ set_cp0_status(SRB_TIMOCLK);
}
void __init hub_rtc_init(cnodeid_t cnode)
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv20204/drivers/char
Modified Files:
Config.in
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- Config.in 2001/10/26 17:36:56 1.15
+++ Config.in 2001/10/27 17:28:54 1.16
@@ -68,11 +68,6 @@
fi
if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
- if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
- define_bool CONFIG_IT8172_CIR y
- else
- bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
- fi
bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
fi
@@ -87,6 +82,24 @@
fi
bool ' Console on DC21285 serial port' CONFIG_SERIAL_21285_CONSOLE
fi
+ if [ "$CONFIG_MIPS" = "y" ]; then
+ bool ' TMPTX3912/PR31700 serial port support' CONFIG_SERIAL_TX3912
+ dep_bool ' Console on TMPTX3912/PR31700 serial port' CONFIG_SERIAL_TX3912_CONSOLE $CONFIG_SERIAL_TX3912
+ bool ' Enable Au1000 UART Support' CONFIG_AU1000_UART
+ if [ "$CONFIG_AU1000_UART" = "y" ]; then
+ bool ' Enable Au1000 serial console' CONFIG_AU1000_SERIAL_CONSOLE
+ fi
+ fi
+fi
+if [ "$CONFIG_IT8712" = "y" ]; then
+ bool 'Enable Qtronix 990P Keyboard Support' CONFIG_QTRONIX_KEYBOARD
+ if [ "$CONFIG_QTRONIX_KEYBOARD" = "y" ]; then
+ define_bool CONFIG_IT8172_CIR y
+ else
+ bool ' Enable PS2 Keyboard Support' CONFIG_PC_KEYB
+ fi
+ bool 'Enable Smart Card Reader 0 Support ' CONFIG_IT8172_SCR0
+ bool 'Enable Smart Card Reader 1 Support ' CONFIG_IT8172_SCR1
fi
bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv20204/include/asm-mips64
Modified Files:
bootinfo.h mipsregs.h softirq.h system.h
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bootinfo.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- bootinfo.h 2001/07/09 19:28:48 1.2
+++ bootinfo.h 2001/10/27 17:28:55 1.3
@@ -91,8 +91,9 @@
#define MACH_SGI_CHALLENGE_S 1 /* The Challenge S server */
#define MACH_SGI_INDIGO2 2 /* The Indigo2 system */
#define MACH_SGI_IP27 3 /* Origin 200, Origin 2000, Onyx 2 */
+#define MACH_SGI_IP32 4 /* O2 */
-#define GROUP_SGI_NAMES { "Indy", "Challenge S", "Indigo2", "IP27" }
+#define GROUP_SGI_NAMES { "Indy", "Challenge S", "Indigo2", "IP27", "O2" }
/*
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mipsregs.h 2001/08/20 16:03:12 1.3
+++ mipsregs.h 2001/10/27 17:28:55 1.4
@@ -145,14 +145,39 @@
* Mostly used to access the interrupt bits.
*/
#define __BUILD_SET_CP0(name,register) \
-extern __inline__ unsigned int \
-set_cp0_##name(unsigned int change, unsigned int new) \
+extern inline unsigned int \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+extern inline unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+extern inline unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
\
res = read_32bit_cp0_register(register); \
res &= ~change; \
res |= (new & change); \
+ if (change) \
write_32bit_cp0_register(register, res); \
\
return res; \
Index: softirq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/softirq.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- softirq.h 2001/09/26 16:48:21 1.3
+++ softirq.h 2001/10/27 17:28:55 1.4
@@ -39,18 +39,4 @@
#define in_softirq() (local_bh_count(smp_processor_id()) != 0)
-extern inline void __cpu_raise_softirq(int cpu, int nr)
-{
- unsigned int *m = (unsigned int *) &softirq_pending(cpu);
- unsigned int temp;
-
- __asm__ __volatile__(
- "1:\tll\t%0, %1\t\t\t# __cpu_raise_softirq\n\t"
- "or\t%0, %2\n\t"
- "sc\t%0, %1\n\t"
- "beqz\t%0, 1b"
- : "=&r" (temp), "=m" (*m)
- : "ir" (1UL << nr), "m" (*m));
-}
-
#endif /* _ASM_SOFTIRQ_H */
Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- system.h 2001/10/17 17:16:09 1.5
+++ system.h 2001/10/27 17:28:55 1.6
@@ -212,7 +212,7 @@
#define SWITCH_DO_LAZY_FPU \
if (prev->flags & PF_USEDFPU) { \
lazy_fpu_switch(prev, 0); \
- set_cp0_status(ST0_CU1, ~ST0_CU1); \
+ clear_cp0_status(ST0_CU1); \
prev->flags &= ~PF_USEDFPU; \
}
#else /* CONFIG_SMP */
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32
In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/sgi-ip32
Modified Files:
ip32-irq.c
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: ip32-irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-irq.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ip32-irq.c 2001/10/26 16:13:55 1.2
+++ ip32-irq.c 2001/10/27 17:28:54 1.3
@@ -159,22 +159,23 @@
* uses this it seems, which is IRQ 0 and IP7.
*/
-static void enable_cpu_irq (unsigned int irq)
+static void enable_cpu_irq(unsigned int irq)
{
- set_cp0_status (STATUSF_IP7,~ST0_CU1);
+ set_cp0_status(STATUSF_IP7);
}
-static unsigned int startup_cpu_irq (unsigned int irq) {
- enable_cpu_irq (irq);
+static unsigned int startup_cpu_irq(unsigned int irq)
+{
+ enable_cpu_irq(irq);
return 0;
}
-static void disable_cpu_irq (unsigned int irq)
+static void disable_cpu_irq(unsigned int irq)
{
- clear_cp0_status (STATUSF_IP7);
+ clear_cp0_status(STATUSF_IP7);
}
-static void end_cpu_irq (unsigned int irq)
+static void end_cpu_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_cpu_irq (irq);
@@ -199,34 +200,34 @@
* We get to split the register in half and do faster lookups.
*/
-static void enable_crime_irq (unsigned int irq)
+static void enable_crime_irq(unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
- save_and_cli (flags);
- crime_mask = crime_read_64 (CRIME_INT_MASK);
+ save_and_cli(flags);
+ crime_mask = crime_read_64(CRIME_INT_MASK);
crime_mask |= 1 << (irq - 1);
- crime_write_64 (CRIME_INT_MASK, crime_mask);
- restore_flags (flags);
+ crime_write_64(CRIME_INT_MASK, crime_mask);
+ restore_flags(flags);
}
-static unsigned int startup_crime_irq (unsigned int irq)
+static unsigned int startup_crime_irq(unsigned int irq)
{
- enable_crime_irq (irq);
+ enable_crime_irq(irq);
return 0; /* This is probably not right; we could have pending irqs */
}
-static void disable_crime_irq (unsigned int irq)
+static void disable_crime_irq(unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
- save_and_cli (flags);
- crime_mask = crime_read_64 (CRIME_INT_MASK);
+ save_and_cli(flags);
+ crime_mask = crime_read_64(CRIME_INT_MASK);
crime_mask &= ~(1 << (irq - 1));
- crime_write_64 (CRIME_INT_MASK, crime_mask);
- restore_flags (flags);
+ crime_write_64(CRIME_INT_MASK, crime_mask);
+ restore_flags(flags);
}
static void mask_and_ack_crime_irq (unsigned int irq)
@@ -238,16 +239,16 @@
if ((irq <= CRIME_GBE0_IRQ && irq >= CRIME_GBE3_IRQ)
|| (irq <= CRIME_RE_EMPTY_E_IRQ && irq >= CRIME_RE_IDLE_E_IRQ)
|| (irq <= CRIME_SOFT0_IRQ && irq >= CRIME_SOFT2_IRQ)) {
- save_and_cli (flags);
- crime_mask = crime_read_64 (CRIME_HARD_INT);
+ save_and_cli(flags);
+ crime_mask = crime_read_64(CRIME_HARD_INT);
crime_mask &= ~(1 << (irq - 1));
- crime_write_64 (CRIME_HARD_INT, crime_mask);
- restore_flags (flags);
+ crime_write_64(CRIME_HARD_INT, crime_mask);
+ restore_flags(flags);
}
- disable_crime_irq (irq);
+ disable_crime_irq(irq);
}
-static void end_crime_irq (unsigned int irq)
+static void end_crime_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_crime_irq (irq);
@@ -266,48 +267,50 @@
NULL
};
-/* This is for MACE PCI interrupts. We can decrease bus traffic by masking
+/*
+ * This is for MACE PCI interrupts. We can decrease bus traffic by masking
* as close to the source as possible. This also means we can take the
* next chunk of the CRIME register in one piece.
*/
-static void enable_macepci_irq (unsigned int irq)
+static void enable_macepci_irq(unsigned int irq)
{
u32 mace_mask;
u64 crime_mask;
unsigned long flags;
- save_and_cli (flags);
- mace_mask = mace_read_32 (MACEPCI_CONTROL);
- mace_mask |= MACEPCI_CONTROL_INT (irq - 9);
- mace_write_32 (MACEPCI_CONTROL, mace_mask);
+ save_and_cli(flags);
+ mace_mask = mace_read_32(MACEPCI_CONTROL);
+ mace_mask |= MACEPCI_CONTROL_INT(irq - 9);
+ mace_write_32(MACEPCI_CONTROL, mace_mask);
/* In case the CRIME interrupt isn't enabled, we must enable it;
* however, we never disable interrupts at that level.
*/
- crime_mask = crime_read_64 (CRIME_INT_MASK);
+ crime_mask = crime_read_64(CRIME_INT_MASK);
crime_mask |= 1 << (irq - 1);
- crime_write_64 (CRIME_INT_MASK, crime_mask);
- restore_flags (flags);
+ crime_write_64(CRIME_INT_MASK, crime_mask);
+ restore_flags(flags);
}
-static unsigned int startup_macepci_irq (unsigned int irq) {
+static unsigned int startup_macepci_irq(unsigned int irq)
+{
enable_macepci_irq (irq);
return 0; /* XXX */
}
-static void disable_macepci_irq (unsigned int irq)
+static void disable_macepci_irq(unsigned int irq)
{
u32 mace_mask;
unsigned long flags;
- save_and_cli (flags);
- mace_mask = mace_read_32 (MACEPCI_CONTROL);
- mace_mask &= ~MACEPCI_CONTROL_INT (irq - 9);
- mace_write_32 (MACEPCI_CONTROL, mace_mask);
- restore_flags (flags);
+ save_and_cli(flags);
+ mace_mask = mace_read_32(MACEPCI_CONTROL);
+ mace_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
+ mace_write_32(MACEPCI_CONTROL, mace_mask);
+ restore_flags(flags);
}
-static void end_macepci_irq (unsigned int irq)
+static void end_macepci_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_macepci_irq (irq);
@@ -352,34 +355,35 @@
break;
}
DBG ("crime_int %016lx enabled\n", crime_int);
- save_and_cli (flags);
- crime_mask = crime_read_64 (CRIME_INT_MASK);
+ save_and_cli(flags);
+ crime_mask = crime_read_64(CRIME_INT_MASK);
crime_mask |= crime_int;
- crime_write_64 (CRIME_INT_MASK, crime_mask);
- mace_mask = mace_read_32 (MACEISA_INT_MASK);
+ crime_write_64(CRIME_INT_MASK, crime_mask);
+ mace_mask = mace_read_32(MACEISA_INT_MASK);
mace_mask |= 1 << (irq - 33);
- mace_write_32 (MACEISA_INT_MASK, mace_mask);
- restore_flags (flags);
+ mace_write_32(MACEISA_INT_MASK, mace_mask);
+ restore_flags(flags);
}
-static unsigned int startup_maceisa_irq (unsigned int irq) {
- enable_maceisa_irq (irq);
+static unsigned int startup_maceisa_irq (unsigned int irq)
+{
+ enable_maceisa_irq(irq);
return 0;
}
-static void disable_maceisa_irq (unsigned int irq)
+static void disable_maceisa_irq(unsigned int irq)
{
u32 mace_mask;
unsigned long flags;
save_and_cli (flags);
- mace_mask = mace_read_32 (MACEISA_INT_MASK);
+ mace_mask = mace_read_32(MACEISA_INT_MASK);
mace_mask &= ~(1 << (irq - 33));
- mace_write_32 (MACEISA_INT_MASK, mace_mask);
- restore_flags (flags);
+ mace_write_32(MACEISA_INT_MASK, mace_mask);
+ restore_flags(flags);
}
-static void mask_and_ack_maceisa_irq (unsigned int irq)
+static void mask_and_ack_maceisa_irq(unsigned int irq)
{
u32 mace_mask;
unsigned long flags;
@@ -388,17 +392,17 @@
case MACEISA_PARALLEL_IRQ:
case MACEISA_SERIAL1_TDMAPR_IRQ:
case MACEISA_SERIAL2_TDMAPR_IRQ:
- save_and_cli (flags);
- mace_mask = mace_read_32 (MACEISA_INT_STAT);
+ save_and_cli(flags);
+ mace_mask = mace_read_32(MACEISA_INT_STAT);
mace_mask &= ~(1 << (irq - 33));
- mace_write_32 (MACEISA_INT_STAT, mace_mask);
- restore_flags (flags);
+ mace_write_32(MACEISA_INT_STAT, mace_mask);
+ restore_flags(flags);
break;
}
- disable_maceisa_irq (irq);
+ disable_maceisa_irq(irq);
}
-static void end_maceisa_irq (unsigned irq)
+static void end_maceisa_irq(unsigned irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_maceisa_irq (irq);
@@ -421,7 +425,7 @@
* bits 0-3 and 7 in the CRIME register.
*/
-static void enable_mace_irq (unsigned int irq)
+static void enable_mace_irq(unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
@@ -433,13 +437,13 @@
restore_flags (flags);
}
-static unsigned int startup_mace_irq (unsigned int irq)
+static unsigned int startup_mace_irq(unsigned int irq)
{
- enable_mace_irq (irq);
+ enable_mace_irq(irq);
return 0;
}
-static void disable_mace_irq (unsigned int irq)
+static void disable_mace_irq(unsigned int irq)
{
u64 crime_mask;
unsigned long flags;
@@ -448,10 +452,10 @@
crime_mask = crime_read_64 (CRIME_INT_MASK);
crime_mask &= ~(1 << (irq - 1));
crime_write_64 (CRIME_INT_MASK, crime_mask);
- restore_flags (flags);
+ restore_flags(flags);
}
-static void end_mace_irq (unsigned int irq)
+static void end_mace_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
enable_mace_irq (irq);
@@ -493,12 +497,12 @@
mace = mace_read_32 (MACEPCI_CONTROL);
printk ("MACE PCI control register: %08x\n", mace);
- printk ("Register dump:\n");
- show_regs (regs);
+ printk("Register dump:\n");
+ show_regs(regs);
- printk ("Please mail this report to lin...@os...\n");
- printk ("Spinning...");
- while (1) ;
+ printk("Please mail this report to lin...@os...\n");
+ printk("Spinning...");
+ while(1) ;
}
void __init init_IRQ(void)
@@ -509,11 +513,11 @@
/* Install our interrupt handler, then clear and disable all
* CRIME and MACE interrupts.
*/
- crime_write_64 (CRIME_INT_MASK, 0);
- crime_write_64 (CRIME_HARD_INT, 0);
- crime_write_64 (CRIME_SOFT_INT, 0);
- mace_write_32 (MACEISA_INT_STAT, 0);
- mace_write_32 (MACEISA_INT_MASK, 0);
+ crime_write_64(CRIME_INT_MASK, 0);
+ crime_write_64(CRIME_HARD_INT, 0);
+ crime_write_64(CRIME_SOFT_INT, 0);
+ mace_write_32(MACEISA_INT_STAT, 0);
+ mace_write_32(MACEISA_INT_MASK, 0);
set_except_vector(0, ip32_handle_int);
for (i = 0; i < NR_IRQS; i++) {
@@ -542,12 +546,12 @@
irq_desc[irq].depth = 0;
irq_desc[irq].handler = controller;
}
- setup_irq (CRIME_MEMERR_IRQ, &memerr_irq);
- setup_irq (CRIME_CPUERR_IRQ, &cpuerr_irq);
+ setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
+ setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
}
/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
-void ip32_irq0 (struct pt_regs *regs)
+void ip32_irq0(struct pt_regs *regs)
{
u64 crime_int = crime_read_64 (CRIME_INT_STAT);
int irq = 0;
@@ -571,32 +575,32 @@
irq = ffs (crime_int) + 16;
}
if (irq == 0)
- ip32_unknown_interrupt (regs);
- DBG ("*irq %u*\n", irq);
- do_IRQ (irq, regs);
+ ip32_unknown_interrupt(regs);
+ DBG("*irq %u*\n", irq);
+ do_IRQ(irq, regs);
}
-void ip32_irq1 (struct pt_regs *regs)
+void ip32_irq1(struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
-void ip32_irq2 (struct pt_regs *regs)
+void ip32_irq2(struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
-void ip32_irq3 (struct pt_regs *regs)
+void ip32_irq3(struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
-void ip32_irq4 (struct pt_regs *regs)
+void ip32_irq4(struct pt_regs *regs)
{
ip32_unknown_interrupt (regs);
}
-void ip32_irq5 (struct pt_regs *regs)
+void ip32_irq5(struct pt_regs *regs)
{
do_IRQ (CLOCK_IRQ, regs);
}
@@ -830,6 +834,7 @@
return;
}
}
+
/*
* IRQ autodetection code..
*
@@ -1230,4 +1235,3 @@
do_softirq();
return 1;
}
-
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/drivers/pci In directory usw-pr-cvs1:/tmp/cvs-serv20204/drivers/pci Modified Files: Makefile Log Message: Sync with OSS (except for sysmips, which is waiting to be tested first). Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/pci/Makefile,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- Makefile 2001/10/19 21:19:39 1.6 +++ Makefile 2001/10/27 17:28:54 1.7 @@ -29,6 +29,7 @@ obj-$(CONFIG_SUPERH) += setup-bus.o setup-irq.o obj-$(CONFIG_ALL_PPC) += setup-bus.o obj-$(CONFIG_SGI_IP27) += setup-irq.o +obj-$(CONFIG_SGI_IP32) += setup-irq.o ifndef CONFIG_X86 obj-y += syscall.o |
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip22 In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/sgi-ip22 Modified Files: ip22-timer.c Log Message: Sync with OSS (except for sysmips, which is waiting to be tested first). Index: ip22-timer.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip22/ip22-timer.c,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- ip22-timer.c 2001/06/22 02:29:32 1.1.1.1 +++ ip22-timer.c 2001/10/27 17:28:54 1.2 @@ -221,7 +221,7 @@ r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); write_32bit_cp0_register(CP0_COMPARE, r4k_cur); - set_cp0_status(ST0_IM, ALLINTS); + change_cp0_status(ST0_IM, ALLINTS); sti(); write_lock_irq(&xtime_lock); |
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:58
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv20204/include/asm-mips
Modified Files:
mipsregs.h
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- mipsregs.h 2001/10/24 23:32:54 1.8
+++ mipsregs.h 2001/10/27 17:28:55 1.9
@@ -273,7 +273,7 @@
* Mostly used to access the interrupt bits.
*/
#define __BUILD_SET_CP0(name,register) \
-extern __inline__ unsigned int \
+extern inline unsigned int \
set_cp0_##name(unsigned int set) \
{ \
unsigned int res; \
@@ -285,7 +285,7 @@
return res; \
} \
\
-extern __inline__ unsigned int \
+extern inline unsigned int \
clear_cp0_##name(unsigned int clear) \
{ \
unsigned int res; \
@@ -297,7 +297,7 @@
return res; \
} \
\
-extern __inline__ unsigned int \
+extern inline unsigned int \
change_cp0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
@@ -305,7 +305,6 @@
res = read_32bit_cp0_register(register); \
res &= ~change; \
res |= (new & change); \
- if(change) \
write_32bit_cp0_register(register, res); \
\
return res; \
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/mm
Modified Files:
r4xx0.c
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- r4xx0.c 2001/10/11 23:06:13 1.5
+++ r4xx0.c 2001/10/27 17:28:54 1.6
@@ -330,7 +330,7 @@
"sd\t$0,-8(%0)\n\t"
".set\tat\n\t"
".set\treorder"
- : (page)
+ : "=r" (page)
: "0" (page), "I" (PAGE_SIZE), "i" (Create_Dirty_Excl_SD)
: "memory");
}
@@ -1907,7 +1907,7 @@
}
}
-static void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
+void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
if (CPU_CONTEXT(smp_processor_id(), mm) != 0) {
@@ -1957,7 +1957,7 @@
}
}
-static void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
if (CPU_CONTEXT(smp_processor_id(), vma->vm_mm) != 0) {
unsigned long flags;
@@ -2363,9 +2363,9 @@
printk("CPU revision is: %08x\n", read_32bit_cp0_register(CP0_PRID));
#ifdef CONFIG_MIPS_UNCACHED
- set_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
#else
- set_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
+ change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_NONCOHERENT);
#endif /* UNCACHED */
probe_icache(config);
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/mips-boards/generic In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/mips-boards/generic Modified Files: time.c Log Message: Sync with OSS (except for sysmips, which is waiting to be tested first). Index: time.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/mips-boards/generic/time.c,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- time.c 2001/10/05 17:07:14 1.2 +++ time.c 2001/10/27 17:28:54 1.3 @@ -263,7 +263,7 @@ r4k_cur = (read_32bit_cp0_register(CP0_COUNT) + r4k_offset); write_32bit_cp0_register(CP0_COMPARE, r4k_cur); - set_cp0_status(ST0_IM, ALLINTS); + change_cp0_status(ST0_IM, ALLINTS); /* Read time from the RTC chipset. */ write_lock_irqsave (&xtime_lock, flags); |
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64
In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64
Modified Files:
config.in
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/config.in,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- config.in 2001/10/15 16:09:45 1.4
+++ config.in 2001/10/27 17:28:54 1.5
@@ -13,7 +13,8 @@
comment 'Machine selection'
choice 'Machine type' \
"SGI-IP22,Indy/Indigo2 CONFIG_SGI_IP22 \
- SGI-IP27,Origin200/2000 CONFIG_SGI_IP27" SGI-IP27,Origin200/2000
+ SGI-IP27,Origin200/2000 CONFIG_SGI_IP27 \
+ SGI-IP32,O2 CONFIG_SGI_IP32" CONFIG_SGI_IP27
if [ "$CONFIG_SGI_IP27" = "y" ]; then
bool ' IP27 N-Mode' CONFIG_SGI_SN0_N_MODE
@@ -61,6 +62,17 @@
define_bool CONFIG_PCI y
define_bool CONFIG_QL_ISP_A64 y
define_int CONFIG_L1_CACHE_SHIFT 7
+fi
+
+if [ "$CONFIG_SGI_IP32" = "y" ]; then
+ define_bool CONFIG_BOOT_ELF32 y
+ define_bool CONFIG_ARC32 y
+ define_bool CONFIG_PC_KEYB y
+ define_bool CONFIG_PCI y
+ #define_bool CONFIG_BOARD_SCACHE y
+ define_bool CONFIG_MAPPED_PCI_IO y
+ define_bool CONFIG_ARC_MEMORY y
+ define_int CONFIG_L1_CACHE_SHIFT 5
fi
if [ "$CONFIG_ISA" != "y" ]; then
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips64/kernel
Modified Files:
process.c setup.c traps.c
Log Message:
Sync with OSS (except for sysmips, which is waiting to be tested first).
Index: process.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/process.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- process.c 2001/10/19 21:19:38 1.2
+++ process.c 2001/10/27 17:28:54 1.3
@@ -53,7 +53,7 @@
{
/* Forget lazy fpu state */
if (IS_FPU_OWNER()) {
- set_cp0_status(ST0_CU1, ST0_CU1);
+ set_cp0_status(ST0_CU1);
__asm__ __volatile__("cfc1\t$0,$31");
CLEAR_FPU_OWNER();
}
@@ -63,7 +63,7 @@
{
/* Forget lazy fpu state */
if (IS_FPU_OWNER()) {
- set_cp0_status(ST0_CU1, ST0_CU1);
+ set_cp0_status(ST0_CU1);
__asm__ __volatile__("cfc1\t$0,$31");
CLEAR_FPU_OWNER();
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- setup.c 2001/07/24 17:03:46 1.2
+++ setup.c 2001/10/27 17:28:54 1.3
@@ -97,6 +97,7 @@
extern void ip22_setup(void);
extern void ip27_setup(void);
+extern void ip32_setup(void);
static inline void cpu_probe(void)
{
@@ -143,6 +144,9 @@
#endif
#ifdef CONFIG_SGI_IP27
ip27_setup();
+#endif
+#ifdef CONFIG_SGI_IP32
+ ip32_setup();
#endif
#ifdef CONFIG_ARC_MEMORY
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- traps.c 2001/09/13 16:59:16 1.4
+++ traps.c 2001/10/27 17:28:54 1.5
@@ -441,7 +441,7 @@
switch(mips_cputype) {
case CPU_NEVADA:
memcpy((void *)(KSEG0 + 0x200), except_vec4, 8);
- set_cp0_cause(CAUSEF_IV, CAUSEF_IV);
+ set_cp0_cause(CAUSEF_IV);
dedicated_iv_available = 1;
}
}
@@ -473,7 +473,7 @@
case CPU_R8000:
case CPU_R10000:
mips4_available = 1;
- set_cp0_status(ST0_XX, ST0_XX);
+ set_cp0_status(ST0_XX);
}
}
@@ -482,7 +482,7 @@
unsigned int bits;
bits = ST0_KX|ST0_SX|ST0_UX;
- set_cp0_status(bits, bits);
+ set_cp0_status(bits);
printk("Entering 64-bit mode.\n");
}
@@ -496,7 +496,7 @@
unsigned long i;
/* Some firmware leaves the BEV flag set, clear it. */
- set_cp0_status(ST0_BEV, 0);
+ clear_cp0_status(ST0_BEV);
/* Copy the generic exception handler code to it's final destination. */
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
@@ -527,7 +527,7 @@
* should get some special optimizations.
*/
write_32bit_cp0_register(CP0_FRAMEMASK, 0);
- set_cp0_status(ST0_XX, ST0_XX);
+ set_cp0_status(ST0_XX);
goto r4k;
case CPU_R4000MC:
|
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:57
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips/philips/nino Modified Files: Makefile Log Message: Sync with OSS (except for sysmips, which is waiting to be tested first). Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- Makefile 2001/10/26 22:30:51 1.3 +++ Makefile 2001/10/27 17:28:54 1.4 @@ -22,6 +22,12 @@ obj-$(CONFIG_REMOTE_DEBUG) += kgdb.o +obj-$(CONFIG_BLK_DEV_INITRD) += ramdisk.o + +ramdisk.o: + $(MAKE) -C ramdisk + mv ramdisk/ramdisk.o ramdisk.o + clean: rm -f *.o |
|
From: Paul M. <le...@us...> - 2001-10-27 17:28:56
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv20204/arch/mips/kernel Modified Files: pci-dma.c Log Message: Sync with OSS (except for sysmips, which is waiting to be tested first). Index: pci-dma.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci-dma.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- pci-dma.c 2001/10/26 20:00:15 1.3 +++ pci-dma.c 2001/10/27 17:28:54 1.4 @@ -8,7 +8,6 @@ * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. */ #include <linux/config.h> -#include <linux/module.h> #include <linux/types.h> #include <linux/mm.h> #include <linux/string.h> |
|
From: Pete P. <pp...@us...> - 2001-10-26 22:36:06
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/galileo-boards In directory usw-pr-cvs1:/tmp/cvs-serv30237/include/asm-mips/galileo-boards Modified Files: ev96100.h Log Message: * the proper fix for the ev96100 serial console * ev96100 freezes when using the 'wait' instruction Index: ev96100.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/galileo-boards/ev96100.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -d -r1.1.1.1 -r1.2 --- ev96100.h 2001/06/22 02:29:33 1.1.1.1 +++ ev96100.h 2001/10/26 22:36:04 1.2 @@ -24,8 +24,8 @@ /* * Duart I/O ports. */ -#define EV96100_COM1_BASE_ADDR (0x1d000000 + 0x20) -#define EV96100_COM2_BASE_ADDR (0x1d000000 + 0x00) +#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20) +#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00) /* |
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