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From: James S. <jsi...@us...> - 2001-10-30 00:53:43
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt In directory usw-pr-cvs1:/tmp/cvs-serv26407 Modified Files: setup.c Log Message: Thansk to Jim Paris for pointing out this typo. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/setup.c,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- setup.c 2001/10/26 17:49:18 1.9 +++ setup.c 2001/10/30 00:53:41 1.10 @@ -148,7 +148,7 @@ ioport_resource.start = 0; ioport_resource.end = 0xffffffff; iomem_resource.start = 0; - ioport_resource.end = 0xffffffff; + iomem_resource.end = 0xffffffff; _machine_restart = cobalt_machine_restart; _machine_halt = cobalt_machine_halt; |
|
From: James S. <jsi...@us...> - 2001-10-30 00:51:02
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv25056
Modified Files:
config.in
Log Message:
Since the new pci code almost works for the qube I added this in. The tulip card is still broken :-( but it almost works.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.42
retrieving revision 1.43
diff -u -d -r1.42 -r1.43
--- config.in 2001/10/28 23:04:19 1.42
+++ config.in 2001/10/30 00:50:59 1.43
@@ -247,6 +247,7 @@
define_bool CONFIG_COBALT_LCD y
define_bool CONFIG_PCI y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_VADEM_CLIO_1000" = "y" ]; then
|
|
From: James S. <jsi...@us...> - 2001-10-30 00:50:09
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv24166
Modified Files:
pci_ops.c
Log Message:
Nice fixes to the new pci code.
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/pci_ops.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pci_ops.c 2001/10/25 21:39:48 1.5
+++ pci_ops.c 2001/10/30 00:50:06 1.6
@@ -117,8 +117,8 @@
|| ((PCI_SLOT (dev->devfn) > 6)
&& (PCI_SLOT (dev->devfn) <= 12)))) {
/* OK device number */
+ PCI_CFG_SET(dev, where);
if (access_type == PCI_ACCESS_READ) {
- PCI_CFG_SET(dev, (where & ~0x3));
*data = *PCI_CFG_DATA;
} else
*PCI_CFG_DATA = *data;
@@ -132,7 +132,7 @@
{
u32 data = 0;
- if (config_access(PCI_ACCESS_READ, dev, where, &data)) {
+ if (config_access(PCI_ACCESS_READ, dev, (where & ~0x3), &data)) {
*val = 0xff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -151,7 +151,7 @@
if (where & 0x1)
return PCIBIOS_BAD_REGISTER_NUMBER;
- if (config_access(PCI_ACCESS_READ, dev, where, &data)) {
+ if (config_access(PCI_ACCESS_READ, dev, (where & ~0x3), &data)) {
*val = 0xffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
@@ -179,13 +179,12 @@
return PCIBIOS_SUCCESSFUL;
}
-
static int
write_config_byte (struct pci_dev *dev, int where, u8 val)
{
u32 data = 0;
- if (config_access(PCI_ACCESS_READ, dev, where, &data))
+ if (config_access(PCI_ACCESS_READ, dev, (where & ~0x3), &data))
return PCIBIOS_DEVICE_NOT_FOUND;
data = (data & ~(0xff << ((where & 3) << 3))) |
@@ -207,7 +206,7 @@
if (where & 0x1)
return PCIBIOS_BAD_REGISTER_NUMBER;
- if (config_access(PCI_ACCESS_READ, dev, where, &data))
+ if (config_access(PCI_ACCESS_READ, dev, (where & ~0x3), &data))
return PCIBIOS_DEVICE_NOT_FOUND;
data = (data & ~(0xffff << ((where & 3) << 3))) |
@@ -233,8 +232,6 @@
DBG("cfg write dword: bus %d dev_fn %x where %x: val %x\n",
dev->bus->number, dev->devfn, where, val);
- if (config_access(PCI_ACCESS_WRITE, dev, where, &val))
- return -1;
return PCIBIOS_SUCCESSFUL;
}
|
|
From: Pete P. <pp...@us...> - 2001-10-29 19:23:56
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv5310/arch/mips/au1000/common
Modified Files:
serial.c
Log Message:
Applied Sato-san's patch to fix the 9600 baud problem.
Index: serial.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/serial.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- serial.c 2001/08/28 07:23:54 1.2
+++ serial.c 2001/10/29 19:23:51 1.3
@@ -244,12 +244,12 @@
static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
{
- return (inl(info->port+offset) & 0xff);
+ return (inl(info->port+offset) & 0xffff);
}
static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
{
- outl(value & 0xff, info->port+offset);
+ outl(value & 0xffff, info->port+offset);
}
|
|
From: James S. <jsi...@us...> - 2001-10-29 19:08:08
|
Update of /cvsroot/linux-mips/linux/drivers/char In directory usw-pr-cvs1:/tmp/cvs-serv1037 Modified Files: rtc_dallas.c Log Message: Added in proper copyright. Index: rtc_dallas.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/char/rtc_dallas.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- rtc_dallas.c 2001/10/26 16:47:44 1.1 +++ rtc_dallas.c 2001/10/29 19:08:06 1.2 @@ -4,6 +4,10 @@ * arch/mips/kernel/rtc_dallas.c * low-level RTC hookups for Dallas PC style chip. * + * Based on rtc_ds1386.c by Jun Sun <js...@mv...> + * Copyright 2001 MontaVista Software Inc. + * Author: js...@mv... or js...@ju... + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your |
|
From: James S. <jsi...@us...> - 2001-10-29 17:45:25
|
Update of /cvsroot/linux-mips/linux/arch/mips64/arc In directory usw-pr-cvs1:/tmp/cvs-serv10871 Added Files: identify.c Log Message: Add IP32 to table. |
|
From: James S. <jsi...@us...> - 2001-10-29 17:42:50
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv10000/include/asm-mips
Modified Files:
bugs.h
Log Message:
Move check_bugs() and co. away from a headerfile.
Index: bugs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bugs.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- bugs.h 2001/10/26 22:36:04 1.5
+++ bugs.h 2001/10/29 17:42:46 1.6
@@ -1,57 +1,12 @@
/*
- * Copyright (C) 1995 Waldorf Electronics
- * Copyright (C) 1997, 1999 Ralf Baechle
- */
-#include <asm/bootinfo.h>
-#include <asm/processor.h>
-#include <asm/cpu.h>
-
-/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
-
+#ifndef __ASM_BUGS_H
+#define __ASM_BUGS_H
-static inline void check_wait(void)
-{
- printk("Checking for 'wait' instruction... ");
- switch(mips_cpu.cputype) {
- case CPU_R3081:
- case CPU_R3081E:
- cpu_wait = r3081_wait;
- printk(" available.\n");
- break;
- case CPU_TX3927:
- case CPU_TX39XX:
- cpu_wait = r39xx_wait;
- printk(" available.\n");
- break;
- case CPU_R4200:
-/* case CPU_R4300: */
- case CPU_R4600:
- case CPU_R4640:
- case CPU_R4650:
- case CPU_R4700:
- case CPU_R5000:
- case CPU_NEVADA:
-#ifndef CONFIG_MIPS_EV96100
- /* ev96100 freezes when using the wait instruction */
- case CPU_RM7000:
-#endif
- case CPU_TX49XX:
- cpu_wait = r4k_wait;
- printk(" available.\n");
- break;
- default:
- printk(" unavailable.\n");
- break;
- }
-}
+extern void check_bugs(void);
-static void __init
-check_bugs(void)
-{
- check_wait();
-}
+#endif /* __ASM_BUGS_H */
|
|
From: James S. <jsi...@us...> - 2001-10-29 17:42:50
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv10000/arch/mips64/kernel
Modified Files:
setup.c
Log Message:
Move check_bugs() and co. away from a headerfile.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2001/10/27 17:28:54 1.3
+++ setup.c 2001/10/29 17:42:46 1.4
@@ -4,7 +4,8 @@
* for more details.
*
* Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999 Ralf Baechle
+ * Copyright (C) 1995 Waldorf Electronics
+ * Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle
* Copyright (C) 1996 Stoned Elipot
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
@@ -98,6 +99,30 @@
extern void ip22_setup(void);
extern void ip27_setup(void);
extern void ip32_setup(void);
+
+static inline void check_wait(void)
+{
+ printk("Checking for 'wait' instruction... ");
+ switch(mips_cputype) {
+ case CPU_R4200:
+ case CPU_R4300:
+ case CPU_R4600:
+ case CPU_R4700:
+ case CPU_R5000:
+ case CPU_NEVADA:
+ wait_available = 1;
+ printk(" available.\n");
+ break;
+ default:
+ printk(" unavailable.\n");
+ break;
+ }
+}
+
+void __init check_bugs(void)
+{
+ check_wait();
+}
static inline void cpu_probe(void)
{
|
|
From: James S. <jsi...@us...> - 2001-10-29 17:42:50
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv10000/arch/mips/kernel
Modified Files:
setup.c
Log Message:
Move check_bugs() and co. away from a headerfile.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.25
retrieving revision 1.26
diff -u -d -r1.25 -r1.26
--- setup.c 2001/10/28 23:04:19 1.25
+++ setup.c 2001/10/29 17:42:46 1.26
@@ -4,7 +4,8 @@
* for more details.
*
* Copyright (C) 1995 Linus Torvalds
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Ralf Baechle
+ * Copyright (C) 1995 Waldorf Electronics
+ * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001 Ralf Baechle
* Copyright (C) 1996 Stoned Elipot
* Copyright (C) 2000 Maciej W. Rozycki
*/
@@ -120,6 +121,44 @@
static struct resource code_resource = { "Kernel code" };
static struct resource data_resource = { "Kernel data" };
+
+static inline void check_wait(void)
+{
+ printk("Checking for 'wait' instruction... ");
+ switch(mips_cpu.cputype) {
+ case CPU_R3081:
+ case CPU_R3081E:
+ cpu_wait = r3081_wait;
+ printk(" available.\n");
+ break;
+ case CPU_TX3927:
+ case CPU_TX39XX:
+ cpu_wait = r39xx_wait;
+ printk(" available.\n");
+ break;
+ case CPU_R4200:
+/* case CPU_R4300: */
+ case CPU_R4600:
+ case CPU_R4640:
+ case CPU_R4650:
+ case CPU_R4700:
+ case CPU_R5000:
+ case CPU_NEVADA:
+ case CPU_RM7000:
+ case CPU_TX49XX:
+ cpu_wait = r4k_wait;
+ printk(" available.\n");
+ break;
+ default:
+ printk(" unavailable.\n");
+ break;
+ }
+}
+
+void __init check_bugs(void)
+{
+ check_wait();
+}
/*
* Probe whether cpu has config register by trying to play with
|
|
From: James S. <jsi...@us...> - 2001-10-29 17:42:49
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64 In directory usw-pr-cvs1:/tmp/cvs-serv10000/include/asm-mips64 Added Files: bugs.h Log Message: Move check_bugs() and co. away from a headerfile. --- NEW FILE: bugs.h --- /* * This is included by init/main.c to check for architecture-dependent bugs. * * Needs: * void check_bugs(void); */ #ifndef __ASM_BUGS_H #define __ASM_BUGS_H extern void check_bugs(void); #endif /* __ASM_BUGS_H */ |
|
From: James S. <jsi...@us...> - 2001-10-29 17:37:04
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv8130/philips/nino
Modified Files:
irq.c prom.c setup.c time.c
Log Message:
Nino updates.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq.c 2001/10/26 22:30:51 1.3
+++ irq.c 2001/10/29 17:37:01 1.4
@@ -1,65 +1,24 @@
/*
- * irq.c: Fine grained interrupt handling for Nino
+ * include/arch/mips/philips/nino/irq.c
*
* Copyright (C) 2001 Steven J. Hill (sj...@re...)
*/
#include <linux/init.h>
-
-#include <linux/errno.h>
-#include <linux/kernel_stat.h>
-#include <linux/signal.h>
#include <linux/sched.h>
-#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-
-#include <asm/bitops.h>
-#include <asm/bootinfo.h>
-#include <asm/io.h>
#include <asm/irq.h>
#include <asm/mipsregs.h>
-#include <asm/system.h>
-
-#include <asm/ptrace.h>
-#include <asm/processor.h>
#include <asm/tx3912.h>
-/*
- * Linux has a controller-independent x86 interrupt architecture.
- * every controller has a 'controller-template', that is used
- * by the main code to do the right thing. Each driver-visible
- * interrupt source is transparently wired to the apropriate
- * controller. Thus drivers need not be aware of the
- * interrupt-controller.
- *
- * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
- * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
- * (IO-APICs assumed to be messaging to Pentium local-APICs)
- *
- * the code is designed to be easily extended with new/different
- * interrupt controllers, without having to do assembly magic.
- */
-
-extern asmlinkage void ninoIRQ(void);
extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
-extern void init_generic_irq(void);
static void enable_irq4(unsigned int irq)
{
- unsigned long flags;
-
- save_and_cli(flags);
if(irq == 0) {
IntEnable5 |= INT5_PERIODICINT;
IntEnable6 |= INT6_PERIODICINT;
}
- restore_flags(flags);
}
static unsigned int startup_irq4(unsigned int irq)
@@ -71,15 +30,11 @@
static void disable_irq4(unsigned int irq)
{
- unsigned long flags;
-
- save_and_cli(flags);
if(irq == 0) {
- IntEnable6 &= ~INT6_PERIODICINT;
- IntClear5 |= INT5_PERIODICINT;
- IntClear6 |= INT6_PERIODICINT;
+ IntEnable6 &= ~INT6_PERIODICINT;
+ IntClear5 |= INT5_PERIODICINT;
+ IntClear6 |= INT6_PERIODICINT;
}
- restore_flags(flags);
}
#define shutdown_irq4 disable_irq4
@@ -92,7 +47,7 @@
}
static struct hw_interrupt_type irq4_type = {
- "IRQ4",
+ "MIPS",
startup_irq4,
shutdown_irq4,
enable_irq4,
@@ -113,7 +68,7 @@
/* if irq == -1, then the interrupt has already been cleared */
if(irq == -1) {
- printk("IRQ6 Status Register = 0x%08x\n", IntStatus6);
+ printk("IRQ6 Status Register = 0x%08lx\n", IntStatus6);
goto end;
}
@@ -126,21 +81,11 @@
static void enable_irq2(unsigned int irq)
{
- unsigned long flags;
-
- save_and_cli(flags);
+ set_cp0_status(STATUSF_IP4);
if(irq == 2 || irq == 3) {
- IntEnable1 = 0x00000000;
- IntEnable2 = 0xfffff000;
- IntEnable3 = 0x00000000;
- IntEnable4 = 0x00000000;
- IntClear1 = 0xffffffff;
IntClear2 = 0xffffffff;
- IntClear3 = 0xffffffff;
- IntClear4 = 0xffffffff;
- IntClear5 = 0xffffffff;
+ IntEnable2 = 0xfffff000;
}
- restore_flags(flags);
}
static unsigned int startup_irq2(unsigned int irq)
@@ -152,19 +97,7 @@
static void disable_irq2(unsigned int irq)
{
- unsigned long flags;
-
- save_and_cli(flags);
- IntEnable1 = 0x00000000;
- IntEnable2 = 0x00000000;
- IntEnable3 = 0x00000000;
- IntEnable4 = 0x00000000;
- IntClear1 = 0xffffffff;
- IntClear2 = 0xffffffff;
- IntClear3 = 0xffffffff;
- IntClear4 = 0xffffffff;
- IntClear5 = 0xffffffff;
- restore_flags(flags);
+ clear_cp0_status(STATUSF_IP4);
}
#define shutdown_irq2 disable_irq2
@@ -177,7 +110,7 @@
}
static struct hw_interrupt_type irq2_type = {
- "IRQ2",
+ "MIPS",
startup_irq2,
shutdown_irq2,
enable_irq2,
@@ -202,6 +135,7 @@
/* if irq == -1, then the interrupt has already been cleared */
if (irq == -1) {
+ printk("EEK\n");
IntClear1 = 0xffffffff;
IntClear3 = 0xffffffff;
IntClear4 = 0xffffffff;
@@ -219,7 +153,7 @@
void irq_bad(struct pt_regs *regs)
{
/* This should never happen */
- printk("Invalid interrupt, spinning...\n");
+ printk("Stray interrupt, spinning...\n");
printk(" CAUSE register = 0x%08lx\n", regs->cp0_cause);
printk("STATUS register = 0x%08lx\n", regs->cp0_status);
printk(" EPC register = 0x%08lx\n", regs->cp0_epc);
@@ -228,30 +162,32 @@
void __init nino_irq_setup(void)
{
+ extern asmlinkage void ninoIRQ(void);
+ extern void init_generic_irq(void);
+
unsigned int i;
- /* Disable interrupts */
- IntEnable1 = 0x00000000;
- IntEnable2 = 0x00000000;
- IntEnable3 = 0x00000000;
- IntEnable4 = 0x00000000;
- IntEnable5 = 0x00000000;
- IntEnable6 = 0x00000000;
+ /* Disable all hardware interrupts */
+ change_cp0_status(ST0_IM, 0x00);
- /* Clear interrupts */
+ /* Clear any pending interrupts */
IntClear1 = 0xffffffff;
IntClear2 = 0xffffffff;
IntClear3 = 0xffffffff;
IntClear4 = 0xffffffff;
IntClear5 = 0xffffffff;
- /* Change location of exception vector table */
- change_cp0_status(ST0_BEV, 0);
+ /* FIXME: disable interrupts 1,3,4 */
+ IntEnable1 = 0x00000000;
+ IntEnable2 = 0xfffff000;
+ IntEnable3 = 0x00000000;
+ IntEnable4 = 0x00000000;
+ IntEnable5 = 0xffffffff;
/* Initialize IRQ vector table */
init_generic_irq();
- /* Initialize hardware IRQ structure */
+ /* Initialize IRQ action handlers */
for (i = 0; i < 16; i++) {
hw_irq_controller *handler = NULL;
if (i == 0)
@@ -269,6 +205,12 @@
/* Set up the external interrupt exception vector */
set_except_vector(0, ninoIRQ);
+
+ /* Enable high priority interrupts */
+ IntEnable6 = (INT6_GLOBALEN | 0xffff);
+
+ /* Enable interrupts */
+ change_cp0_status(ST0_IM, IE_IRQ2 | IE_IRQ4);
}
void (*irq_setup)(void);
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/prom.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- prom.c 2001/06/22 02:29:32 1.1.1.1
+++ prom.c 2001/10/29 17:37:01 1.2
@@ -20,26 +20,19 @@
char arcs_cmdline[COMMAND_LINE_SIZE];
#ifdef CONFIG_FB_TX3912
-extern u_long tx3912fb_paddr;
-extern u_long tx3912fb_vaddr;
-extern u_long tx3912fb_size;
+extern unsigned long tx3912fb_paddr;
+extern unsigned long tx3912fb_vaddr;
+extern unsigned long tx3912fb_size;
#endif
/* Do basic initialization */
void __init prom_init(int argc, char **argv,
unsigned long magic, int *prom_vec)
{
- u_long free_end, mem_size;
- u_int i;
+ unsigned long mem_size;
+ unsigned int i;
- /*
- * collect args and prepare cmd_line
- */
- for (i = 1; i < argc; i++) {
- strcat(arcs_cmdline, argv[i]);
- if (i < (argc - 1))
- strcat(arcs_cmdline, " ");
- }
+ strcpy(arcs_cmdline, "console=tty0 console=ttyS0,115200");
mips_machgroup = MACH_GROUP_PHILIPS;
mips_machtype = MACH_PHILIPS_NINO;
@@ -53,6 +46,9 @@
#endif
#ifdef CONFIG_FB_TX3912
+{
+ unsigned long free_end;
+
/*
* The LCD controller requires that the framebuffer
* start address fall within a 1MB segment and is
@@ -70,6 +66,7 @@
*/
tx3912fb_paddr = PHYSADDR(free_end);
tx3912fb_vaddr = KSEG1ADDR(free_end);
+}
#else
add_memory_region(0, mem_size, BOOT_MEM_RAM);
#endif
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- setup.c 2001/10/26 22:30:51 1.2
+++ setup.c 2001/10/29 17:37:01 1.3
@@ -10,6 +10,7 @@
* Interrupt and exception initialization for Philips Nino.
*/
#include <linux/init.h>
+#include <linux/interrupt.h>
#include <linux/sched.h>
#include <asm/addrspace.h>
#include <asm/io.h>
@@ -18,7 +19,7 @@
#include <asm/time.h>
#include <asm/tx3912.h>
-void nino_machine_restart(char *command)
+static void nino_machine_restart(char *command)
{
static void (*back_to_prom)(void) = (void (*)(void)) 0xbfc00000;
@@ -26,13 +27,13 @@
back_to_prom();
}
-void nino_machine_halt(void)
+static void nino_machine_halt(void)
{
printk("Nino halted.\n");
while(1);
}
-void nino_machine_power_off(void)
+static void nino_machine_power_off(void)
{
printk("Nino halted. Please turn off power.\n");
while(1);
@@ -56,35 +57,26 @@
outl(scratch, TX3912_CLK_CTRL_BASE);
}
-extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
-
static __init void nino_timer_setup(struct irqaction *irq)
{
+ irq->dev_id = (void *) irq;
setup_irq(0, irq);
-
- /* Enable all hardware interrupts */
- set_cp0_status(IE_IRQ5 | IE_IRQ4 | IE_IRQ3 |
- IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
-
- /* Enable all the high priority interrupts */
- IntEnable6 = (INT6_GLOBALEN | 0xffff);
-
}
-extern void nino_irq_setup(void);
-extern void nino_wait(void);
-
void __init nino_setup(void)
{
+ extern void nino_irq_setup(void);
+ extern void nino_wait(void);
+
irq_setup = nino_irq_setup;
- mips_io_port_base = KSEG1ADDR(0xb0c00000);
+ mips_io_port_base = KSEG1ADDR(0x10c00000);
+ _machine_restart = nino_machine_restart;
+ _machine_halt = nino_machine_halt;
+ _machine_power_off = nino_machine_power_off;
+
board_time_init = nino_time_init;
board_timer_setup = nino_timer_setup;
-
- _machine_restart = nino_machine_restart;
- _machine_halt = nino_machine_halt;
- _machine_power_off = nino_machine_power_off;
cpu_wait = nino_wait;
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/time.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- time.c 2001/10/26 22:30:51 1.2
+++ time.c 2001/10/29 17:37:01 1.3
@@ -29,8 +29,8 @@
static struct timeval xbase;
-void (*board_time_init)(void) = NULL;
-void (*board_timer_setup)(struct irqaction *irq) = NULL;
+void (*board_time_init) (void) = NULL;
+void (*board_timer_setup) (struct irqaction * irq) = NULL;
#define USECS_PER_JIFFY (1000000/HZ)
@@ -41,10 +41,10 @@
static unsigned long do_gettimeoffset(void)
{
- /*
- * This is a kludge
- */
- return 0;
+ /*
+ * This is a kludge
+ */
+ return 0;
}
static
@@ -57,7 +57,7 @@
do {
*high = RTChigh & RTC_HIGHMASK;
*low = RTClow;
- } while (*high != (RTChigh & RTC_HIGHMASK) || RTClow!=*low);
+ } while (*high != (RTChigh & RTC_HIGHMASK) || RTClow != *low);
}
/*
@@ -65,71 +65,71 @@
*/
void do_gettimeofday(struct timeval *tv)
{
- unsigned long flags;
- unsigned long high, low;
+ unsigned long flags;
+ unsigned long high, low;
- read_lock_irqsave(&xtime_lock, flags);
- // 40 bit RTC, driven by 32khz source:
- // +-----------+-----------------------------------------+
- // | HHHH.HHHH | LLLL.LLLL.LLLL.LLLL.LMMM.MMMM.MMMM.MMMM |
- // +-----------+-----------------------------------------+
- readRTC(&high,&low);
- tv->tv_sec = (high << 17) | (low >> 15);
- tv->tv_usec = (low % 32768) * 1953 / 64;
- tv->tv_sec += xbase.tv_sec;
- tv->tv_usec += xbase.tv_usec;
+ read_lock_irqsave(&xtime_lock, flags);
+ // 40 bit RTC, driven by 32khz source:
+ // +-----------+-----------------------------------------+
+ // | HHHH.HHHH | LLLL.LLLL.LLLL.LLLL.LMMM.MMMM.MMMM.MMMM |
+ // +-----------+-----------------------------------------+
+ readRTC(&high, &low);
+ tv->tv_sec = (high << 17) | (low >> 15);
+ tv->tv_usec = (low % 32768) * 1953 / 64;
+ tv->tv_sec += xbase.tv_sec;
+ tv->tv_usec += xbase.tv_usec;
- tv->tv_usec += do_gettimeoffset();
+ tv->tv_usec += do_gettimeoffset();
- /*
- * xtime is atomically updated in timer_bh. lost_ticks is
- * nonzero if the timer bottom half hasnt executed yet.
- */
- if (jiffies - wall_jiffies)
- tv->tv_usec += USECS_PER_JIFFY;
+ /*
+ * xtime is atomically updated in timer_bh. lost_ticks is
+ * nonzero if the timer bottom half hasnt executed yet.
+ */
+ if (jiffies - wall_jiffies)
+ tv->tv_usec += USECS_PER_JIFFY;
- read_unlock_irqrestore(&xtime_lock, flags);
+ read_unlock_irqrestore(&xtime_lock, flags);
- if (tv->tv_usec >= 1000000) {
- tv->tv_usec -= 1000000;
- tv->tv_sec++;
- }
+ if (tv->tv_usec >= 1000000) {
+ tv->tv_usec -= 1000000;
+ tv->tv_sec++;
+ }
}
void do_settimeofday(struct timeval *tv)
{
- write_lock_irq(&xtime_lock);
- /* This is revolting. We need to set the xtime.tv_usec
- * correctly. However, the value in this location is
- * is value at the last tick.
- * Discover what correction gettimeofday
- * would have done, and then undo it!
- */
- tv->tv_usec -= do_gettimeoffset();
+ write_lock_irq(&xtime_lock);
+ /* This is revolting. We need to set the xtime.tv_usec
+ * correctly. However, the value in this location is
+ * is value at the last tick.
+ * Discover what correction gettimeofday
+ * would have done, and then undo it!
+ */
+ tv->tv_usec -= do_gettimeoffset();
- if (tv->tv_usec < 0) {
- tv->tv_usec += 1000000;
- tv->tv_sec--;
- }
+ if (tv->tv_usec < 0) {
+ tv->tv_usec += 1000000;
+ tv->tv_sec--;
+ }
- /* reset RTC to 0 (real time is xbase + RTC) */
- xbase = *tv;
- RTCtimerControl |= TIM_RTCCLEAR;
- RTCtimerControl &= ~TIM_RTCCLEAR;
- RTCalarmHigh = RTCalarmLow = ~0UL;
+ /* reset RTC to 0 (real time is xbase + RTC) */
+ xbase = *tv;
+ RTCtimerControl |= TIM_RTCCLEAR;
+ RTCtimerControl &= ~TIM_RTCCLEAR;
+ RTCalarmHigh = RTCalarmLow = ~0UL;
- xtime = *tv;
- time_state = TIME_BAD;
- time_maxerror = MAXPHASE;
- time_esterror = MAXPHASE;
- write_unlock_irq(&xtime_lock);
+ xtime = *tv;
+ time_state = TIME_BAD;
+ time_maxerror = MAXPHASE;
+ time_esterror = MAXPHASE;
+ write_unlock_irq(&xtime_lock);
}
static int set_rtc_mmss(unsigned long nowtime)
{
- int retval = 0;
+ int retval = 0;
- return retval;
+ return retval;
}
/* last time the cmos clock got updated */
@@ -142,78 +142,77 @@
int do_write = 1;
-static void
-timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
#ifdef POLL_STATUS
- static unsigned long old_IntStatus1 = 0;
- static unsigned long old_IntStatus3 = 0;
- static unsigned long old_IntStatus4 = 0;
- static unsigned long old_IntStatus5 = 0;
- static int counter = 0;
- int i;
+ static unsigned long old_IntStatus1 = 0;
+ static unsigned long old_IntStatus3 = 0;
+ static unsigned long old_IntStatus4 = 0;
+ static unsigned long old_IntStatus5 = 0;
+ static int counter = 0;
+ int i;
- new_spircv = SPIData & 0xff;
- if ((old_spircv != new_spircv) && (new_spircv != 0xff)) {
- printk( "SPIData changed: %x\n", new_spircv );
- }
- old_spircv = new_spircv;
- if (do_write)
- SPIData = 0;
+ new_spircv = SPIData & 0xff;
+ if ((old_spircv != new_spircv) && (new_spircv != 0xff)) {
+ printk("SPIData changed: %x\n", new_spircv);
+ }
+ old_spircv = new_spircv;
+ if (do_write)
+ SPIData = 0;
#endif
- if (!user_mode(regs)) {
- if (prof_buffer && current->pid) {
- extern int _stext;
- unsigned long pc = regs->cp0_epc;
+ if (!user_mode(regs)) {
+ if (prof_buffer && current->pid) {
+ extern int _stext;
+ unsigned long pc = regs->cp0_epc;
- pc -= (unsigned long) &_stext;
- pc >>= prof_shift;
- /*
- * Dont ignore out-of-bounds pc values silently,
- * put them into the last histogram slot, so if
- * present, they will show up as a sharp peak.
- */
- if (pc > prof_len - 1)
- pc = prof_len - 1;
- atomic_inc((atomic_t *) & prof_buffer[pc]);
- }
- }
+ pc -= (unsigned long) &_stext;
+ pc >>= prof_shift;
+ /*
+ * Dont ignore out-of-bounds pc values silently,
+ * put them into the last histogram slot, so if
+ * present, they will show up as a sharp peak.
+ */
+ if (pc > prof_len - 1)
+ pc = prof_len - 1;
+ atomic_inc((atomic_t *) & prof_buffer[pc]);
+ }
+ }
- /*
- * aaaand... action!
- */
- do_timer(regs);
+ /*
+ * aaaand... action!
+ */
+ do_timer(regs);
- /*
- * If we have an externally syncronized Linux clock, then update
- * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
- * called as close as possible to 500 ms before the new second starts.
- */
- if (time_state != TIME_BAD && xtime.tv_sec > last_rtc_update + 660 &&
- xtime.tv_usec > 500000 - (tick >> 1) &&
- xtime.tv_usec < 500000 + (tick >> 1))
- {
- if (set_rtc_mmss(xtime.tv_sec) == 0)
- last_rtc_update = xtime.tv_sec;
- else
- last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
- }
+ /*
+ * If we have an externally syncronized Linux clock, then update
+ * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
+ * called as close as possible to 500 ms before the new second starts.
+ */
+ if (time_state != TIME_BAD && xtime.tv_sec > last_rtc_update + 660
+ && xtime.tv_usec > 500000 - (tick >> 1)
+ && xtime.tv_usec < 500000 + (tick >> 1)) {
+ if (set_rtc_mmss(xtime.tv_sec) == 0)
+ last_rtc_update = xtime.tv_sec;
+ else
+ last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
+ }
}
-static struct irqaction irq0 = {timer_interrupt, SA_INTERRUPT, 0,
- "timer", NULL, NULL};
+static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, 0,
+ "timer", NULL, NULL
+};
int __init time_init(void)
{
- struct timeval starttime;
+ struct timeval starttime;
- starttime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
- starttime.tv_usec = 0;
- do_settimeofday(&starttime);
+ starttime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
+ starttime.tv_usec = 0;
+ do_settimeofday(&starttime);
- board_time_init();
- board_timer_setup(&irq0);
+ board_time_init();
+ board_timer_setup(&irq0);
- return 0;
+ return 0;
}
|
|
From: James S. <jsi...@us...> - 2001-10-29 17:37:03
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv8130/configs Modified Files: defconfig-nino Log Message: Nino updates. Index: defconfig-nino =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-nino,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig-nino 2001/10/26 22:30:51 1.11 +++ defconfig-nino 2001/10/29 17:37:01 1.12 @@ -121,7 +121,7 @@ # CONFIG_BLK_DEV_NBD is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=2048 -CONFIG_BLK_DEV_INITRD=y +# CONFIG_BLK_DEV_INITRD is not set # # Multi-device support (RAID and LVM) @@ -202,8 +202,7 @@ CONFIG_SERIAL_TX3912=y CONFIG_SERIAL_TX3912_CONSOLE=y # CONFIG_AU1000_UART is not set -CONFIG_UNIX98_PTYS=y -CONFIG_UNIX98_PTY_COUNT=256 +# CONFIG_UNIX98_PTYS is not set # # I2C support @@ -288,7 +287,7 @@ # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set -CONFIG_DEVPTS_FS=y +# CONFIG_DEVPTS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set |
|
From: James S. <jsi...@us...> - 2001-10-29 17:33:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv7143
Modified Files:
fault.c
Log Message:
Synced to Ralph's tree. We already fixed this problem.
Index: fault.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/fault.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- fault.c 2001/10/22 21:04:22 1.4
+++ fault.c 2001/10/29 17:33:15 1.5
@@ -33,6 +33,39 @@
*/
#define dpf_reg(r) (regs->regs[r])
+extern spinlock_t timerlist_lock;
+
+/*
+ * Unlock any spinlocks which will prevent us from getting the
+ * message out (timerlist_lock is acquired through the
+ * console unblank code)
+ */
+void bust_spinlocks(int yes)
+{
+ spin_lock_init(&timerlist_lock);
+ if (yes) {
+ oops_in_progress = 1;
+#ifdef CONFIG_SMP
+ /* Many serial drivers do __global_cli() */
+ global_irq_lock = SPIN_LOCK_UNLOCKED;
+#endif
+ } else {
+ int loglevel_save = console_loglevel;
+#ifdef CONFIG_VT
+ unblank_screen();
+#endif
+ oops_in_progress = 0;
+ /*
+ * OK, the message is on the console. Now we call printk()
+ * without oops_in_progress set so that printk will give klogd
+ * a poke. Hold onto your hats...
+ */
+ console_loglevel = 15; /* NMI oopser may have shut the console up */
+ printk(" ");
+ console_loglevel = loglevel_save;
+ }
+}
+
/*
* This routine handles page faults. It determines the address,
* and the problem, and then passes it off to one of the appropriate
@@ -95,12 +128,12 @@
goto bad_area;
}
+survive:
/*
* If for any reason at all we couldn't handle the fault,
* make sure we exit gracefully rather than endlessly redo
* the fault.
*/
-survive:
switch (handle_mm_fault(mm, vma, address, write)) {
case 1:
tsk->min_flt++;
@@ -169,6 +202,7 @@
"address %08lx, epc == %08lx, ra == %08lx\n",
address, regs->cp0_epc, regs->regs[31]);
die("Oops", regs);
+ bust_spinlock(0);
do_exit(SIGKILL);
/*
@@ -177,8 +211,8 @@
*/
out_of_memory:
up_read(&mm->mmap_sem);
- if (current->pid == 1) {
- current->policy |= SCHED_YIELD;
+ if (tsk->pid == 1) {
+ tsk->policy |= SCHED_YIELD;
schedule();
down_read(&mm->mmap_sem);
goto survive;
@@ -196,7 +230,7 @@
* or user mode.
*/
tsk->thread.cp0_badvaddr = address;
- info.si_code = SIGBUS;
+ info.si_signo = SIGBUS;
info.si_errno = 0;
info.si_code = BUS_ADRERR;
info.si_addr = (void *) address;
|
|
From: James S. <jsi...@us...> - 2001-10-29 17:32:30
|
Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv6933
Modified Files:
fault.c
Log Message:
Synced to Ralph's tree. We already fixed this problem.
Index: fault.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/fault.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- fault.c 2001/10/22 21:04:22 1.5
+++ fault.c 2001/10/29 17:32:28 1.6
@@ -70,6 +70,10 @@
spin_lock_init(&timerlist_lock);
if (yes) {
oops_in_progress = 1;
+#ifdef CONFIG_SMP
+ /* Many serial drivers do __global_cli() */
+ global_irq_lock = SPIN_LOCK_UNLOCKED;
+#endif
} else {
int loglevel_save = console_loglevel;
#ifdef CONFIG_VT
@@ -149,12 +153,12 @@
goto bad_area;
}
+survive:
/*
* If for any reason at all we couldn't handle the fault,
* make sure we exit gracefully rather than endlessly redo
* the fault.
*/
-survive:
switch (handle_mm_fault(mm, vma, address, write)) {
case 1:
tsk->min_flt++;
@@ -178,7 +182,6 @@
bad_area:
up_read(&mm->mmap_sem);
-bad_area_nosemaphore:
if (user_mode(regs)) {
tsk->thread.cp0_badvaddr = address;
tsk->thread.error_code = write;
@@ -235,8 +238,8 @@
*/
out_of_memory:
up_read(&mm->mmap_sem);
- if (current->pid == 1) {
- current->policy |= SCHED_YIELD;
+ if (tsk->pid == 1) {
+ tsk->policy |= SCHED_YIELD;
schedule();
down_read(&mm->mmap_sem);
goto survive;
@@ -254,7 +257,7 @@
* or user mode.
*/
tsk->thread.cp0_badvaddr = address;
- info.si_code = SIGBUS;
+ info.si_signo = SIGBUS;
info.si_errno = 0;
info.si_code = BUS_ADRERR;
info.si_addr = (void *) address;
|
|
From: James S. <jsi...@us...> - 2001-10-29 17:30:58
|
Update of /cvsroot/linux-mips/linux/arch/mips64/configs In directory usw-pr-cvs1:/tmp/cvs-serv6461/configs Modified Files: defconfig-ip22 defconfig-ip27 Log Message: Rebuild. Index: defconfig-ip22 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/configs/defconfig-ip22,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- defconfig-ip22 2001/10/19 21:19:38 1.3 +++ defconfig-ip22 2001/10/29 17:30:56 1.4 @@ -12,6 +12,7 @@ # CONFIG_SGI_IP22=y # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_BOOT_ELF32=y Index: defconfig-ip27 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/configs/defconfig-ip27,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- defconfig-ip27 2001/10/19 21:19:38 1.3 +++ defconfig-ip27 2001/10/29 17:30:56 1.4 @@ -12,6 +12,7 @@ # # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y +# CONFIG_SGI_IP32 is not set # CONFIG_SGI_SN0_N_MODE is not set CONFIG_DISCONTIGMEM=y CONFIG_NUMA=y |
|
From: James S. <jsi...@us...> - 2001-10-29 17:30:58
|
Update of /cvsroot/linux-mips/linux/arch/mips64 In directory usw-pr-cvs1:/tmp/cvs-serv6461 Modified Files: defconfig Log Message: Rebuild. Index: defconfig =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/defconfig,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- defconfig 2001/10/19 21:19:38 1.7 +++ defconfig 2001/10/29 17:30:56 1.8 @@ -12,6 +12,7 @@ # # CONFIG_SGI_IP22 is not set CONFIG_SGI_IP27=y +# CONFIG_SGI_IP32 is not set # CONFIG_SGI_SN0_N_MODE is not set CONFIG_DISCONTIGMEM=y CONFIG_NUMA=y |
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From: James S. <jsi...@us...> - 2001-10-29 17:28:50
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Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv5762 Modified Files: defconfig-it8172 Log Message: Remove duplicate entries in Config.in. Index: defconfig-it8172 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-it8172,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig-it8172 2001/10/26 16:37:55 1.11 +++ defconfig-it8172 2001/10/29 17:28:47 1.12 @@ -18,8 +18,6 @@ # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set -# CONFIG_NEC_EAGLE is not set -# CONFIG_NEC_KORVA is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set @@ -31,6 +29,8 @@ # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_NEC_OSPREY is not set +# CONFIG_NEC_EAGLE is not set +# CONFIG_NEC_KORVA is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set @@ -497,10 +497,10 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_IT8172_SCR0 is not set -# CONFIG_IT8172_SCR1 is not set CONFIG_QTRONIX_KEYBOARD=y CONFIG_IT8172_CIR=y +# CONFIG_IT8172_SCR0 is not set +# CONFIG_IT8172_SCR1 is not set CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 |
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From: James S. <jsi...@us...> - 2001-10-29 17:14:01
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Update of /cvsroot/linux-mips/linux/arch/mips64/configs In directory usw-pr-cvs1:/tmp/cvs-serv1208 Modified Files: defconfig-ip32 Log Message: IP32 defconfig. Index: defconfig-ip32 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/configs/defconfig-ip32,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- defconfig-ip32 2001/08/25 06:34:24 1.1 +++ defconfig-ip32 2001/10/29 17:13:58 1.2 @@ -19,6 +19,7 @@ CONFIG_ARC32=y CONFIG_PC_KEYB=y CONFIG_PCI=y +CONFIG_MAPPED_PCI_IO=y CONFIG_ARC_MEMORY=y CONFIG_L1_CACHE_SHIFT=5 # CONFIG_ISA is not set @@ -48,7 +49,7 @@ CONFIG_SYSVIPC=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_SYSCTL=y -# CONFIG_PROM_CONSOLE is not set +CONFIG_ARC_CONSOLE=y CONFIG_BINFMT_ELF=y CONFIG_MIPS32_COMPAT=y CONFIG_BINFMT_ELF32=y @@ -93,6 +94,7 @@ # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID5 is not set +# CONFIG_MD_MULTIPATH is not set # CONFIG_BLK_DEV_LVM is not set # @@ -145,6 +147,7 @@ # # CONFIG_PHONE is not set # CONFIG_PHONE_IXJ is not set +# CONFIG_PHONE_IXJ_PCMCIA is not set # # ATA/IDE/MFM/RLL support @@ -191,6 +194,7 @@ CONFIG_AIC7XXX_CMDS_PER_DEVICE=8 CONFIG_AIC7XXX_RESET_DELAY_MS=15000 # CONFIG_AIC7XXX_BUILD_FIRMWARE is not set +# CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_IN2000 is not set # CONFIG_SCSI_AM53C974 is not set @@ -208,6 +212,7 @@ # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_NCR53C406A is not set +# CONFIG_SCSI_NCR_D700 is not set # CONFIG_SCSI_NCR53C7xx is not set # CONFIG_SCSI_NCR53C8XX is not set # CONFIG_SCSI_SYM53C8XX is not set @@ -249,60 +254,39 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set -# CONFIG_NET_SB1000 is not set # # Ethernet (10 or 100Mbit) # CONFIG_NET_ETHERNET=y +# CONFIG_SUNLANCE is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNBMAC is not set +# CONFIG_SUNQE is not set +# CONFIG_SUNLANCE is not set +# CONFIG_SUNGEM is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_LANCE is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_APRICOT is not set -# CONFIG_CS89x0 is not set -CONFIG_TULIP=y -# CONFIG_DE4X5 is not set -# CONFIG_DGRS is not set -# CONFIG_DM9102 is not set -CONFIG_EEPRO100=y -# CONFIG_EEPRO100_PM is not set -# CONFIG_LNE390 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_NE3210 is not set -# CONFIG_ES3210 is not set -# CONFIG_8139TOO is not set -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_LAN_SAA9730 is not set +# CONFIG_NET_PCI is not set # CONFIG_NET_POCKET is not set # # Ethernet (1000 Mbit) # # CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_MYRI_SBUS is not set +# CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_SK98LIN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set +# CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -372,7 +356,11 @@ # # Joysticks # -# CONFIG_JOYSTICK is not set +# CONFIG_INPUT_GAMEPORT is not set + +# +# Input core support is needed for gameports +# # # Input core support is needed for joysticks @@ -389,6 +377,7 @@ # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set +# CONFIG_SONYPI is not set # # Ftape, the floppy tape device driver @@ -441,7 +430,6 @@ # CONFIG_ROMFS_FS is not set CONFIG_EXT2_FS=y # CONFIG_SYSV_FS is not set -# CONFIG_SYSV_FS_WRITE is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set @@ -480,6 +468,7 @@ # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set # CONFIG_MSDOS_PARTITION is not set +# CONFIG_LDM_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set @@ -501,6 +490,10 @@ # Input core support # # CONFIG_INPUT is not set +# CONFIG_INPUT_KEYBDEV is not set +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set # # Kernel hacking |
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From: James S. <jsi...@us...> - 2001-10-29 17:09:53
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Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv32246
Added Files:
page.h
Log Message:
Set PAGE_OFFSET to 0xa800000000000000 for IP32.
--- NEW FILE: page.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 - 1999, 2000 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_PAGE_H
#define _ASM_PAGE_H
#include <linux/config.h>
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#ifdef __KERNEL__
#ifndef _LANGUAGE_ASSEMBLY
#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); *(int *)0=0; } while (0)
#define PAGE_BUG(page) do { BUG(); } while (0)
extern void (*_clear_page)(void * page);
extern void (*_copy_page)(void * to, void * from);
#define clear_page(page) _clear_page(page)
#define copy_page(to, from) _copy_page(to, from)
#define clear_user_page(page, vaddr) clear_page(page)
#define copy_user_page(to, from, vaddr) copy_page(to, from)
/*
* These are used to make use of C type-checking..
*/
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pmd; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((x).pmd)
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __pme(x) ((pme_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
#endif /* _LANGUAGE_ASSEMBLY */
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
/*
* This handles the memory map.
* We handle pages at KSEG0 for kernels with upto 512mb of memory,
* at XKPHYS for kernels with more than that.
*/
#ifdef CONFIG_SGI_IP22
#define PAGE_OFFSET 0xffffffff80000000UL
#endif
#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP32)
#define PAGE_OFFSET 0xa800000000000000UL
#endif
#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
#ifndef CONFIG_DISCONTIGMEM
#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
#endif
#endif /* defined (__KERNEL__) */
#endif /* _ASM_PAGE_H */
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From: Paul M. <le...@us...> - 2001-10-29 08:20:59
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4122 In directory usw-pr-cvs1:/tmp/cvs-serv23171/vr4122 Modified Files: vr4122.h Log Message: Add VR4121 header.. fix a typo in vr4111.h, remove DSU entry from vr4122 definitions. Index: vr4122.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4122/vr4122.h,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- vr4122.h 2001/10/28 03:48:46 1.2 +++ vr4122.h 2001/10/29 08:20:55 1.3 @@ -219,13 +219,6 @@ #define VR4122_PMUCLKRUNREG KSEG1ADDR(0x0F0000D6) /* PMU CLKRUN control register */ -/* Deadman's Switch Unit (DSU) */ -#define VR41XX_DSUCNTREG KSEG1ADDR(0x0f0000e0) /* DSU Control Register */ -#define VR41XX_DSUSETREG KSEG1ADDR(0x0f0000e2) /* DSU Dead Time Set Register */ -#define VR41XX_DSUCLRREG KSEG1ADDR(0x0f0000e4) /* DSU Clear Register */ -#define VR41XX_DSUTIMREG KSEG1ADDR(0x0f0000e6) /* DSU Elapsed Time Register */ - - /* Real Time Clock Unit (RTC) */ #define VR4122_ETIMELREG KSEG1ADDR(0x0F000100) /* Elapsed Time L Register */ #define VR4122_ETIMEMREG KSEG1ADDR(0x0F000102) /* Elapsed Time M Register */ |
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From: Paul M. <le...@us...> - 2001-10-29 08:20:58
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4121 In directory usw-pr-cvs1:/tmp/cvs-serv23171/vr4121 Added Files: vr4121.h Log Message: Add VR4121 header.. fix a typo in vr4111.h, remove DSU entry from vr4122 definitions. --- NEW FILE: vr4121.h --- /* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1999 by Michael Klar */ #ifndef __ASM_VR4121_VR4121_H #define __ASM_VR4121_VR4121_H #include <asm/addrspace.h> /* CPU interrupts */ #define VR41XX_IRQ_SW1 0 /* IP0 - Software interrupt */ #define VR41XX_IRQ_SW2 1 /* IP1 - Software interrupt */ #define VR41XX_IRQ_INT0 2 /* IP2 - All but battery, high speed modem, and real time clock */ #define VR41XX_IRQ_INT1 3 /* IP3 - RTC Long1 (system timer) */ #define VR41XX_IRQ_INT2 4 /* IP4 - RTC Long2 */ #define VR41XX_IRQ_INT3 5 /* IP5 - High Speed Modem */ #define VR41XX_IRQ_INT4 6 /* IP6 - Unused */ #define VR41XX_IRQ_TIMER 7 /* IP7 - Timer interrupt from CPO_COMPARE (Note: RTC Long1 is the system timer.) */ /* Cascaded from VR41XX_IRQ_INT0 (ICU mapped interrupts) */ #define VR41XX_IRQ_BATTERY 8 #define VR41XX_IRQ_POWER 9 #define VR41XX_IRQ_RTCL1 10 /* Use VR41XX_IRQ_INT1 instead. */ #define VR41XX_IRQ_ETIMER 11 #define VR41XX_IRQ_RFU12 12 #define VR41XX_IRQ_PIU 13 #define VR41XX_IRQ_AIU 14 #define VR41XX_IRQ_KIU 15 #define VR41XX_IRQ_GIU 16 /* This is a cascade to IRQs 40-71. Do not use. */ #define VR41XX_IRQ_SIU 17 #define VR41XX_IRQ_WRBERR 18 #define VR41XX_IRQ_SOFT 19 #define VR41XX_IRQ_RFU20 20 #define VR41XX_IRQ_DOZEPIU 21 #define VR41XX_IRQ_RFU22 22 #define VR41XX_IRQ_RFU23 23 #define VR41XX_IRQ_RTCL2 24 /* Use VR41XX_IRQ_INT2 instead. */ #define VR41XX_IRQ_LED 25 #define VR41XX_IRQ_HSP 26 /* Use VR41XX_IRQ_INT3 instead. */ #define VR41XX_IRQ_TCLK 27 #define VR41XX_IRQ_FIR 28 #define VR41XX_IRQ_DSIU 29 #define VR41XX_IRQ_RFU30 30 #define VR41XX_IRQ_RFU31 31 #define VR41XX_IRQ_RFU32 32 #define VR41XX_IRQ_RFU33 33 #define VR41XX_IRQ_RFU34 34 #define VR41XX_IRQ_RFU35 35 #define VR41XX_IRQ_RFU36 36 #define VR41XX_IRQ_RFU37 37 #define VR41XX_IRQ_RFU38 38 #define VR41XX_IRQ_RFU39 39 /* Cascaded from VR41XX_IRQ_GIU */ #define VR41XX_IRQ_GPIO0 40 #define VR41XX_IRQ_GPIO1 41 #define VR41XX_IRQ_GPIO2 42 #define VR41XX_IRQ_GPIO3 43 #define VR41XX_IRQ_GPIO4 44 #define VR41XX_IRQ_GPIO5 45 #define VR41XX_IRQ_GPIO6 46 #define VR41XX_IRQ_GPIO7 47 #define VR41XX_IRQ_GPIO8 48 #define VR41XX_IRQ_GPIO9 49 #define VR41XX_IRQ_GPIO10 50 #define VR41XX_IRQ_GPIO11 51 #define VR41XX_IRQ_GPIO12 52 #define VR41XX_IRQ_GPIO13 53 #define VR41XX_IRQ_GPIO14 54 #define VR41XX_IRQ_GPIO15 55 #define VR41XX_IRQ_GPIO16 56 #define VR41XX_IRQ_GPIO17 57 #define VR41XX_IRQ_GPIO18 58 #define VR41XX_IRQ_GPIO19 59 #define VR41XX_IRQ_GPIO20 60 #define VR41XX_IRQ_GPIO21 61 #define VR41XX_IRQ_GPIO22 62 #define VR41XX_IRQ_GPIO23 63 #define VR41XX_IRQ_GPIO24 64 #define VR41XX_IRQ_GPIO25 65 #define VR41XX_IRQ_GPIO26 66 #define VR41XX_IRQ_GPIO27 67 #define VR41XX_IRQ_GPIO28 68 #define VR41XX_IRQ_GPIO29 69 #define VR41XX_IRQ_GPIO30 70 #define VR41XX_IRQ_GPIO31 71 /* Alternative to above GPIO IRQ defines */ #define VR41XX_IRQ_GPIO(pin) ((VR41XX_IRQ_GPIO0) + (pin)) #define VR41XX_IRQ_MAX 71 #ifndef _LANGUAGE_ASSEMBLY #define __preg8 (volatile unsigned char*) #define __preg16 (volatile unsigned short*) #define __preg32 (volatile unsigned int*) #else #define __preg8 #define __preg16 #define __preg32 #endif /* Embedded CPU peripheral registers */ /* Bus Control Unit (BCU) */ #define VR41XX_BCUCNTREG1 __preg16(KSEG1 + 0x0B000000) /* BCU Control Register 1 (R/W) */ #define VR41XX_BCUCNTREG2 __preg16(KSEG1 + 0x0B000002) /* BCU Control Register 2 (R/W) */ #define VR41XX_ROMSIZEREG __preg16(KSEG1 + 0x0B000004) /* ROM Size Register (R/W) */ #define VR41XX_RAMSIZEREG __preg16(KSEG1 + 0x0B000006) /* DRAM Size Register (R/W) */ #define VR41XX_BCUSPEEDREG __preg16(KSEG1 + 0x0B00000A) /* BCU Access Cycle Change Register (R/W) */ #define VR41XX_BCUERRSTREG __preg16(KSEG1 + 0x0B00000C) /* BCU BUS ERROR Status Register (R/W) */ #define VR41XX_BCURFCNTREG __preg16(KSEG1 + 0x0B00000E) /* BCU Refresh Control Register (R/W) */ #define VR41XX_REVIDREG __preg16(KSEG1 + 0x0B000010) /* Revision ID Register (R) */ #define VR41XX_BCURFCOUNTREG __preg16(KSEG1 + 0x0B000012) /* BCU Refresh Count Register (R/W) */ #define VR41XX_CLKSPEEDREG __preg16(KSEG1 + 0x0B000014) /* Clock Speed Register (R) */ #define VR41XX_BCUCNTREG3 __preg16(KSEG1 + 0x0B000016) /* BCU Control Register 3 (R/W) */ #define VR41XX_SDRAMMODEREG __preg16(KSEG1 + 0x0B00001A) /* SDRAM Mode Register */ #define VR41XX_SROMMODEREG __preg16(KSEG1 + 0x0B00001C) /* SROM Mode Register */ #define VR41XX_SDRAMCNTREG __preg16(KSEG1 + 0x0B00001E) /* SDRAM Control Register */ #define VR41XX_BCUTOUTCNTREG __preg16(KSEG1 + 0x0B000300) /* BCU Timeout Control Register */ #define VR41XX_BCUTOUTCOUNTREG __preg16(KSEG1 + 0x0B000302) /* BCU Timeout Count Register */ /* DMA Address Unit (DMAAU) */ #define VR41XX_AIUIBALREG __preg16(KSEG1 + 0x0B000020) /* AIU IN DMA Base Address Register Low (R/W) */ #define VR41XX_AIUIBAHREG __preg16(KSEG1 + 0x0B000022) /* AIU IN DMA Base Address Register High (R/W) */ #define VR41XX_AIUIALREG __preg16(KSEG1 + 0x0B000024) /* AIU IN DMA Address Register Low (R/W) */ #define VR41XX_AIUIAHREG __preg16(KSEG1 + 0x0B000026) /* AIU IN DMA Address Register High (R/W) */ #define VR41XX_AIUOBALREG __preg16(KSEG1 + 0x0B000028) /* AIU OUT DMA Base Address Register Low (R/W) */ #define VR41XX_AIUOBAHREG __preg16(KSEG1 + 0x0B00002A) /* AIU OUT DMA Base Address Register High (R/W) */ #define VR41XX_AIUOALREG __preg16(KSEG1 + 0x0B00002C) /* AIU OUT DMA Address Register Low (R/W) */ #define VR41XX_AIUOAHREG __preg16(KSEG1 + 0x0B00002E) /* AIU OUT DMA Address Register High (R/W) */ #define VR41XX_FIRBALREG __preg16(KSEG1 + 0x0B000030) /* FIR DMA Base Address Register Low (R/W) */ #define VR41XX_FIRBAHREG __preg16(KSEG1 + 0x0B000032) /* FIR DMA Base Address Register High (R/W) */ #define VR41XX_FIRALREG __preg16(KSEG1 + 0x0B000034) /* FIR DMA Address Register Low (R/W) */ #define VR41XX_FIRAHREG __preg16(KSEG1 + 0x0B000036) /* FIR DMA Address Register High (R/W) */ /* DMA Control Unit (DCU) */ #define VR41XX_DMARSTREG __preg16(KSEG1 + 0x0B000040) /* DMA Reset Register (R/W) */ #define VR41XX_DMAIDLEREG __preg16(KSEG1 + 0x0B000042) /* DMA Idle Register (R) */ #define VR41XX_DMASENREG __preg16(KSEG1 + 0x0B000044) /* DMA Sequencer Enable Register (R/W) */ #define VR41XX_DMAMSKREG __preg16(KSEG1 + 0x0B000046) /* DMA Mask Register (R/W) */ #define VR41XX_DMAREQREG __preg16(KSEG1 + 0x0B000048) /* DMA Request Register (R) */ #define VR41XX_TDREG __preg16(KSEG1 + 0x0B00004A) /* Transfer Direction Register (R/W) */ /* Clock Mask Unit (CMU) */ #define VR41XX_CMUCLKMSK __preg16(KSEG1 + 0x0B000060) /* CMU Clock Mask Register (R/W) */ #define VR41XX_CMUCLKMSK_MSKPIUPCLK 0x0001 #define VR41XX_CMUCLKMSK_MSKSIU 0x0102 /* Interrupt Control Unit (ICU) */ #define VR41XX_SYSINT1REG __preg16(KSEG1 + 0x0B000080) /* Level 1 System interrupt register 1 (R) */ #define VR41XX_PIUINTREGro __preg16(KSEG1 + 0x0B000082) /* Level 2 PIU interrupt register (R) */ #define VR41XX_AIUINTREG __preg16(KSEG1 + 0x0B000084) /* Level 2 AIU interrupt register (R) */ #define VR41XX_KIUINTREG __preg16(KSEG1 + 0x0B000086) /* Level 2 KIU interrupt register (R) */ #define VR41XX_GIUINTLREG __preg16(KSEG1 + 0x0B000088) /* Level 2 GIU interrupt register Low (R) */ #define VR41XX_DSIUINTREG __preg16(KSEG1 + 0x0B00008A) /* Level 2 DSIU interrupt register (R) */ #define VR41XX_MSYSINT1REG __preg16(KSEG1 + 0x0B00008C) /* Level 1 mask system interrupt register 1 (R/W) */ #define VR41XX_MPIUINTREG __preg16(KSEG1 + 0x0B00008E) /* Level 2 mask PIU interrupt register (R/W) */ #define VR41XX_MAIUINTREG __preg16(KSEG1 + 0x0B000090) /* Level 2 mask AIU interrupt register (R/W) */ #define VR41XX_MKIUINTREG __preg16(KSEG1 + 0x0B000092) /* Level 2 mask KIU interrupt register (R/W) */ #define VR41XX_MGIUINTLREG __preg16(KSEG1 + 0x0B000094) /* Level 2 mask GIU interrupt register Low (R/W) */ #define VR41XX_MDSIUINTREG __preg16(KSEG1 + 0x0B000096) /* Level 2 mask DSIU interrupt register (R/W) */ #define VR41XX_NMIREG __preg16(KSEG1 + 0x0B000098) /* NMI register (R/W) */ #define VR41XX_SOFTINTREG __preg16(KSEG1 + 0x0B00009A) /* Software interrupt register (R/W) */ #define VR41XX_SYSINT2REG __preg16(KSEG1 + 0x0B000200) /* Level 1 System interrupt register 2 (R) */ #define VR41XX_GIUINTHREG __preg16(KSEG1 + 0x0B000202) /* Level 2 GIU interrupt register High (R) */ #define VR41XX_FIRINTREG __preg16(KSEG1 + 0x0B000204) /* Level 2 FIR interrupt register (R) */ #define VR41XX_MSYSINT2REG __preg16(KSEG1 + 0x0B000206) /* Level 1 mask system interrupt register 2 (R/W) */ #define VR41XX_MGIUINTHREG __preg16(KSEG1 + 0x0B000208) /* Level 2 mask GIU interrupt register High (R/W) */ #define VR41XX_MFIRINTREG __preg16(KSEG1 + 0x0B00020A) /* Level 2 mask FIR interrupt register (R/W) */ /* Power Management Unit (PMU) */ #define VR41XX_PMUINTREG __preg16(KSEG1 + 0x0B0000A0) /* PMU Status Register (R/W) */ #define VR41XX_PMUINT_POWERSW 0x1 /* Power switch */ #define VR41XX_PMUINT_BATT 0x2 /* Low batt during normal operation */ #define VR41XX_PMUINT_DEADMAN 0x4 /* Deadman's switch */ #define VR41XX_PMUINT_RESET 0x8 /* Reset switch */ #define VR41XX_PMUINT_RTCRESET 0x10 /* RTC Reset */ #define VR41XX_PMUINT_TIMEOUT 0x20 /* HAL Timer Reset */ #define VR41XX_PMUINT_BATTLOW 0x100 /* Battery low */ #define VR41XX_PMUINT_RTC 0x200 /* RTC Alarm */ #define VR41XX_PMUINT_DCD 0x400 /* DCD# */ #define VR41XX_PMUINT_GPIO0 0x1000 /* GPIO0 */ #define VR41XX_PMUINT_GPIO1 0x2000 /* GPIO1 */ #define VR41XX_PMUINT_GPIO2 0x4000 /* GPIO2 */ #define VR41XX_PMUINT_GPIO3 0x8000 /* GPIO3 */ #define VR41XX_PMUCNTREG __preg16(KSEG1 + 0x0B0000A2) /* PMU Control Register (R/W) */ #define VR41XX_PMUWAITREG __preg16(KSEG1 + 0x0B0000A8) /* PMU Wait Counter Register (R/W) */ #define VR41XX_PMUINT2REG __preg16(KSEG1 + 0x0B0000A4) /* PMU Interrupt/Status 2 Register (R/W) */ #define VR41XX_PMUCNT2REG __preg16(KSEG1 + 0x0B0000A6) /* PMU Control 2 Resister (R/W) */ /* Real Time Clock Unit (RTC) */ #define VR41XX_ETIMELREG __preg16(KSEG1 + 0x0B0000C0) /* Elapsed Time L Register (R/W) */ #define VR41XX_ETIMEMREG __preg16(KSEG1 + 0x0B0000C2) /* Elapsed Time M Register (R/W) */ #define VR41XX_ETIMEHREG __preg16(KSEG1 + 0x0B0000C4) /* Elapsed Time H Register (R/W) */ #define VR41XX_ECMPLREG __preg16(KSEG1 + 0x0B0000C8) /* Elapsed Compare L Register (R/W) */ #define VR41XX_ECMPMREG __preg16(KSEG1 + 0x0B0000CA) /* Elapsed Compare M Register (R/W) */ #define VR41XX_ECMPHREG __preg16(KSEG1 + 0x0B0000CC) /* Elapsed Compare H Register (R/W) */ #define VR41XX_RTCL1LREG __preg16(KSEG1 + 0x0B0000D0) /* RTC Long 1 L Register (R/W) */ #define VR41XX_RTCL1HREG __preg16(KSEG1 + 0x0B0000D2) /* RTC Long 1 H Register (R/W) */ #define VR41XX_RTCL1CNTLREG __preg16(KSEG1 + 0x0B0000D4) /* RTC Long 1 Count L Register (R) */ #define VR41XX_RTCL1CNTHREG __preg16(KSEG1 + 0x0B0000D6) /* RTC Long 1 Count H Register (R) */ #define VR41XX_RTCL2LREG __preg16(KSEG1 + 0x0B0000D8) /* RTC Long 2 L Register (R/W) */ #define VR41XX_RTCL2HREG __preg16(KSEG1 + 0x0B0000DA) /* RTC Long 2 H Register (R/W) */ #define VR41XX_RTCL2CNTLREG __preg16(KSEG1 + 0x0B0000DC) /* RTC Long 2 Count L Register (R) */ #define VR41XX_RTCL2CNTHREG __preg16(KSEG1 + 0x0B0000DE) /* RTC Long 2 Count H Register (R) */ #define VR41XX_RTCINTREG __preg16(KSEG1 + 0x0B0001DE) /* RTC Interrupt Register (R/W) */ #define VR41XX_TCLKLREG __preg16(KSEG1 + 0x0B0001C0) /* TCLK L Register (R/W) */ #define VR41XX_TCLKHREG __preg16(KSEG1 + 0x0B0001C2) /* TCLK H Register (R/W) */ #define VR41XX_TCLKCNTLREG __preg16(KSEG1 + 0x0B0001C4) /* TCLK Count L Register (R) */ #define VR41XX_TCLKCNTHREG __preg16(KSEG1 + 0x0B0001C6) /* TCLK Count H Register (R) */ /* Deadman's Switch Unit (DSU) */ #define VR41XX_DSUCNTREG __preg16(KSEG1 + 0x0B0000E0) /* DSU Control Register (R/W) */ #define VR41XX_DSUSETREG __preg16(KSEG1 + 0x0B0000E2) /* DSU Dead Time Set Register (R/W) */ #define VR41XX_DSUCLRREG __preg16(KSEG1 + 0x0B0000E4) /* DSU Clear Register (W) */ #define VR41XX_DSUTIMREG __preg16(KSEG1 + 0x0B0000E6) /* DSU Elapsed Time Register (R/W) */ /* General Purpose I/O Unit (GIU) */ #define VR41XX_GIUIOSELL __preg16(KSEG1 + 0x0B000100) /* GPIO Input/Output Select Register L (R/W) */ #define VR41XX_GIUIOSELH __preg16(KSEG1 + 0x0B000102) /* GPIO Input/Output Select Register H (R/W) */ #define VR41XX_GIUPIODL __preg16(KSEG1 + 0x0B000104) /* GPIO Port Input/Output Data Register L (R/W) */ #define VR41XX_GIUPIODL_GPIO15 0x8000 #define VR41XX_GIUPIODL_GPIO14 0x4000 #define VR41XX_GIUPIODL_GPIO13 0x2000 #define VR41XX_GIUPIODL_GPIO12 0x1000 #define VR41XX_GIUPIODL_GPIO11 0x0800 #define VR41XX_GIUPIODL_GPIO10 0x0400 #define VR41XX_GIUPIODL_GPIO9 0x0200 #define VR41XX_GIUPIODL_GPIO8 0x0100 #define VR41XX_GIUPIODL_GPIO7 0x0080 #define VR41XX_GIUPIODL_GPIO6 0x0040 #define VR41XX_GIUPIODL_GPIO5 0x0020 #define VR41XX_GIUPIODL_GPIO4 0x0010 #define VR41XX_GIUPIODL_GPIO3 0x0008 #define VR41XX_GIUPIODL_GPIO2 0x0004 #define VR41XX_GIUPIODL_GPIO1 0x0002 #define VR41XX_GIUPIODL_GPIO0 0x0001 #define VR41XX_GIUPIODH __preg16(KSEG1 + 0x0B000106) /* GPIO Port Input/Output Data Register H (R/W) */ #define VR41XX_GIUPIODH_GPIO31 0x8000 #define VR41XX_GIUPIODH_GPIO30 0x4000 #define VR41XX_GIUPIODH_GPIO29 0x2000 #define VR41XX_GIUPIODH_GPIO28 0x1000 #define VR41XX_GIUPIODH_GPIO27 0x0800 #define VR41XX_GIUPIODH_GPIO26 0x0400 #define VR41XX_GIUPIODH_GPIO25 0x0200 #define VR41XX_GIUPIODH_GPIO24 0x0100 #define VR41XX_GIUPIODH_GPIO23 0x0080 #define VR41XX_GIUPIODH_GPIO22 0x0040 #define VR41XX_GIUPIODH_GPIO21 0x0020 #define VR41XX_GIUPIODH_GPIO20 0x0010 #define VR41XX_GIUPIODH_GPIO19 0x0008 #define VR41XX_GIUPIODH_GPIO18 0x0004 #define VR41XX_GIUPIODH_GPIO17 0x0002 #define VR41XX_GIUPIODH_GPIO16 0x0001 #define VR41XX_GIUINTSTATL __preg16(KSEG1 + 0x0B000108) /* GPIO Interrupt Status Register L (R/W) */ #define VR41XX_GIUINTSTATH __preg16(KSEG1 + 0x0B00010A) /* GPIO Interrupt Status Register H (R/W) */ #define VR41XX_GIUINTENL __preg16(KSEG1 + 0x0B00010C) /* GPIO Interrupt Enable Register L (R/W) */ #define VR41XX_GIUINTENH __preg16(KSEG1 + 0x0B00010E) /* GPIO Interrupt Enable Register H (R/W) */ #define VR41XX_GIUINTTYPL __preg16(KSEG1 + 0x0B000110) /* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */ #define VR41XX_GIUINTTYPH __preg16(KSEG1 + 0x0B000112) /* GPIO Interrupt Type (Edge or Level) Select Register (R/W) */ #define VR41XX_GIUINTALSELL __preg16(KSEG1 + 0x0B000114) /* GPIO Interrupt Active Level Select Register L (R/W) */ #define VR41XX_GIUINTALSELH __preg16(KSEG1 + 0x0B000116) /* GPIO Interrupt Active Level Select Register H (R/W) */ #define VR41XX_GIUINTHTSELL __preg16(KSEG1 + 0x0B000118) /* GPIO Interrupt Hold/Through Select Register L (R/W) */ #define VR41XX_GIUINTHTSELH __preg16(KSEG1 + 0x0B00011A) /* GPIO Interrupt Hold/Through Select Register H (R/W) */ #define VR41XX_GIUPODATL __preg16(KSEG1 + 0x0B00011C) /* GPIO Port Output Data Register L (R/W) */ #define VR41XX_GIUPODATL_GPIO47 0x8000 #define VR41XX_GIUPODATL_GPIO46 0x4000 #define VR41XX_GIUPODATL_GPIO45 0x2000 #define VR41XX_GIUPODATL_GPIO44 0x1000 #define VR41XX_GIUPODATL_GPIO43 0x0800 #define VR41XX_GIUPODATL_GPIO42 0x0400 #define VR41XX_GIUPODATL_GPIO41 0x0200 #define VR41XX_GIUPODATL_GPIO40 0x0100 #define VR41XX_GIUPODATL_GPIO39 0x0080 #define VR41XX_GIUPODATL_GPIO38 0x0040 #define VR41XX_GIUPODATL_GPIO37 0x0020 #define VR41XX_GIUPODATL_GPIO36 0x0010 #define VR41XX_GIUPODATL_GPIO35 0x0008 #define VR41XX_GIUPODATL_GPIO34 0x0004 #define VR41XX_GIUPODATL_GPIO33 0x0002 #define VR41XX_GIUPODATL_GPIO32 0x0001 #define VR41XX_GIUPODATL_PODAT15 0x8000 #define VR41XX_GIUPODATL_PODAT14 0x4000 #define VR41XX_GIUPODATL_PODAT13 0x2000 #define VR41XX_GIUPODATL_PODAT12 0x1000 #define VR41XX_GIUPODATL_PODAT11 0x0800 #define VR41XX_GIUPODATL_PODAT10 0x0400 #define VR41XX_GIUPODATL_PODAT9 0x0200 #define VR41XX_GIUPODATL_PODAT8 0x0100 #define VR41XX_GIUPODATL_PODAT7 0x0080 #define VR41XX_GIUPODATL_PODAT6 0x0040 #define VR41XX_GIUPODATL_PODAT5 0x0020 #define VR41XX_GIUPODATL_PODAT4 0x0010 #define VR41XX_GIUPODATL_PODAT3 0x0008 #define VR41XX_GIUPODATL_PODAT2 0x0004 #define VR41XX_GIUPODATL_PODAT1 0x0002 #define VR41XX_GIUPODATL_PODAT0 0x0001 #define VR41XX_GIUPODATH __preg16(KSEG1 + 0x0B00011E) /* GPIO Port Output Data Register H (R/W) */ #define VR41XX_GIUPODATH_GPIO51 0x0008 #define VR41XX_GIUPODATH_GPIO50 0x0004 #define VR41XX_GIUPODATH_GPIO49 0x0002 #define VR41XX_GIUPODATH_GPIO48 0x0001 #define VR41XX_GIUPODATH_PODAT3 0x0008 #define VR41XX_GIUPODATH_PODAT2 0x0004 #define VR41XX_GIUPODATH_PODAT1 0x0002 #define VR41XX_GIUPODATH_PODAT0 0x0001 #define VR41XX_GIUUSEUPDN __preg16(KSEG1 + 0x0B0002E0) /* GPIO Pullup/Down User Register (R/W) */ #define VR41XX_GIUTERMUPDN __preg16(KSEG1 + 0x0B0002E2) /* GPIO Terminal Pullup/Down Register (R/W) */ #define VR41XX_SECIRQMASKL VR41XX_GIUINTENL #define VR41XX_SECIRQMASKH VR41XX_GIUINTENH /* Touch Panel Interface Unit (PIU) */ #define VR41XX_PIUCNTREG __preg16(KSEG1 + 0x0B000122) /* PIU Control register (R/W) */ #define VR41XX_PIUCNTREG_PIUSEQEN 0x0004 #define VR41XX_PIUCNTREG_PIUPWR 0x0002 #define VR41XX_PIUCNTREG_PADRST 0x0001 #define VR41XX_PIUINTREG __preg16(KSEG1 + 0x0B000124) /* PIU Interrupt cause register (R/W) */ #define VR41XX_PIUINTREG_OVP 0x8000 #define VR41XX_PIUINTREG_PADCMD 0x0040 #define VR41XX_PIUINTREG_PADADP 0x0020 #define VR41XX_PIUINTREG_PADPAGE1 0x0010 #define VR41XX_PIUINTREG_PADPAGE0 0x0008 #define VR41XX_PIUINTREG_PADDLOST 0x0004 #define VR41XX_PIUINTREG_PENCHG 0x0001 #define VR41XX_PIUSIVLREG __preg16(KSEG1 + 0x0B000126) /* PIU Data sampling interval register (R/W) */ #define VR41XX_PIUSTBLREG __preg16(KSEG1 + 0x0B000128) /* PIU A/D converter start delay register (R/W) */ #define VR41XX_PIUCMDREG __preg16(KSEG1 + 0x0B00012A) /* PIU A/D command register (R/W) */ #define VR41XX_PIUASCNREG __preg16(KSEG1 + 0x0B000130) /* PIU A/D port scan register (R/W) */ #define VR41XX_PIUAMSKREG __preg16(KSEG1 + 0x0B000132) /* PIU A/D scan mask register (R/W) */ #define VR41XX_PIUCIVLREG __preg16(KSEG1 + 0x0B00013E) /* PIU Check interval register (R) */ #define VR41XX_PIUPB00REG __preg16(KSEG1 + 0x0B0002A0) /* PIU Page 0 Buffer 0 register (R/W) */ #define VR41XX_PIUPB01REG __preg16(KSEG1 + 0x0B0002A2) /* PIU Page 0 Buffer 1 register (R/W) */ #define VR41XX_PIUPB02REG __preg16(KSEG1 + 0x0B0002A4) /* PIU Page 0 Buffer 2 register (R/W) */ #define VR41XX_PIUPB03REG __preg16(KSEG1 + 0x0B0002A6) /* PIU Page 0 Buffer 3 register (R/W) */ #define VR41XX_PIUPB10REG __preg16(KSEG1 + 0x0B0002A8) /* PIU Page 1 Buffer 0 register (R/W) */ #define VR41XX_PIUPB11REG __preg16(KSEG1 + 0x0B0002AA) /* PIU Page 1 Buffer 1 register (R/W) */ #define VR41XX_PIUPB12REG __preg16(KSEG1 + 0x0B0002AC) /* PIU Page 1 Buffer 2 register (R/W) */ #define VR41XX_PIUPB13REG __preg16(KSEG1 + 0x0B0002AE) /* PIU Page 1 Buffer 3 register (R/W) */ #define VR41XX_PIUAB0REG __preg16(KSEG1 + 0x0B0002B0) /* PIU A/D scan Buffer 0 register (R/W) */ #define VR41XX_PIUAB1REG __preg16(KSEG1 + 0x0B0002B2) /* PIU A/D scan Buffer 1 register (R/W) */ #define VR41XX_PIUAB2REG __preg16(KSEG1 + 0x0B0002B4) /* PIU A/D scan Buffer 2 register (R/W) */ #define VR41XX_PIUAB3REG __preg16(KSEG1 + 0x0B0002B6) /* PIU A/D scan Buffer 3 register (R/W) */ #define VR41XX_PIUPB04REG __preg16(KSEG1 + 0x0B0002BC) /* PIU Page 0 Buffer 4 register (R/W) */ #define VR41XX_PIUPB14REG __preg16(KSEG1 + 0x0B0002BE) /* PIU Page 1 Buffer 4 register (R/W) */ /* Audio Interface Unit (AIU) */ #define VR41XX_SODATREG __preg16(KSEG1 + 0x0B000166) /* Speaker Output Data Register (R/W) */ #define VR41XX_SCNTREG __preg16(KSEG1 + 0x0B000168) /* Speaker Output Control Register (R/W) */ #define VR41XX_MIDATREG __preg16(KSEG1 + 0x0B000170) /* Mike Input Data Register (R/W) */ #define VR41XX_MCNTREG __preg16(KSEG1 + 0x0B000172) /* Mike Input Control Register (R/W) */ #define VR41XX_DVALIDREG __preg16(KSEG1 + 0x0B000178) /* Data Valid Register (R/W) */ #define VR41XX_SEQREG __preg16(KSEG1 + 0x0B00017A) /* Sequential Register (R/W) */ #define VR41XX_INTREG __preg16(KSEG1 + 0x0B00017C) /* Interrupt Register (R/W) */ #define VR41XX_MDMADATREG __preg16(KSEG1 + 0x0B000160) /* Mike DMA Data Register (R/W) */ #define VR41XX_SDMADATREG __preg16(KSEG1 + 0x0B000162) /* Speaker DMA Data Register (R/W) */ #define VR41XX_SCNVRREG __preg16(KSEG1 + 0x0B00016A) /* Speaker Conversion Rate Register (R/W) */ #define VR41XX_MCNVRREG __preg16(KSEG1 + 0x0B000174) /* Mike Conversion Rate Register (R/W) */ /* Keyboard Interface Unit (KIU) */ #define VR41XX_KIUDAT0 __preg16(KSEG1 + 0x0B000180) /* KIU Data0 Register (R/W) */ #define VR41XX_KIUDAT1 __preg16(KSEG1 + 0x0B000182) /* KIU Data1 Register (R/W) */ #define VR41XX_KIUDAT2 __preg16(KSEG1 + 0x0B000184) /* KIU Data2 Register (R/W) */ #define VR41XX_KIUDAT3 __preg16(KSEG1 + 0x0B000186) /* KIU Data3 Register (R/W) */ #define VR41XX_KIUDAT4 __preg16(KSEG1 + 0x0B000188) /* KIU Data4 Register (R/W) */ #define VR41XX_KIUDAT5 __preg16(KSEG1 + 0x0B00018A) /* KIU Data5 Register (R/W) */ #define VR41XX_KIUSCANREP __preg16(KSEG1 + 0x0B000190) /* KIU Scan/Repeat Register (R/W) */ #define VR41XX_KIUSCANREP_KEYEN 0x8000 #define VR41XX_KIUSCANREP_SCANSTP 0x0008 #define VR41XX_KIUSCANREP_SCANSTART 0x0004 #define VR41XX_KIUSCANREP_ATSTP 0x0002 #define VR41XX_KIUSCANREP_ATSCAN 0x0001 #define VR41XX_KIUSCANS __preg16(KSEG1 + 0x0B000192) /* KIU Scan Status Register (R) */ #define VR41XX_KIUWKS __preg16(KSEG1 + 0x0B000194) /* KIU Wait Keyscan Stable Register (R/W) */ #define VR41XX_KIUWKI __preg16(KSEG1 + 0x0B000196) /* KIU Wait Keyscan Interval Register (R/W) */ #define VR41XX_KIUINT __preg16(KSEG1 + 0x0B000198) /* KIU Interrupt Register (R/W) */ #define VR41XX_KIUINT_KDATLOST 0x0004 #define VR41XX_KIUINT_KDATRDY 0x0002 #define VR41XX_KIUINT_SCANINT 0x0001 #define VR41XX_KIURST __preg16(KSEG1 + 0x0B00019A) /* KIU Reset Register (W) */ #define VR41XX_KIUGPEN __preg16(KSEG1 + 0x0B00019C) /* KIU General Purpose Output Enable (R/W) */ #define VR41XX_SCANLINE __preg16(KSEG1 + 0x0B00019E) /* KIU Scan Line Register (R/W) */ /* Debug Serial Interface Unit (DSIU) */ #define VR41XX_PORTREG __preg16(KSEG1 + 0x0B0001A0) /* Port Change Register (R/W) */ #define VR41XX_MODEMREG __preg16(KSEG1 + 0x0B0001A2) /* Modem Control Register (R) */ #define VR41XX_ASIM00REG __preg16(KSEG1 + 0x0B0001A4) /* Asynchronous Mode 0 Register (R/W) */ #define VR41XX_ASIM01REG __preg16(KSEG1 + 0x0B0001A6) /* Asynchronous Mode 1 Register (R/W) */ #define VR41XX_RXB0RREG __preg16(KSEG1 + 0x0B0001A8) /* Receive Buffer Register (Extended) (R) */ #define VR41XX_RXB0LREG __preg16(KSEG1 + 0x0B0001AA) /* Receive Buffer Register (R) */ #define VR41XX_TXS0RREG __preg16(KSEG1 + 0x0B0001AC) /* Transmit Data Register (Extended) (R/W) */ #define VR41XX_TXS0LREG __preg16(KSEG1 + 0x0B0001AE) /* Transmit Data Register (R/W) */ #define VR41XX_ASIS0REG __preg16(KSEG1 + 0x0B0001B0) /* Status Register (R) */ #define VR41XX_INTR0REG __preg16(KSEG1 + 0x0B0001B2) /* Debug SIU Interrupt Register (R/W) */ #define VR41XX_BPRM0REG __preg16(KSEG1 + 0x0B0001B6) /* Baud rate Generator Prescaler Mode Register (R/W) */ #define VR41XX_DSIURESETREG __preg16(KSEG1 + 0x0B0001B8) /* Debug SIU Reset Register (R/W) */ /* LED Control Unit (LED) */ #define VR41XX_LEDHTSREG __preg16(KSEG1 + 0x0B000240) /* LED H Time Set register (R/W) */ #define VR41XX_LEDLTSREG __preg16(KSEG1 + 0x0B000242) /* LED L Time Set register (R/W) */ #define VR41XX_LEDCNTREG __preg16(KSEG1 + 0x0B000248) /* LED Control register (R/W) */ #define VR41XX_LEDASTCREG __preg16(KSEG1 + 0x0B00024A) /* LED Auto Stop Time Count register (R/W) */ #define VR41XX_LEDINTREG __preg16(KSEG1 + 0x0B00024C) /* LED Interrupt register (R/W) */ /* Serial Interface Unit (SIU / SIU1 and SIU2) */ #define VR41XX_SIURB __preg8(KSEG1 + 0x0C000000) /* Receiver Buffer Register (Read) DLAB = 0 (R) */ #define VR41XX_SIUTH __preg8(KSEG1 + 0x0C000000) /* Transmitter Holding Register (Write) DLAB = 0 (W) */ #define VR41XX_SIUDLL __preg8(KSEG1 + 0x0C000000) /* Divisor Latch (Least Significant Byte) DLAB = 1 (R/W) */ #define VR41XX_SIUIE __preg8(KSEG1 + 0x0C000001) /* Interrupt Enable DLAB = 0 (R/W) */ #define VR41XX_SIUDLM __preg8(KSEG1 + 0x0C000001) /* Divisor Latch (Most Significant Byte) DLAB = 1 (R/W) */ #define VR41XX_SIUIID __preg8(KSEG1 + 0x0C000002) /* Interrupt Identification Register (Read) (R) */ #define VR41XX_SIUFC __preg8(KSEG1 + 0x0C000002) /* FIFO Control Register (Write) (W) */ #define VR41XX_SIULC __preg8(KSEG1 + 0x0C000003) /* Line Control Register (R/W) */ #define VR41XX_SIUMC __preg8(KSEG1 + 0x0C000004) /* MODEM Control Register (R/W) */ #define VR41XX_SIULS __preg8(KSEG1 + 0x0C000005) /* Line Status Register (R/W) */ #define VR41XX_SIUMS __preg8(KSEG1 + 0x0C000006) /* MODEM Status Register (R/W) */ #define VR41XX_SIUSC __preg8(KSEG1 + 0x0C000007) /* Scratch Register (R/W) */ #define VR41XX_SIUIRSEL __preg8(KSEG1 + 0x0C000008) /* SIU/FIR IrDA Selector (R/W) */ #define VR41XX_SIURESET __preg8(KSEG1 + 0x0C000009) /* SIU Reset Register (R/W) */ #define VR41XX_SIUCSEL __preg8(KSEG1 + 0x0C00000A) /* SIU Echo-Back Control Register (R/W) */ /* Modem Interface Unit (HSP) */ /* Not sure if some of these are right type, some may be 16 bit regs: */ #define VR41XX_HSPINIT __preg8(KSEG1 + 0x0C000020) /* HSP Initialize Register (R/W) */ #define VR41XX_HSPDATAL __preg8(KSEG1 + 0x0C000022) /* HSP Data Register L (R/W) */ #define VR41XX_HSPDATAH __preg8(KSEG1 + 0x0C000023) /* HSP Data Register H (R/W) */ #define VR41XX_HSPINDEX __preg8(KSEG1 + 0x0C000024) /* HSP Index Register (W) */ #define VR41XX_HSPID __preg8(KSEG1 + 0x0C000028) /* HSP ID Register (R) */ #define VR41XX_HSPPCS __preg8(KSEG1 + 0x0C000029) /* HSP I/O Address Program Confirmation Register (R) */ #define VR41XX_HSPPCTEL __preg8(KSEG1 + 0x0C000029) /* HSP Signature Checking Port (W) */ /* Fast IrDA Interface Unit (FIR) */ #define VR41XX_FRSTR __preg16(KSEG1 + 0x0C000040) /* FIR Reset register (R/W) */ #define VR41XX_DPINTR __preg16(KSEG1 + 0x0C000042) /* DMA Page Interrupt register (R/W) */ #define VR41XX_DPCNTR __preg16(KSEG1 + 0x0C000044) /* DMA Control register (R/W) */ #define VR41XX_TDR __preg16(KSEG1 + 0x0C000050) /* Transmit Data register (W) */ #define VR41XX_RDR __preg16(KSEG1 + 0x0C000052) /* Receive Data register (R) */ #define VR41XX_IMR __preg16(KSEG1 + 0x0C000054) /* Interrupt Mask register (R/W) */ #define VR41XX_FSR __preg16(KSEG1 + 0x0C000056) /* FIFO Setup register (R/W) */ #define VR41XX_IRSR1 __preg16(KSEG1 + 0x0C000058) /* Infrared Setup register 1 (R/W) */ #define VR41XX_CRCSR __preg16(KSEG1 + 0x0C00005C) /* CRC Setup register (R/W) */ #define VR41XX_FIRCR __preg16(KSEG1 + 0x0C00005E) /* FIR Control register (R/W) */ #define VR41XX_MIRCR __preg16(KSEG1 + 0x0C000060) /* MIR Control register (R/W) */ #define VR41XX_DMACR __preg16(KSEG1 + 0x0C000062) /* DMA Control register (R/W) */ #define VR41XX_DMAER __preg16(KSEG1 + 0x0C000064) /* DMA Enable register (R/W) */ #define VR41XX_TXIR __preg16(KSEG1 + 0x0C000066) /* Transmit Indication register (R) */ #define VR41XX_RXIR __preg16(KSEG1 + 0x0C000068) /* Receive Indication register (R) */ #define VR41XX_IFR __preg16(KSEG1 + 0x0C00006A) /* Interrupt Flag register (R) */ #define VR41XX_RXSTS __preg16(KSEG1 + 0x0C00006C) /* Receive Status (R) */ #define VR41XX_TXFL __preg16(KSEG1 + 0x0C00006E) /* Transmit Frame Length (R/W) */ #define VR41XX_MRXF __preg16(KSEG1 + 0x0C000070) /* Maximum Receive Frame Length (R/W) */ #define VR41XX_RXFL __preg16(KSEG1 + 0x0C000074) /* Receive Frame Length (R) */ /* physical address spaces */ #define VR41XX_LCD 0x0a000000 #define VR41XX_INTERNAL_IO_2 0x0b000000 #define VR41XX_INTERNAL_IO_1 0x0c000000 #define VR41XX_ISA_MEM 0x10000000 #define VR41XX_ISA_IO 0x14000000 #define VR41XX_ROM 0x18000000 /* This is the base address for IO port decoding to which the 16 bit * IO port address is added. Defining it to 0 will usually cause a * kernel oops any time port IO is attempted, which can be handy for * turning up parts of the kernel that make incorrect architecture * assumptions (by assuming that everything acts like a PC), but we * need it correctly defined to use the PCMCIA/CF controller: */ #define VR41XX_PORT_BASE (KSEG1 + VR41XX_ISA_IO) #define VR41XX_ISAMEM_BASE (KSEG1 + VR41XX_ISA_MEM) #endif /* __ASM_VR4121_VR4121_H */ |
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From: Paul M. <le...@us...> - 2001-10-29 08:20:58
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Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4111 In directory usw-pr-cvs1:/tmp/cvs-serv23171/vr4111 Modified Files: vr4111.h Log Message: Add VR4121 header.. fix a typo in vr4111.h, remove DSU entry from vr4122 definitions. Index: vr4111.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4111/vr4111.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- vr4111.h 2001/10/28 23:04:19 1.1 +++ vr4111.h 2001/10/29 08:20:55 1.2 @@ -501,4 +501,4 @@ #define VR41XX_PORT_BASE (KSEG1 + VR41XX_ISA_IO) #define VR41XX_ISAMEM_BASE (KSEG1 + VR41XX_ISA_MEM) -#endif /* __ASM_VR41XX_VR41XX_H */ +#endif /* __ASM_VR4111_VR4111_H */ |
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From: Paul M. <le...@us...> - 2001-10-29 08:20:58
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Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv23171 Modified Files: vr41xx.h Log Message: Add VR4121 header.. fix a typo in vr4111.h, remove DSU entry from vr4122 definitions. Index: vr41xx.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr41xx.h,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- vr41xx.h 2001/10/28 03:40:09 1.1 +++ vr41xx.h 2001/10/29 08:20:55 1.2 @@ -31,6 +31,8 @@ */ #if defined(CONFIG_VR4111) #include <asm/vr4111/vr4111.h> +#elif defined(CONFIG_VR4121) + #include <asm/vr4121/vr4121.h> #elif defined(CONFIG_VR4122) #include <asm/vr4122/vr4122.h> #elif defined(CONFIG_VR4181) |
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From: Paul M. <le...@us...> - 2001-10-29 08:12:58
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Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4121 In directory usw-pr-cvs1:/tmp/cvs-serv21326/vr4121 Log Message: Directory /cvsroot/linux-mips/linux/include/asm-mips/vr4121 added to the repository |
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From: Paul M. <le...@us...> - 2001-10-29 07:35:16
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Update of /cvsroot/linux-mips/linux/arch/mips/vr41xx/common In directory usw-pr-cvs1:/tmp/cvs-serv717/arch/mips/vr41xx/common Modified Files: reset.c Log Message: Add missing copyright notice. Index: reset.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/vr41xx/common/reset.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- reset.c 2001/10/28 23:04:19 1.1 +++ reset.c 2001/10/29 07:35:10 1.2 @@ -2,6 +2,7 @@ * VR41xx reset * * Copyright (C) 2000 Michael Klar + * Copyright (C) 2000 SATO Kazumi * Copyright (C) 2001 Jim Paris <ji...@jt...> * * This file is subject to the terms and conditions of the GNU General Public |
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