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From: James S. <jsi...@us...> - 2001-10-31 18:43:59
|
Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476
In directory usw-pr-cvs1:/tmp/cvs-serv16408/ddb5xxx/ddb5476
Modified Files:
vrc5476_irq.c
Added Files:
irq_5477.c
Log Message:
Interrupt handler fixes.
--- NEW FILE: irq_5477.c ---
/***********************************************************************
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, js...@mv... or js...@ju...
*
* arch/mips/ddb5xxx/ddb5477/irq_5477.c
* This file defines the irq handler for Vrc5477.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
***********************************************************************
*/
/*
* Vrc5477 defines 32 IRQs.
*
* This file exports one function:
* vrc5477_irq_init(u32 irq_base);
*/
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/* number of total irqs supported by Vrc5477 */
#define NUM_5477_IRQ 32
static int vrc5477_irq_base=-1;
static void
vrc5477_irq_enable(unsigned int irq)
{
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
ll_vrc5477_irq_enable(irq - vrc5477_irq_base);
}
static void
vrc5477_irq_disable(unsigned int irq)
{
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
}
static unsigned int vrc5477_irq_startup(unsigned int irq)
{
vrc5477_irq_enable(irq);
return 0;
}
#define vrc5477_irq_shutdown vrc5477_irq_disable
static void
vrc5477_irq_ack(unsigned int irq)
{
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base+ NUM_5477_IRQ);
/* clear the interrupt bit */
/* some irqs require the driver to clear the sources */
ddb_out32(DDB_INTCLR32, 1 << (irq - vrc5477_irq_base));
/* disable interrupt - some handler will re-enable the irq
* and if the interrupt is leveled, we will have infinite loop
*/
ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
}
static void
vrc5477_irq_end(unsigned int irq)
{
db_assert(vrc5477_irq_base != -1);
db_assert(irq >= vrc5477_irq_base);
db_assert(irq < vrc5477_irq_base + NUM_5477_IRQ);
ll_vrc5477_irq_enable( irq - vrc5477_irq_base);
}
hw_irq_controller vrc5477_irq_controller = {
"vrc5477_irq",
vrc5477_irq_startup,
vrc5477_irq_shutdown,
vrc5477_irq_enable,
vrc5477_irq_disable,
vrc5477_irq_ack,
vrc5477_irq_end,
NULL /* no affinity stuff for UP */
};
void
vrc5477_irq_init(u32 irq_base)
{
extern irq_desc_t irq_desc[];
u32 i;
for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &vrc5477_irq_controller;
}
vrc5477_irq_base = irq_base;
}
int vrc5477_irq_to_irq(int irq)
{
db_assert(irq >= 0);
db_assert(irq < NUM_5477_IRQ);
return irq + vrc5477_irq_base;
}
void ll_vrc5477_irq_route(int vrc5477_irq, int ip)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
db_assert(vrc5477_irq >= 0);
db_assert(vrc5477_irq < NUM_5477_IRQ);
db_assert(ip >= 0);
db_assert((ip < 5) || (ip == 6));
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 7 << (vrc5477_irq % 8 * 4);
reg_value &= ~reg_bitmask;
reg_value |= ip << (vrc5477_irq % 8 * 4);
ddb_out32(reg_index, reg_value);
}
void ll_vrc5477_irq_enable(int vrc5477_irq)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
db_assert(vrc5477_irq >= 0);
db_assert(vrc5477_irq < NUM_5477_IRQ);
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
db_assert((reg_value & reg_bitmask) == 0);
ddb_out32(reg_index, reg_value | reg_bitmask);
}
void ll_vrc5477_irq_disable(int vrc5477_irq)
{
u32 reg_value;
u32 reg_bitmask;
u32 reg_index;
db_assert(vrc5477_irq >= 0);
db_assert(vrc5477_irq < NUM_5477_IRQ);
reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4;
reg_value = ddb_in32(reg_index);
reg_bitmask = 8 << (vrc5477_irq % 8 * 4);
/* we assert that the interrupt is enabled (perhaps over-zealous) */
db_assert( (reg_value & reg_bitmask) != 0);
ddb_out32(reg_index, reg_value & ~reg_bitmask);
}
Index: vrc5476_irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- vrc5476_irq.c 2001/10/11 20:45:26 1.2
+++ vrc5476_irq.c 2001/10/31 18:43:56 1.3
@@ -45,7 +45,11 @@
nile4_disable_irq(irq - irq_base);
}
-#define vrc5476_irq_end vrc5476_irq_enable
+static void vrc5476_irq_end(uint irq)
+{
+ if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ vrc5476_irq_enable(irq);
+}
static hw_irq_controller vrc5476_irq_controller = {
"vrc5476",
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:30:17
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv10579 Modified Files: tx3912.h Log Message: Your daily dose of Nino updates. Index: tx3912.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/tx3912.h,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- tx3912.h 2001/10/26 22:30:51 1.3 +++ tx3912.h 2001/10/31 18:30:14 1.4 @@ -1,5 +1,5 @@ /* - * linux/include/asm-mips/tx3912.h + * include/asm-mips/tx3912.h * * Copyright (C) 2001 Steven J. Hill (sj...@re...) * @@ -9,8 +9,8 @@ * * Register includes for TMPR3912/05 and PR31700 processors */ -#ifndef __TX3912_H__ -#define __TX3912_H__ +#ifndef _TX3912_H_ +#define _TX3912_H_ #include <asm/addrspace.h> @@ -276,6 +276,8 @@ #define INT6_CHIDMACNTINT BIT(2) #define INT6_IOPOSNEGINT0 BIT(1) +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) + /****************************************************************************** * * 09 GPIO and MFIO modules @@ -573,4 +575,4 @@ #define TX3912_UART_CTRL2_B600 0x17f /* 383 */ #define TX3912_UART_CTRL2_B300 0x2ff /* 767 */ -#endif /* __TX3912_H__ */ +#endif /* _TX3912_H_ */ |
|
From: James S. <jsi...@us...> - 2001-10-31 18:29:12
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv10055
Modified Files:
int-handler.S irq.c kgdb.c power.c prom.c setup.c time.c
Removed Files:
rtc.c
Log Message:
Your daily dose of Nino updates.
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/int-handler.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- int-handler.S 2001/10/26 22:30:51 1.2
+++ int-handler.S 2001/10/31 18:29:07 1.3
@@ -1,9 +1,14 @@
/*
- * int-handler.S: Interrupt exception dispatch code for Philips Nino
+ * arch/mips/philips/nino/int-handler.S
*
- * Copyright (C) 2001 Steven J. Hill (sj...@re...)
+ * Copyright (C) 2001 Steven J. Hill (sj...@re...)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Interrupt exception dispatch code for Philips Nino
*/
-
#include <asm/asm.h>
#include <asm/mipsregs.h>
#include <asm/regdef.h>
@@ -12,27 +17,17 @@
/*
* Here is the table of interrupts for the Philips Nino
* which uses the Philips PR31700/Toshiba TMPR3912 core.
- *
- * MIPS IRQ PR31700 IRQ Source
- * -------- ----------- ------
- * 0 1 Sound, LCD, telecom
- * 1 2 UARTA & UARTB
- * 2 3 MFIO (positive edge)
- * 3 4 MFIO (negative edge)
- * 4 5 Timers, power management
- * 5 6 High priority interrupts
- *
- * We handle the IRQ according to the priorities below:
- *
- * Highest ---- High priority interrupts
- * UARTA & UARTB
- * Timers, power management
- * Sound, LCD, telecom
- * Multi-function IO (positive edge)
- * Lowest ---- Multi-function IO (negative edge)
*
- * then we just return, if multiple IRQs are pending then
- * we will just take another exception, big deal.
+ * MIPS IRQ Description
+ * -------- --------------------------------
+ * 0 SW0 interrupt (unused)
+ * 1 SW1 interrupt (unused)
+ * 2
+ * 3
+ * 4 PR31700 low priority interrupts
+ * 5
+ * 6 PR31700 high priority interrupts
+ * 7
*/
.text
@@ -43,40 +38,29 @@
SAVE_ALL
CLI
.set at
- mfc0 s0, CP0_CAUSE # get irq mask
+ mfc0 s0, CP0_CAUSE # determine cause
- /* Check for IRQ4 */
- andi a0, s0, C_IRQ4
+ andi a0, s0, CAUSEF_IP6
beq a0, zero, 1f
- andi a0, s0, C_IRQ2 # delay slot, check for IRQ2
-
- /* High priority interrupt */
+ andi a0, s0, CAUSEF_IP4 # delay slot
move a0, sp
- jal irq4_dispatch
+ jal irq6_dispatch
nop # delay slot
-
j ret_from_irq
nop # delay slot
1:
- /* Check for IRQ2 */
beq a0, zero, 1f
nop # delay slot
-
- /* UART interrupt of some sort */
move a0, sp
- jal irq2_dispatch
+ jal irq4_dispatch
nop # delay slot
-
j ret_from_irq
nop # delay slot
1:
/* We should never get here */
move a0, sp
- jal irq_bad
- nop
-
- j ret_from_irq
+ j irq_bad
nop
END(ninoIRQ)
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq.c 2001/10/29 17:37:01 1.4
+++ irq.c 2001/10/31 18:29:07 1.5
@@ -1,7 +1,13 @@
/*
- * include/arch/mips/philips/nino/irq.c
+ * arch/mips/philips/nino/irq.c
*
- * Copyright (C) 2001 Steven J. Hill (sj...@re...)
+ * Copyright (C) 2001 Steven J. Hill (sj...@re...)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Interrupt service routines for Philips Nino
*/
#include <linux/init.h>
#include <linux/sched.h>
@@ -13,7 +19,7 @@
extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
-static void enable_irq4(unsigned int irq)
+static void enable_irq6(unsigned int irq)
{
if(irq == 0) {
IntEnable5 |= INT5_PERIODICINT;
@@ -21,14 +27,14 @@
}
}
-static unsigned int startup_irq4(unsigned int irq)
+static unsigned int startup_irq6(unsigned int irq)
{
- enable_irq4(irq);
+ enable_irq6(irq);
return 0; /* Never anything pending */
}
-static void disable_irq4(unsigned int irq)
+static void disable_irq6(unsigned int irq)
{
if(irq == 0) {
IntEnable6 &= ~INT6_PERIODICINT;
@@ -37,27 +43,27 @@
}
}
-#define shutdown_irq4 disable_irq4
-#define mask_and_ack_irq4 disable_irq4
+#define shutdown_irq6 disable_irq6
+#define mask_and_ack_irq6 disable_irq6
-static void end_irq4(unsigned int irq)
+static void end_irq6(unsigned int irq)
{
if(!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_irq4(irq);
+ enable_irq6(irq);
}
-static struct hw_interrupt_type irq4_type = {
+static struct hw_interrupt_type irq6_type = {
"MIPS",
- startup_irq4,
- shutdown_irq4,
- enable_irq4,
- disable_irq4,
- mask_and_ack_irq4,
- end_irq4,
+ startup_irq6,
+ shutdown_irq6,
+ enable_irq6,
+ disable_irq6,
+ mask_and_ack_irq6,
+ end_irq6,
NULL
};
-void irq4_dispatch(struct pt_regs *regs)
+void irq6_dispatch(struct pt_regs *regs)
{
int irq = -1;
@@ -68,8 +74,7 @@
/* if irq == -1, then the interrupt has already been cleared */
if(irq == -1) {
- printk("IRQ6 Status Register = 0x%08lx\n", IntStatus6);
- goto end;
+ panic("No handler installed for MIPS IRQ6\n");
}
done:
@@ -79,68 +84,59 @@
return;
}
-static void enable_irq2(unsigned int irq)
+static void enable_irq4(unsigned int irq)
{
set_cp0_status(STATUSF_IP4);
- if(irq == 2 || irq == 3) {
+ if(irq == 2) {
IntClear2 = 0xffffffff;
- IntEnable2 = 0xfffff000;
+ IntEnable2 |= 0x07c00000;
}
}
-static unsigned int startup_irq2(unsigned int irq)
+static unsigned int startup_irq4(unsigned int irq)
{
- enable_irq2(irq);
+ enable_irq4(irq);
return 0; /* Never anything pending */
}
-static void disable_irq2(unsigned int irq)
+static void disable_irq4(unsigned int irq)
{
clear_cp0_status(STATUSF_IP4);
}
-#define shutdown_irq2 disable_irq2
-#define mask_and_ack_irq2 disable_irq2
+#define shutdown_irq4 disable_irq4
+#define mask_and_ack_irq4 disable_irq4
-static void end_irq2(unsigned int irq)
+static void end_irq4(unsigned int irq)
{
if(!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
- enable_irq2(irq);
+ enable_irq4(irq);
}
-static struct hw_interrupt_type irq2_type = {
+static struct hw_interrupt_type irq4_type = {
"MIPS",
- startup_irq2,
- shutdown_irq2,
- enable_irq2,
- disable_irq2,
- mask_and_ack_irq2,
- end_irq2,
+ startup_irq4,
+ shutdown_irq4,
+ enable_irq4,
+ disable_irq4,
+ mask_and_ack_irq4,
+ end_irq4,
NULL
};
-void irq2_dispatch(struct pt_regs *regs)
+void irq4_dispatch(struct pt_regs *regs)
{
int irq = -1;
- if(IntStatus2 & 0xfffff000) {
+ if(IntStatus2 & 0x07c00000) {
irq = 2;
goto done;
}
- if(IntStatus2 & 0xfffff000) {
- irq = 3;
- goto done;
- }
/* if irq == -1, then the interrupt has already been cleared */
if (irq == -1) {
- printk("EEK\n");
- IntClear1 = 0xffffffff;
- IntClear3 = 0xffffffff;
- IntClear4 = 0xffffffff;
- IntClear5 = 0xffffffff;
- goto end;
+ panic("No handler installed for MIPS IRQ4\n");
}
done:
@@ -190,10 +186,10 @@
/* Initialize IRQ action handlers */
for (i = 0; i < 16; i++) {
hw_irq_controller *handler = NULL;
- if (i == 0)
+ if (i == 0 || i == 3)
+ handler = &irq6_type;
+ else if (i == 2)
handler = &irq4_type;
- else if (i > 1 && i < 4)
- handler = &irq2_type;
else
handler = NULL;
@@ -209,8 +205,8 @@
/* Enable high priority interrupts */
IntEnable6 = (INT6_GLOBALEN | 0xffff);
- /* Enable interrupts */
- change_cp0_status(ST0_IM, IE_IRQ2 | IE_IRQ4);
+ /* Enable all interrupts */
+ change_cp0_status(ST0_IM, ALLINTS);
}
void (*irq_setup)(void);
Index: kgdb.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/kgdb.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- kgdb.c 2001/06/22 02:29:32 1.1.1.1
+++ kgdb.c 2001/10/31 18:29:07 1.2
@@ -1,5 +1,5 @@
/*
- * linux/arch/mips/philips/nino/kgdb.c
+ * arch/mips/philips/nino/kgdb.c
*
* Copyright (C) 2001 Steven J. Hill (sj...@re...)
*
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * Kernel debugging on the Philips Nino.
+ * Kernel debugging for the Philips Nino
*/
#include <asm/system.h>
#include <asm/tx3912.h>
Index: power.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/power.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- power.c 2001/06/22 02:29:32 1.1.1.1
+++ power.c 2001/10/31 18:29:07 1.2
@@ -1,5 +1,5 @@
/*
- * linux/arch/mips/philips/nino/power.c
+ * arch/mips/philips/nino/power.c
*
* Copyright (C) 2000 Jim Pick <ji...@ji...>
* Copyright (C) 2001 Steven J. Hill (sj...@re...)
@@ -8,7 +8,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * Power management routines on the Philips Nino.
+ * Power management routines for the Philips Nino
*/
#include <asm/tx3912.h>
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/prom.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- prom.c 2001/10/29 17:37:01 1.2
+++ prom.c 2001/10/31 18:29:08 1.3
@@ -1,5 +1,5 @@
/*
- * linux/arch/mips/philips/nino/prom.c
+ * arch/mips/philips/nino/prom.c
*
* Copyright (C) 2001 Steven J. Hill (sj...@re...)
*
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * Early initialization code for the Philips Nino.
+ * Early initialization code for the Philips Nino
*/
#include <linux/config.h>
#include <linux/init.h>
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2001/10/29 17:37:01 1.3
+++ setup.c 2001/10/31 18:29:08 1.4
@@ -1,5 +1,5 @@
/*
- * linux/arch/mips/philips/nino/setup.c
+ * arch/mips/philips/nino/setup.c
*
* Copyright (C) 2001 Steven J. Hill (sj...@re...)
*
@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * Interrupt and exception initialization for Philips Nino.
+ * Interrupt and exception initialization for Philips Nino
*/
#include <linux/init.h>
#include <linux/interrupt.h>
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c 2001/10/29 17:37:01 1.3
+++ time.c 2001/10/31 18:29:08 1.4
@@ -1,5 +1,5 @@
/*
- * linux/arch/mips/philips/nino/time.c
+ * arch/mips/philips/nino/time.c
*
* Copyright (C) 1999 Harald Koerfgen
* Copyright (C) 2000 Pavel Machek (pa...@su...)
@@ -9,7 +9,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
- * Time handling functinos for Philips Nino.
+ * Time handling functinos for Philips Nino
*/
#include <linux/errno.h>
#include <linux/init.h>
--- rtc.c DELETED ---
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:26:55
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv9038/include/asm-mips64
Modified Files:
checksum.h io.h mipsregs.h mmu_context.h pci.h pgtable.h
processor.h softirq.h
Added Files:
bcache.h branch.h r10kcache.h siginfo.h unaligned.h
Log Message:
Replace all incarnations of extern inline with static inline.
--- NEW FILE: bcache.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1997, 1999 by Ralf Baechle
* Copyright (c) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_BCACHE_H
#define _ASM_BCACHE_H
#include <linux/config.h>
#ifdef CONFIG_BOARD_SCACHE
/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
chipset implemented caches. On machines with other CPUs the CPU does the
cache thing itself. */
struct bcache_ops {
void (*bc_enable)(void);
void (*bc_disable)(void);
void (*bc_wback_inv)(unsigned long page, unsigned long size);
void (*bc_inv)(unsigned long page, unsigned long size);
};
extern void indy_sc_init(void);
extern void sni_pcimt_sc_init(void);
extern struct bcache_ops *bcops;
static inline void bc_enable(void)
{
bcops->bc_enable();
}
static inline void bc_disable(void)
{
bcops->bc_disable();
}
static inline void bc_wback_inv(unsigned long page, unsigned long size)
{
bcops->bc_wback_inv(page, size);
}
static inline void bc_inv(unsigned long page, unsigned long size)
{
bcops->bc_inv(page, size);
}
#else /* !defined(CONFIG_BOARD_SCACHE) */
/* Not R4000 / R4400 / R4600 / R5000. */
#define bc_enable() do { } while (0)
#define bc_disable() do { } while (0)
#define bc_wback_inv(page, size) do { } while (0)
#define bc_inv(page, size) do { } while (0)
#endif /* !defined(CONFIG_BOARD_SCACHE) */
#endif /* _ASM_BCACHE_H */
--- NEW FILE: branch.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Branch and jump emulation.
*
* Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
*/
#include <asm/ptrace.h>
static inline int delay_slot(struct pt_regs *regs)
{
return regs->cp0_cause & CAUSEF_BD;
}
extern int __compute_return_epc(struct pt_regs *regs);
static inline int compute_return_epc(struct pt_regs *regs)
{
if (!delay_slot(regs)) {
regs->cp0_epc += 4;
return 0;
}
return __compute_return_epc(regs);
}
--- NEW FILE: r10kcache.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Inline assembly cache operations.
*
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*
* FIXME: Handle split L2 caches.
*/
#ifndef _ASM_R10KCACHE_H
#define _ASM_R10KCACHE_H
#include <asm/asm.h>
#include <asm/r10kcacheops.h>
/* These are fixed for the current R10000. */
#define icache_size 0x8000
#define dcache_size 0x8000
#define icache_way_size 0x4000
#define dcache_way_size 0x4000
#define ic_lsize 64
#define dc_lsize 32
/* These are configuration dependant. */
#define scache_size() ({ \
unsigned long __res; \
__res = (read_32bit_cp0_register(CP0_CONFIG) >> 16) & 3; \
__res = 1 << (__res + 19); \
__res; \
})
#define sc_lsize() ({ \
unsigned long __res; \
__res = (read_32bit_cp0_register(CP0_CONFIG) >> 13) & 1; \
__res = 1 << (__res + 6); \
__res; \
})
static inline void flush_icache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Index_Invalidate_I));
}
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Index_Writeback_Inv_D));
}
static inline void flush_scache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Index_Writeback_Inv_S));
}
static inline void flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Hit_Invalidate_I));
}
static inline void flush_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Hit_Writeback_Inv_D));
}
static inline void invalidate_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Hit_Invalidate_D));
}
static inline void invalidate_scache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Hit_Invalidate_S));
}
static inline void flush_scache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"cache %1, (%0)\n\t"
".set reorder"
:
: "r" (addr), "i" (Hit_Writeback_Inv_S));
}
/*
* The next two are for badland addresses like signal trampolines.
*/
static inline void protected_flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"1:\tcache %1,(%0)\n"
"2:\t.set reorder\n\t"
".section\t__ex_table,\"a\"\n\t"
".dword\t1b,2b\n\t"
".previous"
:
: "r" (addr), "i" (Hit_Invalidate_I));
}
static inline void protected_writeback_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
"1:\tcache %1,(%0)\n"
"2:\t.set reorder\n\t"
".section\t__ex_table,\"a\"\n\t"
".dword\t1b,2b\n\t"
".previous"
:
: "r" (addr), "i" (Hit_Writeback_Inv_D));
}
#define cache32_unroll16(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
cache %1, 0x000(%0); cache %1, 0x020(%0); \
cache %1, 0x040(%0); cache %1, 0x060(%0); \
cache %1, 0x080(%0); cache %1, 0x0a0(%0); \
cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \
cache %1, 0x100(%0); cache %1, 0x120(%0); \
cache %1, 0x140(%0); cache %1, 0x160(%0); \
cache %1, 0x180(%0); cache %1, 0x1a0(%0); \
cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \
.set reorder" \
: \
: "r" (base), \
"i" (op));
#define cache32_unroll32(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
cache %1, 0x000(%0); cache %1, 0x020(%0); \
cache %1, 0x040(%0); cache %1, 0x060(%0); \
cache %1, 0x080(%0); cache %1, 0x0a0(%0); \
cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \
cache %1, 0x100(%0); cache %1, 0x120(%0); \
cache %1, 0x140(%0); cache %1, 0x160(%0); \
cache %1, 0x180(%0); cache %1, 0x1a0(%0); \
cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \
cache %1, 0x200(%0); cache %1, 0x220(%0); \
cache %1, 0x240(%0); cache %1, 0x260(%0); \
cache %1, 0x280(%0); cache %1, 0x2a0(%0); \
cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \
cache %1, 0x300(%0); cache %1, 0x320(%0); \
cache %1, 0x340(%0); cache %1, 0x360(%0); \
cache %1, 0x380(%0); cache %1, 0x3a0(%0); \
cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \
.set reorder" \
: \
: "r" (base), \
"i" (op));
static inline void blast_dcache32(void)
{
unsigned long way0 = KSEG0;
unsigned long way1 = way0 ^ 1;
unsigned long end = (way0 + dcache_way_size);
while (way0 < end) {
cache32_unroll16(way0, Index_Writeback_Inv_D);
cache32_unroll16(way1, Index_Writeback_Inv_D);
way0 += 0x200;
way1 += 0x200;
}
}
static inline void blast_dcache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
while (start < end) {
cache32_unroll32(start, Hit_Writeback_Inv_D);
start += 0x400;
}
}
static inline void blast_dcache32_page_indexed(unsigned long page)
{
unsigned long way0 = page;
unsigned long way1 = page ^ 1;
unsigned long end = page + PAGE_SIZE;
while (way0 < end) {
cache32_unroll16(way0, Index_Writeback_Inv_D);
cache32_unroll16(way1, Index_Writeback_Inv_D);
way0 += 0x200;
way1 += 0x200;
}
}
#define cache64_unroll16(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
cache %1, 0x000(%0); cache %1, 0x040(%0); \
cache %1, 0x080(%0); cache %1, 0x0c0(%0); \
cache %1, 0x100(%0); cache %1, 0x140(%0); \
cache %1, 0x180(%0); cache %1, 0x1c0(%0); \
cache %1, 0x200(%0); cache %1, 0x240(%0); \
cache %1, 0x280(%0); cache %1, 0x2c0(%0); \
cache %1, 0x300(%0); cache %1, 0x340(%0); \
cache %1, 0x380(%0); cache %1, 0x3c0(%0); \
.set reorder" \
: \
: "r" (base), \
"i" (op));
#define cache64_unroll32(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
cache %1, 0x000(%0); cache %1, 0x040(%0); \
cache %1, 0x080(%0); cache %1, 0x0c0(%0); \
cache %1, 0x100(%0); cache %1, 0x140(%0); \
cache %1, 0x180(%0); cache %1, 0x1c0(%0); \
cache %1, 0x200(%0); cache %1, 0x240(%0); \
cache %1, 0x280(%0); cache %1, 0x2c0(%0); \
cache %1, 0x300(%0); cache %1, 0x340(%0); \
cache %1, 0x380(%0); cache %1, 0x3c0(%0); \
cache %1, 0x400(%0); cache %1, 0x440(%0); \
cache %1, 0x480(%0); cache %1, 0x4c0(%0); \
cache %1, 0x500(%0); cache %1, 0x540(%0); \
cache %1, 0x580(%0); cache %1, 0x5c0(%0); \
cache %1, 0x600(%0); cache %1, 0x640(%0); \
cache %1, 0x680(%0); cache %1, 0x6c0(%0); \
cache %1, 0x700(%0); cache %1, 0x740(%0); \
cache %1, 0x780(%0); cache %1, 0x7c0(%0); \
.set reorder" \
: \
: "r" (base), \
"i" (op));
static inline void blast_icache64(void)
{
unsigned long way0 = KSEG0;
unsigned long way1 = way0 ^ 1;
unsigned long end = way0 + icache_way_size;
while (way0 < end) {
cache64_unroll16(way0,Index_Invalidate_I);
cache64_unroll16(way1,Index_Invalidate_I);
way0 += 0x400;
way1 += 0x400;
}
}
static inline void blast_icache64_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
while (start < end) {
cache64_unroll32(start,Hit_Invalidate_I);
start += 0x800;
}
}
static inline void blast_icache64_page_indexed(unsigned long page)
{
unsigned long way0 = page;
unsigned long way1 = page ^ 1;
unsigned long end = page + PAGE_SIZE;
while (way0 < end) {
cache64_unroll16(way0,Index_Invalidate_I);
cache64_unroll16(way1,Index_Invalidate_I);
way0 += 0x400;
way1 += 0x400;
}
}
static inline void blast_scache64(void)
{
unsigned long way0 = KSEG0;
unsigned long way1 = way0 ^ 1;
unsigned long end = KSEG0 + scache_size();
while (way0 < end) {
cache64_unroll16(way0,Index_Writeback_Inv_S);
cache64_unroll16(way1,Index_Writeback_Inv_S);
way0 += 0x400;
way1 += 0x400;
}
}
static inline void blast_scache64_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
while (start < end) {
cache64_unroll32(start,Hit_Writeback_Inv_S);
start += 0x800;
}
}
static inline void blast_scache64_page_indexed(unsigned long page)
{
unsigned long way0 = page;
unsigned long way1 = page ^ 1;
unsigned long end = page + PAGE_SIZE;
while (way0 < end) {
cache64_unroll16(way0,Index_Writeback_Inv_S);
cache64_unroll16(way1,Index_Writeback_Inv_S);
way0 += 0x400;
way1 += 0x400;
}
}
#define cache128_unroll16(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
cache %1, 0x000(%0); cache %1, 0x080(%0); \
cache %1, 0x100(%0); cache %1, 0x180(%0); \
cache %1, 0x200(%0); cache %1, 0x280(%0); \
cache %1, 0x300(%0); cache %1, 0x380(%0); \
cache %1, 0x400(%0); cache %1, 0x480(%0); \
cache %1, 0x500(%0); cache %1, 0x580(%0); \
cache %1, 0x600(%0); cache %1, 0x680(%0); \
cache %1, 0x700(%0); cache %1, 0x780(%0); \
.set reorder" \
: \
: "r" (base), \
"i" (op));
#define cache128_unroll32(base,op) \
__asm__ __volatile__(" \
.set noreorder; \
cache %1, 0x000(%0); cache %1, 0x080(%0); \
cache %1, 0x100(%0); cache %1, 0x180(%0); \
cache %1, 0x200(%0); cache %1, 0x280(%0); \
cache %1, 0x300(%0); cache %1, 0x380(%0); \
cache %1, 0x400(%0); cache %1, 0x480(%0); \
cache %1, 0x500(%0); cache %1, 0x580(%0); \
cache %1, 0x600(%0); cache %1, 0x680(%0); \
cache %1, 0x700(%0); cache %1, 0x780(%0); \
cache %1, 0x800(%0); cache %1, 0x880(%0); \
cache %1, 0x900(%0); cache %1, 0x980(%0); \
cache %1, 0xa00(%0); cache %1, 0xa80(%0); \
cache %1, 0xb00(%0); cache %1, 0xb80(%0); \
cache %1, 0xc00(%0); cache %1, 0xc80(%0); \
cache %1, 0xd00(%0); cache %1, 0xd80(%0); \
cache %1, 0xe00(%0); cache %1, 0xe80(%0); \
cache %1, 0xf00(%0); cache %1, 0xf80(%0); \
.set reorder" \
: \
: "r" (base), \
"i" (op));
static inline void blast_scache128(void)
{
unsigned long way0 = KSEG0;
unsigned long way1 = way0 ^ 1;
unsigned long end = way0 + scache_size();
while (way0 < end) {
cache128_unroll16(way0, Index_Writeback_Inv_S);
cache128_unroll16(way1, Index_Writeback_Inv_S);
way0 += 0x800;
way1 += 0x800;
}
}
static inline void blast_scache128_page(unsigned long page)
{
cache128_unroll32(page, Hit_Writeback_Inv_S);
}
static inline void blast_scache128_page_indexed(unsigned long page)
{
cache128_unroll32(page , Index_Writeback_Inv_S);
cache128_unroll32(page ^ 1, Index_Writeback_Inv_S);
}
#endif /* _ASM_R10KCACHE_H */
Index: checksum.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/checksum.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- checksum.h 2001/10/23 17:14:04 1.4
+++ checksum.h 2001/10/31 18:26:52 1.5
@@ -43,7 +43,7 @@
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
-extern inline unsigned int csum_and_copy_to_user (const char *src, char *dst,
+static inline unsigned int csum_and_copy_to_user (const char *src, char *dst,
int len, int sum,
int *err_ptr)
{
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/io.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- io.h 2001/10/22 19:16:45 1.6
+++ io.h 2001/10/31 18:26:52 1.7
@@ -155,7 +155,7 @@
*/
#define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned long port) {
+static inline void __out##s(unsigned int value, unsigned long port) {
#define __OUT2(m) \
__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -169,7 +169,7 @@
SLOW_DOWN_IO; }
#define __IN1(t,s) \
-extern inline t __in##s(unsigned long port) { t _v;
+static inline t __in##s(unsigned long port) { t _v;
/*
* Required nops will be inserted by the assembler
@@ -184,7 +184,7 @@
__IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return _v; }
#define __INS1(s) \
-extern inline void __ins##s(unsigned long port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned long port, void * addr, unsigned long count) {
#define __INS2(m) \
if (count) \
@@ -210,7 +210,7 @@
"I" (i));}
#define __OUTS1(s) \
-extern inline void __outs##s(unsigned long port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned long port, const void * addr, unsigned long count) {
#define __OUTS2(m) \
if (count) \
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- mipsregs.h 2001/10/27 17:28:55 1.4
+++ mipsregs.h 2001/10/31 18:26:52 1.5
@@ -85,37 +85,6 @@
#define PL_16M 24
/*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- "mfc0\t%0,"STR(source) \
- : "=r" (__res)); \
- __res;})
-
-#define read_64bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0,"STR(source)"\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res;})
-
-#define write_32bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- "mtc0\t%0,"STR(register) \
- : : "r" (value));
-
-#define write_64bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%0,"STR(register)"\n\t" \
- ".set\tmips0" \
- : : "r" (value))
-
-/*
* R4x00 interrupt enable / cause bits
*/
#define IE_SW0 (1<< 8)
@@ -139,57 +108,7 @@
#define C_IRQ4 (1<<14)
#define C_IRQ5 (1<<15)
-#ifndef _LANGUAGE_ASSEMBLY
/*
- * Manipulate the status register.
- * Mostly used to access the interrupt bits.
- */
-#define __BUILD_SET_CP0(name,register) \
-extern inline unsigned int \
-set_cp0_##name(unsigned int set) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res |= set; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern inline unsigned int \
-clear_cp0_##name(unsigned int clear) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~clear; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern inline unsigned int \
-change_cp0_##name(unsigned int change, unsigned int new) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~change; \
- res |= (new & change); \
- if (change) \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-}
-
-__BUILD_SET_CP0(status,CP0_STATUS)
-__BUILD_SET_CP0(cause,CP0_CAUSE)
-__BUILD_SET_CP0(config,CP0_CONFIG)
-
-#endif /* defined (_LANGUAGE_ASSEMBLY) */
-
-/*
* Bitfields in the R4xx0 cp0 status register
*/
#define ST0_IE 0x00000001
@@ -350,6 +269,375 @@
extern asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val);
extern asmlinkage unsigned int read_perf_cntl(unsigned int counter);
extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val);
-#endif
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ "mfc0\t%0,"STR(source) \
+ : "=r" (__res)); \
+ __res;})
+
+#define read_64bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0,"STR(source)"\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_32bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ "mtc0\t%0,"STR(register) \
+ : : "r" (value));
+
+#define write_64bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%0,"STR(register)"\n\t" \
+ ".set\tmips0" \
+ : : "r" (value))
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbp\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_read(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbr\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwi\n\t"
+ ".set reorder");
+}
+
+static inline void tlb_write_random(void)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "tlbwr\n\t"
+ ".set reorder");
+}
+
+/* Dealing with various CP0 mmu/cache related registers. */
+
+/* CP0_PAGEMASK register */
+static inline unsigned long get_pagemask(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mfc0 %0, $5\n\t"
+ ".set reorder"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_pagemask(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mtc0 %z0, $5\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
+static inline unsigned long get_entrylo0(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmfc0 %0, $2\n\t"
+ ".set reorder"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_entrylo0(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmtc0 %z0, $2\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo1(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmfc0 %0, $3\n\t"
+ ".set reorder" : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entrylo1(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmtc0 %z0, $3\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+/* CP0_ENTRYHI register */
+static inline unsigned long get_entryhi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmfc0 %0, $10\n\t"
+ ".set reorder"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entryhi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmtc0 %z0, $10\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+/* CP0_INDEX register */
+static inline unsigned int get_index(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mfc0 %0, $0\n\t"
+ ".set reorder"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_index(unsigned int val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mtc0 %z0, $0\n\t"
+ ".set reorder\n\t"
+ : : "Jr" (val));
+}
+
+/* CP0_WIRED register */
+static inline unsigned long get_wired(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mfc0 %0, $6\n\t"
+ ".set reorder\n\t"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_wired(unsigned long val)
+{
+ __asm__ __volatile__(
+ "\n\t.set noreorder\n\t"
+ "mtc0 %z0, $6\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_info(void)
+{
+ unsigned long val;
+
+ __asm__(".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $7\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+/* CP0_STATUS registers */
+static inline unsigned long get_status(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mfc0 %0, $12\n\t"
+ ".set reorder"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_status(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mtc0 %z0, $12\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+/* CP0_TAGLO and CP0_TAGHI registers */
+static inline unsigned long get_taglo(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mfc0 %0, $28\n\t"
+ ".set reorder"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taglo(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mtc0 %z0, $28\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_taghi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mfc0 %0, $29\n\t"
+ ".set reorder"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taghi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "mtc0 %z0, $29\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+/* CP0_CONTEXT register */
+static inline unsigned long get_context(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmfc0 %0, $4\n\t"
+ ".set reorder"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_context(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set noreorder\n\t"
+ "dmtc0 %z0, $4\n\t"
+ ".set reorder"
+ : : "Jr" (val));
+}
+
+/*
+ * Manipulate the status register.
+ * Mostly used to access the interrupt bits.
+ */
+#define __BUILD_SET_CP0(name,register) \
+static inline unsigned int \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~change; \
+ res |= (new & change); \
+ if (change) \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+}
+
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
+
+#define __enable_fpu() \
+do { \
+ set_cp0_status(ST0_CU1); \
+ asm("nop;nop;nop;nop"); /* max. hazard */ \
+} while (0)
+
+#define __disable_fpu() \
+do { \
+ clear_cp0_status(ST0_CU1); \
+ /* We don't care about the cp0 hazard here */ \
+} while (0)
+
+#define enable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __enable_fpu(); \
+} while (0)
+
+#define disable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __disable_fpu(); \
+} while (0)
+#endif /* defined (_LANGUAGE_ASSEMBLY) */
#endif /* _ASM_MIPSREGS_H */
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- mmu_context.h 2001/10/09 21:54:37 1.1
+++ mmu_context.h 2001/10/31 18:26:52 1.2
@@ -51,7 +51,7 @@
#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
-extern inline void
+static inline void
get_new_cpu_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
unsigned long asid = ASID_CACHE(cpu);
@@ -68,7 +68,7 @@
* Initialize the context related info for a new mm_struct
* instance.
*/
-extern inline int
+static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifndef CONFIG_SMP
@@ -87,7 +87,7 @@
return 0;
}
-extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
struct task_struct *tsk, unsigned cpu)
{
/* Check if our ASID is of an older version and thus invalid */
@@ -102,7 +102,7 @@
* Destroy context related info for an mm_struct that is about
* to be put to rest.
*/
-extern inline void destroy_context(struct mm_struct *mm)
+static inline void destroy_context(struct mm_struct *mm)
{
#ifdef CONFIG_SMP
if (mm->context)
@@ -114,7 +114,7 @@
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
*/
-extern inline void
+static inline void
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
/* Unconditionally get a new ASID. */
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pci.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci.h 2001/09/04 16:16:15 1.3
+++ pci.h 2001/10/31 18:26:52 1.4
@@ -23,12 +23,12 @@
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x10000000
-extern inline void pcibios_set_master(struct pci_dev *dev)
+static inline void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
}
-extern inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq)
{
/* We don't do dynamic PCI IRQ allocation */
}
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pgtable.h 2001/10/19 21:19:40 1.5
+++ pgtable.h 2001/10/31 18:26:52 1.6
@@ -566,259 +566,13 @@
#define kern_addr_valid(addr) (1)
#endif
-/* TLB operations. */
-static inline void tlb_probe(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbp\n\t"
- ".set reorder");
-}
-
-static inline void tlb_read(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbr\n\t"
- ".set reorder");
-}
-
-static inline void tlb_write_indexed(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbwi\n\t"
- ".set reorder");
-}
-
-static inline void tlb_write_random(void)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "tlbwr\n\t"
- ".set reorder");
-}
-
-/* Dealing with various CP0 mmu/cache related registers. */
-
-/* CP0_PAGEMASK register */
-static inline unsigned long get_pagemask(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $5\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-static inline void set_pagemask(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $5\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-static inline unsigned long get_entrylo0(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $2\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-static inline void set_entrylo0(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $2\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-static inline unsigned long get_entrylo1(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $3\n\t"
- ".set reorder" : "=r" (val));
-
- return val;
-}
-
-static inline void set_entrylo1(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $3\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYHI register */
-static inline unsigned long get_entryhi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $10\n\t"
- ".set reorder"
- : "=r" (val));
-
- return val;
-}
-
-static inline void set_entryhi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $10\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_INDEX register */
-static inline unsigned int get_index(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $0\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-static inline void set_index(unsigned int val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $0\n\t"
- ".set reorder\n\t"
- : : "Jr" (val));
-}
-
-/* CP0_WIRED register */
-static inline unsigned long get_wired(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $6\n\t"
- ".set reorder\n\t"
- : "=r" (val));
- return val;
-}
-
-static inline void set_wired(unsigned long val)
-{
- __asm__ __volatile__(
- "\n\t.set noreorder\n\t"
- "mtc0 %z0, $6\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-static inline unsigned long get_info(void)
-{
- unsigned long val;
-
- __asm__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $7\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-/* CP0_TAGLO and CP0_TAGHI registers */
-static inline unsigned long get_taglo(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $28\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-static inline void set_taglo(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $28\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-static inline unsigned long get_taghi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mfc0 %0, $29\n\t"
- ".set reorder"
- : "=r" (val));
- return val;
-}
-
-static inline void set_taghi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "mtc0 %z0, $29\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-/* CP0_CONTEXT register */
-static inline unsigned long get_context(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmfc0 %0, $4\n\t"
- ".set reorder"
- : "=r" (val));
-
- return val;
-}
-
-static inline void set_context(unsigned long val)
-{
- __asm__ __volatile__(
- ".set noreorder\n\t"
- "dmtc0 %z0, $4\n\t"
- ".set reorder"
- : : "Jr" (val));
-}
-
-#include <asm-generic/pgtable.h>
-
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
/*
* No page table caches to initialise
*/
#define pgtable_cache_init() do { } while (0)
+
+#include <asm-generic/pgtable.h>
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#endif /* _ASM_PGTABLE_H */
Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/processor.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- processor.h 2001/10/19 21:19:40 1.4
+++ processor.h 2001/10/31 18:26:52 1.5
@@ -249,7 +249,7 @@
/*
* Return saved PC of a blocked thread.
*/
-extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
{
extern void ret_from_sys_call(void);
Index: softirq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/softirq.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- softirq.h 2001/10/27 17:28:55 1.4
+++ softirq.h 2001/10/31 18:26:52 1.5
@@ -13,13 +13,13 @@
#include <asm/atomic.h>
#include <asm/hardirq.h>
-extern inline void cpu_bh_disable(int cpu)
+static inline void cpu_bh_disable(int cpu)
{
local_bh_count(cpu)++;
barrier();
}
-extern inline void __cpu_bh_enable(int cpu)
+static inline void __cpu_bh_enable(int cpu)
{
barrier();
local_bh_count(cpu)--;
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:26:55
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/ip32
In directory usw-pr-cvs1:/tmp/cvs-serv9038/include/asm-mips64/ip32
Modified Files:
crime.h mace.h
Log Message:
Replace all incarnations of extern inline with static inline.
Index: crime.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/ip32/crime.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- crime.h 2001/09/04 22:41:02 1.1
+++ crime.h 2001/10/31 18:26:52 1.2
@@ -23,10 +23,10 @@
#endif
#ifndef _LANGUAGE_ASSEMBLY
-extern inline u64 crime_read_64 (unsigned long __offset) {
+static inline u64 crime_read_64 (unsigned long __offset) {
return *((volatile u64 *) (CRIME_BASE + __offset));
}
-extern inline void crime_write_64 (unsigned long __offset, u64 __val) {
+static inline void crime_write_64 (unsigned long __offset, u64 __val) {
*((volatile u64 *) (CRIME_BASE + __offset)) = __val;
}
#endif
Index: mace.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/ip32/mace.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- mace.h 2001/09/04 22:41:02 1.1
+++ mace.h 2001/10/31 18:26:53 1.2
@@ -37,30 +37,46 @@
/*
* XXX Some of these are probably not needed (or even legal?)
*/
-extern inline u8 mace_read_8 (unsigned long __offset) {
+static inline u8 mace_read_8 (unsigned long __offset)
+{
return *((volatile u8 *) (MACE_BASE + __offset));
}
-extern inline u16 mace_read_16 (unsigned long __offset) {
+
+static inline u16 mace_read_16 (unsigned long __offset)
+{
return *((volatile u16 *) (MACE_BASE + __offset));
}
-extern inline u32 mace_read_32 (unsigned long __offset) {
+
+static inline u32 mace_read_32 (unsigned long __offset)
+{
return *((volatile u32 *) (MACE_BASE + __offset));
}
-extern inline u64 mace_read_64 (unsigned long __offset) {
+
+static inline u64 mace_read_64 (unsigned long __offset)
+{
return *((volatile u64 *) (MACE_BASE + __offset));
}
-extern inline void mace_write_8 (unsigned long __offset, u8 __val) {
+
+static inline void mace_write_8 (unsigned long __offset, u8 __val)
+{
*((volatile u8 *) (MACE_BASE + __offset)) = __val;
}
-extern inline void mace_write_16 (unsigned long __offset, u16 __val) {
+
+static inline void mace_write_16 (unsigned long __offset, u16 __val)
+{
*((volatile u16 *) (MACE_BASE + __offset)) = __val;
}
-extern inline void mace_write_32 (unsigned long __offset, u32 __val) {
+
+static inline void mace_write_32 (unsigned long __offset, u32 __val)
+{
*((volatile u32 *) (MACE_BASE + __offset)) = __val;
}
-extern inline void mace_write_64 (unsigned long __offset, u64 __val) {
+
+static inline void mace_write_64 (unsigned long __offset, u64 __val)
+{
*((volatile u64 *) (MACE_BASE + __offset)) = __val;
}
+
#endif
#undef BIT
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:26:55
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv9038/include/asm-mips
Modified Files:
checksum.h io.h mmu_context.h pci.h pgalloc.h processor.h
r4kcache.h softirq.h
Added Files:
bcache.h branch.h jazz.h mips32_cache.h siginfo.h unaligned.h
Log Message:
Replace all incarnations of extern inline with static inline.
--- NEW FILE: branch.h ---
/*
* Branch and jump emulation.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
*/
#include <asm/ptrace.h>
static inline int delay_slot(struct pt_regs *regs)
{
return regs->cp0_cause & CAUSEF_BD;
}
extern int __compute_return_epc(struct pt_regs *regs);
static inline int compute_return_epc(struct pt_regs *regs)
{
if (!delay_slot(regs)) {
regs->cp0_epc += 4;
return 0;
}
return __compute_return_epc(regs);
}
--- NEW FILE: jazz.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
*/
#ifndef __ASM_JAZZ_H
#define __ASM_JAZZ_H
/*
* The addresses below are virtual address. The mappings are
* created on startup via wired entries in the tlb. The Mips
* Magnum R3000 and R4000 machines are similar in many aspects,
* but many hardware register are accessible at 0xb9000000 in
* instead of 0xe0000000.
*/
#define JAZZ_LOCAL_IO_SPACE 0xe0000000
/*
* Revision numbers in PICA_ASIC_REVISION
*
* 0xf0000000 - Rev1
* 0xf0000001 - Rev2
* 0xf0000002 - Rev3
*/
#define PICA_ASIC_REVISION 0xe0000008
/*
* The segments of the seven segment LED are mapped
* to the control bits as follows:
*
* (7)
* ---------
* | |
* (2) | | (6)
* | (1) |
* ---------
* | |
* (3) | | (5)
* | (4) |
* --------- . (0)
*/
#define PICA_LED 0xe000f000
/*
* Some characters for the LED control registers
* The original Mips machines seem to have a LED display
* with integrated decoder while the Acer machines can
* control each of the seven segments and the dot independently.
* It's only a toy, anyway...
*/
#define LED_DOT 0x01
#define LED_SPACE 0x00
#define LED_0 0xfc
#define LED_1 0x60
#define LED_2 0xda
#define LED_3 0xf2
#define LED_4 0x66
#define LED_5 0xb6
#define LED_6 0xbe
#define LED_7 0xe0
#define LED_8 0xfe
#define LED_9 0xf6
#define LED_A 0xee
#define LED_b 0x3e
#define LED_C 0x9c
#define LED_d 0x7a
#define LED_E 0x9e
#define LED_F 0x8e
#ifndef _LANGUAGE_ASSEMBLY
extern __inline__ void pica_set_led(unsigned int bits)
{
volatile unsigned int *led_register = (unsigned int *) PICA_LED;
*led_register = bits;
}
#endif
/*
* Base address of the Sonic Ethernet adapter in Jazz machines.
*/
#define JAZZ_ETHERNET_BASE 0xe0001000
/*
* Base address of the 53C94 SCSI hostadapter in Jazz machines.
*/
#define JAZZ_SCSI_BASE 0xe0002000
/*
* i8042 keyboard controller for JAZZ and PICA chipsets.
* This address is just a guess and seems to differ from
* other mips machines such as RC3xxx...
*/
#define JAZZ_KEYBOARD_ADDRESS 0xe0005000
#define JAZZ_KEYBOARD_DATA 0xe0005000
#define JAZZ_KEYBOARD_COMMAND 0xe0005001
#ifndef _LANGUAGE_ASSEMBLY
typedef struct {
unsigned char data;
unsigned char command;
} jazz_keyboard_hardware;
typedef struct {
unsigned char pad0[3];
unsigned char data;
unsigned char pad1[3];
unsigned char command;
} mips_keyboard_hardware;
/*
* For now. Needs to be changed for RC3xxx support. See below.
*/
#define keyboard_hardware jazz_keyboard_hardware
#endif
/*
* i8042 keyboard controller for most other Mips machines.
*/
#define MIPS_KEYBOARD_ADDRESS 0xb9005000
#define MIPS_KEYBOARD_DATA 0xb9005003
#define MIPS_KEYBOARD_COMMAND 0xb9005007
/*
* Serial and parallel ports (WD 16C552) on the Mips JAZZ
*/
#define JAZZ_SERIAL1_BASE (unsigned int)0xe0006000
#define JAZZ_SERIAL2_BASE (unsigned int)0xe0007000
#define JAZZ_PARALLEL_BASE (unsigned int)0xe0008000
/*
* Dummy Device Address. Used in jazzdma.c
*/
#define JAZZ_DUMMY_DEVICE 0xe000d000
/*
* JAZZ timer registers and interrupt no.
* Note that the hardware timer interrupt is actually on
* cpu level 6, but to keep compatibility with PC stuff
* it is remapped to vector 0. See arch/mips/kernel/entry.S.
*/
#define JAZZ_TIMER_INTERVAL 0xe0000228
#define JAZZ_TIMER_REGISTER 0xe0000230
/*
* DRAM configuration register
*/
#ifndef _LANGUAGE_ASSEMBLY
#ifdef __MIPSEL__
typedef struct {
unsigned int bank2 : 3;
unsigned int bank1 : 3;
unsigned int mem_bus_width : 1;
unsigned int reserved2 : 1;
unsigned int page_mode : 1;
unsigned int reserved1 : 23;
} dram_configuration;
#else /* defined (__MIPSEB__) */
typedef struct {
unsigned int reserved1 : 23;
unsigned int page_mode : 1;
unsigned int reserved2 : 1;
unsigned int mem_bus_width : 1;
unsigned int bank1 : 3;
unsigned int bank2 : 3;
} dram_configuration;
#endif
#endif /* _LANGUAGE_ASSEMBLY */
#define PICA_DRAM_CONFIG 0xe00fffe0
/*
* JAZZ interrupt control registers
*/
#define JAZZ_IO_IRQ_SOURCE 0xe0010000
#define JAZZ_IO_IRQ_ENABLE 0xe0010002
/*
* JAZZ interrupt enable bits
*/
#define JAZZ_IE_PARALLEL (1 << 0)
#define JAZZ_IE_FLOPPY (1 << 1)
#define JAZZ_IE_SOUND (1 << 2)
#define JAZZ_IE_VIDEO (1 << 3)
#define JAZZ_IE_ETHERNET (1 << 4)
#define JAZZ_IE_SCSI (1 << 5)
#define JAZZ_IE_KEYBOARD (1 << 6)
#define JAZZ_IE_MOUSE (1 << 7)
#define JAZZ_IE_SERIAL1 (1 << 8)
#define JAZZ_IE_SERIAL2 (1 << 9)
/*
* JAZZ Interrupt Level definitions
*
* This is somewhat broken. For reasons which nobody can remember anymore
* we remap the Jazz interrupts to the usual ISA style interrupt numbers.
*/
#define JAZZ_PARALLEL_IRQ 16
#define JAZZ_FLOPPY_IRQ 6 /* needs to be consistent with floppy driver! */
#define JAZZ_SOUND_IRQ 18
#define JAZZ_VIDEO_IRQ 19
#define JAZZ_ETHERNET_IRQ 20
#define JAZZ_SCSI_IRQ 21
#define JAZZ_KEYBOARD_IRQ 22
#define JAZZ_MOUSE_IRQ 23
#define JAZZ_SERIAL1_IRQ 24
#define JAZZ_SERIAL2_IRQ 25
#define JAZZ_TIMER_IRQ 31
/*
* JAZZ DMA Channels
* Note: Channels 4...7 are not used with respect to the Acer PICA-61
* chipset which does not provide these DMA channels.
*/
#define JAZZ_SCSI_DMA 0 /* SCSI */
#define JAZZ_FLOPPY_DMA 1 /* FLOPPY */
#define JAZZ_AUDIOL_DMA 2 /* AUDIO L */
#define JAZZ_AUDIOR_DMA 3 /* AUDIO R */
/*
* JAZZ R4030 MCT_ADR chip (DMA controller)
* Note: Virtual Addresses !
*/
#define JAZZ_R4030_CONFIG 0xE0000000 /* R4030 config register */
#define JAZZ_R4030_REVISION 0xE0000008 /* same as PICA_ASIC_REVISION */
#define JAZZ_R4030_INV_ADDR 0xE0000010 /* Invalid Address register */
#define JAZZ_R4030_TRSTBL_BASE 0xE0000018 /* Translation Table Base */
#define JAZZ_R4030_TRSTBL_LIM 0xE0000020 /* Translation Table Limit */
#define JAZZ_R4030_TRSTBL_INV 0xE0000028 /* Translation Table Invalidate */
#define JAZZ_R4030_CACHE_MTNC 0xE0000030 /* Cache Maintenance */
#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038 /* Remote Failed Address */
#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040 /* Memory Failed Address */
#define JAZZ_R4030_CACHE_PTAG 0xE0000048 /* I/O Cache Physical Tag */
#define JAZZ_R4030_CACHE_LTAG 0xE0000050 /* I/O Cache Logical Tag */
#define JAZZ_R4030_CACHE_BMASK 0xE0000058 /* I/O Cache Byte Mask */
#define JAZZ_R4030_CACHE_BWIN 0xE0000060 /* I/O Cache Buffer Window */
/*
* Remote Speed Registers.
*
* 0: free, 1: Ethernet, 2: SCSI, 3: Floppy,
* 4: RTC, 5: Kb./Mouse 6: serial 1, 7: serial 2,
* 8: parallel, 9: NVRAM, 10: CPU, 11: PROM,
* 12: reserved, 13: free, 14: 7seg LED, 15: ???
*/
#define JAZZ_R4030_REM_SPEED 0xE0000070 /* 16 Remote Speed Registers */
/* 0xE0000070,78,80... 0xE00000E8 */
#define JAZZ_R4030_IRQ_ENABLE 0xE00000E8 /* Internal Interrupt Enable */
#define JAZZ_R4030_INVAL_ADDR 0xE0000010 /* Invalid address Register */
#define JAZZ_R4030_IRQ_SOURCE 0xE0000200 /* Interrupt Source Register */
#define JAZZ_R4030_I386_ERROR 0xE0000208 /* i386/EISA Bus Error */
/*
* Virtual (E)ISA controller address
*/
#define JAZZ_EISA_IRQ_ACK 0xE0000238 /* EISA interrupt acknowledge */
/*
* Access the R4030 DMA and I/O Controller
*/
#ifndef _LANGUAGE_ASSEMBLY
static inline void r4030_delay(void)
{
__asm__ __volatile__(
".set\tnoreorder\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
".set\treorder");
}
static inline unsigned short r4030_read_reg16(unsigned addr)
{
unsigned short ret = *((volatile unsigned short *)addr);
r4030_delay();
return ret;
}
static inline unsigned int r4030_read_reg32(unsigned addr)
{
unsigned int ret = *((volatile unsigned int *)addr);
r4030_delay();
return ret;
}
static inline void r4030_write_reg16(unsigned addr, unsigned val)
{
*((volatile unsigned short *)addr) = val;
r4030_delay();
}
static inline void r4030_write_reg32(unsigned addr, unsigned val)
{
*((volatile unsigned int *)addr) = val;
r4030_delay();
}
#endif /* !LANGUAGE_ASSEMBLY__ */
#define JAZZ_FDC_BASE 0xe0003000
#define JAZZ_RTC_BASE 0xe0004000
#define JAZZ_PORT_BASE 0xe2000000
#define JAZZ_EISA_BASE 0xe3000000
#endif /* __ASM_JAZZ_H */
--- NEW FILE: siginfo.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 1999 by Ralf Baechle
*/
#ifndef _ASM_SIGINFO_H
#define _ASM_SIGINFO_H
#include <linux/types.h>
/* This structure matches IRIX 32/n32 ABIs for binary compatibility. */
typedef union sigval {
int sival_int;
void *sival_ptr;
} sigval_t;
/* This structure matches IRIX 32/n32 ABIs for binary compatibility but
has Linux extensions. */
#define SI_MAX_SIZE 128
#define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 3)
typedef struct siginfo {
int si_signo;
int si_code;
int si_errno;
union {
int _pad[SI_PAD_SIZE];
/* kill() */
struct {
pid_t _pid; /* sender's pid */
uid_t _uid; /* sender's uid */
} _kill;
/* SIGCHLD */
struct {
pid_t _pid; /* which child */
uid_t _uid; /* sender's uid */
clock_t _utime;
int _status; /* exit code */
clock_t _stime;
} _sigchld;
/* IRIX SIGCHLD */
struct {
pid_t _pid; /* which child */
clock_t _utime;
int _status; /* exit code */
clock_t _stime;
} _irix_sigchld;
/* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
struct {
void *_addr; /* faulting insn/memory ref. */
} _sigfault;
/* SIGPOLL, SIGXFSZ (To do ...) */
struct {
int _band; /* POLL_IN, POLL_OUT, POLL_MSG */
int _fd;
} _sigpoll;
/* POSIX.1b timers */
struct {
unsigned int _timer1;
unsigned int _timer2;
} _timer;
/* POSIX.1b signals */
struct {
pid_t _pid; /* sender's pid */
uid_t _uid; /* sender's uid */
sigval_t _sigval;
} _rt;
} _sifields;
} siginfo_t;
/*
* How these fields are to be accessed.
*/
#define si_pid _sifields._kill._pid
#define si_uid _sifields._kill._uid
#define si_status _sifields._sigchld._status
#define si_utime _sifields._sigchld._utime
#define si_stime _sifields._sigchld._stime
#define si_value _sifields._rt._sigval
#define si_int _sifields._rt._sigval.sival_int
#define si_ptr _sifields._rt._sigval.sival_ptr
#define si_addr _sifields._sigfault._addr
#define si_band _sifields._sigpoll._band
#define si_fd _sifields._sigpoll._fd
#ifdef __KERNEL__
#define __SI_MASK 0xffff0000
#define __SI_KILL (0 << 16)
#define __SI_TIMER (1 << 16)
#define __SI_POLL (2 << 16)
#define __SI_FAULT (3 << 16)
#define __SI_CHLD (4 << 16)
#define __SI_RT (5 << 16)
#define __SI_CODE(T,N) ((T) << 16 | ((N) & 0xffff))
#else
#define __SI_KILL 0
#define __SI_TIMER 0
#define __SI_POLL 0
#define __SI_FAULT 0
#define __SI_CHLD 0
#define __SI_RT 0
#define __SI_CODE(T,N) (N)
#endif
/*
* si_code values
* Again these have been choosen to be IRIX compatible.
*/
#define SI_USER 0 /* sent by kill, sigsend, raise */
#define SI_KERNEL 0x80 /* sent by the kernel from somewhere */
#define SI_QUEUE -1 /* sent by sigqueue */
#define SI_ASYNCIO -2 /* sent by AIO completion */
#define SI_TIMER __SI_CODE(__SI_TIMER,-3) /* sent by timer expiration */
#define SI_MESGQ -4 /* sent by real time mesq state change */
#define SI_SIGIO -5 /* sent by queued SIGIO */
#define SI_FROMUSER(siptr) ((siptr)->si_code <= 0)
#define SI_FROMKERNEL(siptr) ((siptr)->si_code > 0)
/*
* SIGILL si_codes
*/
#define ILL_ILLOPC (__SI_FAULT|1) /* illegal opcode */
#define ILL_ILLOPN (__SI_FAULT|2) /* illegal operand */
#define ILL_ILLADR (__SI_FAULT|3) /* illegal addressing mode */
#define ILL_ILLTRP (__SI_FAULT|4) /* illegal trap */
#define ILL_PRVOPC (__SI_FAULT|5) /* privileged opcode */
#define ILL_PRVREG (__SI_FAULT|6) /* privileged register */
#define ILL_COPROC (__SI_FAULT|7) /* coprocessor error */
#define ILL_BADSTK (__SI_FAULT|8) /* internal stack error */
#define NSIGILL 8
/*
* SIGFPE si_codes
*/
#define FPE_INTDIV (__SI_FAULT|1) /* integer divide by zero */
#define FPE_INTOVF (__SI_FAULT|2) /* integer overflow */
#define FPE_FLTDIV (__SI_FAULT|3) /* floating point divide by zero */
#define FPE_FLTOVF (__SI_FAULT|4) /* floating point overflow */
#define FPE_FLTUND (__SI_FAULT|5) /* floating point underflow */
#define FPE_FLTRES (__SI_FAULT|6) /* floating point inexact result */
#define FPE_FLTINV (__SI_FAULT|7) /* floating point invalid operation */
#define FPE_FLTSUB (__SI_FAULT|8) /* subscript out of range */
#define NSIGFPE 8
/*
* SIGSEGV si_codes
*/
#define SEGV_MAPERR (__SI_FAULT|1) /* address not mapped to object */
#define SEGV_ACCERR (__SI_FAULT|2) /* invalid permissions for mapped object */
#define NSIGSEGV 2
/*
* SIGBUS si_codes
*/
#define BUS_ADRALN (__SI_FAULT|1) /* invalid address alignment */
#define BUS_ADRERR (__SI_FAULT|2) /* non-existant physical address */
#define BUS_OBJERR (__SI_FAULT|3) /* object specific hardware error */
#define NSIGBUS 3
/*
* SIGTRAP si_codes
*/
#define TRAP_BRKPT (__SI_FAULT|1) /* process breakpoint */
#define TRAP_TRACE (__SI_FAULT|2) /* process trace trap */
#define NSIGTRAP 2
/*
* SIGCHLD si_codes
*/
#define CLD_EXITED (__SI_CHLD|1) /* child has exited */
#define CLD_KILLED (__SI_CHLD|2) /* child was killed */
#define CLD_DUMPED (__SI_CHLD|3) /* child terminated abnormally */
#define CLD_TRAPPED (__SI_CHLD|4) /* traced child has trapped */
#define CLD_STOPPED (__SI_CHLD|5) /* child has stopped */
#define CLD_CONTINUED (__SI_CHLD|6) /* stopped child has continued */
#define NSIGCHLD 6
/*
* SIGPOLL si_codes
*/
#define POLL_IN (__SI_POLL|1) /* data input available */
#define POLL_OUT (__SI_POLL|2) /* output buffers available */
#define POLL_MSG (__SI_POLL|3) /* input message available */
#define POLL_ERR (__SI_POLL|4) /* i/o error */
#define POLL_PRI (__SI_POLL|5) /* high priority input available */
#define POLL_HUP (__SI_POLL|6) /* device disconnected */
#define NSIGPOLL 6
/*
* sigevent definitions
*
* It seems likely that SIGEV_THREAD will have to be handled from
* userspace, libpthread transmuting it to SIGEV_SIGNAL, which the
* thread manager then catches and does the appropriate nonsense.
* However, everything is written out here so as to not get lost.
*/
#define SIGEV_NONE 128 /* other notification: meaningless */
#define SIGEV_SIGNAL 129 /* notify via signal */
#define SIGEV_CALLBACK 130 /* ??? */
#define SIGEV_THREAD 131 /* deliver via thread creation */
#define SIGEV_MAX_SIZE 64
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4)
/* XXX This one isn't yet IRIX / ABI compatible. */
typedef struct sigevent {
int sigev_notify;
sigval_t sigev_value;
int sigev_signo;
union {
int _pad[SIGEV_PAD_SIZE];
struct {
void (*_function)(sigval_t);
void *_attribute; /* really pthread_attr_t */
} _sigev_thread;
} _sigev_un;
} sigevent_t;
#define sigev_notify_function _sigev_un._sigev_thread._function
#define sigev_notify_attributes _sigev_un._sigev_thread._attribute
#ifdef __KERNEL__
#include <linux/string.h>
static inline void copy_siginfo(siginfo_t *to, siginfo_t *from)
{
if (from->si_code < 0)
memcpy(to, from, sizeof(siginfo_t));
else
/* _sigchld is currently the largest know union member */
memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
}
extern int copy_siginfo_to_user(siginfo_t *to, siginfo_t *from);
#endif /* __KERNEL__ */
#endif /* _ASM_SIGINFO_H */
Index: checksum.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/checksum.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- checksum.h 2001/10/23 17:14:04 1.4
+++ checksum.h 2001/10/31 18:26:52 1.5
@@ -41,7 +41,7 @@
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
-extern inline unsigned int csum_and_copy_to_user (const char *src, char *dst,
+static inline unsigned int csum_and_copy_to_user (const char *src, char *dst,
int len, int sum,
int *err_ptr)
{
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- io.h 2001/09/25 03:36:35 1.6
+++ io.h 2001/10/31 18:26:52 1.7
@@ -102,12 +102,12 @@
* Change virtual addresses to physical addresses and vv.
* These are trivial on the 1:1 Linux/MIPS mapping
*/
-extern inline unsigned long virt_to_phys(volatile void * address)
+static inline unsigned long virt_to_phys(volatile void * address)
{
return PHYSADDR(address);
}
-extern inline void * phys_to_virt(unsigned long address)
+static inline void * phys_to_virt(unsigned long address)
{
return (void *)KSEG0ADDR(address);
}
@@ -115,12 +115,12 @@
/*
* IO bus memory addresses are also 1:1 with the physical address
*/
-extern inline unsigned long virt_to_bus(volatile void * address)
+static inline unsigned long virt_to_bus(volatile void * address)
{
return PHYSADDR(address);
}
-extern inline void * bus_to_virt(unsigned long address)
+static inline void * bus_to_virt(unsigned long address)
{
return (void *)KSEG0ADDR(address);
}
@@ -140,12 +140,12 @@
extern void * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
-extern inline void *ioremap(unsigned long offset, unsigned long size)
+static inline void *ioremap(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
-extern inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _CACHE_UNCACHED);
}
@@ -227,7 +227,7 @@
*/
#define __OUT1(s) \
-extern inline void __out##s(unsigned int value, unsigned int port) {
+static inline void __out##s(unsigned int value, unsigned int port) {
#define __OUT2(m) \
__asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
@@ -275,7 +275,7 @@
#define __inlc_p(port) __INMAC_P(unsigned int,w,32,port)
#define __INS1(s) \
-extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
+static inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
#define __INS2(m,count) \
if (count) \
@@ -295,7 +295,7 @@
: "=r" (addr), "=r" (count) \
: "0" (addr), "1" (count), "i" (0), \
"r" (mips_io_port_base+port), "I" (i) \
- : "$1");}
+ : "$1");} \
#define __INSMAC(m,i,port,addr,count) ({ void *_a = (addr); unsigned long _c = (count); \
__INS2(m,_c) \
@@ -303,12 +303,13 @@
: "0" (_a), "1" (_c), "i#*X" (port), \
"r" (mips_io_port_base), "I" (i) \
: "$1"); })
+
#define __insbc(port,addr,count) __INSMAC(b,1,port,addr,count)
#define __inswc(port,addr,count) __INSMAC(h,2,port,addr,count)
#define __inslc(port,addr,count) __INSMAC(w,4,port,addr,count)
-
+
#define __OUTS1(s) \
-extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
+static inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
#define __OUTS2(m,count) \
if (count) \
@@ -327,7 +328,7 @@
__OUTS1(s) __OUTS2(m,count) \
: "=r" (addr), "=r" (count) \
: "0" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
- : "$1");}
+ : "$1");}
#define __OUTSMAC(m,i,port,addr,count) ({ void *_a = (addr); unsigned long _c = (count); \
__OUTS2(m,_c) \
Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mmu_context.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- mmu_context.h 2001/10/24 23:32:54 1.5
+++ mmu_context.h 2001/10/31 18:26:52 1.6
@@ -60,7 +60,7 @@
#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
-extern inline void
+static inline void
get_new_cpu_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
unsigned long asid = ASID_CACHE(cpu);
@@ -77,7 +77,7 @@
* Initialize the context related info for a new mm_struct
* instance.
*/
-extern inline int
+static inline int
init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
#ifndef CONFIG_SMP
@@ -96,7 +96,7 @@
return 0;
}
-extern inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
struct task_struct *tsk, unsigned cpu)
{
/* Check if our ASID is of an older version and thus invalid */
@@ -111,7 +111,7 @@
* Destroy context related info for an mm_struct that is about
* to be put to rest.
*/
-extern inline void destroy_context(struct mm_struct *mm)
+static inline void destroy_context(struct mm_struct *mm)
{
#ifdef CONFIG_SMP
if (mm->context)
@@ -123,7 +123,7 @@
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
*/
-extern inline void
+static inline void
activate_mm(struct mm_struct *prev, struct mm_struct *next)
{
/* Unconditionally get a new ASID. */
Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pci.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci.h 2001/08/22 18:18:14 1.3
+++ pci.h 2001/10/31 18:26:52 1.4
@@ -23,12 +23,12 @@
#define PCIBIOS_MIN_IO 0x1000
#define PCIBIOS_MIN_MEM 0x10000000
-extern inline void pcibios_set_master(struct pci_dev *dev)
+static inline void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
}
-extern inline void pcibios_penalize_isa_irq(int irq)
+static inline void pcibios_penalize_isa_irq(int irq)
{
/* We don't do dynamic PCI IRQ allocation */
}
@@ -84,7 +84,7 @@
* Once the device is given the dma address, the device owns this memory
* until either pci_unmap_single or pci_dma_sync_single is performed.
*/
-extern inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
+static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
@@ -105,7 +105,7 @@
* After this call, reads by the cpu to the buffer are guarenteed to see
* whatever the device wrote there.
*/
-extern inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
+static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
size_t size, int direction)
{
if (direction == PCI_DMA_NONE)
@@ -130,7 +130,7 @@
* Device ownership issues as mentioned above for pci_map_single are
* the same here.
*/
-extern inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
#ifndef CONFIG_COHERENT_IO
@@ -154,7 +154,7 @@
* Again, cpu read rules concerning calls here are the same as for
* pci_unmap_single() above.
*/
-extern inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
int nents, int direction)
{
if (direction == PCI_DMA_NONE)
@@ -173,7 +173,7 @@
* next point you give the PCI dma address back to the card, the
* device again owns the buffer.
*/
-extern inline void pci_dma_sync_single(struct pci_dev *hwdev,
+static inline void pci_dma_sync_single(struct pci_dev *hwdev,
dma_addr_t dma_handle,
size_t size, int direction)
{
@@ -192,7 +192,7 @@
* The same as pci_dma_sync_single but for a scatter-gather list,
* same rules and usage.
*/
-extern inline void pci_dma_sync_sg(struct pci_dev *hwdev,
+static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
struct scatterlist *sg,
int nelems, int direction)
{
@@ -215,7 +215,7 @@
* only drive the low 24-bits during PCI bus mastering, then
* you would pass 0x00ffffff as the mask to this function.
*/
-extern inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
+static inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
{
/*
* we fall back to GFP_DMA when the mask isn't all 1s,
Index: pgalloc.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgalloc.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- pgalloc.h 2001/10/19 21:19:40 1.4
+++ pgalloc.h 2001/10/31 18:26:52 1.5
@@ -43,7 +43,7 @@
#endif /* CONFIG_SMP */
-extern inline void flush_tlb_pgtables(struct mm_struct *mm,
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{
/* Nothing to do on MIPS. */
Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/processor.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- processor.h 2001/10/26 16:03:53 1.7
+++ processor.h 2001/10/31 18:26:52 1.8
@@ -216,7 +216,7 @@
/*
* Return saved PC of a blocked thread.
*/
-extern inline unsigned long thread_saved_pc(struct thread_struct *t)
+static inline unsigned long thread_saved_pc(struct thread_struct *t)
{
extern void ret_from_fork(void);
Index: r4kcache.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/r4kcache.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- r4kcache.h 2001/10/24 23:32:54 1.1
+++ r4kcache.h 2001/10/31 18:26:52 1.2
@@ -11,7 +11,7 @@
#include <asm/asm.h>
#include <asm/cacheops.h>
-extern inline void flush_icache_line_indexed(unsigned long addr)
+static inline void flush_icache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -24,7 +24,7 @@
"i" (Index_Invalidate_I));
}
-extern inline void flush_dcache_line_indexed(unsigned long addr)
+static inline void flush_dcache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -37,7 +37,7 @@
"i" (Index_Writeback_Inv_D));
}
-extern inline void flush_scache_line_indexed(unsigned long addr)
+static inline void flush_scache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -50,7 +50,7 @@
"i" (Index_Writeback_Inv_SD));
}
-extern inline void flush_icache_line(unsigned long addr)
+static inline void flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -63,7 +63,7 @@
"i" (Hit_Invalidate_I));
}
-extern inline void flush_dcache_line(unsigned long addr)
+static inline void flush_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -76,7 +76,7 @@
"i" (Hit_Writeback_Inv_D));
}
-extern inline void invalidate_dcache_line(unsigned long addr)
+static inline void invalidate_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -89,7 +89,7 @@
"i" (Hit_Invalidate_D));
}
-extern inline void invalidate_scache_line(unsigned long addr)
+static inline void invalidate_scache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -102,7 +102,7 @@
"i" (Hit_Invalidate_SD));
}
-extern inline void flush_scache_line(unsigned long addr)
+static inline void flush_scache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -118,7 +118,7 @@
/*
* The next two are for badland addresses like signal trampolines.
*/
-extern inline void protected_flush_icache_line(unsigned long addr)
+static inline void protected_flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -134,7 +134,7 @@
"i" (Hit_Invalidate_I));
}
-extern inline void protected_writeback_dcache_line(unsigned long addr)
+static inline void protected_writeback_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -176,7 +176,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_dcache16(void)
+static inline void blast_dcache16(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + dcache_size);
@@ -187,7 +187,7 @@
}
}
-extern inline void blast_dcache16_wayLSB(void)
+static inline void blast_dcache16_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz);
@@ -201,7 +201,7 @@
}
}
-extern inline void blast_dcache16_page(unsigned long page)
+static inline void blast_dcache16_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -212,7 +212,7 @@
}
}
-extern inline void blast_dcache16_page_indexed(unsigned long page)
+static inline void blast_dcache16_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -223,7 +223,7 @@
}
}
-extern inline void blast_dcache16_page_indexed_wayLSB(unsigned long page)
+static inline void blast_dcache16_page_indexed_wayLSB(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -237,7 +237,7 @@
}
}
-extern inline void blast_icache16(void)
+static inline void blast_icache16(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size);
@@ -248,7 +248,7 @@
}
}
-extern inline void blast_icache16_wayLSB(void)
+static inline void blast_icache16_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz);
@@ -262,7 +262,7 @@
}
}
-extern inline void blast_icache16_page(unsigned long page)
+static inline void blast_icache16_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -273,7 +273,7 @@
}
}
-extern inline void blast_icache16_page_indexed(unsigned long page)
+static inline void blast_icache16_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -284,7 +284,7 @@
}
}
-extern inline void blast_scache16(void)
+static inline void blast_scache16(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -295,7 +295,7 @@
}
}
-extern inline void blast_scache16_page(unsigned long page)
+static inline void blast_scache16_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -306,7 +306,7 @@
}
}
-extern inline void blast_scache16_page_indexed(unsigned long page)
+static inline void blast_scache16_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -343,7 +343,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_dcache32(void)
+static inline void blast_dcache32(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + dcache_size);
@@ -354,7 +354,7 @@
}
}
-extern inline void blast_dcache32_wayLSB(void)
+static inline void blast_dcache32_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.dcache.sets * mips_cpu.dcache.linesz);
@@ -380,7 +380,7 @@
* (Revision 2.0 device errata from IDT available on http://www.idt.com/
* in .pdf format.)
*/
-extern inline void blast_dcache32_page(unsigned long page)
+static inline void blast_dcache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -397,7 +397,7 @@
}
}
-extern inline void blast_dcache32_page_indexed(unsigned long page)
+static inline void blast_dcache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -408,7 +408,7 @@
}
}
-extern inline void blast_dcache32_page_indexed_wayLSB(unsigned long page)
+static inline void blast_dcache32_page_indexed_wayLSB(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -422,7 +422,7 @@
}
}
-extern inline void blast_icache32(void)
+static inline void blast_icache32(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size);
@@ -433,7 +433,7 @@
}
}
-extern inline void blast_icache32_wayLSB(void)
+static inline void blast_icache32_wayLSB(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + mips_cpu.icache.sets * mips_cpu.icache.linesz);
@@ -447,7 +447,7 @@
}
}
-extern inline void blast_icache32_page(unsigned long page)
+static inline void blast_icache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -458,7 +458,7 @@
}
}
-extern inline void blast_icache32_page_indexed(unsigned long page)
+static inline void blast_icache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -469,7 +469,7 @@
}
}
-extern inline void blast_scache32(void)
+static inline void blast_scache32(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -480,7 +480,7 @@
}
}
-extern inline void blast_scache32_page(unsigned long page)
+static inline void blast_scache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -491,7 +491,7 @@
}
}
-extern inline void blast_scache32_page_indexed(unsigned long page)
+static inline void blast_scache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -528,7 +528,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_scache64(void)
+static inline void blast_scache64(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -539,7 +539,7 @@
}
}
-extern inline void blast_scache64_page(unsigned long page)
+static inline void blast_scache64_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -550,7 +550,7 @@
}
}
-extern inline void blast_scache64_page_indexed(unsigned long page)
+static inline void blast_scache64_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = page + PAGE_SIZE;
@@ -587,7 +587,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_scache128(void)
+static inline void blast_scache128(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + scache_size;
@@ -598,12 +598,12 @@
}
}
-extern inline void blast_scache128_page(unsigned long page)
+static inline void blast_scache128_page(unsigned long page)
{
cache128_unroll32(page,Hit_Writeback_Inv_SD);
}
-extern inline void blast_scache128_page_indexed(unsigned long page)
+static inline void blast_scache128_page_indexed(unsigned long page)
{
cache128_unroll32(page,Index_Writeback_Inv_SD);
}
Index: softirq.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/softirq.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- softirq.h 2001/10/19 21:19:40 1.3
+++ softirq.h 2001/10/31 18:26:52 1.4
@@ -13,13 +13,13 @@
#include <asm/atomic.h>
#include <asm/hardirq.h>
-extern inline void cpu_bh_disable(int cpu)
+static inline void cpu_bh_disable(int cpu)
{
local_bh_count(cpu)++;
barrier();
}
-extern inline void __cpu_bh_enable(int cpu)
+static inline void __cpu_bh_enable(int cpu)
{
barrier();
local_bh_count(cpu)--;
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:26:55
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/dec
In directory usw-pr-cvs1:/tmp/cvs-serv9038/include/asm-mips/dec
Modified Files:
ioasic.h
Log Message:
Replace all incarnations of extern inline with static inline.
Index: ioasic.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/dec/ioasic.h,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- ioasic.h 2001/06/22 02:29:33 1.1.1.1
+++ ioasic.h 2001/10/31 18:26:52 1.2
@@ -11,12 +11,12 @@
extern volatile unsigned int *ioasic_base;
-extern inline void ioasic_write(unsigned int reg, unsigned int v)
+static inline void ioasic_write(unsigned int reg, unsigned int v)
{
ioasic_base[reg / 4] = v;
}
-extern inline unsigned int ioasic_read(unsigned int reg)
+static inline unsigned int ioasic_read(unsigned int reg)
{
return ioasic_base[reg / 4];
}
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:26:55
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv9038/include/asm-mips/cobalt
Modified Files:
cobalt.h
Log Message:
Replace all incarnations of extern inline with static inline.
Index: cobalt.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cobalt/cobalt.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- cobalt.h 2001/07/10 03:16:40 1.1
+++ cobalt.h 2001/10/31 18:26:52 1.2
@@ -72,7 +72,7 @@
*/
#ifndef _LANGUAGE_ASSEMBLY
-extern inline void r4030_delay(void)
+static inline void r4030_delay(void)
{
__asm__ __volatile__(
".set\tnoreorder\n\t"
@@ -83,27 +83,27 @@
".set\treorder");
}
-extern inline unsigned short r4030_read_reg16(unsigned addr)
+static inline unsigned short r4030_read_reg16(unsigned addr)
{
unsigned short ret = *((volatile unsigned short *)addr);
r4030_delay();
return ret;
}
-extern inline unsigned int r4030_read_reg32(unsigned addr)
+static inline unsigned int r4030_read_reg32(unsigned addr)
{
unsigned int ret = *((volatile unsigned int *)addr);
r4030_delay();
return ret;
}
-extern inline void r4030_write_reg16(unsigned addr, unsigned val)
+static inline void r4030_write_reg16(unsigned addr, unsigned val)
{
*((volatile unsigned short *)addr) = val;
r4030_delay();
}
-extern inline void r4030_write_reg32(unsigned addr, unsigned val)
+static inline void r4030_write_reg32(unsigned addr, unsigned val)
{
*((volatile unsigned int *)addr) = val;
r4030_delay();
|
|
From: James S. <jsi...@us...> - 2001-10-31 18:26:55
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv9038/arch/mips/mm
Modified Files:
c-r5432.c
Log Message:
Replace all incarnations of extern inline with static inline.
Index: c-r5432.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r5432.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- c-r5432.c 2001/10/23 17:20:14 1.1
+++ c-r5432.c 2001/10/31 18:26:52 1.2
@@ -42,7 +42,7 @@
/* -------------------------------------------------------------------- */
/* #include <asm/r4kcache.h> */
-extern inline void flush_icache_line_indexed(unsigned long addr)
+static inline void flush_icache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -56,7 +56,7 @@
"i" (Index_Invalidate_I));
}
-extern inline void flush_dcache_line_indexed(unsigned long addr)
+static inline void flush_dcache_line_indexed(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -70,7 +70,7 @@
"i" (Index_Writeback_Inv_D));
}
-extern inline void flush_icache_line(unsigned long addr)
+static inline void flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -83,7 +83,7 @@
"i" (Hit_Invalidate_I));
}
-extern inline void flush_dcache_line(unsigned long addr)
+static inline void flush_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -96,7 +96,7 @@
"i" (Hit_Writeback_Inv_D));
}
-extern inline void invalidate_dcache_line(unsigned long addr)
+static inline void invalidate_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -113,7 +113,7 @@
/*
* The next two are for badland addresses like signal trampolines.
*/
-extern inline void protected_flush_icache_line(unsigned long addr)
+static inline void protected_flush_icache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -129,7 +129,7 @@
"i" (Hit_Invalidate_I));
}
-extern inline void protected_writeback_dcache_line(unsigned long addr)
+static inline void protected_writeback_dcache_line(unsigned long addr)
{
__asm__ __volatile__(
".set noreorder\n\t"
@@ -172,7 +172,7 @@
: "r" (base), \
"i" (op));
-extern inline void blast_dcache32(void)
+static inline void blast_dcache32(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + dcache_size/2);
@@ -184,7 +184,7 @@
}
}
-extern inline void blast_dcache32_page(unsigned long page)
+static inline void blast_dcache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -195,7 +195,7 @@
}
}
-extern inline void blast_dcache32_page_indexed(unsigned long page)
+static inline void blast_dcache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -207,7 +207,7 @@
}
}
-extern inline void blast_icache32(void)
+static inline void blast_icache32(void)
{
unsigned long start = KSEG0;
unsigned long end = (start + icache_size/2);
@@ -219,7 +219,7 @@
}
}
-extern inline void blast_icache32_page(unsigned long page)
+static inline void blast_icache32_page(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
@@ -230,7 +230,7 @@
}
}
-extern inline void blast_icache32_page_indexed(unsigned long page)
+static inline void blast_icache32_page_indexed(unsigned long page)
{
unsigned long start = page;
unsigned long end = (start + PAGE_SIZE);
|
|
From: James S. <jsi...@us...> - 2001-10-31 17:28:58
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv24711/arch/mips/kernel
Modified Files:
process.c signal.c
Added Files:
ptrace.c
Log Message:
Don't set CU1 bit if we don't have an FPU. Some b0rken silicon doesn't like it at all.
Index: process.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/process.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- process.c 2001/10/19 21:19:38 1.4
+++ process.c 2001/10/31 17:28:54 1.5
@@ -56,8 +56,8 @@
void exit_thread(void)
{
/* Forget lazy fpu state */
- if (last_task_used_math == current) {
- set_cp0_status(ST0_CU1);
+ if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
+ __enable_fpu();
__asm__ __volatile__("cfc1\t$0,$31");
last_task_used_math = NULL;
}
@@ -66,8 +66,8 @@
void flush_thread(void)
{
/* Forget lazy fpu state */
- if (last_task_used_math == current) {
- set_cp0_status(ST0_CU1);
+ if (last_task_used_math == current && mips_cpu.options & MIPS_CPU_FPU) {
+ __enable_fpu();
__asm__ __volatile__("cfc1\t$0,$31");
last_task_used_math = NULL;
}
@@ -85,7 +85,7 @@
if (last_task_used_math == current)
if (mips_cpu.options & MIPS_CPU_FPU) {
- set_cp0_status(ST0_CU1);
+ __enable_fpu();
save_fp(p);
}
/* set up new TSS. */
Index: signal.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/signal.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- signal.c 2001/10/19 21:19:38 1.2
+++ signal.c 2001/10/31 17:28:54 1.3
@@ -22,6 +22,7 @@
#include <asm/asm.h>
#include <asm/bitops.h>
+#include <asm/cpu.h>
#include <asm/pgalloc.h>
#include <asm/stackframe.h>
#include <asm/uaccess.h>
@@ -355,7 +356,7 @@
err |= __put_user(owned_fp, &sc->sc_ownedfp);
if (current->used_math) { /* fp is active. */
- set_cp0_status(ST0_CU1);
+ enable_fpu();
err |= save_fp_context(sc);
last_task_used_math = NULL;
regs->cp0_status &= ~ST0_CU1;
|
|
From: James S. <jsi...@us...> - 2001-10-31 17:28:57
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv24711/include/asm-mips
Modified Files:
bootinfo.h cpu.h mipsregs.h pgtable.h
Log Message:
Don't set CU1 bit if we don't have an FPU. Some b0rken silicon doesn't like it at all.
Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- bootinfo.h 2001/10/28 23:04:19 1.10
+++ bootinfo.h 2001/10/31 17:28:54 1.11
@@ -310,7 +310,6 @@
* values in setup.c (or whereever suitable) so they are in
* .data section
*/
-extern struct mips_cpu mips_cpu;
extern unsigned long mips_machtype;
extern unsigned long mips_machgroup;
extern unsigned long mips_tlb_entries;
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- cpu.h 2001/10/26 16:09:07 1.11
+++ cpu.h 2001/10/31 17:28:54 1.12
@@ -55,12 +55,12 @@
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
#define PRID_IMP_R5000 0x2300
+#define PRID_IMP_TX49 0x2d00
+#define PRID_IMP_R5900 0x2e00
#define PRID_IMP_SONIC 0x2400
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
-#define PRID_IMP_TX49 0x2d00
-#define PRID_IMP_R5900 0x2e00
#define PRID_IMP_R5432 0x5400
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_4KC 0x8000
@@ -89,8 +89,8 @@
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
#define PRID_REV_TX3927 0x0040
-#define PRID_REV_TX3927B 0x0041
-#define PRID_REV_TX39H3TEG 0x0050
+#define PRID_REV_TX3927B 0x0041
+#define PRID_REV_TX39H3TEG 0x0050
#define PRID_REV_TX4955 0x0011
#define PRID_REV_TX4955A 0x0020
#define PRID_REV_TX4927 0x0021
@@ -111,6 +111,8 @@
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
};
+
+extern struct mips_cpu mips_cpu;
#endif
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- mipsregs.h 2001/10/27 17:28:55 1.9
+++ mipsregs.h 2001/10/31 17:28:54 1.10
@@ -148,12 +148,15 @@
*/
#include <linux/config.h>
#ifdef CONFIG_CPU_VR41XX
+
#define PM_1K 0x00000000
#define PM_4K 0x00001800
#define PM_16K 0x00007800
#define PM_64K 0x0001f800
#define PM_256K 0x0007f800
+
#else
+
#define PM_4K 0x00000000
#define PM_16K 0x00006000
#define PM_64K 0x0001e000
@@ -161,6 +164,7 @@
#define PM_1M 0x001fe000
#define PM_4M 0x007fe000
#define PM_16M 0x01ffe000
+
#endif
/*
@@ -175,75 +179,6 @@
#define PL_16M 24
/*
- * Macros to access the system control coprocessor
- */
-#define read_32bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "mfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-
-#define read_32bit_cp0_set1_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- "cfc0\t%0,"STR(source)"\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-
-/*
- * For now use this only with interrupts disabled!
- */
-#define read_64bit_cp0_register(source) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmfc0\t%0,"STR(source)"\n\t" \
- ".set\tmips0" \
- : "=r" (__res)); \
- __res;})
-
-#define write_32bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- "mtc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
-
-#define write_32bit_cp0_set1_register(register,value) \
- __asm__ __volatile__( \
- "ctc0\t%0,"STR(register)"\n\t" \
- "nop" \
- : : "r" (value));
-
-#define write_64bit_cp0_register(register,value) \
- __asm__ __volatile__( \
- ".set\tmips3\n\t" \
- "dmtc0\t%0,"STR(register)"\n\t" \
- ".set\tmips0" \
- : : "r" (value))
-
-/*
- * This should be changed when we get a compiler that support the MIPS32 ISA.
- */
-#define read_mips32_cp0_config1() \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tnoreorder\n\t" \
- ".set\tnoat\n\t" \
- ".word\t0x40018001\n\t" \
- "move\t%0,$1\n\t" \
- ".set\tat\n\t" \
- ".set\treorder" \
- :"=r" (__res)); \
- __res;})
-
-/*
* R4x00 interrupt enable / cause bits
*/
#define IE_SW0 (1<< 8)
@@ -267,55 +202,6 @@
#define C_IRQ4 (1<<14)
#define C_IRQ5 (1<<15)
-#ifndef _LANGUAGE_ASSEMBLY
-/*
- * Manipulate the status register.
- * Mostly used to access the interrupt bits.
- */
-#define __BUILD_SET_CP0(name,register) \
-extern inline unsigned int \
-set_cp0_##name(unsigned int set) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res |= set; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern inline unsigned int \
-clear_cp0_##name(unsigned int clear) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~clear; \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-} \
- \
-extern inline unsigned int \
-change_cp0_##name(unsigned int change, unsigned int new) \
-{ \
- unsigned int res; \
- \
- res = read_32bit_cp0_register(register); \
- res &= ~change; \
- res |= (new & change); \
- write_32bit_cp0_register(register, res); \
- \
- return res; \
-}
-
-__BUILD_SET_CP0(status,CP0_STATUS)
-__BUILD_SET_CP0(cause,CP0_CAUSE)
-__BUILD_SET_CP0(config,CP0_CONFIG)
-
-#endif /* defined (_LANGUAGE_ASSEMBLY) */
-
/*
* Bitfields in the R4xx0 cp0 status register
*/
@@ -547,5 +433,440 @@
#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/*
+ * Macros to access the system control coprocessor
+ */
+#define read_32bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "mfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+#define read_32bit_cp0_set1_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ "cfc0\t%0,"STR(source)"\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+/*
+ * For now use this only with interrupts disabled!
+ */
+#define read_64bit_cp0_register(source) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmfc0\t%0,"STR(source)"\n\t" \
+ ".set\tmips0" \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_32bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ "mtc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_32bit_cp0_set1_register(register,value) \
+ __asm__ __volatile__( \
+ "ctc0\t%0,"STR(register)"\n\t" \
+ "nop" \
+ : : "r" (value));
+
+#define write_64bit_cp0_register(register,value) \
+ __asm__ __volatile__( \
+ ".set\tmips3\n\t" \
+ "dmtc0\t%0,"STR(register)"\n\t" \
+ ".set\tmips0" \
+ : : "r" (value))
+
+/*
+ * This should be changed when we get a compiler that support the MIPS32 ISA.
+ */
+#define read_mips32_cp0_config1() \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tnoreorder\n\t" \
+ ".set\tnoat\n\t" \
+ ".word\t0x40018001\n\t" \
+ "move\t%0,$1\n\t" \
+ ".set\tat\n\t" \
+ ".set\treorder" \
+ :"=r" (__res)); \
+ __res;})
+
+/* TLB operations. */
+static inline void tlb_probe(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbp\n\t"
+ ".set pop");
+}
+
+static inline void tlb_read(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbr\n\t"
+ ".set pop");
+}
+
+static inline void tlb_write_indexed(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbwi\n\t"
+ ".set pop");
+}
+
+static inline void tlb_write_random(void)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "tlbwr\n\t"
+ ".set pop");
+}
+
+/* Dealing with various CP0 mmu/cache related registers. */
+
+
+static inline unsigned long get_pagemask(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $5\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_pagemask(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $5\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
+static inline unsigned long get_entrylo0(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $2\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_entrylo0(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $2\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo1(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $3\n\t"
+ ".set pop" : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entrylo1(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $3\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_ENTRYHI register */
+static inline unsigned long get_entryhi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $10\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_entryhi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $10\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_INDEX register */
+static inline unsigned long get_index(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $0\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_index(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $0\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_WIRED register */
+static inline unsigned long get_wired(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $6\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_wired(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $6\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_STATUS register */
+static inline unsigned int get_status(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $12\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_status(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $12\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_info(void)
+{
+ unsigned long val;
+
+ __asm__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $7\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+/* CP0_TAGLO and CP0_TAGHI registers */
+static inline unsigned long get_taglo(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $28\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taglo(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $28\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_taghi(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $29\n\t"
+ ".set pop"
+ : "=r" (val));
+ return val;
+}
+
+static inline void set_taghi(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $29\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/* CP0_CONTEXT register */
+static inline unsigned long get_context(void)
+{
+ unsigned long val;
+
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mfc0 %0, $4\n\t"
+ ".set pop"
+ : "=r" (val));
+
+ return val;
+}
+
+static inline void set_context(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $4\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+/*
+ * Manipulate the status register.
+ * Mostly used to access the interrupt bits.
+ */
+#define __BUILD_SET_CP0(name,register) \
+static inline unsigned int \
+set_cp0_##name(unsigned int set) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res |= set; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+clear_cp0_##name(unsigned int clear) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~clear; \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+} \
+ \
+static inline unsigned int \
+change_cp0_##name(unsigned int change, unsigned int new) \
+{ \
+ unsigned int res; \
+ \
+ res = read_32bit_cp0_register(register); \
+ res &= ~change; \
+ res |= (new & change); \
+ write_32bit_cp0_register(register, res); \
+ \
+ return res; \
+}
+
+__BUILD_SET_CP0(status,CP0_STATUS)
+__BUILD_SET_CP0(cause,CP0_CAUSE)
+__BUILD_SET_CP0(config,CP0_CONFIG)
+
+#define __enable_fpu() \
+do { \
+ set_cp0_status(ST0_CU1); \
+ asm("nop;nop;nop;nop"); /* max. hazard */ \
+} while (0)
+
+#define __disable_fpu() \
+do { \
+ clear_cp0_status(ST0_CU1); \
+ /* We don't care about the cp0 hazard here */ \
+} while (0)
+
+#define enable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __enable_fpu(); \
+} while (0)
+
+#define disable_fpu() \
+do { \
+ if (mips_cpu.options & MIPS_CPU_FPU) \
+ __disable_fpu(); \
+} while (0)
+
+#endif /* !defined (_LANGUAGE_ASSEMBLY) */
#endif /* _ASM_MIPSREGS_H */
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pgtable.h 2001/10/24 23:32:54 1.6
+++ pgtable.h 2001/10/31 17:28:54 1.7
@@ -261,29 +261,29 @@
* Conversion functions: convert a page and protection to a page entry,
* and a page entry and page directory to the page they refer to.
*/
-extern inline unsigned long pmd_page(pmd_t pmd)
+static inline unsigned long pmd_page(pmd_t pmd)
{
return pmd_val(pmd);
}
-extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
+static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
{
pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
}
-extern inline int pte_none(pte_t pte) { return !pte_val(pte); }
-extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
+static inline int pte_none(pte_t pte) { return !pte_val(pte); }
+static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
/* Certain architectures need to do special things when pte's
* within a page table are directly modified. Thus, the following
* hook is made available.
*/
-extern inline void set_pte(pte_t *ptep, pte_t pteval)
+static inline void set_pte(pte_t *ptep, pte_t pteval)
{
*ptep = pteval;
}
-extern inline void pte_clear(pte_t *ptep)
+static inline void pte_clear(pte_t *ptep)
{
set_pte(ptep, __pte(0));
}
@@ -298,23 +298,23 @@
/*
* Empty pgd/pmd entries point to the invalid_pte_table.
*/
-extern inline int pmd_none(pmd_t pmd)
+static inline int pmd_none(pmd_t pmd)
{
return pmd_val(pmd) == (unsigned long) invalid_pte_table;
}
-extern inline int pmd_bad(pmd_t pmd)
+static inline int pmd_bad(pmd_t pmd)
{
return ((pmd_page(pmd) > (unsigned long) high_memory) ||
(pmd_page(pmd) < PAGE_OFFSET));
}
-extern inline int pmd_present(pmd_t pmd)
+static inline int pmd_present(pmd_t pmd)
{
return (pmd_val(pmd) != (unsigned long) invalid_pte_table);
}
-extern inline void pmd_clear(pmd_t *pmdp)
+static inline void pmd_clear(pmd_t *pmdp)
{
pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
}
@@ -324,10 +324,10 @@
* setup: the pgd is never bad, and a pmd always exists (as it's folded
* into the pgd entry)
*/
-extern inline int pgd_none(pgd_t pgd) { return 0; }
-extern inline int pgd_bad(pgd_t pgd) { return 0; }
-extern inline int pgd_present(pgd_t pgd) { return 1; }
-extern inline void pgd_clear(pgd_t *pgdp) { }
+static inline int pgd_none(pgd_t pgd) { return 0; }
+static inline int pgd_bad(pgd_t pgd) { return 0; }
+static inline int pgd_present(pgd_t pgd) { return 1; }
+static inline void pgd_clear(pgd_t *pgdp) { }
/*
* Permanent address of a page. On MIPS we never have highmem, so this
@@ -344,36 +344,36 @@
* The following only work if pte_present() is true.
* Undefined behaviour if not..
*/
-extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
-extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
-extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
-extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
-extern inline pte_t pte_wrprotect(pte_t pte)
+static inline pte_t pte_wrprotect(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
return pte;
}
-extern inline pte_t pte_rdprotect(pte_t pte)
+static inline pte_t pte_rdprotect(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
return pte;
}
-extern inline pte_t pte_mkclean(pte_t pte)
+static inline pte_t pte_mkclean(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
return pte;
}
-extern inline pte_t pte_mkold(pte_t pte)
+static inline pte_t pte_mkold(pte_t pte)
{
pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
return pte;
}
-extern inline pte_t pte_mkwrite(pte_t pte)
+static inline pte_t pte_mkwrite(pte_t pte)
{
pte_val(pte) |= _PAGE_WRITE;
if (pte_val(pte) & _PAGE_MODIFIED)
@@ -381,7 +381,7 @@
return pte;
}
-extern inline pte_t pte_mkread(pte_t pte)
+static inline pte_t pte_mkread(pte_t pte)
{
pte_val(pte) |= _PAGE_READ;
if (pte_val(pte) & _PAGE_ACCESSED)
@@ -389,7 +389,7 @@
return pte;
}
-extern inline pte_t pte_mkdirty(pte_t pte)
+static inline pte_t pte_mkdirty(pte_t pte)
{
pte_val(pte) |= _PAGE_MODIFIED;
if (pte_val(pte) & _PAGE_WRITE)
@@ -414,7 +414,7 @@
return __pgprot(prot);
}
-extern inline pte_t pte_mkyoung(pte_t pte)
+static inline pte_t pte_mkyoung(pte_t pte)
{
pte_val(pte) |= _PAGE_ACCESSED;
if (pte_val(pte) & _PAGE_READ)
@@ -448,7 +448,7 @@
})
#endif
-extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
+static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
{
#ifdef CONFIG_CPU_VR41XX
return __pte((physpage << 2) | pgprot_val(pgprot));
@@ -457,7 +457,7 @@
#endif
}
-extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
}
@@ -470,19 +470,19 @@
#define pgd_index(address) ((address) >> PGDIR_SHIFT)
/* to find an entry in a page-table-directory */
-extern inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
+static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
{
return mm->pgd + pgd_index(address);
}
/* Find an entry in the second-level page table.. */
-extern inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
+static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
{
return (pmd_t *) dir;
}
/* Find an entry in the third-level page table.. */
-extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
+static inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
{
return (pte_t *) (pmd_page(*dir)) +
((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
@@ -506,274 +506,6 @@
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
#define PageSkip(page) (0)
#define kern_addr_valid(addr) (1)
-
-/* TLB operations. */
-extern inline void tlb_probe(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbp\n\t"
- ".set pop");
-}
-
-extern inline void tlb_read(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbr\n\t"
- ".set pop");
-}
-
-extern inline void tlb_write_indexed(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbwi\n\t"
- ".set pop");
-}
-
-extern inline void tlb_write_random(void)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "tlbwr\n\t"
- ".set pop");
-}
-
-/* Dealing with various CP0 mmu/cache related registers. */
-
-/* CP0_PAGEMASK register */
-extern inline unsigned long get_pagemask(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $5\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_pagemask(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $5\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-extern inline unsigned long get_entrylo0(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $2\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_entrylo0(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $2\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_entrylo1(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $3\n\t"
- ".set pop" : "=r" (val));
-
- return val;
-}
-
-extern inline void set_entrylo1(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $3\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_ENTRYHI register */
-extern inline unsigned long get_entryhi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $10\n\t"
- ".set pop"
- : "=r" (val));
-
- return val;
-}
-
-extern inline void set_entryhi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $10\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_INDEX register */
-extern inline unsigned long get_index(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $0\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_index(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $0\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_WIRED register */
-extern inline unsigned long get_wired(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $6\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_wired(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $6\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_info(void)
-{
- unsigned long val;
-
- __asm__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $7\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-/* CP0_TAGLO and CP0_TAGHI registers */
-extern inline unsigned long get_taglo(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $28\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_taglo(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $28\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-extern inline unsigned long get_taghi(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $29\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
-extern inline void set_taghi(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $29\n\t"
- ".set pop"
- : : "Jr" (val));
-}
-
-/* CP0_CONTEXT register */
-extern inline unsigned long get_context(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $4\n\t"
- ".set pop"
- : "=r" (val));
-
- return val;
-}
-
-extern inline void set_context(unsigned long val)
-{
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mtc0 %z0, $4\n\t"
- ".set pop"
- : : "Jr" (val));
-}
#include <asm-generic/pgtable.h>
|
|
From: James S. <jsi...@us...> - 2001-10-31 17:28:57
|
Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv24711/arch/mips64/kernel
Modified Files:
process.c
Added Files:
ptrace.c
Log Message:
Don't set CU1 bit if we don't have an FPU. Some b0rken silicon doesn't like it at all.
Index: process.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/process.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- process.c 2001/10/27 17:28:54 1.3
+++ process.c 2001/10/31 17:28:54 1.4
@@ -53,7 +53,7 @@
{
/* Forget lazy fpu state */
if (IS_FPU_OWNER()) {
- set_cp0_status(ST0_CU1);
+ __enable_fpu();
__asm__ __volatile__("cfc1\t$0,$31");
CLEAR_FPU_OWNER();
}
@@ -63,7 +63,7 @@
{
/* Forget lazy fpu state */
if (IS_FPU_OWNER()) {
- set_cp0_status(ST0_CU1);
+ __enable_fpu();
__asm__ __volatile__("cfc1\t$0,$31");
CLEAR_FPU_OWNER();
}
@@ -123,10 +123,11 @@
/* We actually store the FPU info in the task->thread
* area.
*/
- if(regs->cp0_status & ST0_CU1) {
+ if (regs->cp0_status & ST0_CU1) {
memcpy(r, ¤t->thread.fpu, sizeof(current->thread.fpu));
return 1;
}
+
return 0; /* Task didn't use the fpu at all. */
}
|
|
From: Pete P. <pp...@us...> - 2001-10-31 06:17:39
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv20790/arch/mips/kernel Modified Files: head.S Log Message: Removed AU1000 ifdefs, which are now in tlbex-r4k.S. Index: head.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/head.S,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- head.S 2001/10/22 19:16:44 1.9 +++ head.S 2001/10/31 06:17:36 1.10 @@ -165,144 +165,14 @@ END(smp_bootstrap) #endif -#ifdef CONFIG_MIPS_AU1000 -/* - * On entry k0 contains the pte with the pseudo address. - * On exit, k0 contains the "real" address, which is a - * 36 bit physicall address. - * This function is called only after it has been - * determined that the pte is a pseudo physical address. - * - * Destroys k0, k1, and at. It's assumed that the calling - * function will preserve those. - */ -LEAF(get_real_pte) - .set mips3 - - li k1, 0xe0000000 # check lcd - bltu k0, k1, check_pcmcia_socket_1 - nop - # lcd pseudo access - li k1, 0x0fffffff - and k0, k0, k1 # get offset - srl k0, k0, 6 - lui k1, 0xe000>>2 - or k0, k0, k1 - j ra - nop -check_pcmcia_socket_1: - li k1, 0xD0000000 - bltu k0, k1, pcmcia_socket_0 - nop - # famous last words, should not happen ... -1: - b 1b # fixme -- to something a little more useful - # pcmcia socket 1 pseudo access - -pcmcia_socket_0: - # check mem access - li k1, 0xC8000000 - bltu k0, k1, check_attr - # handle pseudo memory access - li k1, 0x00ffffff - and k1, k0, k1 # get access offset - lui k0, 0x8000 - or k0, k0, k1 - # now we have the correct even pte ... bits 31:0 - srl k0, k0, 6 - lui k1, 0xf000>>2 - or k0, k0, k1 - j ra # done - nop -check_attr: - li k1, 0xC4000000 - bltu k0, k1, io_access - # handle pseudo attribute access - li k1, 0x00ffffff - and k1, k0, k1 # get access offset - lui k0, 0x4000 - or k0, k0, k1 - # now we have the correct even pte ... bits 31:0 - srl k0, k0, 6 - lui k1, 0xf000>>2 - or k0, k0, k1 - j ra # done - nop -io_access: - # handle pseudo io access - li k1, 0x00ffffff - and k0, k0, k1 # get access offset - # now we have the correct even pte ... bits 31:0 - srl k0, k0, 6 - lui k1, 0xf000>>2 - or k0, k0, k1 - j ra # done - nop -END(get_real_pte) /* - * On entry k1 contains pte pointer. Clobbers only k0 and k1. - */ - LEAF(translate_pte) - .set mips3 - lui k0, %hi(__saved_at) - sw $at, %lo(__saved_at)(k0) # save at - sw k1, %lo(__saved_pte)(k0) # save pte pointer - sw ra, %lo(__saved_ra)(k0) # save ra - lw k0, 0(k1) # get even pte - - li k1, 0xC0000000 # check pseudo addr - bltu k0, k1, 1f - nop - bal get_real_pte - nop - b 2f - nop -1: - srl k0, k0, 6 -2: - mtc0 k0, CP0_ENTRYLO0 # load it - - lui k1, %hi(__saved_pte) - lw k1, %lo(__saved_pte)(k1) # recover pte pointer - lw k0, 4(k1) # get odd pte - - li k1, 0xC0000000 # check pseudo addr - bltu k0, k1, 1f - nop - bal get_real_pte - nop - b 2f - nop - -1: - srl k0, k0, 6 # convert to entrylo0 -2: - mtc0 k0, CP0_ENTRYLO1 # load it - nop - b 1f - tlbwr # write random tlb entry -1: - lui k0, %hi(__saved_at) - lw $at, %lo(__saved_at)(k0) # restore at - lw ra, %lo(__saved_ra)(k0) # restore ra - eret # return from trap - END(translate_pte) -#endif - - -/* * This buffer is reserved for the use of the cache error handler. */ .data EXPORT(cache_error_buffer) .fill 32*4,1,0 -#ifdef CONFIG_MIPS_AU1000 -__saved_at: PTR 0 -__saved_pte: PTR 0 -__saved_ra: PTR 0 -#endif __FINIT .comm kernelsp, NR_CPUS * 8, 8 |
|
From: Pete P. <pp...@us...> - 2001-10-31 06:16:27
|
Update of /cvsroot/linux-mips/linux/arch/mips/au1000/common
In directory usw-pr-cvs1:/tmp/cvs-serv20100/arch/mips/au1000/common
Modified Files:
irq.c
Log Message:
Sync up with oss tree:
* explicitly set polarity of all interrupts
* added pci_auto config option
* updated defconfig file
* moved the au1000 specific tlb handler to tlbex-r4k.S
* updated au1000.h with IrDA registers
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/au1000/common/irq.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- irq.c 2001/10/03 22:49:23 1.8
+++ irq.c 2001/10/31 06:16:24 1.9
@@ -388,12 +388,14 @@
for (i = 0; i <= NR_IRQS; i++) {
switch (i) {
- case AU1000_GPIO_15:
- setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
- irq_desc[i].handler = &level_irq_type;
- break;
- case AU1000_MAC0_DMA_INT:
- case AU1000_MAC1_DMA_INT:
+ case AU1000_UART0_INT:
+ case AU1000_UART1_INT:
+ case AU1000_UART2_INT:
+ case AU1000_UART3_INT:
+
+ case AU1000_SSI0_INT:
+ case AU1000_SSI1_INT:
+
case AU1000_DMA_INT_BASE:
case AU1000_DMA_INT_BASE+1:
case AU1000_DMA_INT_BASE+2:
@@ -402,22 +404,40 @@
case AU1000_DMA_INT_BASE+5:
case AU1000_DMA_INT_BASE+6:
case AU1000_DMA_INT_BASE+7:
+
+ case AU1000_IRDA_TX_INT:
+ case AU1000_IRDA_RX_INT:
+
+ case AU1000_MAC0_DMA_INT:
+ case AU1000_MAC1_DMA_INT:
setup_local_irq(i, INTC_INT_HIGH_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
+
+ case AU1000_GPIO_15:
case AU1000_USB_HOST_INT:
setup_local_irq(i, INTC_INT_LOW_LEVEL, 0);
irq_desc[i].handler = &level_irq_type;
break;
+ case AU1000_ACSYNC_INT:
+ case AU1000_AC97C_INT:
case AU1000_USB_DEV_REQ_INT:
case AU1000_USB_DEV_SUS_INT:
+ case AU1000_PC0_INT:
+ case AU1000_PC0_MATCH0_INT:
+ case AU1000_PC0_MATCH1_INT:
+ case AU1000_PC1_INT:
+ case AU1000_PC1_MATCH0_INT:
+ case AU1000_PC1_MATCH1_INT:
+ case AU1000_PC1_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 0);
irq_desc[i].handler = &rise_edge_irq_type;
break;
+
// Careful if you change match 2 request!
// The interrupt handler is called directly
// from the low level dispatch code.
- case AU1000_PC0_MATCH2_INT:
+ case AU1000_PC0_MATCH2_INT:
setup_local_irq(i, INTC_INT_RISE_EDGE, 1);
irq_desc[i].handler = &rise_edge_irq_type;
break;
|
|
From: Pete P. <pp...@us...> - 2001-10-31 06:16:27
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv20100/arch/mips/configs Modified Files: defconfig-pb1000 Log Message: Sync up with oss tree: * explicitly set polarity of all interrupts * added pci_auto config option * updated defconfig file * moved the au1000 specific tlb handler to tlbex-r4k.S * updated au1000.h with IrDA registers Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig-pb1000 2001/10/26 16:37:55 1.11 +++ defconfig-pb1000 2001/10/31 06:16:24 1.12 @@ -37,6 +37,7 @@ # CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_IVR is not set CONFIG_MIPS_PB1000=y +CONFIG_PCI_AUTO=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set @@ -44,9 +45,9 @@ CONFIG_MIPS_AU1000=y CONFIG_NEW_IRQ=y CONFIG_PCI=y -CONFIG_PC_KEYB=y -CONFIG_PCI_AUTO=y CONFIG_NEW_PCI=y +CONFIG_PC_KEYB=y +MAX_HWIFS=1 # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_I8259 is not set |
|
From: Pete P. <pp...@us...> - 2001-10-31 06:16:27
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv20100/include/asm-mips
Modified Files:
au1000.h pb1000.h
Log Message:
Sync up with oss tree:
* explicitly set polarity of all interrupts
* added pci_auto config option
* updated defconfig file
* moved the au1000 specific tlb handler to tlbex-r4k.S
* updated au1000.h with IrDA registers
Index: au1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/au1000.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- au1000.h 2001/10/22 19:16:45 1.8
+++ au1000.h 2001/10/31 06:16:24 1.9
@@ -608,21 +608,43 @@
#define SSI1_CONTROL 0xB1680100
/* IrDA Controller */
-#define IR_RING_PTR_STATUS 0xB1500000
-#define IR_RING_BASE_ADDR_H 0xB1500004
-#define IR_RING_BASE_ADDR_L 0xB1500008
-#define IR_RING_SIZE 0xB150000C
-#define IR_RING_PROMPT 0xB1500010
-#define IR_RING_ADDR_CMPR 0xB1500014
-#define IR_CONFIG_1 0xB1500020
-#define IR_SIR_FLAGS 0xB1500024
-#define IR_ENABLE 0xB1500028
-#define IR_READ_PHY_CONFIG 0xB150002C
-#define IR_WRITE_PHY_CONFIG 0xB1500030
-#define IR_MAX_PKT_LEN 0xB1500034
-#define IR_RX_BYTE_CNT 0xB1500038
-#define IR_CONFIG_2 0xB150003C
-#define IR_INTERFACE_CONFIG 0xB1500040
+#define IRDA_BASE 0xB0300000
+#define IR_RING_PTR_STATUS (IRDA_BASE+0x00)
+#define IR_RING_BASE_ADDR_H (IRDA_BASE+0x04)
+#define IR_RING_BASE_ADDR_L (IRDA_BASE+0x08)
+#define IR_RING_SIZE (IRDA_BASE+0x0C)
+#define IR_RING_PROMPT (IRDA_BASE+0x10)
+#define IR_RING_ADDR_CMPR (IRDA_BASE+0x14)
+#define IR_INT_CLEAR (IRDA_BASE+0x18)
+#define IR_CONFIG_1 (IRDA_BASE+0x20)
+ #define IR_RX_INVERT_LED (1<<0)
+ #define IR_TX_INVERT_LED (1<<1)
+ #define IR_ST (1<<2)
+ #define IR_SF (1<<3)
+ #define IR_SIR (1<<4)
+ #define IR_MIR (1<<5)
+ #define IR_FIR (1<<6)
+ #define IR_16CRC (1<<7)
+ #define IR_TD (1<<8)
+ #define IR_RX_ALL (1<<9)
+ #define IR_DMA_ENABLE (1<<10)
+ #define IR_RX_ENABLE (1<<11)
+ #define IR_TX_ENABLE (1<<12)
+ #define IR_LOOPBACK (1<<14)
+ #define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
+ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+#define IR_SIR_FLAGS (IRDA_BASE+0x24)
+#define IR_ENABLE (IRDA_BASE+0x28)
+ #define IR_RX_STATUS (1<<9)
+ #define IR_TX_STATUS (1<<10)
+#define IR_READ_PHY_CONFIG (IRDA_BASE+0x2C)
+#define IR_WRITE_PHY_CONFIG (IRDA_BASE+0x30)
+#define IR_MAX_PKT_LEN (IRDA_BASE+0x34)
+#define IR_RX_BYTE_CNT (IRDA_BASE+0x38)
+#define IR_CONFIG_2 (IRDA_BASE+0x3C)
+ #define IR_MODE_INV (1<<0)
+ #define IR_ONE_PIN (1<<1)
+#define IR_INTERFACE_CONFIG (IRDA_BASE+0x40)
/* GPIO */
#define PIN_FUNCTION 0xB190002C
Index: pb1000.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pb1000.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pb1000.h 2001/10/22 19:16:45 1.5
+++ pb1000.h 2001/10/31 06:16:24 1.6
@@ -110,54 +110,54 @@
#define PCI_MEM_START 0x18000000
#define PCI_MEM_END 0x18ffffff
-extern inline u8 au_pci_io_readb(u32 addr)
+static inline u8 au_pci_io_readb(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xff);
}
-extern inline u16 au_pci_io_readw(u32 addr)
+static inline u16 au_pci_io_readw(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
return (readl(PCI_IO_DATA_PORT) & 0xffff);
}
-extern inline u32 au_pci_io_readl(u32 addr)
+static inline u32 au_pci_io_readl(u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff), PCI_BRIDGE_CONFIG);
return readl(PCI_IO_DATA_PORT);
}
-extern inline void au_pci_io_writeb(u8 val, u32 addr)
+static inline void au_pci_io_writeb(u8 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<12), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
-extern inline void au_pci_io_writew(u16 val, u32 addr)
+static inline void au_pci_io_writew(u16 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffcfff) | (1<<13), PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
-extern inline void au_pci_io_writel(u32 val, u32 addr)
+static inline void au_pci_io_writel(u32 val, u32 addr)
{
writel(addr, PCI_IO_ADDR);
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffcfff, PCI_BRIDGE_CONFIG);
writel(val, PCI_IO_DATA_PORT);
}
-extern inline void set_sdram_extbyte(void)
+static inline void set_sdram_extbyte(void)
{
writel(readl(PCI_BRIDGE_CONFIG) & 0xffffff00, PCI_BRIDGE_CONFIG);
}
-extern inline void set_slot_extbyte(void)
+static inline void set_slot_extbyte(void)
{
writel((readl(PCI_BRIDGE_CONFIG) & 0xffffbf00) | 0x18, PCI_BRIDGE_CONFIG);
}
|
|
From: Pete P. <pp...@us...> - 2001-10-31 06:16:27
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv20100/arch/mips/mm Modified Files: tlbex-r4k.S Log Message: Sync up with oss tree: * explicitly set polarity of all interrupts * added pci_auto config option * updated defconfig file * moved the au1000 specific tlb handler to tlbex-r4k.S * updated au1000.h with IrDA registers Index: tlbex-r4k.S =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlbex-r4k.S,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- tlbex-r4k.S 2001/10/22 20:43:28 1.1 +++ tlbex-r4k.S 2001/10/31 06:16:24 1.2 @@ -259,6 +259,29 @@ END(except_vec0_r4k_MP250MHZhwbug) #endif +#ifdef CONFIG_MIPS_AU1000 + /* TLB refill, EXL == 0, Au1000 version */ + /* we'll worry about smp later */ + .set noreorder + .set noat + LEAF(except_vec0_au1000) + .set mips3 + mfc0 k0, CP0_BADVADDR # Get faulting address + srl k0, k0, 22 # get pgd only bits + lw k1, pgd_current # get pgd pointer + sll k0, k0, 2 + addu k1, k1, k0 # add in pgd offset + mfc0 k0, CP0_CONTEXT # get context reg + lw k1, (k1) + srl k0, k0, 1 # get pte offset + and k0, k0, 0xff8 + addu k1, k1, k0 # add in offset + j translate_pte + nop + END(except_vec0_au1000) +#endif + + __FINIT /* @@ -467,3 +490,132 @@ nowrite_mod: DO_FAULT(1) END(handle_mod) + +#ifdef CONFIG_MIPS_AU1000 +/* + * On entry k0 contains the pte with the pseudo address. + * On exit, k0 contains the "real" address, which is a + * 36 bit physicall address. + * This function is called only after it has been + * determined that the pte is a pseudo physical address. + * + * Destroys k0, k1, and at. It's assumed that the calling + * function will preserve those. + */ +LEAF(get_real_pte) + .set mips3 + + li k1, 0xe0000000 # check lcd + bltu k0, k1, check_pcmcia_socket_1 + nop + # lcd pseudo access + li k1, 0x0fffffff + and k0, k0, k1 # get offset + srl k0, k0, 6 + lui k1, 0xe000>>2 + or k0, k0, k1 + j ra + nop +check_pcmcia_socket_1: + li k1, 0xD0000000 + bltu k0, k1, pcmcia_socket_0 + nop + # famous last words, should not happen ... +1: + b 1b # fixme -- to something a little more useful + # pcmcia socket 1 pseudo access + +pcmcia_socket_0: + # check mem access + li k1, 0xC8000000 + bltu k0, k1, check_attr + # handle pseudo memory access + li k1, 0x00ffffff + and k1, k0, k1 # get access offset + lui k0, 0x8000 + or k0, k0, k1 + # now we have the correct even pte ... bits 31:0 + srl k0, k0, 6 + lui k1, 0xf000>>2 + or k0, k0, k1 + j ra # done + nop +check_attr: + li k1, 0xC4000000 + bltu k0, k1, io_access + # handle pseudo attribute access + li k1, 0x00ffffff + and k1, k0, k1 # get access offset + lui k0, 0x4000 + or k0, k0, k1 + # now we have the correct even pte ... bits 31:0 + srl k0, k0, 6 + lui k1, 0xf000>>2 + or k0, k0, k1 + j ra # done + nop +io_access: + # handle pseudo io access + li k1, 0x00ffffff + and k0, k0, k1 # get access offset + # now we have the correct even pte ... bits 31:0 + srl k0, k0, 6 + lui k1, 0xf000>>2 + or k0, k0, k1 + j ra # done + nop +END(get_real_pte) + +/* + * On entry k1 contains pte pointer. Clobbers only k0 and k1. + */ + LEAF(translate_pte) + .set mips3 + lui k0, %hi(__saved_at) + sw $at, %lo(__saved_at)(k0) # save at + sw k1, %lo(__saved_pte)(k0) # save pte pointer + sw ra, %lo(__saved_ra)(k0) # save ra + lw k0, 0(k1) # get even pte + + li k1, 0xC0000000 # check pseudo addr + bltu k0, k1, 1f + nop + bal get_real_pte + nop + b 2f + nop +1: + srl k0, k0, 6 +2: + mtc0 k0, CP0_ENTRYLO0 # load it + + lui k1, %hi(__saved_pte) + lw k1, %lo(__saved_pte)(k1) # recover pte pointer + lw k0, 4(k1) # get odd pte + + li k1, 0xC0000000 # check pseudo addr + bltu k0, k1, 1f + nop + bal get_real_pte + nop + b 2f + nop + +1: + srl k0, k0, 6 # convert to entrylo0 +2: + mtc0 k0, CP0_ENTRYLO1 # load it + nop + b 1f + tlbwr # write random tlb entry +1: + lui k0, %hi(__saved_at) + lw $at, %lo(__saved_at)(k0) # restore at + lw ra, %lo(__saved_ra)(k0) # restore ra + eret # return from trap + END(translate_pte) + +__saved_at: PTR 0 +__saved_pte: PTR 0 +__saved_ra: PTR 0 +#endif |
|
From: Pete P. <pp...@us...> - 2001-10-31 06:16:27
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv20100/arch/mips
Modified Files:
config.in
Log Message:
Sync up with oss tree:
* explicitly set polarity of all interrupts
* added pci_auto config option
* updated defconfig file
* moved the au1000 specific tlb handler to tlbex-r4k.S
* updated au1000.h with IrDA registers
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.44
retrieving revision 1.45
diff -u -d -r1.44 -r1.45
--- config.in 2001/10/30 18:10:40 1.44
+++ config.in 2001/10/31 06:16:23 1.45
@@ -62,6 +62,10 @@
fi
bool 'Support for Globespan IVR board' CONFIG_MIPS_IVR
bool 'Support for Alchemy Semi PB1000 board' CONFIG_MIPS_PB1000
+ if [ "$CONFIG_MIPS_PB1000" = "y" ]; then
+ bool ' Support for PCI AUTO Config' CONFIG_PCI_AUTO
+ fi
+
define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y
define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
@@ -234,9 +238,9 @@
define_bool CONFIG_MIPS_AU1000 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_PCI y
- define_bool CONFIG_PC_KEYB y
- define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_PC_KEYB y
+ define_int MAX_HWIFS 1
fi
if [ "$CONFIG_COBALT_MICRO_SERVER" = "y" ]; then
define_bool COBALT_MICRO_SERVER y
|
|
From: James S. <jsi...@us...> - 2001-10-30 23:26:35
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv9547
Modified Files:
pci_ops.c
Log Message:
Very important bug fixes. Now I have specs for the GT64111. Thanks to Pete for his help.
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/pci_ops.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pci_ops.c 2001/10/30 00:50:06 1.6
+++ pci_ops.c 2001/10/30 23:26:33 1.7
@@ -46,10 +46,10 @@
#define DBG(x...)
#endif
-#define IO_BASE 0x00000000
-#define IO_SIZE 0x1CFFFFFF
-#define MEM_BASE 0x00000000
-#define MEM_SIZE 0x1CFFFFFF
+#define IO_BASE 0x10000000
+#define IO_SIZE 0x11FFFFFF
+#define MEM_BASE 0x12000000
+#define MEM_SIZE 0x13FFFFFF
static struct resource pci_io_resource = {
"pci IO space",
@@ -77,7 +77,7 @@
* to limit the scan.
*/
struct pci_channel mips_pci_channels[] = {
- { &qube_pci_ops, &pci_io_resource, &pci_mem_resource, 0, 0xFF },
+ { &qube_pci_ops, &pci_io_resource, &pci_mem_resource, 1, 0xFF },
{(struct pci_ops *) NULL, (struct resource *) NULL,
(struct resource *) NULL, (int) NULL, (int) NULL}
};
|
|
From: James S. <jsi...@us...> - 2001-10-30 21:43:41
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva
In directory usw-pr-cvs1:/tmp/cvs-serv12226
Modified Files:
irq_cpu.c irq_korva.c setup.c
Log Message:
Moved over to the macros in asm/debug.h
Index: irq_cpu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/irq_cpu.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- irq_cpu.c 2001/08/23 19:13:56 1.1
+++ irq_cpu.c 2001/10/30 21:43:37 1.2
@@ -27,16 +27,16 @@
#include <asm/mipsregs.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
static int mips_cpu_irq_base=-1;
static void
mips_cpu_irq_enable(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+ db_assert(mips_cpu_irq_base != -1);
+ db_assert(irq >= mips_cpu_irq_base);
+ db_assert(irq < mips_cpu_irq_base+8);
clear_cp0_cause( 1 << (irq - mips_cpu_irq_base + 8));
set_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
@@ -45,9 +45,9 @@
static void
mips_cpu_irq_disable(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+ db_assert(mips_cpu_irq_base != -1);
+ db_assert(irq >= mips_cpu_irq_base);
+ db_assert(irq < mips_cpu_irq_base+8);
clear_cp0_status(1 << (irq - mips_cpu_irq_base + 8));
}
@@ -63,9 +63,9 @@
static void
mips_cpu_irq_ack(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+ db_assert(mips_cpu_irq_base != -1);
+ db_assert(irq >= mips_cpu_irq_base);
+ db_assert(irq < mips_cpu_irq_base+8);
/* although we attemp to clear the IP bit in cause reigster, I think
* usually it is cleared by device (irq source)
@@ -79,9 +79,9 @@
static void
mips_cpu_irq_end(unsigned int irq)
{
- MIPS_ASSERT(mips_cpu_irq_base != -1);
- MIPS_ASSERT(irq >= mips_cpu_irq_base);
- MIPS_ASSERT(irq < mips_cpu_irq_base+8);
+ db_assert(mips_cpu_irq_base != -1);
+ db_assert(irq >= mips_cpu_irq_base);
+ db_assert(irq < mips_cpu_irq_base+8);
mips_cpu_irq_enable(irq);
}
Index: irq_korva.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/irq_korva.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq_korva.c 2001/10/30 19:12:37 1.4
+++ irq_korva.c 2001/10/30 21:43:37 1.5
@@ -23,7 +23,7 @@
#include <asm/mipsregs.h>
/* [jsun] sooner or later we should move this debug stuff to MIPS common */
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
#define NUM_KORVA_IRQS 5
@@ -32,9 +32,9 @@
static void
korva_irq_enable(unsigned int irq)
{
- MIPS_ASSERT(korva_irq_base != -1);
- MIPS_ASSERT(irq >= korva_irq_base);
- MIPS_ASSERT(irq < korva_irq_base+NUM_KORVA_IRQS);
+ db_assert(korva_irq_base != -1);
+ db_assert(irq >= korva_irq_base);
+ db_assert(irq < korva_irq_base+NUM_KORVA_IRQS);
irq -= korva_irq_base;
korva_out32(KORVA_S_IMR, korva_in32(KORVA_S_IMR) | (1 << irq) );
@@ -43,9 +43,9 @@
static void
korva_irq_disable(unsigned int irq)
{
- MIPS_ASSERT(korva_irq_base != -1);
- MIPS_ASSERT(irq >= korva_irq_base);
- MIPS_ASSERT(irq < korva_irq_base+NUM_KORVA_IRQS);
+ db_assert(korva_irq_base != -1);
+ db_assert(irq >= korva_irq_base);
+ db_assert(irq < korva_irq_base+NUM_KORVA_IRQS);
irq -= korva_irq_base;
korva_out32(KORVA_S_IMR, korva_in32(KORVA_S_IMR) & ~(1 << irq) );
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/setup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- setup.c 2001/10/17 20:30:09 1.4
+++ setup.c 2001/10/30 21:43:37 1.5
@@ -26,7 +26,7 @@
#include <asm/time.h>
#include <asm/korva.h>
-#include <asm/ddb5xxx/debug.h>
+#include <asm/debug.h>
// #define USE_CPU_TIMER 1 /* are we using cpu counter as timer */
@@ -48,7 +48,7 @@
s.iomem_base = (u8*)(KORVA_BASE_VIRT + KORVA_UARTDLL);
s.iomem_reg_shift = 2;
s.io_type = SERIAL_IO_MEM;
- MIPS_VERIFY(early_serial_setup(&s), == 0);
+ db_verify(early_serial_setup(&s), == 0);
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
@@ -79,7 +79,7 @@
void __init nec_korva_setup(void)
{
- MIPS_DEBUG(printk("nec_korva_setup() starts.\n"));
+ //MIPS_DEBUG(printk("nec_korva_setup() starts.\n"));
#if defined(CONFIG_BLK_DEV_INITRD)
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
|
|
From: James S. <jsi...@us...> - 2001-10-30 21:26:09
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/ddb5xxx In directory usw-pr-cvs1:/tmp/cvs-serv7688 Removed Files: debug.h Log Message: Remove unused file. --- debug.h DELETED --- |
|
From: Jun S. <ju...@us...> - 2001-10-30 19:12:40
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva
In directory usw-pr-cvs1:/tmp/cvs-serv3996
Modified Files:
irq_korva.c
Log Message:
Fix end() so that it will work with probe_irq_on().
Index: irq_korva.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/irq_korva.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq_korva.c 2001/10/10 23:50:48 1.3
+++ irq_korva.c 2001/10/30 19:12:37 1.4
@@ -62,7 +62,12 @@
/* the intr status register is already cleared when we read it */
#define korva_irq_ack korva_irq_disable
-#define korva_irq_end korva_irq_enable
+static void
+korva_irq_end(unsigned int irq)
+{
+ if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ korva_irq_enable(irq);
+}
static hw_irq_controller korva_irq_controller = {
"KORVA_irq",
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From: Paul M. <le...@us...> - 2001-10-30 18:10:42
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv20471
Modified Files:
config.in
Log Message:
Ocelot is already using new time format..
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.43
retrieving revision 1.44
diff -u -d -r1.43 -r1.44
--- config.in 2001/10/30 00:50:59 1.43
+++ config.in 2001/10/30 18:10:40 1.44
@@ -138,7 +138,7 @@
define_bool CONFIG_SYSCLK_100 y
define_bool CONFIG_SWAP_IO_SPACE y
define_bool CONFIG_NEW_IRQ y
- define_bool CONFIG_OLD_TIME_C y
+ define_bool CONFIG_NEW_TIME_C y
fi
if [ "$CONFIG_SGI_IP22" = "y" ]; then
define_bool CONFIG_ARC32 y
|
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From: Paul M. <le...@us...> - 2001-10-30 17:53:20
|
Update of /cvsroot/linux-mips/linux/drivers/char In directory usw-pr-cvs1:/tmp/cvs-serv15325 Modified Files: vr41xxwdt.c Log Message: Sanity checks for 4122/4131 Index: vr41xxwdt.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/char/vr41xxwdt.c,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- vr41xxwdt.c 2001/10/28 03:49:14 1.2 +++ vr41xxwdt.c 2001/10/30 17:53:17 1.3 @@ -29,6 +29,8 @@ #ifndef CONFIG_CPU_VR41XX #error "Can't use VR41xx watchdog on non-VR41xx processor." +#elif defined(CONFIG_VR4122) || defined(CONFIG_VR4131) + #error "Can't use VR41xx watchdog on processors without a DSU." #endif #define DSUMINOVRFLW 0x01 /* DSU Min Overflow Interval */ |
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From: James S. <jsi...@us...> - 2001-10-30 17:47:03
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv13623
Modified Files:
c-r3k.c
Log Message:
Optimize R3k cache routines mostly by removing useless code.
Index: c-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-r3k.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- c-r3k.c 2001/10/23 17:20:14 1.1
+++ c-r3k.c 2001/10/30 17:46:57 1.2
@@ -235,66 +235,23 @@
r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);
}
-static void r3k_flush_cache_mm(struct mm_struct *mm)
+static inline void r3k___flush_cache_all(void)
{
- if (mm->context != 0) {
+ r3k_flush_icache_range(KSEG0, KSEG0 + icache_size);
+}
-#ifdef DEBUG_CACHE
- printk("cmm[%d]", (int)mm->context);
-#endif
- r3k_flush_cache_all();
- }
+static void r3k_flush_cache_mm(struct mm_struct *mm)
+{
}
static void r3k_flush_cache_range(struct mm_struct *mm, unsigned long start,
unsigned long end)
{
- struct vm_area_struct *vma;
-
- if (mm->context == 0)
- return;
-
- start &= PAGE_MASK;
-#ifdef DEBUG_CACHE
- printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
-#endif
- vma = find_vma(mm, start);
- if (!vma)
- return;
-
- if (mm->context != current->active_mm->context) {
- flush_cache_all();
- } else {
- unsigned long flags, physpage;
-
- save_and_cli(flags);
- while (start < end) {
- if ((physpage = get_phys_page(start, mm)))
- r3k_flush_icache_range(physpage,
- physpage + PAGE_SIZE);
- start += PAGE_SIZE;
- }
- restore_flags(flags);
- }
}
static void r3k_flush_cache_page(struct vm_area_struct *vma,
unsigned long page)
{
- struct mm_struct *mm = vma->vm_mm;
-
- if (mm->context == 0)
- return;
-
-#ifdef DEBUG_CACHE
- printk("cpage[%d,%08lx]", (int)mm->context, page);
-#endif
- if (vma->vm_flags & VM_EXEC) {
- unsigned long physpage;
-
- if ((physpage = get_phys_page(page, vma->vm_mm)))
- r3k_flush_icache_range(physpage, physpage + PAGE_SIZE);
- }
}
static void r3k_flush_page_to_ram(struct page * page)
@@ -368,7 +325,7 @@
r3k_probe_cache();
_flush_cache_all = r3k_flush_cache_all;
- ___flush_cache_all = r3k_flush_cache_all;
+ ___flush_cache_all = r3k___flush_cache_all;
_flush_cache_mm = r3k_flush_cache_mm;
_flush_cache_range = r3k_flush_cache_range;
_flush_cache_page = r3k_flush_cache_page;
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