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From: Pete P. <pp...@us...> - 2001-10-26 22:36:06
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv30237/include/asm-mips
Modified Files:
bugs.h serial.h
Log Message:
* the proper fix for the ev96100 serial console
* ev96100 freezes when using the 'wait' instruction
Index: bugs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bugs.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- bugs.h 2001/10/25 17:17:45 1.4
+++ bugs.h 2001/10/26 22:36:04 1.5
@@ -36,7 +36,10 @@
case CPU_R4700:
case CPU_R5000:
case CPU_NEVADA:
+#ifndef CONFIG_MIPS_EV96100
+ /* ev96100 freezes when using the wait instruction */
case CPU_RM7000:
+#endif
case CPU_TX49XX:
cpu_wait = r4k_wait;
printk(" available.\n");
Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/serial.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- serial.h 2001/07/09 21:50:55 1.2
+++ serial.h 2001/10/26 22:36:04 1.3
@@ -103,10 +103,12 @@
#define EV96100_SERIAL_PORT_DEFNS \
{ baud_base: EV96100_BASE_BAUD, port: EV96100_UART0_REGS_BASE, \
irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \
- iomem_base: EV96100_UART0_REGS_BASE }, \
+ iomem_base: EV96100_UART0_REGS_BASE, iomem_reg_shift: 2, \
+ io_type: SERIAL_IO_MEM }, \
{ baud_base: EV96100_BASE_BAUD, port: EV96100_UART1_REGS_BASE, \
irq: EV96100INT_UART_0, flags: STD_COM_FLAGS, type: 0x3, \
- iomem_base: EV96100_UART1_REGS_BASE },
+ iomem_base: EV96100_UART1_REGS_BASE, iomem_reg_shift: 2, \
+ io_type: SERIAL_IO_MEM },
#else
#define EV96100_SERIAL_PORT_DEFNS
#endif
|
|
From: James S. <jsi...@us...> - 2001-10-26 22:30:54
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv29207/include/asm-mips Added Files: tx3912.h Log Message: Nino updates. |
|
From: James S. <jsi...@us...> - 2001-10-26 22:30:54
|
Update of /cvsroot/linux-mips/linux/arch/mips/philips/nino
In directory usw-pr-cvs1:/tmp/cvs-serv29207/arch/mips/philips/nino
Modified Files:
Makefile int-handler.S irq.c setup.c time.c
Removed Files:
reset.c
Log Message:
Nino updates.
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile 2001/10/05 21:29:43 1.2
+++ Makefile 2001/10/26 22:30:51 1.3
@@ -15,7 +15,8 @@
all: nino.o
-obj-y := int-handler.o setup.o irq.o time.o reset.o rtc.o prom.o power.o
+obj-y := int-handler.o irq.o setup.o \
+ prom.o power.o time.o
int-handler.o: int-handler.S
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/int-handler.S,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- int-handler.S 2001/06/22 02:29:32 1.1.1.1
+++ int-handler.S 2001/10/26 22:30:51 1.2
@@ -1,137 +1,82 @@
/*
- * linux/arch/mips/philips/nino/int-handler.S
- *
- * Copyright (C) 1999 Harald Koerfgen
- * Copyright (C) 2000 Jim Pick (ji...@ji...)
- * Copyright (C) 2001 Steven J. Hill (sj...@re...)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
+ * int-handler.S: Interrupt exception dispatch code for Philips Nino
*
- * Interrupt handler for Philips Nino.
+ * Copyright (C) 2001 Steven J. Hill (sj...@re...)
*/
+
#include <asm/asm.h>
-#include <asm/regdef.h>
#include <asm/mipsregs.h>
+#include <asm/regdef.h>
#include <asm/stackframe.h>
-#include <asm/tx3912.h>
-
- .data
- .globl HighPriVect
-
-HighPriVect: .word spurious # Reserved
- .word io_posnegint0 # IOPOSINT(0) or IONEGINT(0)
- .word spurious # CHIDMACNTINT
- .word spurious # TELDMACNTINT
- .word spurious # SNDDMACNTINT
- .word spurious # Reserved
- .word io_negint56 # IONEGINT(6) or IONEGINT(5)
- .word spurious # Reserved
- .word io_posint56 # IOPOSINT(6) or IOPOSINT(5)
- .word spurious # Reserved
- .word spurious # UARTBRXINT
- .word uarta_rx # UARTARXINT
- .word spurious # Reserved
- .word periodic_timer # PERINT
- .word spurious # ALARMINT
- .word spurious # POSPWROKINT or NEGPWROKINT
-
-/*
- * Here is the entry point to handle all interrupts.
- */
- .text
- .set noreorder
- .align 5
- NESTED(nino_handle_int, PT_SIZE, ra)
- .set noat
- SAVE_ALL
- CLI
- .set at
-
- /*
- * Get pending Interrupts
- */
- mfc0 t0, CP0_CAUSE # Get pending interrupts
- andi t2, t0, IE_IRQ4 # IRQ4 (high priority)
- bne t2, IE_IRQ4, low_priority
- nop
-/*
- * Ok, we've got a high priority interrupt (a.k.a. an external interrupt).
- * Read Interrupt Status Register 6 to get vector.
- */
-high_priority:
- lui t0, %hi(IntStatus6)
- lw t1, %lo(IntStatus6)(t0)
- andi t1, INT6_INTVECT
- la t2, HighPriVect
- addu t1, t1, t2
- lw t2, 0(t1)
- jr t2
- nop
+ /*
+ * Here is the table of interrupts for the Philips Nino
+ * which uses the Philips PR31700/Toshiba TMPR3912 core.
+ *
+ * MIPS IRQ PR31700 IRQ Source
+ * -------- ----------- ------
+ * 0 1 Sound, LCD, telecom
+ * 1 2 UARTA & UARTB
+ * 2 3 MFIO (positive edge)
+ * 3 4 MFIO (negative edge)
+ * 4 5 Timers, power management
+ * 5 6 High priority interrupts
+ *
+ * We handle the IRQ according to the priorities below:
+ *
+ * Highest ---- High priority interrupts
+ * UARTA & UARTB
+ * Timers, power management
+ * Sound, LCD, telecom
+ * Multi-function IO (positive edge)
+ * Lowest ---- Multi-function IO (negative edge)
+ *
+ * then we just return, if multiple IRQs are pending then
+ * we will just take another exception, big deal.
+ */
-/*
- * Ok, we've got one of over a hundred other interupts.
- */
-low_priority:
- lui t0, %hi(IntStatus1)
- lw t1, %lo(IntStatus1)(t0)
- j handle_it
- li a0, 20
+ .text
+ .set noreorder
+ .set noat
+ .align 5
+ NESTED(ninoIRQ, PT_SIZE, sp)
+ SAVE_ALL
+ CLI
+ .set at
+ mfc0 s0, CP0_CAUSE # get irq mask
-/*
- * We don't currently handle spurious interrupts.
- */
-spurious:
- j spurious_interrupt
- nop
+ /* Check for IRQ4 */
+ andi a0, s0, C_IRQ4
+ beq a0, zero, 1f
+ andi a0, s0, C_IRQ2 # delay slot, check for IRQ2
-/*
- * We have the IRQ number, dispatch to the real handler.
- */
-handle_it: jal do_IRQ
- move a1,sp
- j ret_from_irq
- nop
+ /* High priority interrupt */
+ move a0, sp
+ jal irq4_dispatch
+ nop # delay slot
-/************************************
- * High priority interrupt mappings *
- ************************************/
-
-/*
- * Periodic timer - IRQ 0
- */
-periodic_timer:
- j handle_it
- li a0, 0
+ j ret_from_irq
+ nop # delay slot
-/*
- * UARTA RX - IRQ 3
- */
-uarta_rx:
- j handle_it
- li a0, 3
+1:
+ /* Check for IRQ2 */
+ beq a0, zero, 1f
+ nop # delay slot
-/*
- * GPIO Pin 0 transition - IRQ 10
- */
-io_posnegint0:
- j handle_it
- li a0, 10
+ /* UART interrupt of some sort */
+ move a0, sp
+ jal irq2_dispatch
+ nop # delay slot
-/*
- * GPIO Pin 5 or 6 transition (0-to-1) - IRQ 11
- */
-io_posint56:
- j handle_it
- li a0, 11
+ j ret_from_irq
+ nop # delay slot
-/*
- * GPIO Pin 5 or 6 transition (1-to-0) - IRQ 12
- */
-io_negint56:
- j handle_it
- li a0, 12
+1:
+ /* We should never get here */
+ move a0, sp
+ jal irq_bad
+ nop
- END(nino_handle_int)
+ j ret_from_irq
+ nop
+ END(ninoIRQ)
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/irq.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- irq.c 2001/09/04 15:58:40 1.2
+++ irq.c 2001/10/26 22:30:51 1.3
@@ -1,28 +1,23 @@
/*
- * linux/arch/mips/philips/nino/irq.c
+ * irq.c: Fine grained interrupt handling for Nino
*
- * Copyright (C) 1992 Linus Torvalds
- * Copyright (C) 1999 Harald Koerfgen
- * Copyright (C) 2000 Pavel Machek (pa...@su...)
- * Copyright (C) 2001 Steven J. Hill (sj...@re...)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Generic interrupt handler for Philips Nino.
+ * Copyright (C) 2001 Steven J. Hill (sj...@re...)
*/
-#include <linux/errno.h>
#include <linux/init.h>
+
+#include <linux/errno.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/ioport.h>
#include <linux/timex.h>
#include <linux/slab.h>
#include <linux/random.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
#include <asm/bitops.h>
#include <asm/bootinfo.h>
@@ -30,285 +25,265 @@
#include <asm/irq.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
+
+#include <asm/ptrace.h>
+#include <asm/processor.h>
#include <asm/tx3912.h>
-unsigned long spurious_count = 0;
+/*
+ * Linux has a controller-independent x86 interrupt architecture.
+ * every controller has a 'controller-template', that is used
+ * by the main code to do the right thing. Each driver-visible
+ * interrupt source is transparently wired to the apropriate
+ * controller. Thus drivers need not be aware of the
+ * interrupt-controller.
+ *
+ * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC,
+ * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC.
+ * (IO-APICs assumed to be messaging to Pentium local-APICs)
+ *
+ * the code is designed to be easily extended with new/different
+ * interrupt controllers, without having to do assembly magic.
+ */
-irq_cpustat_t irq_stat [NR_CPUS];
+extern asmlinkage void ninoIRQ(void);
+extern asmlinkage void do_IRQ(int irq, struct pt_regs *regs);
+extern void init_generic_irq(void);
-static inline void mask_irq(unsigned int irq_nr)
+static void enable_irq4(unsigned int irq)
{
- switch (irq_nr) {
- case 0: /* Periodic Timer Interrupt */
- IntClear5 = INT5_PERIODICINT;
- IntClear6 = INT6_PERIODICINT;
- IntEnable6 &= ~INT6_PERIODICINT;
- break;
-
- case 3:
- /* Serial port receive interrupt */
- break;
-
- case 2:
- /* Serial port transmit interrupt */
- break;
-
- default:
- printk( "Attempt to mask unknown IRQ %d?\n", irq_nr );
- }
-}
+ unsigned long flags;
-static inline void unmask_irq(unsigned int irq_nr)
-{
- switch (irq_nr) {
- case 0:
+ save_and_cli(flags);
+ if(irq == 0) {
+ IntEnable5 |= INT5_PERIODICINT;
IntEnable6 |= INT6_PERIODICINT;
- break;
-
- case 3:
- /* Serial port receive interrupt */
- break;
-
- case 2:
- /* Serial port transmit interrupt */
- break;
-
- default:
- printk( "Attempt to unmask unknown IRQ %d?\n", irq_nr );
}
+ restore_flags(flags);
}
-void disable_irq(unsigned int irq_nr)
+static unsigned int startup_irq4(unsigned int irq)
{
- unsigned long flags;
+ enable_irq4(irq);
- save_and_cli(flags);
- mask_irq(irq_nr);
- restore_flags(flags);
+ return 0; /* Never anything pending */
}
-void enable_irq(unsigned int irq_nr)
+static void disable_irq4(unsigned int irq)
{
- unsigned long flags;
+ unsigned long flags;
- save_and_cli(flags);
- unmask_irq(irq_nr);
- restore_flags(flags);
+ save_and_cli(flags);
+ if(irq == 0) {
+ IntEnable6 &= ~INT6_PERIODICINT;
+ IntClear5 |= INT5_PERIODICINT;
+ IntClear6 |= INT6_PERIODICINT;
+ }
+ restore_flags(flags);
}
-
-/*
- * Pointers to the low-level handlers: first the general ones, then the
- * fast ones, then the bad ones.
- */
-extern void interrupt(void);
-static struct irqaction *irq_action[NR_IRQS] =
-{
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
- NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
-};
+#define shutdown_irq4 disable_irq4
+#define mask_and_ack_irq4 disable_irq4
-int get_irq_list(char *buf)
+static void end_irq4(unsigned int irq)
{
- int i, len = 0;
- struct irqaction *action;
-
- for (i = 0; i < NR_IRQS; i++) {
- action = irq_action[i];
- if (!action)
- continue;
- len += sprintf(buf + len, "%2d: %8d %c %s",
- i, kstat.irqs[0][i],
- (action->flags & SA_INTERRUPT) ? '+' : ' ',
- action->name);
- for (action = action->next; action; action = action->next) {
- len += sprintf(buf + len, ",%s %s",
- (action->flags & SA_INTERRUPT) ? " +" : "",
- action->name);
- }
- len += sprintf(buf + len, "\n");
- }
- return len;
+ if(!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_irq4(irq);
}
-atomic_t __mips_bh_counter;
+static struct hw_interrupt_type irq4_type = {
+ "IRQ4",
+ startup_irq4,
+ shutdown_irq4,
+ enable_irq4,
+ disable_irq4,
+ mask_and_ack_irq4,
+ end_irq4,
+ NULL
+};
-/*
- * do_IRQ handles IRQ's that have been installed without the
- * SA_INTERRUPT flag: it uses the full signal-handling return
- * and runs with other interrupts enabled. All relatively slow
- * IRQ's should use this format: notably the keyboard/timer
- * routines.
- */
-asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
+void irq4_dispatch(struct pt_regs *regs)
{
- struct irqaction *action;
- int do_random, cpu;
+ int irq = -1;
- if (irq == 20) {
- if (IntStatus2 & 0xfffff00) {
- if (IntStatus2 & 0x0f000000)
- return do_IRQ(2, regs);
+ if(IntStatus6 & INT6_PERIODICINT) {
+ irq = 0;
+ goto done;
}
- }
- cpu = smp_processor_id();
- irq_enter(cpu, irq);
- kstat.irqs[cpu][irq]++;
+ /* if irq == -1, then the interrupt has already been cleared */
+ if(irq == -1) {
+ printk("IRQ6 Status Register = 0x%08x\n", IntStatus6);
+ goto end;
+ }
- if (irq == 20) {
- printk("20 %08lx %08lx\n %08lx %08lx\n %08lx\n",
- IntStatus1, IntStatus2, IntStatus3,
- IntStatus4, IntStatus5 );
- printk("20 %08lx %08lx\n %08lx %08lx\n %08lx\n",
- IntEnable1, IntEnable2, IntEnable3,
- IntEnable4, IntEnable5 );
+done:
+ do_IRQ(irq, regs);
- }
+end:
+ return;
+}
- mask_irq(irq);
- action = *(irq + irq_action);
- if (action) {
- if (!(action->flags & SA_INTERRUPT))
- __sti();
- do_random = 0;
- do {
- do_random |= action->flags;
- action->handler(irq, action->dev_id, regs);
- action = action->next;
- } while (action);
- if (do_random & SA_SAMPLE_RANDOM)
- add_interrupt_randomness(irq);
- unmask_irq(irq);
- __cli();
- } else {
- IntClear1 = ~0;
- IntClear3 = ~0;
- IntClear4 = ~0;
- IntClear5 = ~0;
- unmask_irq(irq);
- }
- irq_exit(cpu, irq);
+static void enable_irq2(unsigned int irq)
+{
+ unsigned long flags;
- /* unmasking and bottom half handling is done magically for us. */
+ save_and_cli(flags);
+ if(irq == 2 || irq == 3) {
+ IntEnable1 = 0x00000000;
+ IntEnable2 = 0xfffff000;
+ IntEnable3 = 0x00000000;
+ IntEnable4 = 0x00000000;
+ IntClear1 = 0xffffffff;
+ IntClear2 = 0xffffffff;
+ IntClear3 = 0xffffffff;
+ IntClear4 = 0xffffffff;
+ IntClear5 = 0xffffffff;
+ }
+ restore_flags(flags);
}
-/*
- * Idea is to put all interrupts
- * in a single table and differenciate them just by number.
- */
-int setup_nino_irq(int irq, struct irqaction *new)
+static unsigned int startup_irq2(unsigned int irq)
{
- int shared = 0;
- struct irqaction *old, **p;
- unsigned long flags;
+ enable_irq2(irq);
- p = irq_action + irq;
- if ((old = *p) != NULL) {
- /* Can't share interrupts unless both agree to */
- if (!(old->flags & new->flags & SA_SHIRQ))
- return -EBUSY;
+ return 0; /* Never anything pending */
+}
- /* Can't share interrupts unless both are same type */
- if ((old->flags ^ new->flags) & SA_INTERRUPT)
- return -EBUSY;
+static void disable_irq2(unsigned int irq)
+{
+ unsigned long flags;
- /* add new interrupt at end of irq queue */
- do {
- p = &old->next;
- old = *p;
- } while (old);
- shared = 1;
- }
- if (new->flags & SA_SAMPLE_RANDOM)
- rand_initialize_irq(irq);
+ save_and_cli(flags);
+ IntEnable1 = 0x00000000;
+ IntEnable2 = 0x00000000;
+ IntEnable3 = 0x00000000;
+ IntEnable4 = 0x00000000;
+ IntClear1 = 0xffffffff;
+ IntClear2 = 0xffffffff;
+ IntClear3 = 0xffffffff;
+ IntClear4 = 0xffffffff;
+ IntClear5 = 0xffffffff;
+ restore_flags(flags);
+}
- save_and_cli(flags);
- *p = new;
+#define shutdown_irq2 disable_irq2
+#define mask_and_ack_irq2 disable_irq2
- if (!shared) {
- unmask_irq(irq);
- }
- restore_flags(flags);
- return 0;
+static void end_irq2(unsigned int irq)
+{
+ if(!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+ enable_irq2(irq);
}
-int request_irq(unsigned int irq,
- void (*handler) (int, void *, struct pt_regs *),
- unsigned long irqflags,
- const char *devname,
- void *dev_id)
+static struct hw_interrupt_type irq2_type = {
+ "IRQ2",
+ startup_irq2,
+ shutdown_irq2,
+ enable_irq2,
+ disable_irq2,
+ mask_and_ack_irq2,
+ end_irq2,
+ NULL
+};
+
+void irq2_dispatch(struct pt_regs *regs)
{
- int retval;
- struct irqaction *action;
+ int irq = -1;
- if (irq >= NR_IRQS)
- return -EINVAL;
- if (!handler)
- return -EINVAL;
+ if(IntStatus2 & 0xfffff000) {
+ irq = 2;
+ goto done;
+ }
+ if(IntStatus2 & 0xfffff000) {
+ irq = 3;
+ goto done;
+ }
- action = (struct irqaction *) kmalloc(sizeof(struct irqaction), GFP_KERNEL);
- if (!action)
- return -ENOMEM;
+ /* if irq == -1, then the interrupt has already been cleared */
+ if (irq == -1) {
+ IntClear1 = 0xffffffff;
+ IntClear3 = 0xffffffff;
+ IntClear4 = 0xffffffff;
+ IntClear5 = 0xffffffff;
+ goto end;
+ }
- action->handler = handler;
- action->flags = irqflags;
- action->mask = 0;
- action->name = devname;
- action->next = NULL;
- action->dev_id = dev_id;
+done:
+ do_IRQ(irq, regs);
- retval = setup_nino_irq(irq, action);
+end:
+ return;
+}
- if (retval)
- kfree(action);
- return retval;
+void irq_bad(struct pt_regs *regs)
+{
+ /* This should never happen */
+ printk("Invalid interrupt, spinning...\n");
+ printk(" CAUSE register = 0x%08lx\n", regs->cp0_cause);
+ printk("STATUS register = 0x%08lx\n", regs->cp0_status);
+ printk(" EPC register = 0x%08lx\n", regs->cp0_epc);
+ while(1);
}
-void free_irq(unsigned int irq, void *dev_id)
+void __init nino_irq_setup(void)
{
- struct irqaction *action, **p;
- unsigned long flags;
+ unsigned int i;
- if (irq >= NR_IRQS) {
- printk(KERN_CRIT __FUNCTION__ ": trying to free IRQ%d\n", irq);
- return;
- }
- for (p = irq + irq_action; (action = *p) != NULL; p = &action->next) {
- if (action->dev_id != dev_id)
- continue;
+ /* Disable interrupts */
+ IntEnable1 = 0x00000000;
+ IntEnable2 = 0x00000000;
+ IntEnable3 = 0x00000000;
+ IntEnable4 = 0x00000000;
+ IntEnable5 = 0x00000000;
+ IntEnable6 = 0x00000000;
- /* Found it - now free it */
- save_and_cli(flags);
- *p = action->next;
- if (!irq[irq_action])
- mask_irq(irq);
- restore_flags(flags);
- kfree(action);
- return;
- }
- printk(KERN_CRIT __FUNCTION__ ": trying to free free IRQ%d\n", irq);
-}
+ /* Clear interrupts */
+ IntClear1 = 0xffffffff;
+ IntClear2 = 0xffffffff;
+ IntClear3 = 0xffffffff;
+ IntClear4 = 0xffffffff;
+ IntClear5 = 0xffffffff;
-unsigned long probe_irq_on(void)
-{
- /* TODO */
- return 0;
-}
+ /* Change location of exception vector table */
+ change_cp0_status(ST0_BEV, 0);
-int probe_irq_off(unsigned long irqs)
-{
- /* TODO */
- return 0;
+ /* Initialize IRQ vector table */
+ init_generic_irq();
+
+ /* Initialize hardware IRQ structure */
+ for (i = 0; i < 16; i++) {
+ hw_irq_controller *handler = NULL;
+ if (i == 0)
+ handler = &irq4_type;
+ else if (i > 1 && i < 4)
+ handler = &irq2_type;
+ else
+ handler = NULL;
+
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = 0;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = handler;
+ }
+
+ /* Set up the external interrupt exception vector */
+ set_except_vector(0, ninoIRQ);
}
+void (*irq_setup)(void);
+
void __init init_IRQ(void)
{
- irq_setup();
+#ifdef CONFIG_REMOTE_DEBUG
+ extern void breakpoint(void);
+ extern void set_debug_traps(void);
+
+ printk("Wait for gdb client connection ...\n");
+ set_debug_traps();
+ breakpoint();
+#endif
+
+ /* Invoke board-specific irq setup */
+ irq_setup();
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/setup.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- setup.c 2001/06/22 02:29:32 1.1.1.1
+++ setup.c 2001/10/26 22:30:51 1.2
@@ -9,79 +9,44 @@
*
* Interrupt and exception initialization for Philips Nino.
*/
-#include <linux/console.h>
#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/mc146818rtc.h>
#include <linux/sched.h>
#include <asm/addrspace.h>
-#include <asm/gdb-stub.h>
+#include <asm/io.h>
#include <asm/irq.h>
-#include <asm/wbflush.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
#include <asm/tx3912.h>
-
-extern struct rtc_ops nino_rtc_ops;
-
-extern void nino_wait(void);
-extern void setup_nino_reset_vectors(void);
-extern asmlinkage void nino_handle_int(void);
-extern int setup_nino_irq(int, struct irqaction *);
-void (*board_time_init) (struct irqaction * irq);
-
-#ifdef CONFIG_REMOTE_DEBUG
-extern void set_debug_traps(void);
-extern void breakpoint(void);
-static int remote_debug = 0;
-#endif
-static void __init nino_irq_setup(void)
+void nino_machine_restart(char *command)
{
- unsigned int tmp;
-
- /* Turn all interrupts off */
- IntEnable1 = 0;
- IntEnable2 = 0;
- IntEnable3 = 0;
- IntEnable4 = 0;
- IntEnable5 = 0;
- IntEnable6 = 0;
+ static void (*back_to_prom)(void) = (void (*)(void)) 0xbfc00000;
- /* Clear all interrupts */
- IntClear1 = 0xffffffff;
- IntClear2 = 0xffffffff;
- IntClear3 = 0xffffffff;
- IntClear4 = 0xffffffff;
- IntClear5 = 0xffffffff;
- IntClear6 = 0xffffffff;
+ /* Reboot */
+ back_to_prom();
+}
- /*
- * Enable only the interrupts for the UART and negative
- * edge (1-to-0) triggered multi-function I/O pins.
- */
- change_cp0_status(ST0_BEV, 0);
- tmp = read_32bit_cp0_register(CP0_STATUS);
- change_cp0_status(ST0_IM, tmp | IE_IRQ2 | IE_IRQ4);
+void nino_machine_halt(void)
+{
+ printk("Nino halted.\n");
+ while(1);
+}
- /* Register the global interrupt handler */
- set_except_vector(0, nino_handle_int);
+void nino_machine_power_off(void)
+{
+ printk("Nino halted. Please turn off power.\n");
+ while(1);
+}
-#ifdef CONFIG_REMOTE_DEBUG
- if (remote_debug) {
- set_debug_traps();
- breakpoint();
- }
-#endif
+static void __init nino_board_init()
+{
+ /* Nothing for now */
}
-static __init void nino_time_init(struct irqaction *irq)
+static __init void nino_time_init(void)
{
unsigned int scratch = 0;
- /*
- * Enable periodic interrupts
- */
- setup_nino_irq(0, irq);
-
RTCperiodTimer = PER_TIMER_COUNT;
RTCtimerControl = TIM_ENPERTIMER;
IntEnable5 |= INT5_PERIODICINT;
@@ -89,32 +54,39 @@
scratch = inl(TX3912_CLK_CTRL_BASE);
scratch |= TX3912_CLK_CTRL_ENTIMERCLK;
outl(scratch, TX3912_CLK_CTRL_BASE);
+}
- /* Enable all interrupts */
- IntEnable6 |= INT6_GLOBALEN | INT6_PERIODICINT;
+extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
+
+static __init void nino_timer_setup(struct irqaction *irq)
+{
+ setup_irq(0, irq);
+
+ /* Enable all hardware interrupts */
+ set_cp0_status(IE_IRQ5 | IE_IRQ4 | IE_IRQ3 |
+ IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
+
+ /* Enable all the high priority interrupts */
+ IntEnable6 = (INT6_GLOBALEN | 0xffff);
+
}
+extern void nino_irq_setup(void);
+extern void nino_wait(void);
+
void __init nino_setup(void)
{
irq_setup = nino_irq_setup;
+ mips_io_port_base = KSEG1ADDR(0xb0c00000);
board_time_init = nino_time_init;
-
- /* Base address to use for PC type I/O accesses */
- mips_io_port_base = KSEG1ADDR(0xB0C00000);
+ board_timer_setup = nino_timer_setup;
- setup_nino_reset_vectors();
+ _machine_restart = nino_machine_restart;
+ _machine_halt = nino_machine_halt;
+ _machine_power_off = nino_machine_power_off;
- /* Function called during process idle (cpu_idle) */
cpu_wait = nino_wait;
-
-#ifdef CONFIG_FB
- conswitchp = &dummy_con;
-#endif
-#ifdef CONFIG_REMOTE_DEBUG
- remote_debug = 1;
-#endif
-
- rtc_ops = &nino_rtc_ops;
+ nino_board_init();
}
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/philips/nino/time.c,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -u -d -r1.1.1.1 -r1.2
--- time.c 2001/06/22 02:29:32 1.1.1.1
+++ time.c 2001/10/26 22:30:51 1.2
@@ -19,6 +19,7 @@
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
+#include <linux/time.h>
#include <linux/timex.h>
#include <linux/delay.h>
#include <asm/tx3912.h>
@@ -28,6 +29,9 @@
static struct timeval xbase;
+void (*board_time_init)(void) = NULL;
+void (*board_timer_setup)(struct irqaction *irq) = NULL;
+
#define USECS_PER_JIFFY (1000000/HZ)
/*
@@ -200,8 +204,6 @@
static struct irqaction irq0 = {timer_interrupt, SA_INTERRUPT, 0,
"timer", NULL, NULL};
-void (*board_time_init) (struct irqaction * irq);
-
int __init time_init(void)
{
struct timeval starttime;
@@ -210,7 +212,8 @@
starttime.tv_usec = 0;
do_settimeofday(&starttime);
- board_time_init(&irq0);
+ board_time_init();
+ board_timer_setup(&irq0);
return 0;
}
--- reset.c DELETED ---
|
|
From: James S. <jsi...@us...> - 2001-10-26 22:30:54
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv29207/drivers/char
Modified Files:
serial_tx3912.c
Log Message:
Nino updates.
Index: serial_tx3912.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/serial_tx3912.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- serial_tx3912.c 2001/10/22 19:20:09 1.5
+++ serial_tx3912.c 2001/10/26 22:30:51 1.6
@@ -18,13 +18,13 @@
#include <linux/ptrace.h>
#include <linux/init.h>
#include <linux/console.h>
-#include <linux/serial.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/malloc.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/pm.h>
+#include <linux/serial.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/delay.h>
@@ -904,18 +904,17 @@
rc = rs_init_portstructs ();
rs_init_drivers ();
- if (request_irq(2, rs_tx_interrupt_uarta, SA_SHIRQ | SA_INTERRUPT,
+ if (request_irq(2, rs_tx_interrupt_uarta, SA_INTERRUPT,
"serial", &rs_ports[0])) {
printk(KERN_ERR "rs: Cannot allocate irq for UARTA.\n");
rc = 0;
}
- if (request_irq(3, rs_rx_interrupt_uarta, SA_SHIRQ | SA_INTERRUPT,
+ if (request_irq(3, rs_rx_interrupt_uarta, SA_INTERRUPT,
"serial", &rs_ports[0])) {
printk(KERN_ERR "rs: Cannot allocate irq for UARTA.\n");
rc = 0;
}
- IntEnable6 |= INT6_UARTARXINT;
rs_enable_rx_interrupts(&rs_ports[0]);
#ifndef CONFIG_SERIAL_TX3912_CONSOLE
|
|
From: James S. <jsi...@us...> - 2001-10-26 22:30:53
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv29207/arch/mips/configs Modified Files: defconfig-nino Log Message: Nino updates. Index: defconfig-nino =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-nino,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- defconfig-nino 2001/10/26 16:37:55 1.10 +++ defconfig-nino 2001/10/26 22:30:51 1.11 @@ -44,6 +44,7 @@ # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set # CONFIG_SBUS is not set +CONFIG_NEW_IRQ=y CONFIG_PC_KEYB=y # CONFIG_ISA is not set # CONFIG_EISA is not set |
|
From: James S. <jsi...@us...> - 2001-10-26 22:30:53
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv29207/arch/mips
Modified Files:
config.in
Log Message:
Nino updates.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.39
retrieving revision 1.40
diff -u -d -r1.39 -r1.40
--- config.in 2001/10/26 17:42:26 1.39
+++ config.in 2001/10/26 22:30:51 1.40
@@ -45,7 +45,7 @@
Model-500/510 CONFIG_NINO_16MB" CONFIG_NINO_8MB
fi
bool 'Support for Sony PlayStation 2' CONFIG_PS2
- bool 'Support for Casio Cassiopeia BE-300 (EXPERIMENTAL)' CONFIG_CASIO_BE300
+ bool 'Support for Casio Cassiopeia BE-300 (EXPERIMENTAL)' CONFIG_CASIO_BE300
fi
bool 'Support for Mips Magnum 4000' CONFIG_MIPS_MAGNUM_4000
bool 'Support for Momentum Ocelot board' CONFIG_MOMENCO_OCELOT
@@ -203,7 +203,7 @@
define_bool CONFIG_VRC4173 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
- define_bool CONFIG_DUMMY_KEYB y
+ define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_PCI y
fi
if [ "$CONFIG_NEC_KORVA" = "y" ]; then
@@ -245,10 +245,11 @@
define_bool CONFIG_NO_VIDEO_CONSOLE y
define_bool CONFIG_COBALT_LCD y
define_bool CONFIG_PCI y
- define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_NEW_PCI y
define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_NINO" = "y" ]; then
+ define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_PC_KEYB y
fi
if [ "$CONFIG_PS2" = "y" ]; then
@@ -257,7 +258,7 @@
fi
if [ "$CONFIG_CASIO_BE300" = "y" ]; then
define_bool CONFIG_CPU_VR41XX y
- #
+ #
# Note that the VR4131 is pin compliant with the VR4122,
# leave both specified for now to attempt and reduce code
# duplication as much as possible. -Lethal
@@ -267,7 +268,7 @@
define_bool CONFIG_VRC4173 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
- define_bool CONFIG_DUMMY_KEYB y
+ define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_PCI y
fi
@@ -509,7 +510,7 @@
if [ "$CONFIG_TC" = "y" ]; then
bool 'Z85C30 Serial Support' CONFIG_ZS
fi
- bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
+ bool ' Support for console on serial port' CONFIG_SERIAL_CONSOLE
fi
bool 'Unix98 PTY support' CONFIG_UNIX98_PTYS
if [ "$CONFIG_UNIX98_PTYS" = "y" ]; then
|
|
From: Pete P. <pp...@us...> - 2001-10-26 22:11:46
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv24414/arch/mips/mm Modified Files: c-rm7k.c Log Message: Added cpu.h to fix a compile error. Index: c-rm7k.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-rm7k.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- c-rm7k.c 2001/10/23 17:20:14 1.1 +++ c-rm7k.c 2001/10/26 22:11:25 1.2 @@ -24,6 +24,7 @@ #include <asm/pgtable.h> #include <asm/system.h> #include <asm/bootinfo.h> +#include <asm/cpu.h> #include <asm/mmu_context.h> /* CP0 hazard avoidance. */ |
|
From: James S. <jsi...@us...> - 2001-10-26 20:35:44
|
Update of /cvsroot/linux-mips/linux/drivers/net/tulip
In directory usw-pr-cvs1:/tmp/cvs-serv30738
Modified Files:
tulip_core.c
Log Message:
Fix the bug Pete reported to prevent interrupts from happening before tulip_init_ring() and tulip_up()
Index: tulip_core.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/tulip/tulip_core.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- tulip_core.c 2001/10/22 19:17:55 1.7
+++ tulip_core.c 2001/10/26 20:35:41 1.8
@@ -513,11 +513,6 @@
int retval;
MOD_INC_USE_COUNT;
- if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev))) {
- MOD_DEC_USE_COUNT;
- return retval;
- }
-
tulip_init_ring (dev);
tulip_up (dev);
@@ -528,6 +523,10 @@
netif_start_queue (dev);
+ if ((retval = request_irq(dev->irq, &tulip_interrupt, SA_SHIRQ, dev->name, dev))) {
+ MOD_DEC_USE_COUNT;
+ return retval;
+ }
return 0;
}
|
|
From: James S. <jsi...@us...> - 2001-10-26 20:01:27
|
Update of /cvsroot/linux-mips/linux/drivers/char In directory usw-pr-cvs1:/tmp/cvs-serv20092 Modified Files: lcd.c Log Message: exporting a function so the tulip driver will work. I actually hope to replace this driver Index: lcd.c =================================================================== RCS file: /cvsroot/linux-mips/linux/drivers/char/lcd.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- lcd.c 2001/07/10 03:11:19 1.1 +++ lcd.c 2001/10/26 20:01:25 1.2 @@ -7,6 +7,7 @@ #define RTC_IO_EXTENT 0x10 /*Only really two ports, but... */ +#include <linux/module.h> #include <linux/types.h> #include <linux/errno.h> #include <linux/miscdevice.h> @@ -616,3 +617,5 @@ return ( (READ_FLASH(address) & 0x20) == 0x20 ); } + +EXPORT_SYMBOL(lcd_register_linkcheck_func); |
|
From: James S. <jsi...@us...> - 2001-10-26 20:00:18
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv19348 Modified Files: Makefile pci-dma.c Log Message: Export pci dma allocate and dealloacte functions. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/Makefile,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- Makefile 2001/10/25 16:43:24 1.11 +++ Makefile 2001/10/26 20:00:15 1.12 @@ -57,6 +57,7 @@ obj-$(CONFIG_BINFMT_IRIX) += irixelf.o irixioctl.o irixsig.o sysirix.o \ irixinv.o obj-$(CONFIG_REMOTE_DEBUG) += gdb-low.o gdb-stub.o +export-objs += pci-dma.o obj-$(CONFIG_PCI) += pci-dma.o obj-$(CONFIG_PROC_FS) += proc.o Index: pci-dma.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/pci-dma.c,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- pci-dma.c 2001/07/09 19:28:47 1.2 +++ pci-dma.c 2001/10/26 20:00:15 1.3 @@ -8,6 +8,7 @@ * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. */ #include <linux/config.h> +#include <linux/module.h> #include <linux/types.h> #include <linux/mm.h> #include <linux/string.h> @@ -47,3 +48,6 @@ #endif free_pages(addr, get_order(size)); } + +EXPORT_SYMBOL(pci_alloc_consistent); +EXPORT_SYMBOL(pci_free_consistent); |
|
From: James S. <jsi...@us...> - 2001-10-26 17:49:21
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv9771
Modified Files:
setup.c
Log Message:
While testing the new time code it makes it handy if I can go back and forth between both old time and new time styles.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/setup.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- setup.c 2001/10/26 16:55:56 1.8
+++ setup.c 2001/10/26 17:49:18 1.9
@@ -118,6 +118,8 @@
*((volatile unsigned long *) GALILEO_CPU_MASK) = (unsigned long) 0x00000100;
}
+#ifdef CONFIG_NEW_TIME_C
+
static void __init cobalt_time_init(void)
{
//mips_counter_frequency = 83000000;
@@ -131,6 +133,7 @@
*/
/* rtc_set_time(mktime(2001, 10, 05, 17, 20, 0)); */
}
+#endif
int cobalt_serial_present;
int cobalt_serial_type;
@@ -151,8 +154,12 @@
_machine_halt = cobalt_machine_halt;
_machine_power_off = cobalt_machine_power_off;
+#ifdef CONFIG_NEW_TIME_C
board_time_init = cobalt_time_init;
board_timer_setup = cobalt_timer_setup;
+#else
+ board_time_init = cobalt_timer_setup;
+#endif
rtc_ops = &cobalt_rtc_ops;
#ifdef CONFIG_BLK_DEV_IDE
|
|
From: James S. <jsi...@us...> - 2001-10-26 17:42:29
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv7534
Modified Files:
config.in
Log Message:
The new RTC code is not ready yet.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.38
retrieving revision 1.39
diff -u -d -r1.38 -r1.39
--- config.in 2001/10/26 16:50:01 1.38
+++ config.in 2001/10/26 17:42:26 1.39
@@ -246,7 +246,7 @@
define_bool CONFIG_COBALT_LCD y
define_bool CONFIG_PCI y
define_bool CONFIG_NEW_PCI y
- define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_OLD_TIME_C y
fi
if [ "$CONFIG_NINO" = "y" ]; then
define_bool CONFIG_PC_KEYB y
|
|
From: James S. <jsi...@us...> - 2001-10-26 17:37:00
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv5605
Modified Files:
Config.in Makefile
Log Message:
Added Dallas RTC style chip supprot as a option. Some devices using new devices don't have a Dallas chipset.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- Config.in 2001/10/25 17:27:56 1.14
+++ Config.in 2001/10/26 17:36:56 1.15
@@ -180,6 +180,9 @@
dep_tristate 'Intel i8x0 Random Number Generator support' CONFIG_INTEL_RNG $CONFIG_PCI
tristate '/dev/nvram support' CONFIG_NVRAM
tristate 'Enhanced Real Time Clock Support' CONFIG_RTC
+if [ "$CONFIG_RTC" = "y" -a "$CONFIG_NEW_TIME_C" = "y" ]; then
+ bool 'Generic Dallas PC style RTC chip support' CONFIG_DALLAS_RTC
+fi
if [ "$CONFIG_IA64" = "y" ]; then
bool 'EFI Real Time Clock Services' CONFIG_EFI_RTC
fi
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Makefile,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- Makefile 2001/10/26 16:47:44 1.13
+++ Makefile 2001/10/26 17:36:56 1.14
@@ -192,7 +192,7 @@
obj-$(CONFIG_ADBMOUSE) += adbmouse.o
obj-$(CONFIG_PC110_PAD) += pc110pad.o
obj-$(CONFIG_RTC) += rtc.o
-obj-$(CONFIG_NEW_TIME_C) += rtc_dallas.o
+obj-$(CONFIG_DALLAS_RTC) += rtc_dallas.o
obj-$(CONFIG_EFI_RTC) += efirtc.o
ifeq ($(CONFIG_PPC),)
obj-$(CONFIG_NVRAM) += nvram.o
|
|
From: James S. <jsi...@us...> - 2001-10-26 16:58:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv24596 Modified Files: setup.c Log Message: Made initrd_header and tmp conditional compiles. Makes for less warnings. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v retrieving revision 1.23 retrieving revision 1.24 diff -u -d -r1.23 -r1.24 --- setup.c 2001/10/24 23:32:54 1.23 +++ setup.c 2001/10/26 16:58:29 1.24 @@ -602,9 +602,10 @@ unsigned long bootmap_size; unsigned long start_pfn, max_pfn, first_usable_pfn; +#ifdef CONFIG_BLK_DEV_INITRD + unsigned long *initrd_header; unsigned long tmp; - unsigned long* initrd_header; - +#endif int i; #ifdef CONFIG_BLK_DEV_FD |
|
From: James S. <jsi...@us...> - 2001-10-26 16:55:59
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt
In directory usw-pr-cvs1:/tmp/cvs-serv23706
Modified Files:
setup.c
Log Message:
Fixed white spaces.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- setup.c 2001/10/25 23:58:08 1.7
+++ setup.c 2001/10/26 16:55:56 1.8
@@ -59,32 +59,32 @@
void __init cobalt_irq_setup(void)
{
- /*
- * Clear all of the interrupts while we change the table around a bit.
- */
- change_cp0_status(ST0_IM, 0);
+ /*
+ * Clear all of the interrupts while we change the table around a bit.
+ */
+ change_cp0_status(ST0_IM, 0);
- /* Sets the exception_handler array. */
- set_except_vector(0, cobalt_handle_int);
+ /* Sets the exception_handler array. */
+ set_except_vector(0, cobalt_handle_int);
- request_resource(&ioport_resource, &res_pic1);
- request_resource(&ioport_resource, &res_pic2);
+ request_resource(&ioport_resource, &res_pic1);
+ request_resource(&ioport_resource, &res_pic2);
- change_cp0_status(ST0_IM, 0);
- setup_irq(2, &irq2);
+ change_cp0_status(ST0_IM, 0);
+ setup_irq(2, &irq2);
- cli();
+ cli();
- change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
+ change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1);
- /* Setup VIA irq mask */
- VIA_PORT_WRITE(0x20, 0x10);
- VIA_PORT_WRITE(0x21, 0x00);
- VIA_PORT_WRITE(0x21, 0x00);
+ /* Setup VIA irq mask */
+ VIA_PORT_WRITE(0x20, 0x10);
+ VIA_PORT_WRITE(0x21, 0x00);
+ VIA_PORT_WRITE(0x21, 0x00);
- VIA_PORT_WRITE(0xa0, 0x10);
- VIA_PORT_WRITE(0xa1, 0x00);
- VIA_PORT_WRITE(0xa1, 0x00);
+ VIA_PORT_WRITE(0xa0, 0x10);
+ VIA_PORT_WRITE(0xa1, 0x00);
+ VIA_PORT_WRITE(0xa1, 0x00);
}
#define GALILEO_T0_VAL 0xb4000850
@@ -96,40 +96,40 @@
static void __init cobalt_calibrate_timer(void)
{
- volatile unsigned long *timer_reg = (volatile unsigned long *)GALILEO_T0_VAL;
+ volatile unsigned long *timer_reg = (volatile unsigned long *)GALILEO_T0_VAL;
- /* Default to 150MHZ, since this is what we are shipping. */
- *timer_reg = 500000;
+ /* Default to 150MHZ, since this is what we are shipping. */
+ *timer_reg = 500000;
}
static void __init cobalt_timer_setup(struct irqaction *irq)
{
- /* Load timer value for 150 Hz */
- cobalt_calibrate_timer();
+ /* Load timer value for 150 Hz */
+ cobalt_calibrate_timer();
- setup_irq(0, irq);
+ setup_irq(0, irq);
- change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
+ change_cp0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1 | IE_IRQ0);
- /* Enable timer ints */
- *((volatile unsigned long *) GALILEO_TIMER_CTRL) =
- (unsigned long) (GALILEO_ENTC0 | GALILEO_SELTC0);
- /* Unmask timer int */
- *((volatile unsigned long *) GALILEO_CPU_MASK) = (unsigned long) 0x00000100;
+ /* Enable timer ints */
+ *((volatile unsigned long *) GALILEO_TIMER_CTRL) =
+ (unsigned long) (GALILEO_ENTC0 | GALILEO_SELTC0);
+ /* Unmask timer int */
+ *((volatile unsigned long *) GALILEO_CPU_MASK) = (unsigned long) 0x00000100;
}
static void __init cobalt_time_init(void)
{
- //mips_counter_frequency = 83000000;
+ //mips_counter_frequency = 83000000;
- /* we have ds1396 RTC chip */
- rtc_dallas_init(0x70);
+ /* we have ds1396 RTC chip */
+ rtc_dallas_init(0x70);
- /* optional: we don't have a good way to set RTC time,
- * so we will hack here to set a time. In normal running.
- * it should *not* be called becaues RTC will keep the correct time.
- */
- /* rtc_set_time(mktime(2001, 10, 05, 17, 20, 0)); */
+ /* optional: we don't have a good way to set RTC time,
+ * so we will hack here to set a time. In normal running.
+ * it should *not* be called becaues RTC will keep the correct time.
+ */
+ /* rtc_set_time(mktime(2001, 10, 05, 17, 20, 0)); */
}
int cobalt_serial_present;
@@ -147,39 +147,38 @@
iomem_resource.start = 0;
ioport_resource.end = 0xffffffff;
- _machine_restart = cobalt_machine_restart;
- _machine_halt = cobalt_machine_halt;
- _machine_power_off = cobalt_machine_power_off;
+ _machine_restart = cobalt_machine_restart;
+ _machine_halt = cobalt_machine_halt;
+ _machine_power_off = cobalt_machine_power_off;
board_time_init = cobalt_time_init;
board_timer_setup = cobalt_timer_setup;
rtc_ops = &cobalt_rtc_ops;
#ifdef CONFIG_BLK_DEV_IDE
- ide_ops = &cobalt_ide_ops;
+ ide_ops = &cobalt_ide_ops;
#endif
- /*ns16550_setup_console();*/
-
- /* We have to do this early, here, before the value could
- * possibly be overwritten by the bootup sequence.
- */
+ /*ns16550_setup_console();*/
- cobalt_serial_present = *((unsigned long *) 0xa020001c);
- cobalt_serial_type = *((unsigned long *) 0xa0200020);
- cobalt_is_raq = (cobalt_serial_present != 0x0
- && cobalt_serial_type == 0x1);
+ /* We have to do this early, here, before the value could
+ * possibly be overwritten by the bootup sequence.
+ */
+ cobalt_serial_present = *((unsigned long *) 0xa020001c);
+ cobalt_serial_type = *((unsigned long *) 0xa0200020);
+ cobalt_is_raq = (cobalt_serial_present != 0x0
+ && cobalt_serial_type == 0x1);
}
/* prom_init() is called just after the cpu type is determined, from
init_arch(). */
void __init prom_init(int argc, char **arg)
{
- mips_machgroup = MACH_GROUP_COBALT;
+ mips_machgroup = MACH_GROUP_COBALT;
- add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
+ add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
}
void __init prom_free_prom_memory(void)
{
- /* Something to do here?? */
+ /* Something to do here?? */
}
|
|
From: James S. <jsi...@us...> - 2001-10-26 16:50:05
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv21891
Modified Files:
config.in
Log Message:
Moved cobalt over to new time.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.37
retrieving revision 1.38
diff -u -d -r1.37 -r1.38
--- config.in 2001/10/25 21:39:47 1.37
+++ config.in 2001/10/26 16:50:01 1.38
@@ -246,7 +246,7 @@
define_bool CONFIG_COBALT_LCD y
define_bool CONFIG_PCI y
define_bool CONFIG_NEW_PCI y
- define_bool CONFIG_OLD_TIME_C y
+ define_bool CONFIG_NEW_TIME_C y
fi
if [ "$CONFIG_NINO" = "y" ]; then
define_bool CONFIG_PC_KEYB y
|
|
From: James S. <jsi...@us...> - 2001-10-26 16:48:26
|
Update of /cvsroot/linux-mips/linux/arch/mips/cobalt In directory usw-pr-cvs1:/tmp/cvs-serv21340 Modified Files: Makefile Removed Files: rtc_dallas.c Log Message: Moved the new RTC Dallas standard using the new time code here. This will allow any mips device using a RTC PC style chip still using the old time standard to migrate with almost no change in code :-) Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/cobalt/Makefile,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- Makefile 2001/10/25 23:58:08 1.7 +++ Makefile 2001/10/26 16:48:24 1.8 @@ -16,7 +16,7 @@ O_TARGET := cobalt.o -obj-y += rtc_dallas.o rtc_qube.o irq.o int-handler.o pci_fixups.o pci_ops.o \ +obj-y += rtc_qube.o irq.o int-handler.o pci_fixups.o pci_ops.o \ reset.o setup.o via.o promcon.o ide.o include $(TOPDIR)/Rules.make --- rtc_dallas.c DELETED --- |
|
From: James S. <jsi...@us...> - 2001-10-26 16:47:47
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv21086
Modified Files:
Makefile
Added Files:
rtc_dallas.c
Log Message:
Moved the new RTC Dallas standard using the new time code here. This will allow any mips device using a RTC PC style chip still using the old time standard to migrate with almost no change in code :-)
--- NEW FILE: rtc_dallas.c ---
/*
* Copyright 2001 James Simmons. jsi...@tr...
*
* arch/mips/kernel/rtc_dallas.c
* low-level RTC hookups for Dallas PC style chip.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* This file exports a function, rtc_dallas_init(), which expects an
* uncached base address as the argument. It will set the two function
* pointers expected by the MIPS generic timer code.
*/
#include <linux/types.h>
#include <linux/time.h>
#include <asm/time.h>
#include <asm/addrspace.h>
#include <asm/debug.h>
#include <linux/mc146818rtc.h>
#define EPOCH 2000
#undef BCD_TO_BIN
#define BCD_TO_BIN(val) (((val)&15) + ((val)>>4)*10)
#undef BIN_TO_BCD
#define BIN_TO_BCD(val) ((((val)/10)<<4) + (val)%10)
static unsigned long rtc_base;
#define READ_RTC(x) rtc_ops->rtc_read_data(x)
#define WRITE_RTC(x, y) rtc_ops->rtc_write_data(y, x)
static unsigned long
rtc_dallas_get_time(void)
{
unsigned int year, month, day, hour, minute, second;
u8 byte, temp;
/* let us freeze external registers */
byte = READ_RTC(0xB);
byte &= 0x3f;
WRITE_RTC(0xB, byte);
/* read time data */
year = BCD_TO_BIN(READ_RTC(0xA)) + EPOCH;
month = BCD_TO_BIN(READ_RTC(0x9) & 0x1f);
day = BCD_TO_BIN(READ_RTC(0x8));
minute = BCD_TO_BIN(READ_RTC(0x2));
second = BCD_TO_BIN(READ_RTC(0x1));
/* hour is special - deal with it later */
temp = READ_RTC(0x4);
/* enable time transfer */
byte |= 0x80;
WRITE_RTC(0xB, byte);
/* calc hour */
if (temp & 0x40) {
/* 12 hour format */
hour = BCD_TO_BIN(temp & 0x1f);
if (temp & 0x20) hour += 12; /* PM */
} else {
/* 24 hour format */
hour = BCD_TO_BIN(temp & 0x3f);
}
return mktime(year, month, day, hour, minute, second);
}
static int
rtc_dallas_set_time(unsigned long t)
{
struct rtc_time tm;
u8 year, month, day, hour, minute, second;
u8 byte, temp;
/* let us freeze external registers */
byte = READ_RTC(0xB);
byte &= 0x3f;
WRITE_RTC(0xB, byte);
/* convert */
to_tm(t, &tm);
/* check each field one by one */
year = BIN_TO_BCD(tm.tm_year - EPOCH);
if (year != READ_RTC(0xA)) {
WRITE_RTC(0xA, year);
}
temp = READ_RTC(0x9);
month = BIN_TO_BCD(tm.tm_mon);
if (month != (temp & 0x1f)) {
WRITE_RTC( 0x9,
(month & 0x1f) | (temp & ~0x1f) );
}
day = BIN_TO_BCD(tm.tm_mday);
if (day != READ_RTC(0x8)) {
WRITE_RTC(0x8, day);
}
temp = READ_RTC(0x4);
if (temp & 0x40) {
/* 12 hour format */
hour = 0x40;
if (tm.tm_hour > 12) {
hour |= 0x20 | (BIN_TO_BCD(hour-12) & 0x1f);
} else {
hour |= BIN_TO_BCD(tm.tm_hour);
}
} else {
/* 24 hour format */
hour = BIN_TO_BCD(tm.tm_hour) & 0x3f;
}
if (hour != temp) WRITE_RTC(0x4, hour);
minute = BIN_TO_BCD(tm.tm_min);
if (minute != READ_RTC(0x2)) {
WRITE_RTC(0x2, minute);
}
second = BIN_TO_BCD(tm.tm_sec);
if (second != READ_RTC(0x1)) {
WRITE_RTC(0x1, second);
}
return 0;
}
void
rtc_dallas_init(unsigned long base)
{
unsigned char byte;
/* remember the base */
rtc_base = base;
db_assert((rtc_base & 0xe0000000) == KSEG1);
/* turn on RTC if it is not on */
byte = READ_RTC(0x9);
if (byte & 0x80) {
byte &= 0x7f;
WRITE_RTC(0x9, byte);
}
/* enable time transfer */
byte = READ_RTC(0xB);
byte |= 0x80;
WRITE_RTC(0xB, byte);
/* set the function pointers */
rtc_get_time = rtc_dallas_get_time;
rtc_set_time = rtc_dallas_set_time;
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Makefile,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- Makefile 2001/10/24 05:28:03 1.12
+++ Makefile 2001/10/26 16:47:44 1.13
@@ -192,6 +192,7 @@
obj-$(CONFIG_ADBMOUSE) += adbmouse.o
obj-$(CONFIG_PC110_PAD) += pc110pad.o
obj-$(CONFIG_RTC) += rtc.o
+obj-$(CONFIG_NEW_TIME_C) += rtc_dallas.o
obj-$(CONFIG_EFI_RTC) += efirtc.o
ifeq ($(CONFIG_PPC),)
obj-$(CONFIG_NVRAM) += nvram.o
|
|
From: James S. <jsi...@us...> - 2001-10-26 16:38:05
|
Update of /cvsroot/linux-mips/linux/arch/mips In directory usw-pr-cvs1:/tmp/cvs-serv15722 Modified Files: defconfig Log Message: Rebuild. Index: defconfig =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/defconfig,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig 2001/10/19 21:19:37 1.11 +++ defconfig 2001/10/26 16:38:03 1.12 @@ -63,10 +63,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set |
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv15632 Modified Files: defconfig-atlas defconfig-cobalt defconfig-ddb5476 defconfig-ddb5477 defconfig-decstation defconfig-eagle defconfig-ev64120 defconfig-ev96100 defconfig-ip22 defconfig-it8172 defconfig-korva defconfig-malta defconfig-nino defconfig-ocelot defconfig-osprey defconfig-pb1000 defconfig-rm200 Log Message: Rebuild. Index: defconfig-atlas =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-atlas,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig-atlas 2001/10/19 21:19:37 1.8 +++ defconfig-atlas 2001/10/26 16:37:55 1.9 @@ -56,10 +56,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-cobalt =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-cobalt,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- defconfig-cobalt 2001/10/19 21:19:37 1.9 +++ defconfig-cobalt 2001/10/26 16:37:55 1.10 @@ -64,10 +64,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-ddb5476 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ddb5476,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig-ddb5476 2001/10/19 21:19:37 1.11 +++ defconfig-ddb5476 2001/10/26 16:37:55 1.12 @@ -63,10 +63,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set CONFIG_CPU_R5432=y # CONFIG_CPU_R5900 is not set Index: defconfig-ddb5477 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ddb5477,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- defconfig-ddb5477 2001/10/19 21:19:38 1.10 +++ defconfig-ddb5477 2001/10/26 16:37:55 1.11 @@ -61,10 +61,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set CONFIG_CPU_R5432=y # CONFIG_CPU_R5900 is not set Index: defconfig-decstation =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-decstation,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- defconfig-decstation 2001/10/19 21:19:38 1.9 +++ defconfig-decstation 2001/10/26 16:37:55 1.10 @@ -57,10 +57,12 @@ # CPU selection # CONFIG_CPU_R3000=y +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-eagle =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-eagle,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- defconfig-eagle 2001/10/19 21:19:38 1.7 +++ defconfig-eagle 2001/10/26 16:37:55 1.8 @@ -61,10 +61,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-ev64120 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ev64120,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig-ev64120 2001/10/19 21:19:38 1.8 +++ defconfig-ev64120 2001/10/26 16:37:55 1.9 @@ -64,10 +64,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-ev96100 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ev96100,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- defconfig-ev96100 2001/10/19 21:19:38 1.9 +++ defconfig-ev96100 2001/10/26 16:37:55 1.10 @@ -61,10 +61,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-ip22 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ip22,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- defconfig-ip22 2001/10/19 21:19:38 1.9 +++ defconfig-ip22 2001/10/26 16:37:55 1.10 @@ -63,10 +63,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set CONFIG_CPU_R5000=y # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-it8172 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-it8172,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- defconfig-it8172 2001/10/19 21:19:38 1.10 +++ defconfig-it8172 2001/10/26 16:37:55 1.11 @@ -63,10 +63,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-korva =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-korva,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- defconfig-korva 2001/10/19 21:19:38 1.4 +++ defconfig-korva 2001/10/26 16:37:55 1.5 @@ -63,10 +63,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set CONFIG_CPU_VR41XX=y # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-malta =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-malta,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig-malta 2001/10/19 21:19:38 1.8 +++ defconfig-malta 2001/10/26 16:37:55 1.9 @@ -58,10 +58,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-nino =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-nino,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- defconfig-nino 2001/10/19 21:19:38 1.9 +++ defconfig-nino 2001/10/26 16:37:55 1.10 @@ -61,10 +61,12 @@ # CPU selection # CONFIG_CPU_R3000=y +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-ocelot =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-ocelot,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig-ocelot 2001/10/19 21:19:38 1.8 +++ defconfig-ocelot 2001/10/26 16:37:55 1.9 @@ -59,10 +59,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-osprey =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-osprey,v retrieving revision 1.7 retrieving revision 1.8 diff -u -d -r1.7 -r1.8 --- defconfig-osprey 2001/10/19 21:19:38 1.7 +++ defconfig-osprey 2001/10/26 16:37:55 1.8 @@ -66,10 +66,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set CONFIG_CPU_VR41XX=y # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-pb1000 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-pb1000,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- defconfig-pb1000 2001/10/19 21:19:38 1.10 +++ defconfig-pb1000 2001/10/26 16:37:55 1.11 @@ -62,10 +62,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set Index: defconfig-rm200 =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-rm200,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- defconfig-rm200 2001/10/19 21:19:38 1.8 +++ defconfig-rm200 2001/10/26 16:37:55 1.9 @@ -62,10 +62,12 @@ # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set CONFIG_CPU_R4X00=y +# CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set |
|
From: James S. <jsi...@us...> - 2001-10-26 16:13:58
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32
In directory usw-pr-cvs1:/tmp/cvs-serv32140
Modified Files:
Makefile ip32-irq.c ip32-pci-dma.c ip32-pci.c ip32-setup.c
ip32-timer.c
Added Files:
ip32-reset.c
Log Message:
O2 updates.
--- NEW FILE: ip32-reset.c ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 Keith M Wesolowski
*/
#include <asm/promlib.h>
/* linux/reboot.h */
void machine_restart (char *cmd) {
ArcReboot (cmd);
}
void machine_halt (void) {
ArcEnterInteractiveMode();
}
void machine_power_off (void) {
ArcPowerDown();
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 2001/08/24 19:01:26 1.1
+++ Makefile 2001/10/26 16:13:55 1.2
@@ -18,7 +18,7 @@
all: ip32-kern.a ip32-irq-glue.o
obj-y += ip32-irq.o ip32-rtc.o ip32-setup.o ip32-irq-glue.o \
- ip32-berr.o ip32-timer.o crime.o
+ ip32-berr.o ip32-timer.o crime.o ip32-reset.o
ifdef CONFIG_PCI
obj-y += ip32-pci.o ip32-pci-dma.o
Index: ip32-irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-irq.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- ip32-irq.c 2001/08/24 19:01:26 1.1
+++ ip32-irq.c 2001/10/26 16:13:55 1.2
@@ -23,6 +23,12 @@
#include <asm/ip32/mace.h>
#include <asm/signal.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/random.h>
+#include <linux/sched.h>
+
#undef DEBUG_IRQ
#ifdef DEBUG_IRQ
#define DBG(x...) printk(x)
@@ -112,15 +118,50 @@
unsigned long spurious_count = 0;
extern void ip32_handle_int (void);
-extern void do_IRQ (unsigned int irq, struct pt_regs *regs);
+asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
+
+static void enable_none(unsigned int irq) { }
+static unsigned int startup_none(unsigned int irq) { return 0; }
+static void disable_none(unsigned int irq) { }
+static void ack_none(unsigned int irq)
+{
+ /*
+ * 'what should we do if we get a hw irq event on an illegal vector'.
+ * each architecture has to answer this themselves, it doesnt deserve
+ * a generic callback i think.
+ */
+ printk("unexpected interrupt %d\n", irq);
+}
+
+/* startup is the same as "enable", shutdown is same as "disable" */
+#define shutdown_none disable_none
+#define end_none enable_none
+
+struct hw_interrupt_type no_irq_type = {
+ "none",
+ startup_none,
+ shutdown_none,
+ enable_none,
+ disable_none,
+ ack_none,
+ end_none
+};
+
+/*
+ * Controller mappings for all interrupt sources:
+ */
+irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned =
+ { [0 ... NR_IRQS-1] = { 0, &no_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
+
+
/* For interrupts wired from a single device to the CPU. Only the clock
* uses this it seems, which is IRQ 0 and IP7.
*/
static void enable_cpu_irq (unsigned int irq)
{
- set_cp0_status (STATUSF_IP7);
+ set_cp0_status (STATUSF_IP7,~ST0_CU1);
}
static unsigned int startup_cpu_irq (unsigned int irq) {
@@ -460,11 +501,11 @@
while (1) ;
}
-void __init ip32_irq_init(void)
+void __init init_IRQ(void)
{
unsigned int irq;
- extern void init_generic_irq (void);
-
+ int i;
+
/* Install our interrupt handler, then clear and disable all
* CRIME and MACE interrupts.
*/
@@ -475,7 +516,12 @@
mace_write_32 (MACEISA_INT_MASK, 0);
set_except_vector(0, ip32_handle_int);
- init_generic_irq ();
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].action = NULL;
+ irq_desc[i].depth = 1;
+ irq_desc[i].handler = &no_irq_type;
+ }
for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
hw_irq_controller *controller;
@@ -554,3 +600,634 @@
{
do_IRQ (CLOCK_IRQ, regs);
}
+
+volatile unsigned long irq_err_count, spurious_count;
+
+/*
+ * Generic, controller-independent functions:
+ */
+
+int get_irq_list(char *buf)
+{
+ struct irqaction * action;
+ char *p = buf;
+ int i;
+
+ p += sprintf(p, " ");
+ for (i=0; i < 1 /*smp_num_cpus*/; i++)
+ p += sprintf(p, "CPU%d ", i);
+ *p++ = '\n';
+
+ for (i = 0 ; i < NR_IRQS ; i++) {
+ action = irq_desc[i].action;
+ if (!action)
+ continue;
+ p += sprintf(p, "%3d: ",i);
+ p += sprintf(p, "%10u ", kstat_irqs(i));
+ p += sprintf(p, " %14s", irq_desc[i].handler->typename);
+ p += sprintf(p, " %s", action->name);
+
+ for (action=action->next; action; action = action->next)
+ p += sprintf(p, ", %s", action->name);
+ *p++ = '\n';
+ }
+ p += sprintf(p, "ERR: %10lu\n", irq_err_count);
+ return p - buf;
+}
+
+/* this was setup_x86_irq but it seems pretty generic */
+int setup_irq(unsigned int irq, struct irqaction * new)
+{
+ int shared = 0;
+ unsigned long flags;
+ struct irqaction *old, **p;
+ irq_desc_t *desc = irq_desc + irq;
+
+ /*
+ * Some drivers like serial.c use request_irq() heavily,
+ * so we have to be careful not to interfere with a
+ * running system.
+ */
+ if (new->flags & SA_SAMPLE_RANDOM) {
+ /*
+ * This function might sleep, we want to call it first,
+ * outside of the atomic block.
+ * Yes, this might clear the entropy pool if the wrong
+ * driver is attempted to be loaded, without actually
+ * installing a new handler, but is this really a problem,
+ * only the sysadmin is able to do this.
+ */
+ rand_initialize_irq(irq);
+ }
+
+ /*
+ * The following block of code has to be executed atomically
+ */
+ spin_lock_irqsave(&desc->lock,flags);
+ p = &desc->action;
+ if ((old = *p) != NULL) {
+ /* Can't share interrupts unless both agree to */
+ if (!(old->flags & new->flags & SA_SHIRQ)) {
+ spin_unlock_irqrestore(&desc->lock,flags);
+ return -EBUSY;
+ }
+
+ /* add new interrupt at end of irq queue */
+ do {
+ p = &old->next;
+ old = *p;
+ } while (old);
+ shared = 1;
+ }
+
+ *p = new;
+
+ if (!shared) {
+ desc->depth = 0;
+ desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING);
+ desc->handler->startup(irq);
+ }
+ spin_unlock_irqrestore(&desc->lock,flags);
+
+ /* register_irq_proc(irq); */
+ return 0;
+}
+
+
+/**
+ * request_irq - allocate an interrupt line
+ * @irq: Interrupt line to allocate
+ * @handler: Function to be called when the IRQ occurs
+ * @irqflags: Interrupt type flags
+ * @devname: An ascii name for the claiming device
+ * @dev_id: A cookie passed back to the handler function
+ *
+ * This call allocates interrupt resources and enables the
+ * interrupt line and IRQ handling. From the point this
+ * call is made your handler function may be invoked. Since
+ * your handler function must clear any interrupt the board
+ * raises, you must take care both to initialise your hardware
+ * and to set up the interrupt handler in the right order.
+ *
+ * Dev_id must be globally unique. Normally the address of the
+ * device data structure is used as the cookie. Since the handler
+ * receives this value it makes sense to use it.
+ *
+ * If your interrupt is shared you must pass a non NULL dev_id
+ * as this is required when freeing the interrupt.
+ *
+ * Flags:
+ *
+ * SA_SHIRQ Interrupt is shared
+ *
+ * SA_INTERRUPT Disable local interrupts while processing
+ *
+ * SA_SAMPLE_RANDOM The interrupt can be used for entropy
+ *
+ */
+
+int request_irq(unsigned int irq,
+ void (*handler)(int, void *, struct pt_regs *),
+ unsigned long irqflags,
+ const char * devname,
+ void *dev_id)
+{
+ int retval;
+ struct irqaction * action;
+
+#if 1
+ /*
+ * Sanity-check: shared interrupts should REALLY pass in
+ * a real dev-ID, otherwise we'll have trouble later trying
+ * to figure out which interrupt is which (messes up the
+ * interrupt freeing logic etc).
+ */
+ if (irqflags & SA_SHIRQ) {
+ if (!dev_id)
+ printk("Bad boy: %s (at 0x%x) called us without a dev_id!\n", devname, (&irq)[-1]);
+ }
+#endif
+
+ if (irq >= NR_IRQS)
+ return -EINVAL;
+ if (!handler)
+ return -EINVAL;
+
+ action = (struct irqaction *)
+ kmalloc(sizeof(struct irqaction), GFP_KERNEL);
+ if (!action)
+ return -ENOMEM;
+
+ action->handler = handler;
+ action->flags = irqflags;
+ action->mask = 0;
+ action->name = devname;
+ action->next = NULL;
+ action->dev_id = dev_id;
+
+ retval = setup_irq(irq, action);
+ if (retval)
+ kfree(action);
+ return retval;
+}
+
+/**
+ * free_irq - free an interrupt
+ * @irq: Interrupt line to free
+ * @dev_id: Device identity to free
+ *
+ * Remove an interrupt handler. The handler is removed and if the
+ * interrupt line is no longer in use by any driver it is disabled.
+ * On a shared IRQ the caller must ensure the interrupt is disabled
+ * on the card it drives before calling this function. The function
+ * does not return until any executing interrupts for this IRQ
+ * have completed.
+ *
+ * This function may be called from interrupt context.
+ *
+ * Bugs: Attempting to free an irq in a handler for the same irq hangs
+ * the machine.
+ */
+
+void free_irq(unsigned int irq, void *dev_id)
+{
+ irq_desc_t *desc;
+ struct irqaction **p;
+ unsigned long flags;
+
+ if (irq >= NR_IRQS)
+ return;
+
+ desc = irq_desc + irq;
+ spin_lock_irqsave(&desc->lock,flags);
+ p = &desc->action;
+ for (;;) {
+ struct irqaction * action = *p;
+ if (action) {
+ struct irqaction **pp = p;
+ p = &action->next;
+ if (action->dev_id != dev_id)
+ continue;
+
+ /* Found it - now remove it from the list of entries */
+ *pp = action->next;
+ if (!desc->action) {
+ desc->status |= IRQ_DISABLED;
+ desc->handler->shutdown(irq);
+ }
+ spin_unlock_irqrestore(&desc->lock,flags);
+
+#ifdef CONFIG_SMP
+ /* Wait to make sure it's not being used on another CPU */
+ while (desc->status & IRQ_INPROGRESS)
+ barrier();
+#endif
+ kfree(action);
+ return;
+ }
+ printk("Trying to free free IRQ%d\n",irq);
+ spin_unlock_irqrestore(&desc->lock,flags);
+ return;
+ }
+}
+/*
+ * IRQ autodetection code..
+ *
+ * This depends on the fact that any interrupt that
+ * comes in on to an unassigned handler will get stuck
+ * with "IRQ_WAITING" cleared and the interrupt
+ * disabled.
+ */
+
+static DECLARE_MUTEX(probe_sem);
+
+/**
+ * probe_irq_on - begin an interrupt autodetect
+ *
+ * Commence probing for an interrupt. The interrupts are scanned
+ * and a mask of potential interrupt lines is returned.
+ *
+ */
+
+unsigned long probe_irq_on(void)
+{
+ unsigned int i;
+ irq_desc_t *desc;
+ unsigned long val;
+ unsigned long delay;
+
+ down(&probe_sem);
+ /*
+ * something may have generated an irq long ago and we want to
+ * flush such a longstanding irq before considering it as spurious.
+ */
+ for (i = NR_IRQS-1; i > 0; i--) {
+ desc = irq_desc + i;
+
+ spin_lock_irq(&desc->lock);
+ if (!irq_desc[i].action)
+ irq_desc[i].handler->startup(i);
+ spin_unlock_irq(&desc->lock);
+ }
+
+ /* Wait for longstanding interrupts to trigger. */
+ for (delay = jiffies + HZ/50; time_after(delay, jiffies); )
+ /* about 20ms delay */ synchronize_irq();
+
+ /*
+ * enable any unassigned irqs
+ * (we must startup again here because if a longstanding irq
+ * happened in the previous stage, it may have masked itself)
+ */
+ for (i = NR_IRQS-1; i > 0; i--) {
+ desc = irq_desc + i;
+
+ spin_lock_irq(&desc->lock);
+ if (!desc->action) {
+ desc->status |= IRQ_AUTODETECT | IRQ_WAITING;
+ if (desc->handler->startup(i))
+ desc->status |= IRQ_PENDING;
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+
+ /*
+ * Wait for spurious interrupts to trigger
+ */
+ for (delay = jiffies + HZ/10; time_after(delay, jiffies); )
+ /* about 100ms delay */ synchronize_irq();
+
+ /*
+ * Now filter out any obviously spurious interrupts
+ */
+ val = 0;
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc_t *desc = irq_desc + i;
+ unsigned int status;
+
+ spin_lock_irq(&desc->lock);
+ status = desc->status;
+
+ if (status & IRQ_AUTODETECT) {
+ /* It triggered already - consider it spurious. */
+ if (!(status & IRQ_WAITING)) {
+ desc->status = status & ~IRQ_AUTODETECT;
+ desc->handler->shutdown(i);
+ } else
+ if (i < 32)
+ val |= 1 << i;
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+
+ return val;
+}
+
+/*
+ * Return a mask of triggered interrupts (this
+ * can handle only legacy ISA interrupts).
+ */
+
+/**
+ * probe_irq_mask - scan a bitmap of interrupt lines
+ * @val: mask of interrupts to consider
+ *
+ * Scan the ISA bus interrupt lines and return a bitmap of
+ * active interrupts. The interrupt probe logic state is then
+ * returned to its previous value.
+ *
+ * Note: we need to scan all the irq's even though we will
+ * only return ISA irq numbers - just so that we reset them
+ * all to a known state.
+ */
+unsigned int probe_irq_mask(unsigned long val)
+{
+ int i;
+ unsigned int mask;
+
+ mask = 0;
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc_t *desc = irq_desc + i;
+ unsigned int status;
+
+ spin_lock_irq(&desc->lock);
+ status = desc->status;
+
+ if (status & IRQ_AUTODETECT) {
+ if (i < 16 && !(status & IRQ_WAITING))
+ mask |= 1 << i;
+
+ desc->status = status & ~IRQ_AUTODETECT;
+ desc->handler->shutdown(i);
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+ up(&probe_sem);
+
+ return mask & val;
+}
+
+/*
+ * Return the one interrupt that triggered (this can
+ * handle any interrupt source).
+ */
+
+/**
+ * probe_irq_off - end an interrupt autodetect
+ * @val: mask of potential interrupts (unused)
+ *
+ * Scans the unused interrupt lines and returns the line which
+ * appears to have triggered the interrupt. If no interrupt was
+ * found then zero is returned. If more than one interrupt is
+ * found then minus the first candidate is returned to indicate
+ * their is doubt.
+ *
+ * The interrupt probe logic state is returned to its previous
+ * value.
+ *
+ * BUGS: When used in a module (which arguably shouldnt happen)
+ * nothing prevents two IRQ probe callers from overlapping. The
+ * results of this are non-optimal.
+ */
+
+int probe_irq_off(unsigned long val)
+{
+ int i, irq_found, nr_irqs;
+
+ nr_irqs = 0;
+ irq_found = 0;
+ for (i = 0; i < NR_IRQS; i++) {
+ irq_desc_t *desc = irq_desc + i;
+ unsigned int status;
+
+ spin_lock_irq(&desc->lock);
+ status = desc->status;
+
+ if (status & IRQ_AUTODETECT) {
+ if (!(status & IRQ_WAITING)) {
+ if (!nr_irqs)
+ irq_found = i;
+ nr_irqs++;
+ }
+ desc->status = status & ~IRQ_AUTODETECT;
+ desc->handler->shutdown(i);
+ }
+ spin_unlock_irq(&desc->lock);
+ }
+ up(&probe_sem);
+
+ if (nr_irqs > 1)
+ irq_found = -irq_found;
+ return irq_found;
+}
+
+/*
+ * This should really return information about whether
+ * we should do bottom half handling etc. Right now we
+ * end up _always_ checking the bottom half, which is a
+ * waste of time and is not what some drivers would
+ * prefer.
+ */
+int handle_IRQ_event(unsigned int irq, struct pt_regs * regs, struct irqaction * action)
+{
+ int status;
+ int cpu = smp_processor_id();
+
+ irq_enter(cpu, irq);
+
+ status = 1; /* Force the "do bottom halves" bit */
+
+ if (!(action->flags & SA_INTERRUPT))
+ __sti();
+
+ do {
+ status |= action->flags;
+ action->handler(irq, action->dev_id, regs);
+ action = action->next;
+ } while (action);
+ if (status & SA_SAMPLE_RANDOM)
+ add_interrupt_randomness(irq);
+ __cli();
+
+ irq_exit(cpu, irq);
+
+ return status;
+}
+
+/*
+ * Generic enable/disable code: this just calls
+ * down into the PIC-specific version for the actual
+ * hardware disable after having gotten the irq
+ * controller lock.
+ */
+
+/**
+ * disable_irq_nosync - disable an irq without waiting
+ * @irq: Interrupt to disable
+ *
+ * Disable the selected interrupt line. Disables of an interrupt
+ * stack. Unlike disable_irq(), this function does not ensure existing
+ * instances of the IRQ handler have completed before returning.
+ *
+ * This function may be called from IRQ context.
+ */
+
+void inline disable_irq_nosync(unsigned int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&desc->lock, flags);
+ if (!desc->depth++) {
+ desc->status |= IRQ_DISABLED;
+ desc->handler->disable(irq);
+ }
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+/**
+ * disable_irq - disable an irq and wait for completion
+ * @irq: Interrupt to disable
+ *
+ * Disable the selected interrupt line. Disables of an interrupt
+ * stack. That is for two disables you need two enables. This
+ * function waits for any pending IRQ handlers for this interrupt
+ * to complete before returning. If you use this function while
+ * holding a resource the IRQ handler may need you will deadlock.
+ *
+ * This function may be called - with care - from IRQ context.
+ */
+
+void disable_irq(unsigned int irq)
+{
+ disable_irq_nosync(irq);
+
+ if (!local_irq_count(smp_processor_id())) {
+ do {
+ barrier();
+ } while (irq_desc[irq].status & IRQ_INPROGRESS);
+ }
+}
+
+/**
+ * enable_irq - enable interrupt handling on an irq
+ * @irq: Interrupt to enable
+ *
+ * Re-enables the processing of interrupts on this IRQ line
+ * providing no disable_irq calls are now in effect.
+ *
+ * This function may be called from IRQ context.
+ */
+
+void enable_irq(unsigned int irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&desc->lock, flags);
+ switch (desc->depth) {
+ case 1: {
+ unsigned int status = desc->status & ~IRQ_DISABLED;
+ desc->status = status;
+ if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) {
+ desc->status = status | IRQ_REPLAY;
+ }
+ desc->handler->enable(irq);
+ /* fall-through */
+ }
+ default:
+ desc->depth--;
+ break;
+ case 0:
+ printk("enable_irq(%u) unbalanced from %p\n", irq,
+ __builtin_return_address(0));
+ }
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+/*
+ * do_IRQ handles all normal device IRQ's (the special
+ * SMP cross-CPU interrupts have their own specific
+ * handlers).
+ */
+asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs)
+{
+ /*
+ * We ack quickly, we don't want the irq controller
+ * thinking we're snobs just because some other CPU has
+ * disabled global interrupts (we have already done the
+ * INT_ACK cycles, it's too late to try to pretend to the
+ * controller that we aren't taking the interrupt).
+ *
+ * 0 return value means that this irq is already being
+ * handled by some other CPU. (or is disabled)
+ */
+ int cpu = smp_processor_id();
+ irq_desc_t *desc = irq_desc + irq;
+ struct irqaction * action;
+ unsigned int status;
+
+ kstat.irqs[cpu][irq]++;
+ spin_lock(&desc->lock);
+ desc->handler->ack(irq);
+ /*
+ REPLAY is when Linux resends an IRQ that was dropped earlier
+ WAITING is used by probe to mark irqs that are being tested
+ */
+ status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING);
+ status |= IRQ_PENDING; /* we _want_ to handle it */
+
+ /*
+ * If the IRQ is disabled for whatever reason, we cannot
+ * use the action we have.
+ */
+ action = NULL;
+ if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
+ action = desc->action;
+ status &= ~IRQ_PENDING; /* we commit to handling */
+ status |= IRQ_INPROGRESS; /* we are handling it */
+ }
+ desc->status = status;
+
+ /*
+ * If there is no IRQ handler or it was disabled, exit early.
+ Since we set PENDING, if another processor is handling
+ a different instance of this same irq, the other processor
+ will take care of it.
+ */
+ if (!action)
+ goto out;
+
+ /*
+ * Edge triggered interrupts need to remember
+ * pending events.
+ * This applies to any hw interrupts that allow a second
+ * instance of the same irq to arrive while we are in do_IRQ
+ * or in the handler. But the code here only handles the _second_
+ * instance of the irq, not the third or fourth. So it is mostly
+ * useful for irq hardware that does not mask cleanly in an
+ * SMP environment.
+ */
+ for (;;) {
+ spin_unlock(&desc->lock);
+ handle_IRQ_event(irq, regs, action);
+ spin_lock(&desc->lock);
+
+ if (!(desc->status & IRQ_PENDING))
+ break;
+ desc->status &= ~IRQ_PENDING;
+ }
+ desc->status &= ~IRQ_INPROGRESS;
+out:
+ /*
+ * The ->end() handler has to deal with interrupts which got
+ * disabled while the handler was running.
+ */
+ desc->handler->end(irq);
+ spin_unlock(&desc->lock);
+
+ if (softirq_pending(cpu))
+ do_softirq();
+ return 1;
+}
+
Index: ip32-pci-dma.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-pci-dma.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- ip32-pci-dma.c 2001/09/04 16:04:16 1.2
+++ ip32-pci-dma.c 2001/10/26 16:13:55 1.3
@@ -29,7 +29,7 @@
if (ret != NULL) {
memset(ret, 0, size);
dma_cache_wback_inv((unsigned long) ret, size);
- *dma_handle = virt_to_bus(ret);
+ *dma_handle = KDM_TO_PHYS(ret);
}
return ret;
}
@@ -37,5 +37,46 @@
void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
- free_pages((unsigned long) vaddr, get_order(size));
+ free_pages((unsigned long) PHYS_TO_K0(vaddr), get_order(size));
}
+
+
+/*
+dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size,
+ int direction)
+{
+ if (direction == PCI_DMA_NONE)
+ BUG();
+
+}
+void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
+ size_t size, int direction)
+{
+ if (direction == PCI_DMA_NONE)
+ BUG();
+}
+int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents,
+ int direction)
+{
+ if (direction == PCI_DMA_NONE)
+ BUG();
+}
+void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+ int nents, int direction)
+{
+ if (direction == PCI_DMA_NONE)
+ BUG();
+}
+void pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle,
+ size_t size, int direction)
+{
+ if (direction == PCI_DMA_NONE)
+ BUG();
+}
+void pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+ int nelems, int direction)
+{
+ if (direction == PCI_DMA_NONE)
+ BUG();
+}
+*/
Index: ip32-pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-pci.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- ip32-pci.c 2001/08/24 19:01:26 1.1
+++ ip32-pci.c 2001/10/26 16:13:55 1.2
@@ -436,3 +436,7 @@
& ~MACEPCI_ERROR_INTERRUPT_TEST);
}
}
+unsigned __init int pcibios_assign_all_busses(void)
+{
+ return 0;
+}
Index: ip32-setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-setup.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- ip32-setup.c 2001/08/24 19:01:26 1.1
+++ ip32-setup.c 2001/10/26 16:13:55 1.2
@@ -25,8 +25,11 @@
extern struct rtc_ops ip32_rtc_ops;
extern u32 cc_interval;
+unsigned long mips_io_port_base = UNCACHEDADDR (MACEPCI_HI_IO);;
+
+
void __init ip32_init (int argc, char **argv, char **envp) {
- arc_meminit ();
+ prom_meminit ();
}
void __init ip32_setup(void)
Index: ip32-timer.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/ip32-timer.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- ip32-timer.c 2001/08/24 19:01:26 1.1
+++ ip32-timer.c 2001/10/26 16:13:55 1.2
@@ -15,11 +15,39 @@
#include <asm/ip32/crime.h>
#include <asm/ip32/ip32_ints.h>
-extern u32 cc_interval;
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/param.h>
+#include <linux/string.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <asm/bootinfo.h>
+#include <asm/cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <linux/mc146818rtc.h>
+#include <linux/timex.h>
+
+extern volatile unsigned long wall_jiffies;
+extern rwlock_t xtime_lock;
+
+u32 cc_interval;
+
+/* Cycle counter value at the previous timer interrupt.. */
+static unsigned int timerhi, timerlo;
+
/* An arbitrary time; this can be decreased if reliability looks good */
#define WAIT_MS 10
#define PER_MHZ (1000000 / 2 / HZ)
+/*
+ * Change this if you have some constant time drift
+ */
+#define USECS_PER_JIFFY (1000000/HZ)
+
void __init ip32_timer_setup (struct irqaction *irq) {
u64 crime_time;
@@ -44,4 +72,216 @@
printk("%d MHz CPU detected\n", (int) (cc_interval / PER_MHZ));
setup_irq (CLOCK_IRQ, irq);
+}
+
+struct irqaction irq0 = { NULL, SA_INTERRUPT, 0,
+ "timer", NULL, NULL};
+
+void cc_timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+ u32 count;
+
+ /*
+ * The cycle counter is only 32 bit which is good for about
+ * a minute at current count rates of upto 150MHz or so.
+ */
+ count = read_32bit_cp0_register(CP0_COUNT);
+ timerhi += (count < timerlo); /* Wrap around */
+ timerlo = count;
+
+ write_32bit_cp0_register (CP0_COMPARE,
+ (u32) (count + cc_interval));
+ kstat.irqs[0][irq]++;
+ do_timer (regs);
+
+ if (!jiffies)
+ {
+ /*
+ * If jiffies has overflowed in this timer_interrupt we must
+ * update the timer[hi]/[lo] to make do_fast_gettimeoffset()
+ * quotient calc still valid. -arca
+ */
+ timerhi = timerlo = 0;
+ }
+}
+
+/*
+ * On MIPS only R4000 and better have a cycle counter.
+ *
+ * FIXME: Does playing with the RP bit in c0_status interfere with this code?
+ */
+static unsigned long do_gettimeoffset(void)
+{
+ u32 count;
+ unsigned long res, tmp;
+
+ /* Last jiffy when do_fast_gettimeoffset() was called. */
+ static unsigned long last_jiffies;
+ u32 quotient;
+
+ /*
+ * Cached "1/(clocks per usec)*2^32" value.
+ * It has to be recalculated once each jiffy.
+ */
+ static u32 cached_quotient;
+
+ tmp = jiffies;
+
+ quotient = cached_quotient;
+
+ if (tmp && last_jiffies != tmp) {
+ last_jiffies = tmp;
+ __asm__(".set\tnoreorder\n\t"
+ ".set\tnoat\n\t"
+ ".set\tmips3\n\t"
+ "lwu\t%0,%2\n\t"
+ "dsll32\t$1,%1,0\n\t"
+ "or\t$1,$1,%0\n\t"
+ "ddivu\t$0,$1,%3\n\t"
+ "mflo\t$1\n\t"
+ "dsll32\t%0,%4,0\n\t"
+ "nop\n\t"
+ "ddivu\t$0,%0,$1\n\t"
+ "mflo\t%0\n\t"
+ ".set\tmips0\n\t"
+ ".set\tat\n\t"
+ ".set\treorder"
+ :"=&r" (quotient)
+ :"r" (timerhi),
+ "m" (timerlo),
+ "r" (tmp),
+ "r" (USECS_PER_JIFFY)
+ :"$1");
+ cached_quotient = quotient;
+ }
+
+ /* Get last timer tick in absolute kernel time */
+ count = read_32bit_cp0_register(CP0_COUNT);
+
+ /* .. relative to previous jiffy (32 bits is enough) */
+ count -= timerlo;
+
+ __asm__("multu\t%1,%2\n\t"
+ "mfhi\t%0"
+ :"=r" (res)
+ :"r" (count),
+ "r" (quotient));
+
+ /*
+ * Due to possible jiffies inconsistencies, we need to check
+ * the result so that we'll get a timer that is monotonic.
+ */
+ if (res >= USECS_PER_JIFFY)
+ res = USECS_PER_JIFFY-1;
+
+ return res;
+}
+
+void __init time_init(void)
+{
+ unsigned int epoch = 0, year, mon, day, hour, min, sec;
+ int i;
+
+ /* The Linux interpretation of the CMOS clock register contents:
+ * When the Update-In-Progress (UIP) flag goes from 1 to 0, the
+ * RTC registers show the second which has precisely just started.
+ * Let's hope other operating systems interpret the RTC the same way.
+ */
+ /* read RTC exactly on falling edge of update flag */
+ for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
+ if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
+ break;
+ for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */
+ if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
+ break;
+ do { /* Isn't this overkill ? UIP above should guarantee consistency */
+ sec = CMOS_READ(RTC_SECONDS);
+ min = CMOS_READ(RTC_MINUTES);
+ hour = CMOS_READ(RTC_HOURS);
+ day = CMOS_READ(RTC_DAY_OF_MONTH);
+ mon = CMOS_READ(RTC_MONTH);
+ year = CMOS_READ(RTC_YEAR);
+ } while (sec != CMOS_READ(RTC_SECONDS));
+ if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+ BCD_TO_BIN(sec);
+ BCD_TO_BIN(min);
+ BCD_TO_BIN(hour);
+ BCD_TO_BIN(day);
+ BCD_TO_BIN(mon);
+ BCD_TO_BIN(year);
+ }
+
+ /* Attempt to guess the epoch. This is the same heuristic as in
+ * rtc.c so no stupid things will happen to timekeeping. Who knows,
+ * maybe Ultrix also uses 1952 as epoch ...
+ */
+ if (year > 10 && year < 44)
+ epoch = 1980;
+ else if (year < 96)
+ epoch = 1952;
+ year += epoch;
+
+ write_lock_irq (&xtime_lock);
+ xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
+ xtime.tv_usec = 0;
+ write_unlock_irq (&xtime_lock);
+
+ write_32bit_cp0_register(CP0_COUNT, 0);
+ irq0.handler = cc_timer_interrupt;
+
+ ip32_timer_setup (&irq0);
+
+#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
+ /* Set ourselves up for future interrupts */
+ write_32bit_cp0_register(CP0_COMPARE,
+ read_32bit_cp0_register(CP0_COUNT)
+ + cc_interval);
+ change_cp0_status(ST0_IM, ALLINTS);
+ sti ();
+}
+/*
+ * This version of gettimeofday has near microsecond resolution.
+ */
+void do_gettimeofday(struct timeval *tv)
+{
+ unsigned long flags;
+ unsigned long usec, sec;
+
+ read_lock_irqsave(&xtime_lock, flags);
+ usec = do_gettimeoffset();
+ {
+ unsigned long lost = jiffies - wall_jiffies;
+ if (lost)
+ usec += lost * (1000000 / HZ);
+ }
+ sec = xtime.tv_sec;
+ usec += xtime.tv_usec;
+ read_unlock_irqrestore(&xtime_lock, flags);
+
+ while (usec >= 1000000) {
+ usec -= 1000000;
+ sec++;
+ }
+
+ tv->tv_sec = sec;
+ tv->tv_usec = usec;
+}
+
+void do_settimeofday(struct timeval *tv)
+{
+ write_lock_irq(&xtime_lock);
+ tv->tv_usec -= do_gettimeoffset();
+ tv->tv_usec -= (jiffies - wall_jiffies) * (1000000 / HZ);
+
+ while (tv->tv_usec < 0) {
+ tv->tv_usec += 1000000;
+ tv->tv_sec--;
+ }
+
+ xtime = *tv;
+ time_adjust = 0; /* stop active adjtime() */
+ time_status |= STA_UNSYNC;
+ time_maxerror = NTP_PHASE_LIMIT;
+ time_esterror = NTP_PHASE_LIMIT;
+ write_unlock_irq(&xtime_lock);
}
|
|
From: James S. <jsi...@us...> - 2001-10-26 16:10:19
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv30672 Modified Files: tlb-r3k.c Log Message: Always compile r3k_have_wired_reg. Index: tlb-r3k.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r3k.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- tlb-r3k.c 2001/10/24 23:32:54 1.3 +++ tlb-r3k.c 2001/10/26 16:10:17 1.4 @@ -27,9 +27,7 @@ #undef DEBUG_TLB -#ifdef CONFIG_CPU_TX39XX int r3k_have_wired_reg = 0; /* should be in mips_cpu? */ -#endif /* TLB operations. */ void local_flush_tlb_all(void) |
|
From: James S. <jsi...@us...> - 2001-10-26 16:09:09
|
Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv30163 Modified Files: cpu.h Log Message: Added in defines for TX chipset. Index: cpu.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v retrieving revision 1.10 retrieving revision 1.11 diff -u -d -r1.10 -r1.11 --- cpu.h 2001/10/12 17:49:17 1.10 +++ cpu.h 2001/10/26 16:09:07 1.11 @@ -59,6 +59,7 @@ #define PRID_IMP_MAGIC 0x2500 #define PRID_IMP_RM7000 0x2700 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */ +#define PRID_IMP_TX49 0x2d00 #define PRID_IMP_R5900 0x2e00 #define PRID_IMP_R5432 0x5400 #define PRID_IMP_R5500 0x5500 @@ -88,6 +89,12 @@ #define PRID_REV_TX3912 0x0010 #define PRID_REV_TX3922 0x0030 #define PRID_REV_TX3927 0x0040 +#define PRID_REV_TX3927B 0x0041 +#define PRID_REV_TX39H3TEG 0x0050 +#define PRID_REV_TX4955 0x0011 +#define PRID_REV_TX4955A 0x0020 +#define PRID_REV_TX4927 0x0021 +#define PRID_REV_TX4927R2 0x0022 #ifndef _LANGUAGE_ASSEMBLY /* |
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From: James S. <jsi...@us...> - 2001-10-26 16:06:07
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Update of /cvsroot/linux-mips/linux/drivers/i2c
In directory usw-pr-cvs1:/tmp/cvs-serv28820
Modified Files:
Config.in
Log Message:
Remove duplicate ITE8172 stuff. I swore I put this fix into CVS earlier.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/i2c/Config.in,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Config.in 2001/10/22 19:16:45 1.2
+++ Config.in 2001/10/26 16:06:05 1.3
@@ -22,13 +22,6 @@
if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
dep_tristate 'ITE I2C Algorithm' CONFIG_ITE_I2C_ALGO $CONFIG_I2C
- if [ "CONFIG_ITE_I2C_ALGO" != "n" ]; then
- dep_tristate ' ITE I2C Adapter' CONFIG_ITE_I2C_ADAP $CONFIG_ITE_I2C_ALGO
- fi
- fi
-
- if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
- dep_tristate 'ITE I2C Algorithm' CONFIG_ITE_I2C_ALGO $CONFIG_I2C
if [ "$CONFIG_ITE_I2C_ALGO" != "n" ]; then
dep_tristate ' ITE I2C Adapter' CONFIG_ITE_I2C_ADAP $CONFIG_ITE_I2C_ALGO
fi
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From: James S. <jsi...@us...> - 2001-10-26 16:03:57
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Update of /cvsroot/linux-mips/linux/include/asm-mips In directory usw-pr-cvs1:/tmp/cvs-serv27870 Modified Files: processor.h Log Message: Just to minimize the diffs. Index: processor.h =================================================================== RCS file: /cvsroot/linux-mips/linux/include/asm-mips/processor.h,v retrieving revision 1.6 retrieving revision 1.7 diff -u -d -r1.6 -r1.7 --- processor.h 2001/10/25 17:17:45 1.6 +++ processor.h 2001/10/26 16:03:53 1.7 @@ -40,8 +40,8 @@ * System setup and hardware flags.. */ extern void (*cpu_wait)(void); /* only available on R4[26]00 and R3081 */ -extern void r39xx_wait(void); extern void r3081_wait(void); +extern void r39xx_wait(void); extern void r4k_wait(void); extern char cyclecounter_available; /* only available from R4000 upwards. */ |
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