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From: James S. <jsi...@us...> - 2002-01-28 20:32:08
|
Update of /cvsroot/linux-mips/linux/include/asm-mips64/sgi In directory usw-pr-cvs1:/tmp/cvs-serv7656/include/asm-mips64/sgi Added Files: sgihpc.h Log Message: Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical. |
|
From: James S. <jsi...@us...> - 2002-01-28 20:32:08
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv7656/include/asm-mips
Added Files:
sgialib.h sgiarcs.h
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.
--- NEW FILE: sgiarcs.h ---
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* ARC firmware interface defines.
*
* Copyright (C) 1996 David S. Miller (dm...@en...)
* Copyright (C) 1999, 2001 Ralf Baechle (ra...@gn...)
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_SGIARCS_H
#define _ASM_SGIARCS_H
#include <linux/config.h>
#include <asm/arc/types.h>
/* Various ARCS error codes. */
#define PROM_ESUCCESS 0x00
#define PROM_E2BIG 0x01
#define PROM_EACCESS 0x02
#define PROM_EAGAIN 0x03
#define PROM_EBADF 0x04
#define PROM_EBUSY 0x05
#define PROM_EFAULT 0x06
#define PROM_EINVAL 0x07
#define PROM_EIO 0x08
#define PROM_EISDIR 0x09
#define PROM_EMFILE 0x0a
#define PROM_EMLINK 0x0b
#define PROM_ENAMETOOLONG 0x0c
#define PROM_ENODEV 0x0d
#define PROM_ENOENT 0x0e
#define PROM_ENOEXEC 0x0f
#define PROM_ENOMEM 0x10
#define PROM_ENOSPC 0x11
#define PROM_ENOTDIR 0x12
#define PROM_ENOTTY 0x13
#define PROM_ENXIO 0x14
#define PROM_EROFS 0x15
/* SGI ARCS specific errno's. */
#define PROM_EADDRNOTAVAIL 0x1f
#define PROM_ETIMEDOUT 0x20
#define PROM_ECONNABORTED 0x21
#define PROM_ENOCONNECT 0x22
/* Device classes, types, and identifiers for prom
* device inventory queries.
*/
enum linux_devclass {
system, processor, cache, adapter, controller, peripheral, memory
};
enum linux_devtypes {
/* Generic stuff. */
Arc, Cpu, Fpu,
/* Primary insn and data caches. */
picache, pdcache,
/* Secondary insn, data, and combined caches. */
sicache, sdcache, sccache,
memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter,
multifunc_adapter, dsk_controller, tp_controller, cdrom_controller,
worm_controller, serial_controller, net_controller, disp_controller,
parallel_controller, ptr_controller, kbd_controller, audio_controller,
misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral,
modem_peripheral, monitor_peripheral, printer_peripheral,
ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral,
net_peripheral, misc_peripheral, anon
};
enum linux_identifier {
bogus, ronly, removable, consin, consout, input, output
};
/* A prom device tree component. */
struct linux_component {
enum linux_devclass class; /* node class */
enum linux_devtypes type; /* node type */
enum linux_identifier iflags; /* node flags */
USHORT vers; /* node version */
USHORT rev; /* node revision */
ULONG key; /* completely magic */
ULONG amask; /* XXX affinity mask??? */
ULONG cdsize; /* size of configuration data */
ULONG ilen; /* length of string identifier */
_PULONG iname; /* string identifier */
};
typedef struct linux_component pcomponent;
struct linux_sysid {
char vend[8], prod[8];
};
/* ARCS prom memory descriptors. */
enum arcs_memtypes {
arcs_eblock, /* exception block */
arcs_rvpage, /* ARCS romvec page */
arcs_fcontig, /* Contiguous and free */
arcs_free, /* Generic free memory */
arcs_bmem, /* Borken memory, don't use */
arcs_prog, /* A loaded program resides here */
arcs_atmp, /* ARCS temporary storage area, wish Sparc OpenBoot told this */
arcs_aperm, /* ARCS permanent storage... */
};
/* ARC has slightly different types than ARCS */
enum arc_memtypes {
arc_eblock, /* exception block */
arc_rvpage, /* romvec page */
arc_free, /* Generic free memory */
arc_bmem, /* Borken memory, don't use */
arc_prog, /* A loaded program resides here */
arc_atmp, /* temporary storage area */
arc_aperm, /* permanent storage */
arc_fcontig, /* Contiguous and free */
};
union linux_memtypes {
enum arcs_memtypes arcs;
enum arc_memtypes arc;
};
struct linux_mdesc {
union linux_memtypes type;
ULONG base;
ULONG pages;
};
/* Time of day descriptor. */
struct linux_tinfo {
unsigned short yr;
unsigned short mnth;
unsigned short day;
unsigned short hr;
unsigned short min;
unsigned short sec;
unsigned short msec;
};
/* ARCS virtual dirents. */
struct linux_vdirent {
ULONG namelen;
unsigned char attr;
char fname[32]; /* XXX imperical, should be a define */
};
/* Other stuff for files. */
enum linux_omode {
rdonly, wronly, rdwr, wronly_creat, rdwr_creat,
wronly_ssede, rdwr_ssede, dirent, dirent_creat
};
enum linux_seekmode {
absolute, relative
};
enum linux_mountops {
media_load, media_unload
};
/* This prom has a bolixed design. */
struct linux_bigint {
#ifdef __MIPSEL__
unsigned long lo;
long hi;
#else /* !(__MIPSEL__) */
long hi;
unsigned long lo;
#endif
};
struct linux_finfo {
struct linux_bigint begin;
struct linux_bigint end;
struct linux_bigint cur;
enum linux_devtypes dtype;
unsigned long namelen;
unsigned char attr;
char name[32]; /* XXX imperical, should be define */
};
/* This describes the vector containing function pointers to the ARC
firmware functions. */
struct linux_romvec {
LONG load; /* Load an executable image. */
LONG invoke; /* Invoke a standalong image. */
LONG exec; /* Load and begin execution of a
standalone image. */
LONG halt; /* Halt the machine. */
LONG pdown; /* Power down the machine. */
LONG restart; /* XXX soft reset??? */
LONG reboot; /* Reboot the machine. */
LONG imode; /* Enter PROM interactive mode. */
LONG _unused1; /* Was ReturnFromMain(). */
/* PROM device tree interface. */
LONG next_component;
LONG child_component;
LONG parent_component;
LONG component_data;
LONG child_add;
LONG comp_del;
LONG component_by_path;
/* Misc. stuff. */
LONG cfg_save;
LONG get_sysid;
/* Probing for memory. */
LONG get_mdesc;
LONG _unused2; /* was Signal() */
LONG get_tinfo;
LONG get_rtime;
/* File type operations. */
LONG get_vdirent;
LONG open;
LONG close;
LONG read;
LONG get_rstatus;
LONG write;
LONG seek;
LONG mount;
/* Dealing with firmware environment variables. */
LONG get_evar;
LONG set_evar;
LONG get_finfo;
LONG set_finfo;
/* Miscellaneous. */
LONG cache_flush;
};
/* The SGI ARCS parameter block is in a fixed location for standalone
* programs to access PROM facilities easily.
*/
typedef struct _SYSTEM_PARAMETER_BLOCK {
ULONG magic; /* magic cookie */
#define PROMBLOCK_MAGIC 0x53435241
ULONG len; /* length of parm block */
USHORT ver; /* ARCS firmware version */
USHORT rev; /* ARCS firmware revision */
_PLONG rs_block; /* Restart block. */
_PLONG dbg_block; /* Debug block. */
_PLONG gevect; /* XXX General vector??? */
_PLONG utlbvect; /* XXX UTLB vector??? */
ULONG rveclen; /* Size of romvec struct. */
_PVOID romvec; /* Function interface. */
ULONG pveclen; /* Length of private vector. */
_PVOID pvector; /* Private vector. */
ULONG adap_cnt; /* Adapter count. */
ULONG adap_typ0; /* First adapter type. */
ULONG adap_vcnt0; /* Adapter 0 vector count. */
_PVOID adap_vector; /* Adapter 0 vector ptr. */
ULONG adap_typ1; /* Second adapter type. */
ULONG adap_vcnt1; /* Adapter 1 vector count. */
_PVOID adap_vector1; /* Adapter 1 vector ptr. */
/* More adapter vectors go here... */
} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK;
#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000)
#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec)
/* Cache layout parameter block. */
union linux_cache_key {
struct param {
#ifdef __MIPSEL__
unsigned short size;
unsigned char lsize;
unsigned char bsize;
#else /* !(__MIPSEL__) */
unsigned char bsize;
unsigned char lsize;
unsigned short size;
#endif
} info;
unsigned long allinfo;
};
/* Configuration data. */
struct linux_cdata {
char *name;
int mlen;
enum linux_devtypes type;
};
/* Common SGI ARCS firmware file descriptors. */
#define SGIPROM_STDIN 0
#define SGIPROM_STDOUT 1
/* Common SGI ARCS firmware file types. */
#define SGIPROM_ROFILE 0x01 /* read-only file */
#define SGIPROM_HFILE 0x02 /* hidden file */
#define SGIPROM_SFILE 0x04 /* System file */
#define SGIPROM_AFILE 0x08 /* Archive file */
#define SGIPROM_DFILE 0x10 /* Directory file */
#define SGIPROM_DELFILE 0x20 /* Deleted file */
/* SGI ARCS boot record information. */
struct sgi_partition {
unsigned char flag;
#define SGIPART_UNUSED 0x00
#define SGIPART_ACTIVE 0x80
unsigned char shead, ssect, scyl; /* unused */
unsigned char systype; /* OS type, Irix or NT */
unsigned char ehead, esect, ecyl; /* unused */
unsigned char rsect0, rsect1, rsect2, rsect3;
unsigned char tsect0, tsect1, tsect2, tsect3;
};
#define SGIBBLOCK_MAGIC 0xaa55
#define SGIBBLOCK_MAXPART 0x0004
struct sgi_bootblock {
unsigned char _unused[446];
struct sgi_partition partitions[SGIBBLOCK_MAXPART];
unsigned short magic;
};
/* BIOS parameter block. */
struct sgi_bparm_block {
unsigned short bytes_sect; /* bytes per sector */
unsigned char sect_clust; /* sectors per cluster */
unsigned short sect_resv; /* reserved sectors */
unsigned char nfats; /* # of allocation tables */
unsigned short nroot_dirents; /* # of root directory entries */
unsigned short sect_volume; /* sectors in volume */
unsigned char media_type; /* media descriptor */
unsigned short sect_fat; /* sectors per allocation table */
unsigned short sect_track; /* sectors per track */
unsigned short nheads; /* # of heads */
unsigned short nhsects; /* # of hidden sectors */
};
struct sgi_bsector {
unsigned char jmpinfo[3];
unsigned char manuf_name[8];
struct sgi_bparm_block info;
};
/* Debugging block used with SGI symmon symbolic debugger. */
#define SMB_DEBUG_MAGIC 0xfeeddead
struct linux_smonblock {
unsigned long magic;
void (*handler)(void); /* Breakpoint routine. */
unsigned long dtable_base; /* Base addr of dbg table. */
int (*printf)(const char *fmt, ...);
unsigned long btable_base; /* Breakpoint table. */
unsigned long mpflushreqs; /* SMP cache flush request list. */
unsigned long ntab; /* Name table. */
unsigned long stab; /* Symbol table. */
int smax; /* Max # of symbols. */
};
/*
* Macros for calling a 32-bit ARC implementation from 64-bit code
*/
#if defined(CONFIG_MIPS64) && defined(CONFIG_ARC32)
#define __arc_clobbers \
"$2","$3","$4","$5","$6","$7","$8","$9","$10","$11", \
"$12","$13","$14","$15","$16","$24","25","$31"
#define ARC_CALL0(dest) \
({ long __res; \
long __vec = (long) romvec->dest; \
__asm__ __volatile__( \
"dsubu\t$29, 32\n\t" \
"jalr\t%1\n\t" \
"daddu\t$29, 32\n\t" \
"move\t%0, $2" \
: "=r" (__res), "=r" (__vec) \
: "1" (__vec) \
: __arc_clobbers); \
(unsigned long) __res; \
})
#define ARC_CALL1(dest,a1) \
({ long __res; \
register signed int __a1 __asm__("$4") = (int) (long) (a1); \
long __vec = (long) romvec->dest; \
__asm__ __volatile__( \
"dsubu\t$29, 32\n\t" \
"jalr\t%1\n\t" \
"daddu\t$29, 32\n\t" \
"move\t%0, $2" \
: "=r" (__res), "=r" (__vec) \
: "1" (__vec), "r" (__a1) \
: __arc_clobbers); \
(unsigned long) __res; \
})
#define ARC_CALL2(dest,a1,a2) \
({ long __res; \
register signed int __a1 __asm__("$4") = (int) (long) (a1); \
register signed int __a2 __asm__("$5") = (int) (long) (a2); \
long __vec = (long) romvec->dest; \
__asm__ __volatile__( \
"dsubu\t$29, 32\n\t" \
"jalr\t%1\n\t" \
"daddu\t$29, 32\n\t" \
"move\t%0, $2" \
: "=r" (__res), "=r" (__vec) \
: "1" (__vec), "r" (__a1), "r" (__a2) \
: __arc_clobbers); \
__res; \
})
#define ARC_CALL3(dest,a1,a2,a3) \
({ long __res; \
register signed int __a1 __asm__("$4") = (int) (long) (a1); \
register signed int __a2 __asm__("$5") = (int) (long) (a2); \
register signed int __a3 __asm__("$6") = (int) (long) (a3); \
long __vec = (long) romvec->dest; \
__asm__ __volatile__( \
"dsubu\t$29, 32\n\t" \
"jalr\t%1\n\t" \
"daddu\t$29, 32\n\t" \
"move\t%0, $2" \
: "=r" (__res), "=r" (__vec) \
: "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3) \
: __arc_clobbers); \
__res; \
})
#define ARC_CALL4(dest,a1,a2,a3,a4) \
({ long __res; \
register signed int __a1 __asm__("$4") = (int) (long) (a1); \
register signed int __a2 __asm__("$5") = (int) (long) (a2); \
register signed int __a3 __asm__("$6") = (int) (long) (a3); \
register signed int __a4 __asm__("$7") = (int) (long) (a4); \
long __vec = (long) romvec->dest; \
__asm__ __volatile__( \
"dsubu\t$29, 32\n\t" \
"jalr\t%1\n\t" \
"daddu\t$29, 32\n\t" \
"move\t%0, $2" \
: "=r" (__res), "=r" (__vec) \
: "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3), \
"r" (__a4) \
: __arc_clobbers); \
__res; \
})
#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \
({ long __res; \
register signed int __a1 __asm__("$4") = (int) (long) (a1); \
register signed int __a2 __asm__("$5") = (int) (long) (a2); \
register signed int __a3 __asm__("$6") = (int) (long) (a3); \
register signed int __a4 __asm__("$7") = (int) (long) (a4); \
register signed int __a5 = (a5); \
long __vec = (long) romvec->dest; \
__asm__ __volatile__( \
"dsubu\t$29, 32\n\t" \
"sw\t%6, 16($29)\n\t" \
"jalr\t%1\n\t" \
"daddu\t$29, 32\n\t" \
"move\t%0, $2" \
: "=r" (__res), "=r" (__vec) \
: "1" (__vec), \
"r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4), \
"r" (__a5) \
: __arc_clobbers); \
__res; \
})
#endif /* defined(CONFIG_MIPS64) && defined(CONFIG_ARC32) */
#if (defined(CONFIG_MIPS32) && defined(CONFIG_ARC32)) || \
(defined(CONFIG_MIPS64) && defined(CONFIG_ARC32))
#define ARC_CALL0(dest) \
({ long __res; \
long (*__vec)(void) = (void *) romvec->dest; \
\
__res = __vec(); \
__res; \
})
#define ARC_CALL1(dest,a1) \
({ long __res; \
long __a1 = (long) (a1); \
long (*__vec)(long) = (void *) romvec->dest; \
\
__res = __vec(__a1); \
__res; \
})
#define ARC_CALL2(dest,a1,a2) \
({ long __res; \
long __a1 = (long) (a1); \
long __a2 = (long) (a2); \
long (*__vec)(long, long) = (void *) romvec->dest; \
\
__res = __vec(__a1, __a2); \
__res; \
})
#define ARC_CALL3(dest,a1,a2,a3) \
({ long __res; \
long __a1 = (long) (a1); \
long __a2 = (long) (a2); \
long __a3 = (long) (a3); \
long (*__vec)(long, long, long) = (void *) romvec->dest; \
\
__res = __vec(__a1, __a2, __a3); \
__res; \
})
#define ARC_CALL4(dest,a1,a2,a3,a4) \
({ long __res; \
long __a1 = (long) (a1); \
long __a2 = (long) (a2); \
long __a3 = (long) (a3); \
long __a4 = (long) (a4); \
long (*__vec)(long, long, long, long) = (void *) romvec->dest; \
\
__res = __vec(__a1, __a2, __a3, __a4); \
__res; \
})
#define ARC_CALL5(dest,a1,a2,a3,a4,a5) \
({ long __res; \
long __a1 = (long) (a1); \
long __a2 = (long) (a2); \
long __a3 = (long) (a3); \
long __a4 = (long) (a4); \
long __a5 = (long) (a5); \
long (*__vec)(long, long, long, long, long); \
__vec = (void *) romvec->dest; \
\
__res = __vec(__a1, __a2, __a3, __a4, __a5); \
__res; \
})
#endif /* both kernel and ARC either 32-bit or 64-bit */
#endif /* _ASM_SGIARCS_H */
|
|
From: James S. <jsi...@us...> - 2002-01-28 20:32:07
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/swarm In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/sibyte/swarm Removed Files: Makefile cmdline.c memory.c rtc.c setup.c smp.c time.c Log Message: Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical. --- Makefile DELETED --- --- cmdline.c DELETED --- --- memory.c DELETED --- --- rtc.c DELETED --- --- setup.c DELETED --- --- smp.c DELETED --- --- time.c DELETED --- |
|
From: James S. <jsi...@us...> - 2002-01-28 20:32:05
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/sb1250 In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/sibyte/sb1250 Removed Files: Makefile irq.c irq_handler.S pci-dma.c pci.c setup.c smp.c time.c Log Message: Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical. --- Makefile DELETED --- --- irq.c DELETED --- --- irq_handler.S DELETED --- --- pci-dma.c DELETED --- --- pci.c DELETED --- --- setup.c DELETED --- --- smp.c DELETED --- --- time.c DELETED --- |
|
From: James S. <jsi...@us...> - 2002-01-28 20:32:03
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/cfe In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/sibyte/cfe Removed Files: Makefile cfe_api.c Log Message: Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical. --- Makefile DELETED --- --- cfe_api.c DELETED --- |
|
From: James S. <jsi...@us...> - 2002-01-28 20:32:03
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sibyte/sb1 In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/sibyte/sb1 Removed Files: Makefile cache.c tlb.c Log Message: Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical. --- Makefile DELETED --- --- cache.c DELETED --- --- tlb.c DELETED --- |
|
From: James S. <jsi...@us...> - 2002-01-28 19:49:11
|
Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32 In directory usw-pr-cvs1:/tmp/cvs-serv22791 Modified Files: Makefile Removed Files: ip32-pci-dma.c Log Message: SGI ip32 updates. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip32/Makefile,v retrieving revision 1.2 retrieving revision 1.3 diff -u -d -r1.2 -r1.3 --- Makefile 2001/10/26 16:13:55 1.2 +++ Makefile 2002/01/28 19:49:08 1.3 @@ -17,11 +17,9 @@ all: ip32-kern.a ip32-irq-glue.o -obj-y += ip32-irq.o ip32-rtc.o ip32-setup.o ip32-irq-glue.o \ - ip32-berr.o ip32-timer.o crime.o ip32-reset.o +obj-y += ip32-rtc.o ip32-setup.o ip32-irq.o ip32-irq-glue.o ip32-timer.o \ + crime.o ip32-reset.o -ifdef CONFIG_PCI -obj-y += ip32-pci.o ip32-pci-dma.o -endif +obj-$(CONFIG_PCI) += ip32-pci.o include $(TOPDIR)/Rules.make --- ip32-pci-dma.c DELETED --- |
|
From: James S. <jsi...@us...> - 2002-01-28 19:44:30
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv20627
Modified Files:
config.in
Log Message:
First cut of a highmem implementation. Only usable on CPUs that don't suffer from virtual aliases. In connection with the recent patches for 64-bit physical addresses in pagetables this patch increases the maximum memory supported by the 32-bit kernel into the gigabyte range.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.83
retrieving revision 1.84
diff -u -d -r1.83 -r1.84
--- config.in 2002/01/24 20:13:33 1.83
+++ config.in 2002/01/28 19:44:27 1.84
@@ -3,7 +3,6 @@
# see Documentation/kbuild/config-language.txt.
#
define_bool CONFIG_MIPS y
-define_bool CONFIG_MIPS32 y
mainmenu_name "Linux Kernel Configuration"
@@ -18,7 +17,7 @@
bool 'Support for Acer PICA 1 chipset' CONFIG_ACER_PICA_61
bool 'Support for Algorithmics P4032 (EXPERIMENTAL)' CONFIG_ALGOR_P4032
bool 'Support for BAGET MIPS series (EXPERIMENTAL)' CONFIG_BAGET_MIPS
- bool 'Support for Cobalt Server (EXPERIMENTAL)' CONFIG_COBALT_MICRO_SERVER
+ bool 'Support for Cobalt Server (EXPERIMENTAL)' CONFIG_MIPS_COBALT
bool 'Support for DECstations (EXPERIMENTAL)' CONFIG_DECSTATION
bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074
bool 'Support for NEC Eagle board (EXPERIMENTAL)' CONFIG_NEC_EAGLE
@@ -27,12 +26,12 @@
fi
bool 'Support for NEC Korva/Markham board (EXPERIMENTAL)' CONFIG_NEC_KORVA
if [ "$CONFIG_NEC_KORVA" = "y" ]; then
- choice 'Board Variant' \
+ choice 'Board Variant' \
"Korva-8MB CONFIG_NEC_KORVA_8MB\
- Markham-32MB CONFIG_NEC_MARKHAM_32MB" CONFIG_NEC_KORVA_8MB
- if [ "$CONFIG_NEC_MARKHAM_32MB" = "y" ]; then
- bool ' Enable Markham onboard PCI controller' CONFIG_PCI
- fi
+ Markham-32MB CONFIG_NEC_MARKHAM_32MB" CONFIG_NEC_KORVA_8MB
+ if [ "$CONFIG_NEC_MARKHAM_32MB" = "y" ]; then
+ bool ' Enable Markham onboard PCI controller' CONFIG_PCI
+ fi
fi
bool 'Support for Galileo EV96100 Evaluation board' CONFIG_MIPS_EV96100
@@ -70,7 +69,7 @@
bool 'Support for Casio Cassiopeia BE-300 (EXPERIMENTAL)' CONFIG_CASIO_BE300
bool 'Support for Casio Cassiopeia E15 (EXPERIMENTAL)' CONFIG_CASIO_E15
bool 'Support for Vadem Clio 1000 (EXPERIMENTAL)' CONFIG_VADEM_CLIO_1000
- bool 'Support for NEC MobilePro 780 PDA (EXPERIMENTAL)' CONFIG_NEC_MOBILEPRO_780
+ bool 'Support for NEC MobilePro 780 PDA (EXPERIMENTAL)' CONFIG_NEC_MOBILEPRO
bool 'Support for IDT 79S334 Evaluation board' CONFIG_IDT_79S334
bool 'Support for IDT 79EB355 Evaluation board' CONFIG_IDT_79EB355
fi
@@ -165,7 +164,7 @@
fi
if [ "$CONFIG_MIPS_ATLAS" = "y" ]; then
define_bool CONFIG_NEW_TIME_C y
- define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PCI y
define_bool CONFIG_SWAP_IO_SPACE y
@@ -175,8 +174,8 @@
define_bool CONFIG_PCI y
define_bool CONFIG_HAVE_STD_PC_SERIAL_PORT y
define_bool CONFIG_NEW_IRQ y
- define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_SWAP_IO_SPACE y
fi
if [ "$CONFIG_MOMENCO_OCELOT" = "y" ]; then
@@ -213,7 +212,7 @@
define_bool CONFIG_ISA y
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_NEW_IRQ y
- define_bool CONFIG_IRQ_CPU y
+ define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_PCI y
define_bool CONFIG_NEW_PCI y
define_bool CONFIG_PCI_AUTO y
@@ -280,6 +279,16 @@
define_bool CONFIG_PCI_AUTO y
fi
fi
+if [ "$CONFIG_MIPS_COBALT" = "y" ]; then
+ define_bool CONFIG_COBALT_LCD y
+ define_bool CONFIG_PCI y
+ define_bool CONFIG_NEW_IRQ y
+ define_bool CONFIG_NEW_TIME_C y
+ define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_I8259 y
+ define_bool CONFIG_NEW_PCI y
+ define_bool CONFIG_PCI_AUTO y
+fi
if [ "$CONFIG_MIPS_ITE8172" = "y" ]; then
define_bool CONFIG_PCI y
define_bool CONFIG_IT8712 y
@@ -332,7 +341,6 @@
define_bool CONFIG_PC_KEYB y
fi
fi
-
if [ "$CONFIG_IDT_79EB355" = "y" ]; then
define_bool CONFIG_CPU_RC32355 y
define_bool CONFIG_NEW_IRQ y
@@ -346,22 +354,6 @@
define_bool CONFIG_PC_KEYB y
fi
fi
-if [ "$CONFIG_COBALT_MICRO_SERVER" = "y" ]; then
- define_bool COBALT_MICRO_SERVER y
- define_bool CONFIG_NO_SWAPPER y
- define_bool CONFIG_COBALT_27 y
- define_bool CONFIG_NO_KEYBOARD y
- define_bool CONFIG_NO_VIDEO_CONSOLE y
- define_bool CONFIG_COBALT_LCD y
- define_bool CONFIG_ISA y
- define_bool CONFIG_PCI y
- define_bool CONFIG_NEW_IRQ y
- define_bool CONFIG_I8259 y
- define_bool CONFIG_NEW_PCI y
- define_bool CONFIG_PCI_AUTO y
- define_bool CONFIG_NONCOHERENT_IO y
- define_bool CONFIG_NEW_TIME_C y
-fi
if [ "$CONFIG_VADEM_CLIO_1000" = "y" ]; then
define_bool CONFIG_CPU_VR41XX y
define_bool CONFIG_VR4111 y
@@ -392,6 +384,7 @@
define_bool CONFIG_NONCOHERENT_IO y
define_bool CONFIG_PC_KEYB y
fi
+
if [ "$CONFIG_PS2" = "y" ]; then
define_bool CONFIG_PC_KEYB y
define_bool CONFIG_BOARD_SCACHE y
@@ -423,6 +416,7 @@
define_bool CONFIG_DUMMY_KEYB y
define_bool CONFIG_FB_SIMPLE y
fi
+
if [ "$CONFIG_HP_LASERJET" = "y" ]; then
define_bool CONFIG_IRQ_CPU y
define_bool CONFIG_NEW_TIME_C y
@@ -432,6 +426,11 @@
define_bool CONFIG_PCI y
#not yet define_bool CONFIG_PCI_AUTO y
fi
+
+if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
+ define_bool CONFIG_NEW_TIME_C y
+fi
+
if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
define_bool CONFIG_TOSHIBA_BOARDS y
define_bool CONFIG_PCI y
@@ -441,7 +440,7 @@
define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_SWAP_IO_SPACE y
define_bool CONFIG_PC_KEYB y
- define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_NONCOHERENT_IO y
fi
if [ "$CONFIG_ISA" != "y" ]; then
@@ -474,7 +473,7 @@
R49XX CONFIG_CPU_TX49XX \
R5000 CONFIG_CPU_R5000 \
R5432 CONFIG_CPU_R5432 \
- R5900 CONFIG_CPU_R5900 \
+ R5900 CONFIG_CPU_R5900 \
RM7000 CONFIG_CPU_RM7000 \
SR7100 CONFIG_CPU_SR7100 \
R52xx CONFIG_CPU_NEVADA \
@@ -490,6 +489,16 @@
define_bool CONFIG_VTAG_ICACHE y
fi
+if [ "$CONFIG_CPU_R4X00" = "y" -o \
+ "$CONFIG_CPU_R5000" = "y" -o \
+ "$CONFIG_CPU_RM7000" = "y" -o \
+ "$CONFIG_CPU_R10000" = "y" -o \
+ "$CONFIG_CPU_SB1" = "y" -o \
+ "$CONFIG_CPU_MIPS32" = "y" -o \
+ "$CONFIG_CPU_MIPS64" = "y" ]; then
+ bool ' Support for 64-bit physical addresspace' CONFIG_64BIT_PHYS_ADDR
+fi
+
bool 'Override CPU Options' CONFIG_CPU_ADVANCED
if [ "$CONFIG_CPU_ADVANCED" = "y" ]; then
bool ' ll/sc Instructions available' CONFIG_CPU_HAS_LLSC
@@ -526,10 +535,11 @@
comment 'General setup'
if [ "$CONFIG_DECSTATION" = "y" -o \
"$CONFIG_DDB5074" = "y" -o \
- "$CONFIG_NINO" = "y" -o
- "$CONFIG_VR4111" = "y" -o \
- "$CONFIG_VR4121" = "y" -o \
- "$CONFIG_VR4122" = "y" -o \
+ "$CONFIG_NINO" = "y" -o \
+ "$CONFIG_MIPS_COBALT" = "y" -o \
+ "$CONFIG_VR4111" = "y" -o \
+ "$CONFIG_VR4121" = "y" -o \
+ "$CONFIG_VR4122" = "y" -o \
"$CONFIG_NEC_KORVA" = "y" ]; then
define_bool CONFIG_CPU_LITTLE_ENDIAN y
else
@@ -540,7 +550,7 @@
dep_bool ' Enable Vr4131 cache fixes for early rev processors' CONFIG_VR4131_CACHE_FIX $CONFIG_VR4131
if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
- bool 'DS1742 BRAM/RTC support' CONFIG_RTC_DS1742
+ bool 'DS1742 BRAM/RTC support' CONFIG_RTC_DS1742
fi
if [ "$CONFIG_PROC_FS" = "y" ]; then
|
|
From: James S. <jsi...@us...> - 2002-01-28 19:24:00
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv10439/include/asm-mips
Added Files:
fixmap.h highmem.h kmap_types.h
Log Message:
First cut of a highmem implementation. Only usable on CPUs that don't suffer from virtual aliases. In connection with the recent patches for 64-bit physical addresses in pagetables this patch increases the maximum memory supported by the 32-bit kernel into the gigabyte range.
--- NEW FILE: fixmap.h ---
/*
* fixmap.h: compile-time virtual memory allocation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Ingo Molnar
*
* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
*/
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
#include <linux/config.h>
#include <linux/kernel.h>
#include <asm/page.h>
#ifdef CONFIG_HIGHMEM
#include <linux/threads.h>
#include <asm/kmap_types.h>
#endif
/*
* Here we define all the compile-time 'special' virtual
* addresses. The point is to have a constant address at
* compile time, but to set the physical address only
* in the boot process. We allocate these special addresses
* from the end of virtual memory (0xfffff000) backwards.
* Also this lets us do fail-safe vmalloc(), we
* can guarantee that these special addresses and
* vmalloc()-ed addresses never overlap.
*
* these 'compile-time allocated' memory buffers are
* fixed-size 4k pages. (or larger if used with an increment
* highger than 1) use fixmap_set(idx,phys) to associate
* physical memory with fixmap indices.
*
* TLB entries of such buffers will not be flushed across
* task switches.
*/
/*
* on UP currently we will have no trace of the fixmap mechanizm,
* no page table allocations, etc. This might change in the
* future, say framebuffers for the console driver(s) could be
* fix-mapped?
*/
enum fixed_addresses {
#ifdef CONFIG_HIGHMEM
FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
#endif
__end_of_fixed_addresses
};
extern void __set_fixmap (enum fixed_addresses idx,
unsigned long phys, pgprot_t flags);
#define set_fixmap(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL)
/*
* Some hardware wants to get fixmapped without caching.
*/
#define set_fixmap_nocache(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
/*
* used by vmalloc.c.
*
* Leave one empty page between vmalloc'ed areas and
* the start of the fixmap, and leave one page empty
* at the top of mem..
*/
#define FIXADDR_TOP (0xffffe000UL)
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
extern void __this_fixmap_does_not_exist(void);
/*
* 'index to address' translation. If anyone tries to use the idx
* directly without tranlation, we catch the bug with a NULL-deference
* kernel oops. Illegal ranges of incoming indices are caught too.
*/
static inline unsigned long fix_to_virt(const unsigned int idx)
{
/*
* this branch gets completely eliminated after inlining,
* except when someone tries to use fixaddr indices in an
* illegal way. (such as mixing up address types or using
* out-of-range indices).
*
* If it doesn't get removed, the linker will complain
* loudly with a reasonably clear error message..
*/
if (idx >= __end_of_fixed_addresses)
__this_fixmap_does_not_exist();
return __fix_to_virt(idx);
}
#endif
--- NEW FILE: highmem.h ---
/*
* highmem.h: virtual kernel memory mappings for high memory
*
* Used in CONFIG_HIGHMEM systems for memory pages which
* are not addressable by direct kernel virtual addresses.
*
* Copyright (C) 1999 Gerhard Wichert, Siemens AG
* Ger...@pd...
*
*
* Redesigned the x86 32-bit VM architecture to deal with
* up to 16 Terabyte physical memory. With current x86 CPUs
* we now support up to 64 Gigabytes physical RAM.
*
* Copyright (C) 1999 Ingo Molnar <mi...@re...>
*/
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/kmap_types.h>
#include <asm/pgtable.h>
/* undef for production */
#define HIGHMEM_DEBUG 1
/* declarations for highmem.c */
extern unsigned long highstart_pfn, highend_pfn;
extern pte_t *kmap_pte;
extern pgprot_t kmap_prot;
extern pte_t *pkmap_page_table;
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM.
*/
#define PKMAP_BASE (0xfe000000UL)
#define LAST_PKMAP 1024
#define LAST_PKMAP_MASK (LAST_PKMAP-1)
#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
extern void * kmap_high(struct page *page);
extern void kunmap_high(struct page *page);
static inline void *kmap(struct page *page)
{
if (in_interrupt())
BUG();
if (page < highmem_start_page)
return page_address(page);
return kmap_high(page);
}
static inline void kunmap(struct page *page)
{
if (in_interrupt())
BUG();
if (page < highmem_start_page)
return;
kunmap_high(page);
}
/*
* The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
* gives a more generic (and caching) interface. But kmap_atomic can
* be used in IRQ contexts, so in some (very limited) cases we need
* it.
*/
static inline void *kmap_atomic(struct page *page, enum km_type type)
{
enum fixed_addresses idx;
unsigned long vaddr;
if (page < highmem_start_page)
return page_address(page);
idx = type + KM_TYPE_NR*smp_processor_id();
vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
set_pte(kmap_pte-idx, mk_pte(page, kmap_prot));
//local_flush_tlb_page(NULL, vaddr);
local_flush_tlb_all();
return (void*) vaddr;
}
static inline void kunmap_atomic(void *kvaddr, enum km_type type)
{
}
#endif /* __KERNEL__ */
#endif /* _ASM_HIGHMEM_H */
--- NEW FILE: kmap_types.h ---
#ifndef _ASM_KMAP_TYPES_H
#define _ASM_KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BIO_IRQ,
KM_TYPE_NR
};
#endif
|
|
From: James S. <jsi...@us...> - 2002-01-28 19:24:00
|
Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv10439/arch/mips/sibyte/swarm
Modified Files:
setup.c
Log Message:
First cut of a highmem implementation. Only usable on CPUs that don't suffer from virtual aliases. In connection with the recent patches for 64-bit physical addresses in pagetables this patch increases the maximum memory supported by the 32-bit kernel into the gigabyte range.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/setup.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- setup.c 2002/01/02 19:12:16 1.6
+++ setup.c 2002/01/28 19:23:58 1.7
@@ -26,6 +26,7 @@
#include <linux/bootmem.h>
#include <linux/blk.h>
#include <linux/init.h>
+#include <linux/ide.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
@@ -34,8 +35,9 @@
#include <asm/sibyte/sb1250.h>
#include <asm/sibyte/sb1250_defs.h>
#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/swarm_ide.h>
#include <asm/reboot.h>
-#include <linux/ide.h>
+#include <asm/time.h>
#include "cfe_xiocb.h"
#include "cfe_api.h"
@@ -45,7 +47,7 @@
extern int cfe_console_handle;
#ifdef CONFIG_BLK_DEV_IDE_SWARM
-struct ide_ops *ide_ops;
+extern struct ide_ops *ide_ops;
#endif
@@ -54,12 +56,21 @@
#endif
/* Max ram addressable in 32-bit segments */
-#define MAX_RAM_SIZE (1024*1024*256)
+#ifdef CONFIG_HIGHMEM
+#ifdef CONFIG_64BIT_PHYS_ADDR
+/* #define MAX_RAM_SIZE (0xffffffffffffffff) */
+#define MAX_RAM_SIZE (0xffffffff)
+#else
+#define MAX_RAM_SIZE (0xffffffff)
+#endif
+#else
+#define MAX_RAM_SIZE (0xfffffff)
+#endif
#ifndef CONFIG_SWARM_STANDALONE
-long swarm_mem_region_addrs[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
-long swarm_mem_region_sizes[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
+phys_t swarm_mem_region_addrs[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
+phys_t swarm_mem_region_sizes[CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS];
unsigned int swarm_mem_region_count;
#endif
@@ -132,6 +143,49 @@
/* release_region(from, extent); */
}
+
+void swarm_ideproc(ide_ide_action_t action, ide_drive_t *drive,
+ void *buffer, unsigned int count)
+{
+ /* slow? vlb_sync? */
+ switch (action) {
+ case ideproc_ide_input_data:
+ if (drive->io_32bit) {
+ swarm_insl(IDE_DATA_REG, buffer, count);
+ } else {
+ swarm_insw(IDE_DATA_REG, buffer, count<<1);
+ }
+ break;
+ case ideproc_ide_output_data:
+ if (drive->io_32bit) {
+ swarm_outsl(IDE_DATA_REG, buffer, count);
+ } else {
+ swarm_outsw(IDE_DATA_REG, buffer, count<<1);
+ }
+ break;
+ case ideproc_atapi_input_bytes:
+ count++;
+ if (drive->io_32bit) {
+ swarm_insl(IDE_DATA_REG, buffer, count>>2);
+ } else {
+ swarm_insw(IDE_DATA_REG, buffer, count>>1);
+ }
+ if ((count & 3) >= 2)
+ swarm_insw(IDE_DATA_REG, (char *)buffer + (count & ~3), 1);
+ break;
+ case ideproc_atapi_output_bytes:
+ count++;
+ if (drive->io_32bit) {
+ swarm_outsl(IDE_DATA_REG, buffer, count>>2);
+ } else {
+ swarm_outsw(IDE_DATA_REG, buffer, count>>1);
+ }
+ if ((count & 3) >= 2)
+ swarm_outsw(IDE_DATA_REG, (char *)buffer + (count & ~3), 1);
+ break;
+ }
+}
+
struct ide_ops swarm_ide_ops = {
&swarm_ide_default_irq,
&swarm_ide_default_io_base,
@@ -144,50 +198,39 @@
};
#endif
-
-static void stop_this_cpu(void *dummy)
-{
- printk("Cpu %d stopping\n", smp_processor_id());
- for (;;);
-}
-static void smp_cpu0_exit(void)
+#ifdef CONFIG_SMP
+static void smp_cpu0_exit(void *unused)
{
- printk("cpu %d poked\n", smp_processor_id());
- /* XXXKW we are in the mailbox handler... */
- __asm__(".set push\n\t"
- ".set mips32\n\t"
- "la $2, swarm_linux_exit\n\t"
- "mtc0 $2, $24\n\t"
- "eret\n\t"
- ".set pop"
- ::: "$2");
+ printk("swarm_linux_exit called (cpu1) - passing control back to CFE\n");
+ cfe_exit(1,0);
}
-
-extern void (*smp_cpu0_finalize)(void);
+#endif
static void swarm_linux_exit(void)
{
+#ifdef CONFIG_SMP
if (smp_processor_id()) {
- /* Make cpu 0 do the swarm_linux_exit */
- /* XXXKW this isn't quite there yet */
- smp_cpu0_finalize = smp_cpu0_exit;
- stop_this_cpu(NULL);
- } else {
- printk("swarm_linux_exit called...passing control back to CFE\n");
- cfe_exit(1, 0);
- printk("cfe_exit returned??\n");
+ smp_call_function(smp_cpu0_exit,NULL,1,1);
while(1);
}
+#endif
+ printk("swarm_linux_exit called...passing control back to CFE\n");
+ cfe_exit(1, 0);
+ printk("cfe_exit returned??\n");
+ while(1);
}
void __init bus_error_init(void)
{
}
+extern void swarm_time_init(void);
+
void __init swarm_setup(void)
{
extern int panic_timeout;
+
rtc_ops = &swarm_rtc_ops;
panic_timeout = 5; /* For debug. This should probably be raised later */
_machine_restart = (void (*)(char *))swarm_linux_exit;
@@ -207,10 +250,11 @@
#endif
" runs\n");
+ board_time_init = swarm_time_init;
+
#ifdef CONFIG_BLK_DEV_IDE_SWARM
- ide_ops = &swarm_ide_ops;
+ ide_ops = &swarm_ide_ops;
#endif
-
}
/* This is the kernel command line. Actually, it's
@@ -226,7 +270,7 @@
static __init void prom_meminit(void)
{
- unsigned long addr, size;
+ unsigned long long addr, size; /* regardless of 64BIT_PHYS_ADDR */
long type;
unsigned int idx;
int rd_flag;
@@ -284,13 +328,11 @@
}
#endif
if (!rd_flag) {
- if (addr < MAX_RAM_SIZE) {
- if (size > MAX_RAM_SIZE) {
- size = MAX_RAM_SIZE - addr;
- }
- add_memory_region(addr, size,
- BOOT_MEM_RAM);
- }
+ if (addr > MAX_RAM_SIZE)
+ continue;
+ if (addr+size > MAX_RAM_SIZE)
+ size = MAX_RAM_SIZE - (addr+size) + 1;
+ add_memory_region(addr, size, BOOT_MEM_RAM);
}
swarm_mem_region_addrs[swarm_mem_region_count] = addr;
swarm_mem_region_sizes[swarm_mem_region_count] = size;
|
|
From: James S. <jsi...@us...> - 2002-01-28 19:24:00
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv10439/arch/mips/kernel
Modified Files:
traps.c
Log Message:
First cut of a highmem implementation. Only usable on CPUs that don't suffer from virtual aliases. In connection with the recent patches for 64-bit physical addresses in pagetables this patch increases the maximum memory supported by the 32-bit kernel into the gigabyte range.
Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/traps.c,v
retrieving revision 1.29
retrieving revision 1.30
diff -u -d -r1.29 -r1.30
--- traps.c 2002/01/02 19:12:16 1.29
+++ traps.c 2002/01/28 19:23:57 1.30
@@ -23,15 +23,17 @@
#include <asm/bootinfo.h>
#include <asm/branch.h>
#include <asm/cpu.h>
+#include <asm/cachectl.h>
#include <asm/inst.h>
+#include <asm/jazz.h>
#include <asm/module.h>
#include <asm/pgtable.h>
+#include <asm/io.h>
#include <asm/siginfo.h>
-#include <asm/paccess.h>
+#include <asm/watch.h>
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/mmu_context.h>
-#include <asm/watch.h>
/*
* Machine specific interrupt handlers
@@ -64,6 +66,9 @@
char watch_available = 0;
+void (*ibe_board_handler)(struct pt_regs *regs);
+void (*dbe_board_handler)(struct pt_regs *regs);
+
int kstack_depth_to_print = 24;
/*
@@ -375,7 +380,8 @@
extern spinlock_t modlist_lock;
-unsigned long search_dbe_table(unsigned long addr)
+static inline unsigned long
+search_dbe_table(unsigned long addr)
{
unsigned long ret = 0;
@@ -411,26 +417,40 @@
#endif
}
-/* Default data and instruction bus error handlers. */
-void do_ibe(struct pt_regs *regs)
-{
- die("Got ibe\n", regs);
-}
-
-void do_dbe(struct pt_regs *regs)
+static void default_be_board_handler(struct pt_regs *regs)
{
+ unsigned long new_epc;
unsigned long fixup;
-
- fixup = search_dbe_table(regs->cp0_epc);
- if (fixup) {
- long new_epc;
+ int data = regs->cp0_cause & 4;
- new_epc = fixup_exception(dpf_reg, fixup, regs->cp0_epc);
- regs->cp0_epc = new_epc;
- return;
+ if (data && !user_mode(regs)) {
+ fixup = search_dbe_table(regs->cp0_epc);
+ if (fixup) {
+ new_epc = fixup_exception(dpf_reg, fixup,
+ regs->cp0_epc);
+ regs->cp0_epc = new_epc;
+ return;
+ }
}
- die("Got DBE\n", regs);
+ /*
+ * Assume it would be too dangerous to continue ...
+ */
+ printk(KERN_ALERT "%s bus error, epc == %08lx, ra == %08lx\n",
+ data ? "Data" : "Instruction",
+ regs->cp0_epc, regs->regs[31]);
+ die_if_kernel("Oops", regs);
+ force_sig(SIGBUS, current);
+}
+
+asmlinkage void do_ibe(struct pt_regs *regs)
+{
+ ibe_board_handler(regs);
+}
+
+asmlinkage void do_dbe(struct pt_regs *regs)
+{
+ dbe_board_handler(regs);
}
asmlinkage void do_ov(struct pt_regs *regs)
@@ -813,7 +833,6 @@
extern char except_vec4;
extern char except_vec_ejtag_debug;
unsigned long i;
- int dummy;
/* Some firmware leaves the BEV flag set, clear it. */
clear_cp0_status(ST0_BEV);
@@ -863,17 +882,15 @@
set_except_vector(4, handle_adel);
set_except_vector(5, handle_ades);
- set_except_vector(6, handle_ibe);
- set_except_vector(7, handle_dbe);
-
/*
- * If nothing uses the DBE protection mechanism this is necessary to
- * get the kernel to link.
+ * The Data Bus Error/ Instruction Bus Errors are signaled
+ * by external hardware. Therefore these two expection have
+ * board specific handlers.
*/
- get_dbe(dummy, (int *)KSEG0);
-
- /* DBE / IBE handlers may be overridden by system specific handlers. */
- bus_error_init();
+ set_except_vector(6, handle_ibe);
+ set_except_vector(7, handle_dbe);
+ ibe_board_handler = default_be_board_handler;
+ dbe_board_handler = default_be_board_handler;
set_except_vector(8, handle_sys);
set_except_vector(9, handle_bp);
@@ -919,6 +936,7 @@
#ifdef CONFIG_SB1_CACHE_ERROR
/* Special cache error handler for SB1 */
extern char except_vec2_sb1;
+ memcpy((void *)(KSEG0 + 0x100), &except_vec2_sb1, 0x80);
memcpy((void *)(KSEG1 + 0x100), &except_vec2_sb1, 0x80);
#endif
|
|
From: James S. <jsi...@us...> - 2002-01-28 19:18:17
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv8167
Added Files:
init_task.c
Log Message:
Support for 64-bit addresses in page tables.
--- NEW FILE: init_task.c ---
#include <linux/mm.h>
#include <linux/sched.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
static struct fs_struct init_fs = INIT_FS;
static struct files_struct init_files = INIT_FILES;
static struct signal_struct init_signals = INIT_SIGNALS;
struct mm_struct init_mm = INIT_MM(init_mm);
/*
* Initial task structure.
*
* We need to make sure that this is 8192-byte aligned due to the
* way process stacks are handled. This is done by making sure
* the linker maps this in the .text segment right after head.S,
* and making head.S ensure the proper alignment.
*
* The things we do for performance..
*/
union task_union init_task_union
__attribute__((__section__(".data.init_task"))) =
{ INIT_TASK(init_task_union.task) };
|
|
From: James S. <jsi...@us...> - 2002-01-28 19:17:22
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv7746/kernel
Modified Files:
setup.c
Log Message:
Rename sgi_setup to ip22_setup.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.48
retrieving revision 1.49
diff -u -d -r1.48 -r1.49
--- setup.c 2002/01/19 21:17:35 1.48
+++ setup.c 2002/01/28 19:17:18 1.49
@@ -150,15 +150,15 @@
case CPU_R4700:
case CPU_R5000:
case CPU_NEVADA:
-// case CPU_RM7000:
+ case CPU_RM7000:
case CPU_TX49XX:
cpu_wait = r4k_wait;
printk(" available.\n");
break;
- case CPU_SR7100:
+ case CPU_SR7100:
cpu_wait = sr7100_wait;
printk(" errata work around.\n");
- break;
+ break;
default:
printk(" unavailable.\n");
break;
@@ -216,9 +216,9 @@
/* declaration of the global struct */
struct mips_cpu mips_cpu = {
- processor_id: PRID_IMP_UNKNOWN,
- fpu_id: FPIR_IMP_NONE,
- cputype: CPU_UNKNOWN,
+ processor_id: PRID_IMP_UNKNOWN,
+ fpu_id: FPIR_IMP_NONE,
+ cputype: CPU_UNKNOWN
};
/* Shortcut for assembler access to mips_cpu.options */
@@ -387,6 +387,8 @@
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
break;
+
+
case PRID_IMP_R6000:
mips_cpu.cputype = CPU_R6000;
mips_cpu.isa_level = MIPS_CPU_ISA_II;
@@ -434,7 +436,7 @@
mips_cpu.cputype = CPU_RC32300;
mips_cpu.isa_level = MIPS_CPU_ISA_M32;
mips_cpu.options = R4K_OPTS | MIPS_CPU_DIVEC |
- MIPS_CPU_WATCH;
+ MIPS_CPU_WATCH;
mips_cpu.tlbsize = 16;
mips_cpu.icache.ways = 2;
mips_cpu.dcache.ways = 2;
@@ -549,9 +551,9 @@
mips_cpu.cputype = CPU_SR7100;
mips_cpu.isa_level = MIPS_CPU_ISA_M64;
mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
- MIPS_CPU_4KTLB | MIPS_CPU_FPU |
- MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
- MIPS_CPU_MCHECK;
+ MIPS_CPU_4KTLB | MIPS_CPU_FPU |
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+ MIPS_CPU_MCHECK;
mips_cpu.scache.ways = 8;
break;
}
@@ -585,13 +587,14 @@
#endif
cpu_report();
+
/*
* Determine the mmu/cache attached to this machine,
* then flush the tlb and caches. On the r4xx0
* variants this also sets CP0_WIRED to zero.
*/
loadmmu();
-
+
/* Disable coprocessors and set FPU for 16 FPRs */
s = read_32bit_cp0_register(CP0_STATUS);
s &= ~(ST0_CU1|ST0_CU2|ST0_CU3|ST0_KX|ST0_SX|ST0_FR);
@@ -720,13 +723,13 @@
void swarm_setup(void);
void hp_setup(void);
void idt_setup(void);
- void casio_be300_setup(void);
+ void casio_be300_setup(void);
unsigned long bootmap_size;
- unsigned long start_pfn, max_pfn, first_usable_pfn;
+ unsigned long start_pfn, max_pfn, max_low_pfn, first_usable_pfn;
#ifdef CONFIG_BLK_DEV_INITRD
- unsigned long* initrd_header;
unsigned long tmp;
+ unsigned long* initrd_header;
#endif
int i;
@@ -751,10 +754,10 @@
baget_setup();
break;
#endif
-#ifdef CONFIG_COBALT_MICRO_SERVER
- case MACH_GROUP_COBALT:
- cobalt_setup();
- break;
+#ifdef CONFIG_MIPS_COBALT
+ case MACH_GROUP_COBALT:
+ cobalt_setup();
+ break;
#endif
#ifdef CONFIG_DECSTATION
case MACH_GROUP_DEC:
@@ -878,16 +881,16 @@
jmr3927_setup();
break;
#endif
-#ifdef CONFIG_PS2
- case MACH_GROUP_EE:
- ps2_setup();
- break;
-#endif
#ifdef CONFIG_SIBYTE_SWARM
case MACH_GROUP_SIBYTE:
swarm_setup();
break;
#endif
+#ifdef CONFIG_PS2
+ case MACH_GROUP_EE:
+ ps2_setup();
+ break;
+#endif
#ifdef CONFIG_HP_LASERJET
case MACH_GROUP_HP_LJ:
hp_setup();
@@ -913,6 +916,9 @@
#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
+#define MAXMEM HIGHMEM_START
+#define MAXMEM_PFN PFN_DOWN(MAXMEM)
+
#ifdef CONFIG_BLK_DEV_INITRD
tmp = (((unsigned long)&_end + PAGE_SIZE-1) & PAGE_MASK) - 8;
if (tmp < (unsigned long)&_end)
@@ -956,9 +962,36 @@
}
}
}
-
- /* Initialize the boot-time allocator. */
- bootmap_size = init_bootmem(first_usable_pfn, max_pfn);
+
+ /*
+ * Determine low and high memory ranges
+ */
+ max_low_pfn = max_pfn;
+ if (max_low_pfn > MAXMEM_PFN) {
+ max_low_pfn = MAXMEM_PFN;
+#ifndef CONFIG_HIGHMEM
+ /* Maximum memory usable is what is directly addressable */
+ printk(KERN_WARNING "Warning only %ldMB will be used.\n",
+ MAXMEM>>20);
+ printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
+#endif
+ }
+
+#ifdef CONFIG_HIGHMEM
+ /*
+ * Crude, we really should make a better attempt at detecting
+ * highstart_pfn
+ */
+ highstart_pfn = highend_pfn = max_pfn;
+ if (max_pfn > MAXMEM_PFN) {
+ highstart_pfn = MAXMEM_PFN;
+ printk(KERN_NOTICE "%ldMB HIGHMEM available.\n",
+ (highend_pfn - highstart_pfn) >> (20 - PAGE_SHIFT));
+ }
+#endif
+
+ /* Initialize the boot-time allocator with low memory only. */
+ bootmap_size = init_bootmem(first_usable_pfn, max_low_pfn);
/*
* Register fully available low RAM pages with the bootmem allocator.
@@ -976,7 +1009,7 @@
* We are rounding up the start address of usable memory:
*/
curr_pfn = PFN_UP(boot_mem_map.map[i].addr);
- if (curr_pfn >= max_pfn)
+ if (curr_pfn >= max_low_pfn)
continue;
if (curr_pfn < start_pfn)
curr_pfn = start_pfn;
@@ -987,17 +1020,28 @@
last_pfn = PFN_DOWN(boot_mem_map.map[i].addr
+ boot_mem_map.map[i].size);
- if (last_pfn > max_pfn)
- last_pfn = max_pfn;
+ if (last_pfn > max_low_pfn)
+ last_pfn = max_low_pfn;
/*
+ * Only register lowmem part of lowmem segment with bootmem.
+ */
+ size = last_pfn - curr_pfn;
+ if (curr_pfn > PFN_DOWN(HIGHMEM_START))
+ continue;
+ if (curr_pfn + size - 1 > PFN_DOWN(HIGHMEM_START))
+ size = PFN_DOWN(HIGHMEM_START) - curr_pfn;
+ if (!size)
+ continue;
+
+ /*
* ... finally, did all the rounding and playing
* around just make the area go away?
*/
if (last_pfn <= curr_pfn)
continue;
- size = last_pfn - curr_pfn;
+ /* Register lowmem ranges */
free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
}
@@ -1093,8 +1137,8 @@
*/
void sr7100_wait(void)
{
- u32 *jump = ((u32 *)&ret_from_irq_sr7100);
-
+u32 *jump = ((u32 *)&ret_from_irq_sr7100);
+
__asm__ __volatile__ (
".set push\n\t"
".set noat\n\t"
|
|
From: James S. <jsi...@us...> - 2002-01-28 18:48:13
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv30246/include/asm-mips
Modified Files:
io.h mipsregs.h page.h pgalloc.h pgtable.h
Log Message:
Support for 64-bit addresses in page tables.
Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/io.h,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- io.h 2002/01/02 18:10:40 1.15
+++ io.h 2002/01/28 18:48:10 1.16
@@ -12,11 +12,10 @@
#define _ASM_IO_H
#include <linux/config.h>
+#include <linux/pagemap.h>
#include <linux/types.h>
-
#include <asm/addrspace.h>
#include <asm/byteorder.h>
-#include <asm/mipsregs.h>
/*
* Slowdown I/O port space accesses for antique hardware.
@@ -143,12 +142,12 @@
static inline void *ioremap(unsigned long offset, unsigned long size)
{
- return __ioremap(offset, size, CONF_CM_UNCACHED << 9);
+ return __ioremap(offset, size, _CACHE_UNCACHED);
}
static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
{
- return __ioremap(offset, size, CONF_CM_UNCACHED << 9);
+ return __ioremap(offset, size, _CACHE_UNCACHED);
}
extern void iounmap(void *addr);
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -d -r1.15 -r1.16
--- mipsregs.h 2002/01/19 21:17:35 1.15
+++ mipsregs.h 2002/01/28 18:48:10 1.16
@@ -466,7 +466,7 @@
* For now use this only with interrupts disabled!
*/
#define read_64bit_cp0_register(source) \
-({ int __res; \
+({ unsigned long __res; \
__asm__ __volatile__( \
".set\tmips3\n\t" \
"dmfc0\t%0,"STR(source)"\n\t" \
@@ -493,26 +493,6 @@
".set\tmips0" \
: : "r" (value))
-#define read_32bit_cp0_registerx(source,sel) \
-({ int __res; \
- __asm__ __volatile__( \
- ".set\tpush\n\t" \
- ".set\treorder\n\t" \
- ".set\tmips64\n\t" \
- "mfc0\t%0,"STR(source)","STR(sel)"\n\t" \
- ".set\tmips0\n\t" \
- ".set\tpop" \
- : "=r" (__res)); \
- __res;})
-
-#define write_32bit_cp0_registerx(register,sel,value) \
- __asm__ __volatile__( \
- ".set\tmips64\n\t" \
- "mtc0\t%0,"STR(register)","STR(sel)"\n\t" \
- ".set\tmips0\n\t" \
- "nop" \
- : : "r" (value));
-
/*
* This should be changed when we get a compiler that support the MIPS32 ISA.
*/
@@ -607,20 +587,6 @@
: : "Jr" (val));
}
-/* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
-static inline unsigned long get_entrylo0(void)
-{
- unsigned long val;
-
- __asm__ __volatile__(
- ".set push\n\t"
- ".set reorder\n\t"
- "mfc0 %0, $2\n\t"
- ".set pop"
- : "=r" (val));
- return val;
-}
-
#if defined(CONFIG_64BIT_PHYS_ADDR) && !defined(CONFIG_CPU_MIPS32)
/*
@@ -644,6 +610,41 @@
__restore_flags(flags);
}
+static inline void set_entrylo1(unsigned long long val)
+{
+ unsigned long flags;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips3\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ "dsll\t%M0, %M0, 32\n\t"
+ "or\t%L0, %L0, %M0\n\t"
+ "dmtc0\t%0, $3\n\t"
+ ".set\tmips0"
+ : : "r" (val));
+ __restore_flags(flags);
+}
+
+static inline unsigned long long get_entrylo0(void)
+{
+ unsigned long flags, val;
+
+ __save_and_cli(flags);
+ __asm__ __volatile__(
+ ".set\tmips0\n\t"
+ "dmfc0 %0, $2\n\t"
+ "dsrl\t%M0, %M0, 32\n\t"
+ "dsll\t%L0, %L0, 32\n\t"
+ "dsrl\t%L0, %L0, 32\n\t"
+ ".set\tmips0"
+ : "=r" (val));
+ __restore_flags(flags);
+
+ return val;
+}
+
static inline unsigned long long get_entrylo1(void)
{
unsigned long flags, val;
@@ -674,30 +675,43 @@
: : "Jr" (val));
}
-static inline unsigned long get_entrylo1(void)
+static inline void set_entrylo1(unsigned long val)
+{
+ __asm__ __volatile__(
+ ".set push\n\t"
+ ".set reorder\n\t"
+ "mtc0 %z0, $3\n\t"
+ ".set pop"
+ : : "Jr" (val));
+}
+
+static inline unsigned long get_entrylo0(void)
{
unsigned long val;
__asm__ __volatile__(
".set push\n\t"
".set reorder\n\t"
- "mfc0 %0, $3\n\t"
+ "mfc0 %0, $2\n\t"
".set pop" : "=r" (val));
return val;
}
-#endif
-
-static inline void set_entrylo1(unsigned long val)
+static inline unsigned long get_entrylo1(void)
{
+ unsigned long val;
+
__asm__ __volatile__(
".set push\n\t"
".set reorder\n\t"
- "mtc0 %z0, $3\n\t"
- ".set pop"
- : : "Jr" (val));
+ "mfc0 %0, $3\n\t"
+ ".set pop" : "=r" (val));
+
+ return val;
}
+
+#endif
/* CP0_ENTRYHI register */
static inline unsigned long get_entryhi(void)
Index: page.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/page.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- page.h 2002/01/02 17:08:26 1.5
+++ page.h 2002/01/28 18:48:10 1.6
@@ -116,6 +116,11 @@
#define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
#define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
+/*
+ * Memory above this physical address will be considered highmem.
+ */
+#define HIGHMEM_START (0x20000000)
+
#endif /* defined (__KERNEL__) */
#endif /* __ASM_PAGE_H */
Index: pgalloc.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgalloc.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- pgalloc.h 2002/01/02 18:10:40 1.6
+++ pgalloc.h 2002/01/28 18:48:10 1.7
@@ -11,6 +11,7 @@
#include <linux/config.h>
#include <linux/mm.h>
+#include <asm/fixmap.h>
/* TLB flushing:
*
@@ -103,8 +104,6 @@
{
free_pages((unsigned long)pgd, PGD_ORDER);
}
-
-extern pte_t *get_pte_slow(pmd_t *pmd, unsigned long address_preadjusted);
extern __inline__ pte_t *get_pte_fast(void)
{
Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- pgtable.h 2002/01/02 18:10:40 1.10
+++ pgtable.h 2002/01/28 18:48:10 1.11
@@ -9,6 +9,7 @@
#ifndef _ASM_PGTABLE_H
#define _ASM_PGTABLE_H
+#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/page.h>
@@ -16,7 +17,7 @@
#include <linux/linkage.h>
#include <asm/cachectl.h>
-#include <linux/config.h>
+#include <asm/fixmap.h>
/* Cache flushing:
*
@@ -34,12 +35,13 @@
extern void (*___flush_cache_all)(void);
extern void (*_flush_cache_mm)(struct mm_struct *mm);
extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
- unsigned long end);
-extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+ unsigned long end);
+extern void (*_flush_cache_page)(struct vm_area_struct *vma,
+ unsigned long page);
extern void (*_flush_page_to_ram)(struct page * page);
extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
extern void (*_flush_icache_page)(struct vm_area_struct *vma,
- struct page *page);
+ struct page *page);
extern void (*_flush_cache_sigtramp)(unsigned long addr);
extern void (*_flush_icache_all)(void);
@@ -118,12 +120,17 @@
#define PGD_ORDER 0
#endif
-#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
+#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
#define FIRST_USER_PGD_NR 0
#define VMALLOC_START KSEG2
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
-#define VMALLOC_END KSEG3
+
+#if CONFIG_HIGHMEM
+# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
+#else
+# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
+#endif
/* Note that we shift the lower 32bits of each EntryLo[01] entry
* 6 bits to the left. That way we can convert the PFN into the
@@ -246,12 +253,17 @@
#if !defined (_LANGUAGE_ASSEMBLY)
+#ifdef CONFIG_64BIT_PHYS_ADDR
#define pte_ERROR(e) \
- printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+ printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
+#else
+#define pte_ERROR(e) \
+ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#endif
#define pmd_ERROR(e) \
- printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+ printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
#define pgd_ERROR(e) \
- printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
+ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
extern unsigned long empty_zero_page;
extern unsigned long zero_page_mask;
@@ -336,8 +348,8 @@
static inline void pgd_clear(pgd_t *pgdp) { }
/*
- * Permanent address of a page. On MIPS we never have highmem, so this
- * is simple.
+ * Permanent address of a page. Obviously must never be called on a highmem
+ * page.
*/
#define page_address(page) ((page)->virtual)
#ifdef CONFIG_CPU_VR41XX
@@ -469,6 +481,10 @@
}
#define page_pte(page) page_pte_prot(page, __pgprot(0))
+
+#define __pgd_offset(address) pgd_index(address)
+#define __pmd_offset(address) \
+ (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
|
|
From: James S. <jsi...@us...> - 2002-01-28 18:38:37
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv27385
Modified Files:
tlb-r4k.c
Log Message:
More CONFIG_64BIT_PHYS_ADDR fixes for TLB exception handlers.
Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- tlb-r4k.c 2002/01/15 00:34:07 1.8
+++ tlb-r4k.c 2002/01/28 18:38:34 1.9
@@ -140,7 +140,7 @@
void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
- if (vma->vm_mm->context != 0) {
+ if (!vma || vma->vm_mm->context != 0) {
unsigned long flags;
int oldpid, newpid, idx;
|
|
From: James S. <jsi...@us...> - 2002-01-28 18:36:01
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv26617/mm
Modified Files:
init.c
Log Message:
CONFIG_64BIT_PHYS_ADDR changes the size of swapper_pg_dir also.
Index: init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/init.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- init.c 2002/01/02 18:10:40 1.3
+++ init.c 2002/01/28 18:35:59 1.4
@@ -39,7 +39,9 @@
#include <asm/tlb.h>
mmu_gather_t mmu_gathers[NR_CPUS];
+unsigned long highstart_pfn, highend_pfn;
static unsigned long totalram_pages;
+static unsigned long totalhigh_pages;
extern void prom_free_prom_memory(void);
@@ -105,6 +107,26 @@
return freed;
}
+#if CONFIG_HIGHMEM
+pte_t *kmap_pte;
+pgprot_t kmap_prot;
+
+#define kmap_get_fixmap_pte(vaddr) \
+ pte_offset(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr))
+
+static void __init kmap_init(void)
+{
+ unsigned long kmap_vstart;
+
+ /* cache the first kmap pte */
+ kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN);
+ kmap_pte = kmap_get_fixmap_pte(kmap_vstart);
+
+ kmap_prot = PAGE_KERNEL;
+}
+
+#endif /* CONFIG_HIGHMEM */
+
void show_mem(void)
{
int i, free = 0, total = 0, reserved = 0;
@@ -139,17 +161,77 @@
extern char _ftext, _etext, _fdata, _edata;
extern char __init_begin, __init_end;
-void __init paging_init(void)
+static void __init fixrange_init (unsigned long start, unsigned long end,
+ pgd_t *pgd_base)
{
- unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
- unsigned long max_dma, low;
+ pgd_t *pgd;
+ pmd_t *pmd;
+ pte_t *pte;
+ int i, j;
+ unsigned long vaddr;
+ vaddr = start;
+ i = __pgd_offset(vaddr);
+ j = __pmd_offset(vaddr);
+ pgd = pgd_base + i;
+
+ for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
+ pmd = (pmd_t *)pgd;
+ for (; (j < PTRS_PER_PMD) && (vaddr != end); pmd++, j++) {
+ if (pmd_none(*pmd)) {
+ pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
+ set_pmd(pmd, __pmd(pte));
+ if (pte != pte_offset(pmd, 0))
+ BUG();
+ }
+ vaddr += PMD_SIZE;
+ }
+ j = 0;
+ }
+}
+
+void __init pagetable_init(void)
+{
+ unsigned long vaddr;
+ pgd_t *pgd, *pgd_base;
+ pmd_t *pmd;
+ pte_t *pte;
+
/* Initialize the entire pgd. */
pgd_init((unsigned long)swapper_pg_dir);
- pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
+ pgd_init((unsigned long)swapper_pg_dir +
+ sizeof(pgd_t ) * USER_PTRS_PER_PGD);
+
+ pgd_base = swapper_pg_dir;
+#ifdef CONFIG_HIGHMEM
+ /*
+ * Permanent kmaps:
+ */
+ vaddr = PKMAP_BASE;
+ fixrange_init(vaddr, vaddr + PAGE_SIZE*LAST_PKMAP, pgd_base);
+
+ pgd = swapper_pg_dir + __pgd_offset(vaddr);
+ pmd = pmd_offset(pgd, vaddr);
+ pte = pte_offset(pmd, vaddr);
+ pkmap_page_table = pte;
+#endif
+}
+
+void __init paging_init(void)
+{
+ unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
+ unsigned long max_dma, high, low;
+
+ pagetable_init();
+
+#ifdef CONFIG_HIGHMEM
+ kmap_init();
+#endif
+
max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
low = max_low_pfn;
+ high = highend_pfn;
#if defined(CONFIG_PCI) || defined(CONFIG_ISA)
if (low < max_dma)
@@ -161,6 +243,9 @@
#else
zones_size[ZONE_DMA] = low;
#endif
+#ifdef CONFIG_HIGHMEM
+ zones_size[ZONE_HIGHMEM] = high - low;
+#endif
free_area_init(zones_size);
}
@@ -195,8 +280,17 @@
unsigned long codesize, reservedpages, datasize, initsize;
unsigned long tmp, ram;
+#ifdef CONFIG_HIGHMEM
+ highstart_pfn = (KSEG1 - KSEG0) >> PAGE_SHIFT;
+ highmem_start_page = mem_map + highstart_pfn;
+#ifdef CONFIG_DISCONTIGMEM
+#error "CONFIG_HIGHMEM and CONFIG_DISCONTIGMEM dont work together yet"
+#endif
+ max_mapnr = num_physpages = highend_pfn;
+#else
max_mapnr = num_physpages = max_low_pfn;
- high_memory = (void *) __va(max_mapnr << PAGE_SHIFT);
+#endif
+ high_memory = (void *) __va(max_low_pfn * PAGE_SIZE);
totalram_pages += free_all_bootmem();
totalram_pages -= setup_zero_pages(); /* Setup zeroed pages. */
@@ -209,18 +303,36 @@
reservedpages++;
}
+#ifdef CONFIG_HIGHMEM
+ for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
+ struct page *page = mem_map + tmp;
+
+ if (!page_is_ram(tmp)) {
+ SetPageReserved(page);
+ continue;
+ }
+ ClearPageReserved(page);
+ set_bit(PG_highmem, &page->flags);
+ atomic_set(&page->count, 1);
+ __free_page(page);
+ totalhigh_pages++;
+ }
+ totalram_pages += totalhigh_pages;
+#endif
+
codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
printk("Memory: %luk/%luk available (%ldk kernel code, %ldk reserved, "
- "%ldk data, %ldk init)\n",
+ "%ldk data, %ldk init, %ldk highmem)\n",
(unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
ram << (PAGE_SHIFT-10),
codesize >> 10,
reservedpages << (PAGE_SHIFT-10),
datasize >> 10,
- initsize >> 10);
+ initsize >> 10,
+ (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
}
#ifdef CONFIG_BLK_DEV_INITRD
@@ -266,7 +378,7 @@
val->sharedram = 0;
val->freeram = nr_free_pages();
val->bufferram = atomic_read(&buffermem_pages);
- val->totalhigh = 0;
+ val->totalhigh = totalhigh_pages;
val->freehigh = nr_free_highpages();
val->mem_unit = PAGE_SIZE;
|
|
From: James S. <jsi...@us...> - 2002-01-28 18:30:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm In directory usw-pr-cvs1:/tmp/cvs-serv25211 Modified Files: fault.c Log Message: Fix address of lower boundary of vmalloc address space. Index: fault.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/fault.c,v retrieving revision 1.8 retrieving revision 1.9 diff -u -d -r1.8 -r1.9 --- fault.c 2001/12/07 19:28:37 1.8 +++ fault.c 2002/01/28 18:30:33 1.9 @@ -89,7 +89,7 @@ * only copy the information from the master page table, * nothing more. */ - if (address >= TASK_SIZE) + if (address >= VMALLOC_START) goto vmalloc_fault; info.si_code = SEGV_MAPERR; |
|
From: Steve L. <slo...@us...> - 2002-01-24 20:13:57
|
Update of /cvsroot/linux-mips/linux/include/asm-mips/rc32300
In directory usw-pr-cvs1:/tmp/cvs-serv9531
Modified Files:
rc32300.h
Log Message:
H/W PCI byte-swapping on the RC32334 does not work - disable and
use s/w swapping instead (CONFIG_SWAP_IO_SPACE).
Index: rc32300.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32300/rc32300.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- rc32300.h 2002/01/17 21:06:46 1.2
+++ rc32300.h 2002/01/24 20:13:54 1.3
@@ -59,6 +59,44 @@
}
/*
+ * Macros to access internal RC32300 registers. No byte
+ * swapping should be done when accessing the internal
+ * registers.
+ */
+static inline u8 rc32300_inb(unsigned long pa)
+{
+ return *((volatile u8 *)(mips_io_port_base + pa));
+}
+static inline u16 rc32300_inw(unsigned long pa)
+{
+ return *((volatile u16 *)(mips_io_port_base + pa));
+}
+static inline u32 rc32300_inl(unsigned long pa)
+{
+ return *((volatile u32 *)(mips_io_port_base + pa));
+}
+static inline void rc32300_outb(u8 val, unsigned long pa)
+{
+ *((volatile u8 *)(mips_io_port_base + pa)) = val;
+}
+static inline void rc32300_outw(u16 val, unsigned long pa)
+{
+ *((volatile u16 *)(mips_io_port_base + pa)) = val;
+}
+static inline void rc32300_outl(u32 val, unsigned long pa)
+{
+ *((volatile u32 *)(mips_io_port_base + pa)) = val;
+}
+static inline u32 rc32300_readl(unsigned long va)
+{
+ return *((volatile u32 *)va);
+}
+static inline void rc32300_writel(u32 val, unsigned long va)
+{
+ *((volatile u32 *)va) = val;
+}
+
+/*
* C access to CLZ and CLO instructions
* (count leading zeroes/ones).
*/
|
|
From: Steve L. <slo...@us...> - 2002-01-24 20:13:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/common
In directory usw-pr-cvs1:/tmp/cvs-serv9288/rc32300/common
Modified Files:
dbg_io.c puts.c reset.c
Log Message:
H/W PCI byte-swapping on the RC32334 does not work - disable and
use s/w swapping instead (CONFIG_SWAP_IO_SPACE).
Index: dbg_io.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/dbg_io.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- dbg_io.c 2002/01/17 21:07:24 1.4
+++ dbg_io.c 2002/01/24 20:13:34 1.5
@@ -58,8 +58,8 @@
/* memory-mapped read/write of the port */
-#define UART16550_READ(y) inb(DEBUG_BASE + y)
-#define UART16550_WRITE(y,z) outb(z, DEBUG_BASE + y)
+#define UART16550_READ(y) rc32300_inb(DEBUG_BASE + y)
+#define UART16550_WRITE(y,z) rc32300_outb(z, DEBUG_BASE + y)
static void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
Index: puts.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/puts.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- puts.c 2002/01/17 21:07:24 1.5
+++ puts.c 2002/01/24 20:13:34 1.6
@@ -58,14 +58,14 @@
int i = 0;
do {
- ch = inb(SER_CMD);
+ ch = rc32300_inb(SER_CMD);
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
- outb(c, SER_DATA);
+ rc32300_outb(c, SER_DATA);
}
void puts(unsigned char *cp)
@@ -75,14 +75,14 @@
while (*cp) {
do {
- ch = inb(SER_CMD);
+ ch = rc32300_inb(SER_CMD);
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
- outb(*cp++, SER_DATA);
+ rc32300_outb(*cp++, SER_DATA);
}
putch('\r');
putch('\n');
@@ -96,14 +96,14 @@
while (*cp) {
do {
- ch = inb(SER_CMD);
+ ch = rc32300_inb(SER_CMD);
slow_down();
i++;
if (i > TIMEOUT) {
break;
}
} while (0 == (ch & TX_BUSY));
- outb(*cp++, SER_DATA);
+ rc32300_outb(*cp++, SER_DATA);
}
}
Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/reset.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- reset.c 2002/01/19 01:35:17 1.4
+++ reset.c 2002/01/24 20:13:34 1.5
@@ -46,11 +46,11 @@
#ifdef CONFIG_CPU_RC32334
// Trigger the WatchDog Timer (Timer 3) to warm reset
- outl(0, TIMER0_CNTL + 3*TIMER_REG_OFFSET);
- outl(0xd8, CPU_IP_BUSERR_CNTL);
- outl(0, TIMER0_COUNT + 3*TIMER_REG_OFFSET);
- outl(2, TIMER0_COMPARE + 3*TIMER_REG_OFFSET);
- outl(1, TIMER0_CNTL + 3*TIMER_REG_OFFSET);
+ rc32300_outl(0, TIMER0_CNTL + 3*TIMER_REG_OFFSET);
+ rc32300_outl(0xd8, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(0, TIMER0_COUNT + 3*TIMER_REG_OFFSET);
+ rc32300_outl(2, TIMER0_COMPARE + 3*TIMER_REG_OFFSET);
+ rc32300_outl(1, TIMER0_CNTL + 3*TIMER_REG_OFFSET);
#else
__asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
#endif
|
|
From: Steve L. <slo...@us...> - 2002-01-24 20:13:36
|
Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv9288/rc32300/79S334
Modified Files:
irq.c pci_fixup.c pci_ops.c setup.c
Log Message:
H/W PCI byte-swapping on the RC32334 does not work - disable and
use s/w swapping instead (CONFIG_SWAP_IO_SPACE).
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/irq.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- irq.c 2002/01/19 01:35:17 1.7
+++ irq.c 2002/01/24 20:13:34 1.8
@@ -105,12 +105,18 @@
{ GROUP14_IRQ_BASE, 1, 0x00000001 } // SPI intr
};
-#define READ_PEND(g) inl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
-#define WRITE_PEND(g,val) outl((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
-#define READ_MASK(g) inl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
-#define WRITE_MASK(g,val) outl((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
-#define READ_CLEAR(g) inl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
-#define WRITE_CLEAR(g,val) outl((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+#define READ_PEND(g) \
+ rc32300_inl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define WRITE_PEND(g,val) \
+ rc32300_outl((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define READ_MASK(g) \
+ rc32300_inl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define WRITE_MASK(g,val) \
+ rc32300_outl((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define READ_CLEAR(g) \
+ rc32300_inl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+#define WRITE_CLEAR(g,val) \
+ rc32300_outl((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
static inline int irq_to_group(unsigned int irq_nr)
{
@@ -381,7 +387,9 @@
return; // no interrupts in this group ???
intr = 31 - rc32300_clz(pend);
+#ifdef DEBUG_IRQ
idtprintf("%02d%02d", group, intr);
+#endif
do_IRQ(g->irq_base + intr, regs);
}
Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_fixup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci_fixup.c 2002/01/17 21:07:24 1.3
+++ pci_fixup.c 2002/01/24 20:13:34 1.4
@@ -53,7 +53,7 @@
/*
* Enable CPU and IP Bus Error exceptions, and disable WatchDog.
*/
- outl(0x18, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(0x18, CPU_IP_BUSERR_CNTL);
}
void __init pcibios_fixup_irqs(void)
Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_ops.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- pci_ops.c 2002/01/17 21:07:24 1.3
+++ pci_ops.c 2002/01/24 20:13:34 1.4
@@ -50,9 +50,9 @@
#endif
#ifdef __MIPSEB__
-#define SWAP_ENDIAN_BIT 1
+#define SWAP_BIT 1
#else
-#define SWAP_ENDIAN_BIT 0
+#define SWAP_BIT 0
#endif
extern struct resource rc32334_res_pci_io;
@@ -60,8 +60,11 @@
extern struct resource rc32334_res_pci_mem2;
extern struct resource rc32334_res_pci_mem3;
+extern char * __init prom_getcmdline(void);
+
#define PCI_CFG_SET(slot,func,off) \
- outl((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), PCI_CFG_CNTL)
+ rc32300_outl((0x80000000 | ((slot)<<11) | ((func)<<8) | (off)), \
+ PCI_CFG_CNTL)
static int
config_access(u8 type, u8 bus, u8 devfn, u8 where, u32 *data)
@@ -82,9 +85,9 @@
rc32300_sync();
if (type == PCI_ACCESS_WRITE)
- outl(*data, PCI_CFG_DATA);
+ rc32300_outl(*data, PCI_CFG_DATA);
else
- *data = inl(PCI_CFG_DATA);
+ *data = rc32300_inl(PCI_CFG_DATA);
rc32300_sync();
/*
@@ -236,13 +239,13 @@
u32 val;
printk("RC32334 PCI Bridge Config:\n");
- printk("PCI_MEM1_BASE: 0x%08x\n", inl(PCI_MEM1_BASE));
- printk("PCI_MEM2_BASE: 0x%08x\n", inl(PCI_MEM2_BASE));
- printk("PCI_MEM3_BASE: 0x%08x\n", inl(PCI_MEM3_BASE));
- printk("PCI_IO1_BASE: 0x%08x\n", inl(PCI_IO1_BASE));
- printk("PCI_ARBITRATION:0x%08x\n", inl(PCI_ARBITRATION));
- printk("PCI_CPU_MEM1_BASE:0x%08x\n", inl(PCI_CPU_MEM1_BASE));
- printk("PCI_CPU_IO_BASE:0x%08x\n", inl(PCI_CPU_IO_BASE));
+ printk("PCI_MEM1_BASE: 0x%08x\n", rc32300_inl(PCI_MEM1_BASE));
+ printk("PCI_MEM2_BASE: 0x%08x\n", rc32300_inl(PCI_MEM2_BASE));
+ printk("PCI_MEM3_BASE: 0x%08x\n", rc32300_inl(PCI_MEM3_BASE));
+ printk("PCI_IO1_BASE: 0x%08x\n", rc32300_inl(PCI_IO1_BASE));
+ printk("PCI_ARBITRATION:0x%08x\n", rc32300_inl(PCI_ARBITRATION));
+ printk("PCI_CPU_MEM1_BASE:0x%08x\n", rc32300_inl(PCI_CPU_MEM1_BASE));
+ printk("PCI_CPU_IO_BASE:0x%08x\n", rc32300_inl(PCI_CPU_IO_BASE));
for (i=0; i<17; i++) {
config_read(0, 0, i*4, &val);
@@ -252,8 +255,10 @@
void __init rc32334_pcibridge_init(void)
{
+ char *argptr;
+
/* allow writes to bridge config space */
- outl(4, PCI_ARBITRATION);
+ rc32300_outl(4, PCI_ARBITRATION);
config_write(0, 0, PCI_VENDOR_ID,
PCI_VENDOR_ID_IDT | (PCI_DEVICE_ID_IDT_RC32334 << 16));
@@ -283,24 +288,56 @@
/* retry timeout, trdy timeout */
config_write(0, 0, PCI_INTERRUPT_LINE+4, 0x00008080);
- outl(0x00000000, PCI_CFG_CNTL);
+ rc32300_outl(0x00000000, PCI_CFG_CNTL);
/*
* CPU -> PCI address translation. Make CPU physical and
* PCI bus addresses the same.
*/
+ /*
+ * Note!
+ *
+ * Contrary to the RC32334 documentation, the behavior of
+ * the PCI byte-swapping bits appears to be the following:
+ *
+ * when cpu is in LE: 0 = don't swap, 1 = swap
+ * when cpu is in BE: 1 = don't swap, 0 = swap
+ *
+ * This is true both when the cpu/DMA accesses PCI device
+ * memory/io, and when a PCI bus master accesses system memory.
+ *
+ * Furthermore, byte-swapping doesn't even seem to work
+ * correctly when it is enabled.
+ *
+ * The solution to all this is to disable h/w byte-swapping,
+ * use s/w swapping (CONFIG_SWAP_IO_SPACE) for the in/out/read/
+ * write macros (which takes care of device accesses by cpu/dma)
+ * and hope that drivers swap device data in memory (which takes
+ * care of memory accesses by bus-masters).
+ *
+ * Finally, despite the above workaround, there are still
+ * PCI h/w problems on the 79S334A. PCI bus timeouts and
+ * system/parity errors have been encountered.
+ */
+
/* mem space 1 */
- outl(rc32334_res_pci_mem1.start, PCI_MEM1_BASE);
+ rc32300_outl(rc32334_res_pci_mem1.start | SWAP_BIT, PCI_MEM1_BASE);
/* mem space 2 */
- outl(rc32334_res_pci_mem2.start, PCI_MEM2_BASE);
+ rc32300_outl(rc32334_res_pci_mem2.start | SWAP_BIT, PCI_MEM2_BASE);
/* mem space 3 */
- outl(rc32334_res_pci_mem3.start, PCI_MEM3_BASE);
+ rc32300_outl(rc32334_res_pci_mem3.start | SWAP_BIT, PCI_MEM3_BASE);
/* i/o space */
- outl(rc32334_res_pci_io.start, PCI_IO1_BASE);
+ rc32300_outl(rc32334_res_pci_io.start | SWAP_BIT, PCI_IO1_BASE);
- /* use internal arbiter, 0=round robin, 1=fixed arbitration */
- outl(0, PCI_ARBITRATION);
+ argptr = prom_getcmdline();
+ if ((argptr = strstr(argptr, "pciextarb")) == NULL) {
+ /* use internal arbiter, 0=round robin, 1=fixed */
+ rc32300_outl(0, PCI_ARBITRATION);
+ } else {
+ /* use external arbiter */
+ rc32300_outl(2, PCI_ARBITRATION);
+ }
/*
* PCI -> CPU accesses
@@ -308,8 +345,8 @@
* Let PCI see system memory at 0x00000000 physical
*/
- outl(0x0 | SWAP_ENDIAN_BIT, PCI_CPU_MEM1_BASE); /* mem space */
- outl(0x0 | SWAP_ENDIAN_BIT, PCI_CPU_IO_BASE); /* i/o space */
+ rc32300_outl(0x0 | SWAP_BIT, PCI_CPU_MEM1_BASE); /* mem space */
+ rc32300_outl(0x0 | SWAP_BIT, PCI_CPU_IO_BASE); /* i/o space */
rc32300_sync();
}
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- setup.c 2002/01/19 01:47:29 1.5
+++ setup.c 2002/01/24 20:13:34 1.6
@@ -138,9 +138,9 @@
printk("RC32334 %s bus error:\n", data ? "Data" : "Instruction");
printk(" EPC == %08lx, RA == %08lx\n", regs->cp0_epc, regs->regs[31]);
- printk(" CPU bus address == %08x\n", readl(CPU_BUSERR_ADDR));
- printk(" IP bus address == %08x\n", inl(CPU_IP_BUSERR_ADDR));
- cntl = inl(CPU_IP_BUSERR_CNTL);
+ printk(" CPU bus address == %08x\n", rc32300_readl(CPU_BUSERR_ADDR));
+ printk(" IP bus address == %08x\n", rc32300_inl(CPU_IP_BUSERR_ADDR));
+ cntl = rc32300_inl(CPU_IP_BUSERR_CNTL);
printk(" Bus error occured on a %s on %s bus\n",
cntl & 1 ? "read" : "write",
cntl & 4 ? "CPU" : "IP");
@@ -149,7 +149,7 @@
rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr
rc32300_ack_irq(GROUP4_IRQ_BASE+5); // ack timer 5 rollover intr
rc32300_ack_irq(GROUP1_IRQ_BASE); // ack bus error intr
- outl(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(cntl & ~0x07, CPU_IP_BUSERR_CNTL);
//die_if_kernel("Oops", regs);
force_sig(SIGBUS, current);
@@ -175,24 +175,24 @@
* Disable CPU and IP Bus Error exceptions (PCI scan will
* cause bus timeouts), and disable WatchDog.
*/
- outl(0x98, CPU_IP_BUSERR_CNTL);
+ rc32300_outl(0x98, CPU_IP_BUSERR_CNTL);
- outl(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
- outl(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
- outl(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
- outl(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
- outl(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
- outl(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+ rc32300_outl(0, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+ rc32300_outl(0, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
+ rc32300_outl(0x3fff, TIMER0_COMPARE + 4*TIMER_REG_OFFSET);
+ rc32300_outl(0x3fff, TIMER0_COMPARE + 5*TIMER_REG_OFFSET);
+ rc32300_outl(1, TIMER0_CNTL + 4*TIMER_REG_OFFSET);
+ rc32300_outl(1, TIMER0_CNTL + 5*TIMER_REG_OFFSET);
#if 0
printk(__FUNCTION__ ": Timer4 Cntl = 0x%08x\n",
- inl(TIMER0_CNTL + 4*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_CNTL + 4*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer4 Cmp = 0x%08x\n",
- inl(TIMER0_COMPARE + 4*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_COMPARE + 4*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer5 Cntl = 0x%08x\n",
- inl(TIMER0_CNTL + 5*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_CNTL + 5*TIMER_REG_OFFSET));
printk(__FUNCTION__ ": Timer5 Cmp = 0x%08x\n",
- inl(TIMER0_COMPARE + 5*TIMER_REG_OFFSET));
+ rc32300_inl(TIMER0_COMPARE + 5*TIMER_REG_OFFSET));
request_irq(GROUP4_IRQ_BASE+4, bus_error_interrupt, SA_INTERRUPT,
"RC32334 CPU Bus Error", NULL);
@@ -230,6 +230,8 @@
// clear out any wired entries
write_32bit_cp0_register(CP0_WIRED, 0);
+ inb(LCD_CLEAR); // clear the 4-digit LCD display
+
#ifdef CONFIG_BLK_DEV_INITRD
ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
initrd_start = (unsigned long)&__rd_start;
@@ -238,43 +240,43 @@
#if 0
printk(__FUNCTION__ ": CPU_PORT_WIDTH = 0x%08x\n",
- readl(CPU_PORT_WIDTH));
+ rc32300_readl(CPU_PORT_WIDTH));
printk(__FUNCTION__ ": CPU_BTA = 0x%08x\n",
- readl(CPU_BTA));
+ rc32300_readl(CPU_BTA));
printk(__FUNCTION__ ": CPU_BUSERR_ADDR = 0x%08x\n",
- readl(CPU_BUSERR_ADDR));
+ rc32300_readl(CPU_BUSERR_ADDR));
printk(__FUNCTION__ ": CPU_IP_BTA = 0x%08x\n",
- inl(CPU_IP_BTA));
+ rc32300_inl(CPU_IP_BTA));
printk(__FUNCTION__ ": CPU_IP_ADDR_LATCH = 0x%08x\n",
- inl(CPU_IP_ADDR_LATCH));
+ rc32300_inl(CPU_IP_ADDR_LATCH));
printk(__FUNCTION__ ": CPU_IP_ARBITRATION = 0x%08x\n",
- inl(CPU_IP_ARBITRATION));
+ rc32300_inl(CPU_IP_ARBITRATION));
printk(__FUNCTION__ ": CPU_IP_BUSERR_CNTL = 0x%08x\n",
- inl(CPU_IP_BUSERR_CNTL));
+ rc32300_inl(CPU_IP_BUSERR_CNTL));
printk(__FUNCTION__ ": CPU_IP_BUSERR_ADDR = 0x%08x\n",
- inl(CPU_IP_BUSERR_ADDR));
+ rc32300_inl(CPU_IP_BUSERR_ADDR));
printk(__FUNCTION__ ": CPU_IP_SYSID = 0x%08x\n",
- inl(CPU_IP_SYSID));
+ rc32300_inl(CPU_IP_SYSID));
printk(__FUNCTION__ ": MEM_BASE_BANK0 = 0x%08x\n",
- inl(MEM_BASE_BANK0));
+ rc32300_inl(MEM_BASE_BANK0));
printk(__FUNCTION__ ": MEM_MASK_BANK0 = 0x%08x\n",
- inl(MEM_MASK_BANK0));
+ rc32300_inl(MEM_MASK_BANK0));
printk(__FUNCTION__ ": MEM_CNTL_BANK0 = 0x%08x\n",
- inl(MEM_CNTL_BANK0));
+ rc32300_inl(MEM_CNTL_BANK0));
printk(__FUNCTION__ ": MEM_BASE_BANK1 = 0x%08x\n",
- inl(MEM_BASE_BANK1));
+ rc32300_inl(MEM_BASE_BANK1));
printk(__FUNCTION__ ": MEM_MASK_BANK1 = 0x%08x\n",
- inl(MEM_MASK_BANK1));
+ rc32300_inl(MEM_MASK_BANK1));
printk(__FUNCTION__ ": MEM_CNTL_BANK1 = 0x%08x\n",
- inl(MEM_CNTL_BANK1));
+ rc32300_inl(MEM_CNTL_BANK1));
printk(__FUNCTION__ ": MEM_CNTL_BANK2 = 0x%08x\n",
- inl(MEM_CNTL_BANK2));
+ rc32300_inl(MEM_CNTL_BANK2));
printk(__FUNCTION__ ": MEM_CNTL_BANK3 = 0x%08x\n",
- inl(MEM_CNTL_BANK3));
+ rc32300_inl(MEM_CNTL_BANK3));
printk(__FUNCTION__ ": MEM_CNTL_BANK4 = 0x%08x\n",
- inl(MEM_CNTL_BANK4));
+ rc32300_inl(MEM_CNTL_BANK4));
printk(__FUNCTION__ ": MEM_CNTL_BANK5 = 0x%08x\n",
- inl(MEM_CNTL_BANK5));
+ rc32300_inl(MEM_CNTL_BANK5));
#endif
#ifdef CONFIG_PCI
|
|
From: Steve L. <slo...@us...> - 2002-01-24 20:13:36
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv9288
Modified Files:
config.in
Log Message:
H/W PCI byte-swapping on the RC32334 does not work - disable and
use s/w swapping instead (CONFIG_SWAP_IO_SPACE).
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.82
retrieving revision 1.83
diff -u -d -r1.82 -r1.83
--- config.in 2002/01/19 21:17:35 1.82
+++ config.in 2002/01/24 20:13:33 1.83
@@ -327,6 +327,7 @@
define_bool CONFIG_NEW_PCI y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_SWAP_IO_SPACE y
if [ "$CONFIG_VT" = "y" ]; then
define_bool CONFIG_PC_KEYB y
fi
@@ -340,6 +341,7 @@
define_bool CONFIG_NEW_PCI y
define_bool CONFIG_PCI_AUTO y
define_bool CONFIG_NONCOHERENT_IO y
+ define_bool CONFIG_SWAP_IO_SPACE y
if [ "$CONFIG_VT" = "y" ]; then
define_bool CONFIG_PC_KEYB y
fi
|
|
From: Steve L. <slo...@us...> - 2002-01-24 19:55:13
|
Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv3939
Modified Files:
Config.in
Log Message:
The TOSHIBA TC35815 option was in the wrong place.
Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/Config.in,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- Config.in 2001/12/02 19:05:31 1.18
+++ Config.in 2002/01/24 19:55:10 1.19
@@ -166,7 +166,6 @@
dep_tristate ' Apricot Xen-II on board Ethernet' CONFIG_APRICOT $CONFIG_ISA
dep_tristate ' CS89x0 support' CONFIG_CS89x0 $CONFIG_ISA
dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
- dep_tristate ' TOSHIBA TC35815 Ethernet support' CONFIG_TC35815 $CONFIG_PCI
if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
dep_bool ' New bus configuration (EXPERIMENTAL)' CONFIG_TULIP_MWI $CONFIG_EXPERIMENTAL
bool ' Use PCI shared mem for NIC registers' CONFIG_TULIP_MMIO
@@ -175,6 +174,7 @@
tristate ' Generic DECchip & DIGITAL EtherWORKS PCI/EISA' CONFIG_DE4X5
tristate ' Digi Intl. RightSwitch SE-X support' CONFIG_DGRS
fi
+ dep_tristate ' TOSHIBA TC35815 Ethernet support' CONFIG_TC35815 $CONFIG_PCI
dep_tristate ' Davicom DM910x/DM980x support' CONFIG_DM9102 $CONFIG_PCI
dep_tristate ' EtherExpressPro/100 support' CONFIG_EEPRO100 $CONFIG_PCI
dep_tristate ' Mylex EISA LNE390A/B support (EXPERIMENTAL)' CONFIG_LNE390 $CONFIG_EISA $CONFIG_EXPERIMENTAL
|
|
From: Paul M. <le...@us...> - 2002-01-22 22:08:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/korva
In directory usw-pr-cvs1:/tmp/cvs-serv5255/korva
Modified Files:
prom.c
Log Message:
Get rid of hardcoded ip=bootp.
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/korva/prom.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- prom.c 2001/12/18 02:10:17 1.4
+++ prom.c 2002/01/22 22:08:13 1.5
@@ -39,8 +39,9 @@
u32 sdtsr;
u32 ramsize;
+#ifdef CONFIG_SERIAL_CONSOLE
strcpy(arcs_cmdline, "console=ttyS0,115200");
- strcat(arcs_cmdline, " ip=bootp");
+#endif
mips_machgroup = MACH_GROUP_NEC_VR41XX;
mips_machtype = MACH_NEC_KORVA;
|
|
From: Paul M. <le...@us...> - 2002-01-22 22:08:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey
In directory usw-pr-cvs1:/tmp/cvs-serv5255/vr4181/osprey
Modified Files:
prom.c
Log Message:
Get rid of hardcoded ip=bootp.
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4181/osprey/prom.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- prom.c 2001/12/12 18:30:53 1.5
+++ prom.c 2002/01/22 22:08:13 1.6
@@ -34,7 +34,6 @@
*/
void __init prom_init()
{
- strcpy(arcs_cmdline, "ip=bootp ");
strcat(arcs_cmdline, "ether=46,0x03fe0300,eth0 ");
// strcpy(arcs_cmdline, "ether=0,0x0300,eth0 "
// strcat(arcs_cmdline, "video=vr4181fb:xres:240,yres:320,bpp:8 ");
|
|
From: Paul M. <le...@us...> - 2002-01-22 22:08:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100
In directory usw-pr-cvs1:/tmp/cvs-serv5255/jmr3927/rbhma3100
Modified Files:
setup.c
Log Message:
Get rid of hardcoded ip=bootp.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/jmr3927/rbhma3100/setup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- setup.c 2002/01/02 19:12:16 1.4
+++ setup.c 2002/01/22 22:08:13 1.5
@@ -279,11 +279,6 @@
if ((argptr = strstr(argptr, "toeon")) != NULL) {
jmr3927_ccfg_toeon = 1;
}
- argptr = prom_getcmdline();
- if ((argptr = strstr(argptr, "ip=")) == NULL) {
- argptr = prom_getcmdline();
- strcat(argptr, " ip=bootp");
- }
#ifdef CONFIG_TXX927_SERIAL_CONSOLE
argptr = prom_getcmdline();
|
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