linux-mips-commits Mailing List for Linux Mips (Page 29)

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Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv2432/asm-mips

Added Files:
	ptrace.h 
Log Message:
Don't include <asm/types.h>.





Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv1741

Modified Files:
	sb1250-mac.c 
Log Message:
Replace inclusion of <linux/malloc.h> with <linux/slab.h>.

Index: sb1250-mac.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/sb1250-mac.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2

--- sb1250-mac.c	7 Nov 2001 20:00:55 -0000	1.1
+++ sb1250-mac.c	12 Feb 2002 17:58:28 -0000	1.2
@@ -59,11 +59,11 @@
 #include <linux/timer.h>
 #include <linux/errno.h>
 #include <linux/ioport.h>
-#include <linux/malloc.h>
 #include <linux/interrupt.h>
 #include <linux/netdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/slab.h>
 #include <linux/init.h>
 #include <linux/config.h>
 #include <asm/processor.h>		/* Processor type for cache alignment. */




Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv7394/79S334

Modified Files:
	pci_fixup.c setup.c 
Log Message:
bus_error_init() was in, now it's out, so call it explicitly.


Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_fixup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- pci_fixup.c	24 Jan 2002 20:13:34 -0000	1.4
+++ pci_fixup.c	8 Feb 2002 00:33:55 -0000	1.5
@@ -41,9 +41,50 @@
 {
 }
 
+#if 0
+
+static void pci_master_error_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+	printk("RC32334 PCI master %s error\n", irq == GROUP11_IRQ_BASE+0 ?
+		"write" : "read");
+}
+
+static void pci_parity_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+	printk("RC32334 PCI %s parity error\n", irq == GROUP11_IRQ_BASE+2 ?
+	       "master" : "target");
+}
+
+static int __init init_pci_interrupts(void)
+{
+	request_irq(GROUP11_IRQ_BASE+0, pci_master_error_intr, SA_INTERRUPT,
+		    "RC32334 PCI Master Write Error", NULL);
+ 	request_irq(GROUP11_IRQ_BASE+1, pci_master_error_intr, SA_INTERRUPT,
+		    "RC32334 PCI Master Read Error", NULL);
+ 	request_irq(GROUP11_IRQ_BASE+2, pci_parity_intr, SA_INTERRUPT,
+		    "RC32334 PCI Master Parity Error", NULL);
+ 	request_irq(GROUP11_IRQ_BASE+3, pci_parity_intr, SA_INTERRUPT,
+		    "RC32334 PCI Target Parity Error", NULL);
+}
+
+static void __exit cleanup_pci_interrupts(void)
+{
+	free_irq(GROUP11_IRQ_BASE+0, NULL);
+	free_irq(GROUP11_IRQ_BASE+1, NULL);
+	free_irq(GROUP11_IRQ_BASE+2, NULL);
+	free_irq(GROUP11_IRQ_BASE+3, NULL);
+}
+
+#endif
+
 void __init pcibios_fixup(void)
 {
+	extern void (*ibe_board_handler)(struct pt_regs *regs);
+	extern void (*dbe_board_handler)(struct pt_regs *regs);
+	extern void rc32334_be_handler(struct pt_regs *regs);
 	extern void rc32300_ack_irq(unsigned int irq_nr);
+
+	ibe_board_handler = dbe_board_handler = rc32334_be_handler;
 
 	// ack any bus errors
 	rc32300_ack_irq(GROUP4_IRQ_BASE+4); // ack timer 4 rollover intr

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- setup.c	4 Feb 2002 21:21:42 -0000	1.7
+++ setup.c	8 Feb 2002 00:33:55 -0000	1.8
@@ -167,10 +167,6 @@
 	 * an interrupt.
 	 */
 
-	/* set bus error vectors to our custom handler */
-	set_except_vector(6, rc32334_be_handler);
-	set_except_vector(7, rc32334_be_handler);
-	
 	/*
 	 * Disable CPU and IP Bus Error exceptions (PCI scan will
 	 * cause bus timeouts), and disable WatchDog.
@@ -229,6 +225,8 @@
 
 	// clear out any wired entries
 	write_32bit_cp0_register(CP0_WIRED, 0);
+
+	bus_error_init();
 
 	inb(LCD_CLEAR); // clear the 4-digit LCD display
 




Update of /cvsroot/linux-mips/linux/drivers/net
In directory usw-pr-cvs1:/tmp/cvs-serv3054

Modified Files:
	ioc3-eth.c 
Log Message:
Start of merging SNIA modifications for the IOC3 driver. Implement byteorder swapping for accesses to the ring entries.

Index: ioc3-eth.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/net/ioc3-eth.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- ioc3-eth.c	2001/11/06 09:10:21	1.6
+++ ioc3-eth.c	2002/02/05 17:05:28	1.7
@@ -434,10 +434,10 @@
 
 	skb = ip->rx_skbs[rx_entry];
 	rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
-	w0 = rxb->w0;
+	w0 = be32_to_cpu(rxb->w0);
 
 	while (w0 & ERXBUF_V) {
-		err = rxb->err;				/* It's valid ...  */
+		err = be32_to_cpu(rxb->err);		/* It's valid ...  */
 		if (err & ERXBUF_GOODPKT) {
 			len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
 			skb_trim(skb, len);
@@ -478,8 +478,8 @@
 			ip->stats.rx_frame_errors++;
 next:
 		ip->rx_skbs[n_entry] = new_skb;
-		rxr[n_entry] = (0xa5UL << 56) |
-		                ((unsigned long) rxb & TO_PHYS_MASK);
+		rxr[n_entry] = cpu_to_be32((0xa5UL << 56) |
+		                         ((unsigned long) rxb & TO_PHYS_MASK));
 		rxb->w0 = 0;				/* Clear valid flag */
 		n_entry = (n_entry + 1) & 511;		/* Update erpir */
 
@@ -487,7 +487,7 @@
 		rx_entry = (rx_entry + 1) & 511;
 		skb = ip->rx_skbs[rx_entry];
 		rxb = (struct ioc3_erxbuf *) (skb->data - RX_OFFSET);
-		w0 = rxb->w0;
+		w0 = be32_to_cpu(rxb->w0);
 	}
 	ioc3->erpir = (n_entry << 3) | ERPIR_ARM;
 	ip->rx_pi = n_entry;
@@ -1189,8 +1189,8 @@
 			/* Because we reserve afterwards. */
 			skb_put(skb, (1664 + RX_OFFSET));
 			rxb = (struct ioc3_erxbuf *) skb->data;
-			rxr[i] = (0xa5UL << 56)
-				| ((unsigned long) rxb & TO_PHYS_MASK);
+			rxr[i] = cpu_to_be64((0xa5UL << 56) |
+			                ((unsigned long) rxb & TO_PHYS_MASK));
 			skb_reserve(skb, RX_OFFSET);
 		}
 		ip->rx_ci = 0;
@@ -1515,7 +1515,7 @@
 	name:		"ioc3-eth",
 	id_table:	ioc3_pci_tbl,
 	probe:		ioc3_probe,
-	remove:		ioc3_remove_one,
+	remove:		__devexit_p(ioc3_remove_one),
 };
 
 static int __init ioc3_init_module(void)
@@ -1554,8 +1554,8 @@
 			memset(desc->data + len, 0, ETH_ZLEN - len);
 			len = ETH_ZLEN;
 		}
-		desc->cmd    = len | ETXD_INTWHENDONE | ETXD_D0V;
-		desc->bufcnt = len;
+		desc->cmd    = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V);
+		desc->bufcnt = cpu_to_be32(len);
 	} else if ((data ^ (data + len)) & 0x4000) {
 		unsigned long b2, s1, s2;
 
@@ -1563,16 +1563,20 @@
 		s1 = b2 - data;
 		s2 = data + len - b2;
 
-		desc->cmd    = len | ETXD_INTWHENDONE | ETXD_B1V | ETXD_B2V;
-		desc->bufcnt = (s1 << ETXD_B1CNT_SHIFT) |
-		               (s2 << ETXD_B2CNT_SHIFT);
-		desc->p1     = (0xa5UL << 56) | (data & TO_PHYS_MASK);
-		desc->p2     = (0xa5UL << 56) | (data & TO_PHYS_MASK);
+		desc->cmd    = cpu_to_be32(len | ETXD_INTWHENDONE |
+		                           ETXD_B1V | ETXD_B2V);
+		desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT)
+		                           | (s2 << ETXD_B2CNT_SHIFT));
+		desc->p1     = cpu_to_be64((0xa5UL << 56) |
+                                           (data & TO_PHYS_MASK));
+		desc->p2     = cpu_to_be64((0xa5UL << 56) |
+		                           (data & TO_PHYS_MASK));
 	} else {
 		/* Normal sized packet that doesn't cross a page boundary. */
-		desc->cmd    = len | ETXD_INTWHENDONE | ETXD_B1V;
-		desc->bufcnt = len << ETXD_B1CNT_SHIFT;
-		desc->p1     = (0xa5UL << 56) | (data & TO_PHYS_MASK);
+		desc->cmd    = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V);
+		desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
+		desc->p1     = cpu_to_be64((0xa5UL << 56) |
+		                           (data & TO_PHYS_MASK));
 	}
 
 	BARRIER();




Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv3723/asm-mips64

Modified Files:
	bitops.h 
Log Message:
Don't include <asm/mipsregs.h>.

Index: bitops.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/bitops.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- bitops.h	2002/01/02 18:21:48	1.6
+++ bitops.h	2002/02/05 17:07:49	1.7
@@ -18,7 +18,6 @@
 
 #include <asm/system.h>
 #include <asm/sgidefs.h>
-#include <asm/mipsregs.h>
 
 /*
  * set_bit - Atomically set a bit in memory
@@ -391,7 +390,7 @@
  *
  * Undefined if no zero exists, so code should check against ~0UL first.
  */
-static inline unsigned long ffz(unsigned long word)
+static __inline__ unsigned long ffz(unsigned long word)
 {
 	int b = 0, s;
 




Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv3723/asm-mips

Modified Files:
	bitops.h 
Log Message:
Don't include <asm/mipsregs.h>.

Index: bitops.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bitops.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- bitops.h	2002/01/02 18:21:48	1.7
+++ bitops.h	2002/02/05 17:07:49	1.8
@@ -43,8 +43,6 @@
 
 #ifdef CONFIG_CPU_HAS_LLSC
 
-#include <asm/mipsregs.h>
-
 /*
  * These functions for MIPS ISA > 1 are interrupt and SMP proof and
  * interrupt friendly
@@ -677,7 +675,7 @@
  *
  * Undefined if no zero exists, so code should check against ~0UL first.
  */
-static inline unsigned long ffz(unsigned long word)
+static __inline__ unsigned long ffz(unsigned long word)
 {
 	int b = 0, s;
 




Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv12360

Modified Files:
	time.c 
Log Message:
Reformat.

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/time.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- time.c	2001/11/12 18:15:24	1.11
+++ time.c	2002/02/05 17:36:46	1.12
@@ -406,7 +406,8 @@
 	0,
 	"timer",
 	NULL,
-	NULL};
+	NULL
+};
 
 void __init time_init(void)
 {




Update of /cvsroot/linux-mips/linux/include/asm-mips64/sgi
In directory usw-pr-cvs1:/tmp/cvs-serv12066/asm-mips64/sgi

Modified Files:
	sgihpc.h 
Log Message:
Compile fix: include <linux/types.h>.

Index: sgihpc.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sgi/sgihpc.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- sgihpc.h	2002/01/28 20:32:06	1.3
+++ sgihpc.h	2002/02/05 17:35:41	1.4
@@ -9,6 +9,7 @@
 #ifndef __ASM_SGI_SGIHPC_H
 #define __ASM_SGI_SGIHPC_H
 
+#include <linux/types.h>
 #include <asm/page.h>
 
 extern int sgi_has_ioc2;	/* to know if we have older ioc1 or ioc2. */




Update of /cvsroot/linux-mips/linux/include/asm-mips/sgi
In directory usw-pr-cvs1:/tmp/cvs-serv12066/asm-mips/sgi

Modified Files:
	sgihpc.h 
Log Message:
Compile fix: include <linux/types.h>.

Index: sgihpc.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/sgi/sgihpc.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sgihpc.h	2002/01/28 20:55:37	1.1
+++ sgihpc.h	2002/02/05 17:35:41	1.2
@@ -9,6 +9,7 @@
 #ifndef __ASM_SGI_SGIHPC_H
 #define __ASM_SGI_SGIHPC_H
 
+#include <linux/types.h>
 #include <asm/page.h>
 
 extern int sgi_has_ioc2;	/* to know if we have older ioc1 or ioc2. */




Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv11659/asm-mips

Modified Files:
	pgtable.h 
Log Message:
Make kernel pages global.

Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/pgtable.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- pgtable.h	2002/01/28 18:48:10	1.11
+++ pgtable.h	2002/02/05 17:34:13	1.12
@@ -222,11 +222,11 @@
 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
 			PAGE_CACHABLE_DEFAULT)
 #define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
-			PAGE_CACHABLE_DEFAULT)
+			_PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
 #define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
 			PAGE_CACHABLE_DEFAULT)
-#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
-			_CACHE_UNCACHED)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
+			__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
 
 /*
  * MIPS can't do page protection for execute, and considers that the same like




Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv11659/asm-mips64

Modified Files:
	pgtable.h 
Log Message:
Make kernel pages global.

Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- pgtable.h	2002/01/28 20:32:05	1.8
+++ pgtable.h	2002/02/05 17:34:13	1.9
@@ -207,11 +207,11 @@
 #define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
 			PAGE_CACHABLE_DEFAULT)
 #define PAGE_KERNEL	__pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
-			PAGE_CACHABLE_DEFAULT)
+			_PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
 #define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
-			_CACHE_UNCACHED)
-#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
 			_CACHE_UNCACHED)
+#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
+			__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
 
 /*
  * MIPS can't do page protection for execute, and considers that the same like




Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv11324

Modified Files:
	config.in defconfig 
Log Message:
New, hopefully faster memcpy using prefetching. I'm interested in lmbench results comparing old / new memcpy benchmark results.

Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.84
retrieving revision 1.85
diff -u -d -r1.84 -r1.85
--- config.in	2002/01/28 19:44:27	1.84
+++ config.in	2002/02/05 17:33:04	1.85
@@ -483,10 +483,23 @@
 	 MIPS64 CONFIG_CPU_MIPS64 \
 	 RC32300 CONFIG_CPU_RC32300" R4x00
 
+if [ "$CONFIG_CPU_MIPS32" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+fi
+
+if [ "$CONFIG_CPU_MIPS64" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+fi
+
+if [ "$CONFIG_CPU_RM7000" = "y" ]; then
+   define_bool CONFIG_CPU_HAS_PREFETCH y
+fi
+
 if [ "$CONFIG_CPU_SB1" = "y" ]; then
    bool '  Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
    bool '  Support for SB1 Cache Error handler' CONFIG_SB1_CACHE_ERROR
    define_bool CONFIG_VTAG_ICACHE y
+   define_bool CONFIG_CPU_HAS_PREFETCH y
 fi
 
 if [ "$CONFIG_CPU_R4X00"  = "y" -o \

Index: defconfig
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/defconfig,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- defconfig	2001/12/02 19:05:28	1.17
+++ defconfig	2002/02/05 17:33:04	1.18
@@ -2,6 +2,7 @@
 # Automatically generated make config: don't edit
 #
 CONFIG_MIPS=y
+CONFIG_MIPS32=y
 
 #
 # Code maturity level options
@@ -14,10 +15,11 @@
 # CONFIG_ACER_PICA_61 is not set
 # CONFIG_ALGOR_P4032 is not set
 # CONFIG_BAGET_MIPS is not set
+# CONFIG_MIPS_COBALT is not set
 # CONFIG_DECSTATION is not set
 # CONFIG_DDB5074 is not set
-# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_EV64120 is not set
+# CONFIG_MIPS_EV96100 is not set
 # CONFIG_MIPS_ATLAS is not set
 # CONFIG_MIPS_MALTA is not set
 # CONFIG_NINO is not set
@@ -35,6 +37,7 @@
 # CONFIG_MIPS_PB1000 is not set
 # CONFIG_TOSHIBA_JMR3927 is not set
 # CONFIG_HP_LASERJET is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
 # CONFIG_MCA is not set
@@ -49,8 +52,6 @@
 CONFIG_NONCOHERENT_IO=y
 # CONFIG_ISA is not set
 # CONFIG_EISA is not set
-# CONFIG_PCI is not set
-# CONFIG_I8259 is not set
 
 #
 # Loadable module support
@@ -77,6 +78,7 @@
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_MIPS32 is not set
 # CONFIG_CPU_MIPS64 is not set
+# CONFIG_64BIT_PHYS_ADDR is not set
 # CONFIG_CPU_ADVANCED is not set
 CONFIG_CPU_HAS_LLSC=y
 CONFIG_CPU_HAS_LLDSCD=y
@@ -143,8 +145,6 @@
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-CONFIG_NETLINK=y
-CONFIG_RTNETLINK=y
 CONFIG_NETLINK_DEV=y
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
@@ -229,6 +229,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 # CONFIG_SCSI_AIC7XXX is not set
 # CONFIG_SCSI_AIC7XXX_OLD is not set
 # CONFIG_SCSI_DPT_I2O is not set




Update of /cvsroot/linux-mips/linux/arch/mips/lib
In directory usw-pr-cvs1:/tmp/cvs-serv10364/arch/mips/lib

Added Files:
	memcpy.S 
Log Message:
New, hopefully faster memcpy using prefetching. I'm interested in lmbench results comparing old / new memcpy benchmark results.





Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv10232/include/asm-mips

Modified Files:
	asm.h 
Log Message:
New, hopefully faster memcpy using prefetching. I'm interested in lmbench results comparing old / new memcpy benchmark results.

Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/asm.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- asm.h	2002/01/28 20:53:19	1.5
+++ asm.h	2002/02/05 17:29:27	1.6
@@ -132,8 +132,8 @@
 #define TTABLE(string)                                  \
 		.pushsection .text;			\
 		.word	1f;                             \
-		.previous;                              \
-		.data;                                  \
+		.popsection				\
+		.pushsection .data;			\
 1:		.asciz	string;                         \
 		.popsection
 
@@ -144,15 +144,24 @@
  * MIPS IV implementations are free to treat this as a nop.  The R5000
  * is one of them.  So we should have an option not to use this instruction.
  */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS64)
+#if CONFIG_CPU_HAS_PREFETCH
+
 #define PREF(hint,addr)                                 \
-		pref	hint,addr
+		.set	push;				\
+		.set	mips4;				\
+		pref	hint,addr;			\
+		.set	pop
+
 #define PREFX(hint,addr)                                \
-		prefx	hint,addr
+		.set	push;				\
+		.set	mips4;				\
+		prefx	hint,addr;			\
+		.set	pop
 #else
+
 #define PREF(hint,addr)
 #define PREFX(hint,addr)
+
 #endif
 
 /*




Update of /cvsroot/linux-mips/linux/arch/mips64/configs
In directory usw-pr-cvs1:/tmp/cvs-serv10232/arch/mips64/configs

Modified Files:
	defconfig-ip32 
Log Message:
New, hopefully faster memcpy using prefetching. I'm interested in lmbench results comparing old / new memcpy benchmark results.

Index: defconfig-ip32
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/configs/defconfig-ip32,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- defconfig-ip32	2001/12/13 21:05:10	1.6
+++ defconfig-ip32	2002/02/05 17:29:27	1.7
@@ -1,6 +1,8 @@
 #
 # Automatically generated make config: don't edit
 #
+CONFIG_MIPS=y
+CONFIG_MIPS64=y
 
 #
 # Code maturity level options
@@ -22,7 +24,7 @@
 CONFIG_ARC32=y
 CONFIG_PC_KEYB=y
 CONFIG_PCI=y
-CONFIG_MAPPED_PCI_IO=y
+# CONFIG_MAPPED_PCI_IO is not set
 CONFIG_NONCOHERENT_IO=y
 CONFIG_ARC_MEMORY=y
 CONFIG_L1_CACHE_SHIFT=5
@@ -110,7 +112,7 @@
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set
 CONFIG_UNIX=y
@@ -123,6 +125,7 @@
 # CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
@@ -199,6 +202,7 @@
 # CONFIG_SCSI_AHA152X is not set
 # CONFIG_SCSI_AHA1542 is not set
 # CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AACRAID is not set
 CONFIG_SCSI_AIC7XXX=y
 CONFIG_AIC7XXX_CMDS_PER_DEVICE=8
 CONFIG_AIC7XXX_RESET_DELAY_MS=15000
@@ -253,6 +257,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)




Update of /cvsroot/linux-mips/linux/arch/mips/sgi-ip22
In directory usw-pr-cvs1:/tmp/cvs-serv9169

Modified Files:
	ip22-time.c 
Log Message:
Fix Indy_rtc_set_time's conversion from system to rtc time.

Index: ip22-time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sgi-ip22/ip22-time.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- ip22-time.c	2002/01/02 19:12:16	1.4
+++ ip22-time.c	2002/02/05 17:26:14	1.5
@@ -67,8 +67,8 @@
 
 	to_tm(tim, &tm);
 
-	tm.tm_mon += 1;
-	tm.tm_year -= 40;
+	tm.tm_mon += 1;		/* tm_mon starts at zero */
+	tm.tm_year -= 1940;
 	if (tm.tm_year >= 100)
 		tm.tm_year -= 100;
 




Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv8883

Modified Files:
	Config.in hal2.c 
Log Message:
Fix harm done by recent Indy patches.

Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/Config.in,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- Config.in	2002/01/28 21:00:02	1.12
+++ Config.in	2002/02/05 17:25:11	1.13
@@ -48,7 +48,9 @@
 fi
 dep_tristate '  RME Hammerfall (RME96XX) support' CONFIG_SOUND_RME96XX $CONFIG_SOUND $CONFIG_PCI $CONFIG_EXPERIMENTAL
 dep_tristate '  S3 SonicVibes' CONFIG_SOUND_SONICVIBES $CONFIG_SOUND
-dep_tristate '  SGI Visual Workstation sound' CONFIG_SOUND_VWSND $CONFIG_SOUND $CONFIG_VISWS
+if [ "$CONFIG_VISWS" = "y" ]; then
+   dep_tristate '  SGI Visual Workstation sound' CONFIG_SOUND_VWSND $CONFIG_SOUND
+fi
 dep_tristate '  SGI HAL2 sound (EXPERIMENTAL)' CONFIG_SOUND_HAL2 $CONFIG_SOUND $CONFIG_SGI_IP22 $CONFIG_EXPERIMENTAL
 
 if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then

Index: hal2.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/hal2.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- hal2.c	2002/01/28 21:00:02	1.1
+++ hal2.c	2002/02/05 17:25:11	1.2
@@ -273,16 +273,18 @@
 	if (running)
 		dac->tail = dac->tail->info.next;
 
-	wake_up(&dac->dma_wait);
-	
 	spin_unlock(&dac->lock);
+
+	wake_up(&dac->dma_wait);
 }
 
 static void hal2_adc_interrupt(hal2_codec_t *adc)
 {
 	spin_lock(&adc->lock);
-	wake_up(&adc->dma_wait);
+	/* TODO :)) */
 	spin_unlock(&adc->lock);
+
+	wake_up(&adc->dma_wait);
 }
 
 static void hal2_interrupt(int irq, void *dev_id, struct pt_regs *regs)
@@ -924,6 +926,8 @@
 	case SNDCTL_DSP_NONBLOCK:
 		file->f_flags |= O_NONBLOCK;
 		return 0;
+	case SNDCTL_DSP_GETBLKSIZE:
+		return put_user(H2_BUFFER_SIZE, (int *)arg);
 	case SOUND_PCM_READ_RATE:
 		val = -EINVAL;
 		if (file->f_mode & FMODE_READ)




Update of /cvsroot/linux-mips/linux/include/asm-mips64/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv8355/asm-mips64/sibyte

Modified Files:
	sb1250_genbus.h 
Log Message:
Fix genbus macro definitions.

Index: sb1250_genbus.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sibyte/sb1250_genbus.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sb1250_genbus.h	2001/11/08 17:28:25	1.1
+++ sb1250_genbus.h	2002/02/05 17:23:49	1.2
@@ -6,7 +6,7 @@
     *  This module contains constants and macros useful for 
     *  manipulating the SB1250's Generic Bus interface
     *  
-    *  SB1250 specification level:  0.2
+    *  SB1250 specification level:  01/02/2002
     *  
     *  Author:  Mitch Lichtenberg (mi...@si...)
     *  
@@ -126,16 +126,16 @@
 #define M_IO_IDLE_CYCLE		_SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
 #define V_IO_IDLE_CYCLE(x)	_SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
 #define G_IO_IDLE_CYCLE(x)	_SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
-
-#define S_IO_CS_TO_OE		12
-#define M_IO_CS_TO_OE		_SB_MAKEMASK(2,S_IO_CS_TO_OE)
-#define V_IO_CS_TO_OE(x)	_SB_MAKEVALUE(x,S_IO_CS_TO_OE)
-#define G_IO_CS_TO_OE(x)	_SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
 
-#define S_IO_OE_TO_CS		14
+#define S_IO_OE_TO_CS		12
 #define M_IO_OE_TO_CS		_SB_MAKEMASK(2,S_IO_OE_TO_CS)
 #define V_IO_OE_TO_CS(x)	_SB_MAKEVALUE(x,S_IO_OE_TO_CS)
 #define G_IO_OE_TO_CS(x)	_SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
+
+#define S_IO_CS_TO_OE		14
+#define M_IO_CS_TO_OE		_SB_MAKEMASK(2,S_IO_CS_TO_OE)
+#define V_IO_CS_TO_OE(x)	_SB_MAKEVALUE(x,S_IO_CS_TO_OE)
+#define G_IO_CS_TO_OE(x)	_SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
 
 /*
  * Generic Bus Interrupt Status Register (Table 11-9)




Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv8355/asm-mips/sibyte

Modified Files:
	sb1250_genbus.h 
Log Message:
Fix genbus macro definitions.

Index: sb1250_genbus.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/sibyte/sb1250_genbus.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sb1250_genbus.h	2001/11/08 17:28:25	1.1
+++ sb1250_genbus.h	2002/02/05 17:23:49	1.2
@@ -6,7 +6,7 @@
     *  This module contains constants and macros useful for 
     *  manipulating the SB1250's Generic Bus interface
     *  
-    *  SB1250 specification level:  0.2
+    *  SB1250 specification level:  01/02/2002
     *  
     *  Author:  Mitch Lichtenberg (mi...@si...)
     *  
@@ -126,16 +126,16 @@
 #define M_IO_IDLE_CYCLE		_SB_MAKEMASK(4,S_IO_IDLE_CYCLE)
 #define V_IO_IDLE_CYCLE(x)	_SB_MAKEVALUE(x,S_IO_IDLE_CYCLE)
 #define G_IO_IDLE_CYCLE(x)	_SB_GETVALUE(x,S_IO_IDLE_CYCLE,M_IO_IDLE_CYCLE)
-
-#define S_IO_CS_TO_OE		12
-#define M_IO_CS_TO_OE		_SB_MAKEMASK(2,S_IO_CS_TO_OE)
-#define V_IO_CS_TO_OE(x)	_SB_MAKEVALUE(x,S_IO_CS_TO_OE)
-#define G_IO_CS_TO_OE(x)	_SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
 
-#define S_IO_OE_TO_CS		14
+#define S_IO_OE_TO_CS		12
 #define M_IO_OE_TO_CS		_SB_MAKEMASK(2,S_IO_OE_TO_CS)
 #define V_IO_OE_TO_CS(x)	_SB_MAKEVALUE(x,S_IO_OE_TO_CS)
 #define G_IO_OE_TO_CS(x)	_SB_GETVALUE(x,S_IO_OE_TO_CS,M_IO_OE_TO_CS)
+
+#define S_IO_CS_TO_OE		14
+#define M_IO_CS_TO_OE		_SB_MAKEMASK(2,S_IO_CS_TO_OE)
+#define V_IO_CS_TO_OE(x)	_SB_MAKEVALUE(x,S_IO_CS_TO_OE)
+#define G_IO_CS_TO_OE(x)	_SB_GETVALUE(x,S_IO_CS_TO_OE,M_IO_CS_TO_OE)
 
 /*
  * Generic Bus Interrupt Status Register (Table 11-9)




Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv7832/asm-mips

Modified Files:
	system.h 
Log Message:
Remove semicolons from macro definitions.

Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/system.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- system.h	2002/01/28 20:52:33	1.7
+++ system.h	2002/02/05 17:22:20	1.8
@@ -98,9 +98,9 @@
 	"xori\t$1, 1\n\t"
 	".set\tnoreorder\n\t"
 	"mtc0\t$1, $12\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
 	".set\tpop\n\t"	
 	".endm");
 
@@ -161,10 +161,10 @@
 #endif /* SMP */
 
 /* For spinlocks etc */
-#define local_irq_save(x)	__save_and_cli(x);
-#define local_irq_restore(x)	__restore_flags(x);
-#define local_irq_disable()	__cli();
-#define local_irq_enable()	__sti();
+#define local_irq_save(x)	__save_and_cli(x)
+#define local_irq_restore(x)	__restore_flags(x)
+#define local_irq_disable()	__cli()
+#define local_irq_enable()	__sti()
 
 /*
  * These are probably defined overly paranoid ...




Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv7832/asm-mips64

Modified Files:
	system.h 
Log Message:
Remove semicolons from macro definitions.

Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- system.h	2002/01/28 20:32:05	1.8
+++ system.h	2002/02/05 17:22:20	1.9
@@ -95,9 +95,9 @@
 	"xori\t$1, 1\n\t"
 	".set\tnoreorder\n\t"
 	"mtc0\t$1, $12\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
 	".set\tpop\n\t"	
 	".endm");
 
@@ -158,10 +158,10 @@
 #endif /* CONFIG_SMP */
 
 /* For spinlocks etc */
-#define local_irq_save(x)	__save_and_cli(x);
-#define local_irq_restore(x)	__restore_flags(x);
-#define local_irq_disable()	__cli();
-#define local_irq_enable()	__sti();
+#define local_irq_save(x)	__save_and_cli(x)
+#define local_irq_restore(x)	__restore_flags(x)
+#define local_irq_disable()	__cli()
+#define local_irq_enable()	__sti()
 
 /*
  * These are probably defined overly paranoid ...




Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477
In directory usw-pr-cvs1:/tmp/cvs-serv5389

Modified Files:
	pci.c 
Log Message:
Same as OSS already so this commit is just to minimize the diff.

Index: pci.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/ddb5477/pci.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- pci.c	2001/12/06 22:00:57	1.5
+++ pci.c	2002/02/05 17:13:33	1.6
@@ -118,12 +118,12 @@
 	pci_for_each_dev(dev) {
 		slot_num = PCI_SLOT(dev->devfn);
 
-		/* we don't do IRQ fixup for sub-bus yet */
-		if (dev->bus->parent != NULL) {
-			db_run(printk("Don't know how to fixup irq for PCI device %d on sub-bus %d\n",
-					slot_num, dev->bus->number));
-			continue;
-		}
+               /* we don't do IRQ fixup for sub-bus yet */
+               if (dev->bus->parent != NULL) {
+                       db_run(printk("Don't know how to fixup irq for PCI device %d on sub-bus %d\n",
+                                       slot_num, dev->bus->number));
+                       continue;
+               }
 
 		db_assert(slot_num < MAX_SLOT_NUM);
 		db_assert(irq_map[slot_num] != 0xff);




Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv2373/mips/mm

Modified Files:
	c-sb1.c 
Log Message:
Latest round of SB1 cache fixes.

Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-sb1.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- c-sb1.c	2002/01/28 23:15:25	1.11
+++ c-sb1.c	2002/02/05 17:03:53	1.12
@@ -142,20 +142,14 @@
 /*
  * When flushing a range in the icache, we have to first writeback
  * the dcache for the same range, so new ifetches will see any
- * data that was dirty in the dcache.  Also, if the flush is very
- * large, just flush the whole cache rather than spinning in here
- * forever.  Fills from the (always coherent) L2 come in relatively
- * quickly.
- *
- * Also, at the moment we just hit-writeback the dcache instead
- * of writeback-invalidating it.  Not doing the invalidates
- * doesn't cost us anything, since we're coherent 
+ * data that was dirty in the dcache.
  *
+ * The start/end arguments are expected to be Kseg addresses.
  */
 
 static void local_sb1_flush_icache_range(unsigned long start, unsigned long end)
 {
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 	unsigned long flags;
 	local_irq_save(flags);
 #endif
@@ -167,45 +161,38 @@
 		".set mips4                 \n"
 		"     move   $1, %0         \n" 
 		"1:                         \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 		".align 3                   \n"
 		"     lw     $0,   0($1)    \n" /* Bug 1370, 1368            */
 		"     sync                  \n"
-		"     cache  0x15, 0($1)    \n" /* Hit-WB-inval this address */
-#else
-		"     cache  0x19, 0($1)    \n" /* Hit-WB this address */
 #endif
+		"     cache  %3, 0($1)      \n" /* Hit-WB{,-inval} this address */
 		"     bne    $1, %1, 1b     \n" /* loop test */
 		"      addu  $1, $1, %2     \n" /* next line */
 		".set pop                   \n"
 		:
 		: "r" (start  & ~(dcache_line_size - 1)),
 		  "r" ((end - 1) & ~(dcache_line_size - 1)),
-		  "r" (dcache_line_size));
+		  "r" (dcache_line_size),
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+		  "i" (Hit_Writeback_Inv_D)
+#else
+		  "i" (Hit_Writeback_D)
+#endif
+		);
 	__asm__ __volatile__ (
 		".set push                  \n"
 		".set noreorder             \n"
 		".set mips2                 \n"
 		"sync                       \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */
 		"sync                       \n"
 #endif
 		".set pop                   \n");
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
-		local_irq_restore(flags);
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+	local_irq_restore(flags);
 #endif
 
-	/* Guess what: these Kseg0 addressese aren't enough to let us figure
-	 * out what may be in the cache under mapped Useg tags.  The situation
-	 * is even worse, because bit 12 belongs to both the page number AND
-	 * the cache index, which means the Kseg0 page number may have a
-	 * different cache index than the Useg address.  For these two reasons,
-	 * we have to flush the entire thing.  Since the Dcache is physically
-	 * tagged, we *can* use hit operations.
-	 */
-	start = 0;
-	end = icache_index_mask;
-
 	__asm__ __volatile__ (
 		".set push                  \n"
 		".set noreorder             \n"
@@ -213,17 +200,18 @@
 		".set mips4                 \n"
 		"     move   $1, %0         \n" 
 		".align 3                   \n"
-		"1:   cache  0, (0<<13)($1) \n" /* Index-inval this address */
-		"     cache  0, (1<<13)($1) \n" /* Index-inval this address */
-		"     cache  0, (2<<13)($1) \n" /* Index-inval this address */
-		"     cache  0, (3<<13)($1) \n" /* Index-inval this address */
+		"1:   cache  %3, (0<<13)($1) \n" /* Index-inval this address */
+		"     cache  %3, (1<<13)($1) \n" /* Index-inval this address */
+		"     cache  %3, (2<<13)($1) \n" /* Index-inval this address */
+		"     cache  %3, (3<<13)($1) \n" /* Index-inval this address */
 		"     bne    $1, %1, 1b     \n" /* loop test */
 		"      addu  $1, $1, %2     \n" /* next line */
 		".set pop                   \n"
 		:
 		: "r" (start & ~(icache_line_size - 1)),
 		  "r" ((end - 1) & ~(dcache_line_size - 1)),
-		  "r" (icache_line_size));
+		  "r" (icache_line_size),
+		  "i" (Index_Invalidate_I));
 }
 
 #ifdef CONFIG_SMP
@@ -257,17 +245,18 @@
  * If there's no context yet, or the page isn't executable, no icache flush
  * is needed
  */
-void sb1_flush_icache_all(void);
-
 static void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
-	unsigned long addr;
-
 	if ((vma->vm_mm->context == 0) || !(vma->vm_flags & VM_EXEC)) {
 		return;
 	}
 
-	sb1_flush_icache_all();
+	/*
+	 * We're not sure of the virtual address(es) involved here, so
+	 * conservatively flush the entire caches on all processors
+	 * (ouch).
+	 */
+	sb1___flush_cache_all();
 }
 
 static inline void protected_flush_icache_line(unsigned long addr)
@@ -276,13 +265,14 @@
 		"    .set push                \n"
 		"    .set noreorder           \n"
 		"    .set mips4               \n"
-		"1:  cache 0x10, (%0)         \n"
+		"1:  cache %1, (%0)           \n"
 		"2:  .set pop                 \n"
 		"    .section __ex_table,\"a\"\n"
 		"     .word  1b, 2b          \n"
 		"     .previous"
 		:
-		: "r" (addr));
+		: "r" (addr),
+		  "i" (Hit_Invalidate_I));
 }
 
 static inline void protected_writeback_dcache_line(unsigned long addr)
@@ -300,20 +290,18 @@
 		"    .set noreorder           \n"
 		"    .set mips4               \n"
 		"1:                           \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
-		"     lw    $0,   (%0)         \n"  
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+		"     lw    $0,   (%0)        \n"
 		"     sync                  \n"
-		"     cache  0x15, 0(%0)    \n" /* Hit-WB-inval this address */
-#else
-		"     cache  0x19, 0(%0)    \n" /* Hit-WB this address */
 #endif
+		"     cache  %1, 0(%0)    \n" /* Hit-WB{-inval} this address */
 		/* XXX: should be able to do this after both dcache cache
 		   ops, but there's no guarantee that this will be inlined,
 		   and the pass1 restriction checker can't detect syncs
 		   following cache ops except in the following basic block.
 		*/
 		"     sync                    \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */
 		"     sync                    \n"
 #endif
 		"2:  .set pop                 \n"
@@ -321,8 +309,14 @@
 		"     .word  1b, 2b          \n"
 		"     .previous"
 		:
-		: "r" (addr));
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
+		: "r" (addr),
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+		  "i" (Hit_Writeback_Inv_D)
+#else
+		  "i" (Hit_Writeback_D)
+#endif
+		  );
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 	local_irq_restore(flags);
 #endif
 }
@@ -398,7 +392,7 @@
 /*
  * This only needs to make sure stores done up to this
  * point are visible to other agents outside the CPU.  Given 
- * the coherent nature of the ZBus, all that's required here is 
+ * the coherent nature of the ZBbus, all that's required here is 
  * a sync to make sure the data gets out to the caches and is
  * visible to an arbitrary A Phase from an external agent 
  *   




Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv2373/mips64/mm

Modified Files:
	c-sb1.c 
Log Message:
Latest round of SB1 cache fixes.

Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/c-sb1.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- c-sb1.c	2002/01/28 20:31:57	1.1
+++ c-sb1.c	2002/02/05 17:03:53	1.2
@@ -125,20 +125,14 @@
 /*
  * When flushing a range in the icache, we have to first writeback
  * the dcache for the same range, so new ifetches will see any
- * data that was dirty in the dcache.  Also, if the flush is very
- * large, just flush the whole cache rather than spinning in here
- * forever.  Fills from the (always coherent) L2 come in relatively
- * quickly.
- *
- * Also, at the moment we just hit-writeback the dcache instead
- * of writeback-invalidating it.  Not doing the invalidates
- * doesn't cost us anything, since we're coherent 
+ * data that was dirty in the dcache.
  *
+ * The start/end arguments are expected to be Kseg addresses.
  */
 
 static void local_sb1_flush_icache_range(unsigned long start, unsigned long end)
 {
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 	unsigned long flags;
 	local_irq_save(flags);
 #endif
@@ -150,45 +144,38 @@
 		".set mips4                 \n"
 		"     move   $1, %0         \n" 
 		"1:                         \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 		".align 3                   \n"
 		"     lw     $0,   0($1)    \n" /* Bug 1370, 1368            */
 		"     sync                  \n"
-		"     cache  0x15, 0($1)    \n" /* Hit-WB-inval this address */
-#else
-		"     cache  0x19, 0($1)    \n" /* Hit-WB this address */
 #endif
+		"     cache  %3, 0($1)      \n" /* Hit-WB{,-inval} this address */
 		"     bne    $1, %1, 1b     \n" /* loop test */
 		"      addu  $1, $1, %2     \n" /* next line */
 		".set pop                   \n"
 		:
 		: "r" (start  & ~(dcache_line_size - 1)),
 		  "r" ((end - 1) & ~(dcache_line_size - 1)),
-		  "r" (dcache_line_size));
+		  "r" (dcache_line_size),
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+		  "i" (Hit_Writeback_Inv_D)
+#else
+		  "i" (Hit_Writeback_D)
+#endif
+		);
 	__asm__ __volatile__ (
 		".set push                  \n"
 		".set noreorder             \n"
 		".set mips2                 \n"
 		"sync                       \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */
 		"sync                       \n"
 #endif
 		".set pop                   \n");
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
-		local_irq_restore(flags);
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+	local_irq_restore(flags);
 #endif
 
-	/* Guess what: these Kseg0 addressese aren't enough to let us figure
-	 * out what may be in the cache under mapped Useg tags.  The situation
-	 * is even worse, because bit 12 belongs to both the page number AND
-	 * the cache index, which means the Kseg0 page number may have a
-	 * different cache index than the Useg address.  For these two reasons,
-	 * we have to flush the entire thing.  Since the Dcache is physically
-	 * tagged, we *can* use hit operations.
-	 */
-	start = 0;
-	end = icache_index_mask;
-
 	__asm__ __volatile__ (
 		".set push                  \n"
 		".set noreorder             \n"
@@ -196,17 +183,18 @@
 		".set mips4                 \n"
 		"     move   $1, %0         \n" 
 		".align 3                   \n"
-		"1:   cache  0, (0<<13)($1) \n" /* Index-inval this address */
-		"     cache  0, (1<<13)($1) \n" /* Index-inval this address */
-		"     cache  0, (2<<13)($1) \n" /* Index-inval this address */
-		"     cache  0, (3<<13)($1) \n" /* Index-inval this address */
+		"1:   cache  %3, (0<<13)($1) \n" /* Index-inval this address */
+		"     cache  %3, (1<<13)($1) \n" /* Index-inval this address */
+		"     cache  %3, (2<<13)($1) \n" /* Index-inval this address */
+		"     cache  %3, (3<<13)($1) \n" /* Index-inval this address */
 		"     bne    $1, %1, 1b     \n" /* loop test */
 		"      addu  $1, $1, %2     \n" /* next line */
 		".set pop                   \n"
 		:
 		: "r" (start & ~(icache_line_size - 1)),
 		  "r" ((end - 1) & ~(dcache_line_size - 1)),
-		  "r" (icache_line_size));
+		  "r" (icache_line_size),
+		  "i" (Index_Invalidate_I));
 }
 
 #ifdef CONFIG_SMP
@@ -242,20 +230,16 @@
  */
 static void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
-	unsigned long addr;
-
 	if ((vma->vm_mm->context == 0) || !(vma->vm_flags & VM_EXEC)) {
 		return;
 	}
 
-	addr = (unsigned long)page_address(page);
 	/*
-	 * XXXKW addr is a Kseg0 address, whereas hidden higher up the call
-	 * stack, we may really need to flush a Useg address.  Our Icache is
-	 * virtually tagged, which means we have to be super conservative.
-	 *  See comments in sb1_flush_icache_rage.
+	 * We're not sure of the virtual address(es) involved here, so
+	 * conservatively flush the entire caches on all processors
+	 * (ouch).
 	 */
-	sb1_flush_icache_range(addr, addr + PAGE_SIZE);
+	sb1___flush_cache_all();
 }
 
 static inline void protected_flush_icache_line(unsigned long addr)
@@ -264,13 +248,14 @@
 		"    .set push                \n"
 		"    .set noreorder           \n"
 		"    .set mips4               \n"
-		"1:  cache 0x10, (%0)         \n"
+		"1:  cache %1, (%0)           \n"
 		"2:  .set pop                 \n"
 		"    .section __ex_table,\"a\"\n"
 		"     .word  1b, 2b          \n"
 		"     .previous"
 		:
-		: "r" (addr));
+		: "r" (addr),
+		  "i" (Hit_Invalidate_I));
 }
 
 static inline void protected_writeback_dcache_line(unsigned long addr)
@@ -288,20 +273,18 @@
 		"    .set noreorder           \n"
 		"    .set mips4               \n"
 		"1:                           \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
-		"     lw    $0,   (%0)         \n"  
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+		"     lw    $0,   (%0)        \n"
 		"     sync                  \n"
-		"     cache  0x15, 0(%0)    \n" /* Hit-WB-inval this address */
-#else
-		"     cache  0x19, 0(%0)    \n" /* Hit-WB this address */
 #endif
+		"     cache  %1, 0(%0)    \n" /* Hit-WB{-inval} this address */
 		/* XXX: should be able to do this after both dcache cache
 		   ops, but there's no guarantee that this will be inlined,
 		   and the pass1 restriction checker can't detect syncs
 		   following cache ops except in the following basic block.
 		*/
 		"     sync                    \n"
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */
 		"     sync                    \n"
 #endif
 		"2:  .set pop                 \n"
@@ -309,8 +292,14 @@
 		"     .word  1b, 2b          \n"
 		"     .previous"
 		:
-		: "r" (addr));
-#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
+		: "r" (addr),
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+		  "i" (Hit_Writeback_Inv_D)
+#else
+		  "i" (Hit_Writeback_D)
+#endif
+		  );
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
 	local_irq_restore(flags);
 #endif
 }
@@ -386,7 +375,7 @@
 /*
  * This only needs to make sure stores done up to this
  * point are visible to other agents outside the CPU.  Given 
- * the coherent nature of the ZBus, all that's required here is 
+ * the coherent nature of the ZBbus, all that's required here is 
  * a sync to make sure the data gets out to the caches and is
  * visible to an arbitrary A Phase from an external agent 
  *   




Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv14475

Modified Files:
	setup.c 
Log Message:
Changed pci memory resource start/end addresses such that the RC32334
bridge base registers don't need to modified on the fly to map all of
PCI memory.


Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- setup.c	2002/01/24 20:13:34	1.6
+++ setup.c	2002/02/04 21:21:42	1.7
@@ -94,7 +94,7 @@
 
 struct resource rc32334_res_pci_mem1 = {
 	"PCI Mem1",
-	0x40000000,
+	0x50000000,
 	0x5FFFFFFF,
 	IORESOURCE_MEM,
 	&rc32334_res_pci_mem1,
@@ -105,7 +105,7 @@
 struct resource rc32334_res_pci_mem2 = {
 	"PCI Mem2",
 	0x60000000,
-	0x7FFFFFFF,
+	0x6FFFFFFF,
 	IORESOURCE_MEM,
 	&rc32334_res_pci_mem1,
 	NULL,





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