linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/arch/mips/mm c-mips32.c,1.3,1.4 c-sb1.c,1.10,1.11 tlb-r3k.c,1.6,1.7 tlb-r4k.c,1.9,1.10 tlb-sb1.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv26521

Modified Files:
	c-mips32.c c-sb1.c tlb-r3k.c tlb-r4k.c tlb-sb1.c 
Log Message:
Sync to OSS

Index: c-mips32.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-mips32.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- c-mips32.c	2001/11/30 18:34:09	1.3
+++ c-mips32.c	2002/01/28 23:15:25	1.4
@@ -649,27 +649,6 @@
 	setup_noscache_funcs();
 }
 
-static void __init probe_tlb(unsigned long config)
-{
-        unsigned long config1;
-
-        if (!(config & (1 << 31))) {
-	        /* 
-		 * Not a MIPS32 complainant CPU. 
-		 * Config 1 register not supported, we assume R4k style.
-		 */  
-	        mips_cpu.tlbsize = 48;
-	} else {
-	        config1 = read_mips32_cp0_config1();
-		if (!((config >> 7) & 3))
-		        panic("No MMU present");
-		else
-		        mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
-	}	
-
-	printk("Number of TLB entries %d.\n", mips_cpu.tlbsize);
-}
-
 void __init ld_mmu_mips32(void)
 {
 	unsigned long config = read_32bit_cp0_register(CP0_CONFIG);
@@ -683,7 +662,6 @@
 	probe_icache(config);
 	probe_dcache(config);
 	setup_scache(config);
-	probe_tlb(config);
 
 	_flush_cache_sigtramp = mips32_flush_cache_sigtramp;
 	_flush_icache_range = mips32_flush_icache_range;	/* Ouch */

Index: c-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/c-sb1.c,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- c-sb1.c	2001/12/11 18:40:07	1.10
+++ c-sb1.c	2002/01/28 23:15:25	1.11
@@ -257,6 +257,8 @@
  * If there's no context yet, or the page isn't executable, no icache flush
  * is needed
  */
+void sb1_flush_icache_all(void);
+
 static void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
 {
 	unsigned long addr;
@@ -265,14 +267,7 @@
 		return;
 	}
 
-	addr = (unsigned long)page_address(page);
-	/*
-	 * XXXKW addr is a Kseg0 address, whereas hidden higher up the call
-	 * stack, we may really need to flush a Useg address.  Our Icache is
-	 * virtually tagged, which means we have to be super conservative.
-	 *  See comments in sb1_flush_icache_rage.
-	 */
-	sb1_flush_icache_range(addr, addr + PAGE_SIZE);
+	sb1_flush_icache_all();
 }
 
 static inline void protected_flush_icache_line(unsigned long addr)

Index: tlb-r3k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r3k.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- tlb-r3k.c	2001/12/11 18:17:25	1.6
+++ tlb-r3k.c	2002/01/28 23:15:25	1.7
@@ -118,7 +118,7 @@
 
 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
-	if (vma->vm_mm->context != 0) {
+	if (!vma || vma->vm_mm->context != 0) {
 		unsigned long flags;
 		int oldpid, newpid, idx;
 

Index: tlb-r4k.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-r4k.c,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- tlb-r4k.c	2002/01/28 18:38:34	1.9
+++ tlb-r4k.c	2002/01/28 23:15:25	1.10
@@ -338,29 +338,19 @@
 	unsigned int prid, config1;
 
 	prid = read_32bit_cp0_register(CP0_PRID) & 0xff00;
-	switch (prid) {
-	case PRID_IMP_RM7000:
-	case PRID_IMP_RC32334:
-	case PRID_IMP_RC32355:
+	if (prid == PRID_IMP_RM7000 || !(config & (1 << 31)))
 		/* 
-		 * Not a MIPS32 compliant CPU.  Config 1 register not
+		 * Not a MIPS32 complianant CPU.  Config 1 register not
 		 * supported, we assume R4k style.  Cpu probing already figured
 		 * out the number of tlb entries.
 		 */  
 		return;
-	default:
-		/* config1 register available? */
-		if (!(config & (1 << 31)))
-			return;
-	}
-	
+
 	config1 = read_mips32_cp0_config1();
 	if (!((config >> 7) & 3))
 		panic("No MMU present");
 	else
 		mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;
-
-	printk("Number of TLB entries %d.\n", mips_cpu.tlbsize);
 }
 
 void __init r4k_tlb_init(void)
@@ -378,7 +368,6 @@
 	set_pagemask(PM_4K);
 	write_32bit_cp0_register(CP0_WIRED, 0);
 	temp_tlb_entry = mips_cpu.tlbsize - 1;
-	printk("TLB has %d entries.\n", mips_cpu.tlbsize);
 	local_flush_tlb_all();
 
 	if ((mips_cpu.options & MIPS_CPU_4KEX)

Index: tlb-sb1.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/tlb-sb1.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- tlb-sb1.c	2001/12/02 19:05:29	1.5
+++ tlb-sb1.c	2002/01/28 23:15:25	1.6
@@ -171,7 +171,7 @@
 			}
 			set_entryhi(oldpid);
 		} else {
-			get_new_mmu_context(mm, smp_processor_id());
+			get_new_mmu_context(mm, cpu);
 			if (mm == current->active_mm)
 				set_entryhi(CPU_CONTEXT(cpu, mm) & 0xff);
 		}
@@ -182,14 +182,17 @@
 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 {
 	unsigned long flags;
-	__save_and_cli(flags);
+
 #ifdef CONFIG_SMP
 	/*
-	 * This variable is eliminated from CPU_CONTEXT() if SMP isn't defined, so
-	 * conditional it to get rid of silly "unused variable" compiler complaints
-	*/
+	 * This variable is eliminated from CPU_CONTEXT() if SMP isn't defined,
+	 * so conditional it to get rid of silly "unused variable" compiler
+	 * complaints
+	 */
 	int cpu = smp_processor_id();
 #endif
+
+	__save_and_cli(flags);
 	if (CPU_CONTEXT(cpu, vma->vm_mm) != 0) {
 		int oldpid, newpid, idx;
 #ifdef DEBUG_TLB

[Linux-mips-commits]CVS: linux/drivers/sound hal2.c,NONE,1.1 hal2.h,NONE,1.1 Config.in,1.11,1.12 Makefile,1.11,1.12

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/sound
In directory usw-pr-cvs1:/tmp/cvs-serv17117

Modified Files:
	Config.in Makefile 
Added Files:
	hal2.c hal2.h 
Log Message:
Adding HAL sound support.

--- NEW FILE: hal2.c ---
/*
 *  Driver for HAL2 sound processors
 *  Copyright (c) 2001 Ladislav Michl <la...@ps...>
 *  
 *  Based on Ulf Carlsson's code.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as 
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
[...1273 lines suppressed...]

static void __exit exit_hal2(void)
{
	int i;
	
	for (i = 0; i < MAXCARDS; i++)
		if (hal2_card[i]) {
			hal2_free_resources(hal2_card[i]);
			unregister_sound_dsp(hal2_card[i]->dev_dsp);
			unregister_sound_mixer(hal2_card[i]->dev_mixer);
			kfree(hal2_card[i]);
	}
}

module_init(init_hal2);
module_exit(exit_hal2);

MODULE_AUTHOR("Ladislav Michl");
MODULE_DESCRIPTION("OSS compatible driver for SGI HAL2 audio");
MODULE_LICENSE("GPL");

--- NEW FILE: hal2.h ---
#ifndef __HAL2_H
#define __HAL2_H

/*
 *  Driver for HAL2 sound processors
 *  Copyright (c) 1999 Ulf Carlsson <ul...@bu...>
 *  Copyright (c) 2001 Ladislav Michl <la...@ps...>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as 
 *  published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */

#include <asm/addrspace.h>
#include <asm/sgi/sgihpc.h>
#include <linux/spinlock.h>

#define H2_HAL2_BASE		0x58000
#define H2_CTL_PIO		(H2_HAL2_BASE + 0 * 0x400)
#define H2_AES_PIO		(H2_HAL2_BASE + 1 * 0x400)
#define H2_VOL_PIO		(H2_HAL2_BASE + 2 * 0x400)
#define H2_SYN_PIO		(H2_HAL2_BASE + 3 * 0x400)

/* Indirect status register */

#define H2_ISR_TSTATUS		0x01	/* RO: transaction status 1=busy */
#define H2_ISR_USTATUS		0x02	/* RO: utime status bit 1=armed */
#define H2_ISR_QUAD_MODE	0x04	/* codec mode 0=indigo 1=quad */
#define H2_ISR_GLOBAL_RESET_N	0x08	/* chip global reset 0=reset */
#define H2_ISR_CODEC_RESET_N	0x10	/* codec/synth reset 0=reset  */

/* Revision register */

#define H2_REV_AUDIO_PRESENT	0x8000	/* RO: audio present 0=present */
#define H2_REV_BOARD_M		0x7000	/* RO: bits 14:12, board revision */
#define H2_REV_MAJOR_CHIP_M	0x00F0	/* RO: bits 7:4, major chip revision */
#define H2_REV_MINOR_CHIP_M	0x000F	/* RO: bits 3:0, minor chip revision */

/* Indirect address register */

/*
 * Address of indirect internal register to be accessed. A write to this
 * register initiates read or write access to the indirect registers in the
 * HAL2. Note that there af four indirect data registers for write access to
 * registers larger than 16 byte.
 */

#define H2_IAR_TYPE_M		0xF000	/* bits 15:12, type of functional */
					/* block the register resides in */
					/* 1=DMA Port */
					/* 9=Global DMA Control */
					/* 2=Bresenham */
					/* 3=Unix Timer */
#define H2_IAR_NUM_M		0x0F00	/* bits 11:8 instance of the */
					/* blockin which the indirect */
					/* register resides */
					/* If IAR_TYPE_M=DMA Port: */
					/* 1=Synth In */
					/* 2=AES In */
					/* 3=AES Out */
					/* 4=DAC Out */
					/* 5=ADC Out */
					/* 6=Synth Control */
					/* If IAR_TYPE_M=Global DMA Control: */
					/* 1=Control */
					/* If IAR_TYPE_M=Bresenham: */
					/* 1=Bresenham Clock Gen 1 */
					/* 2=Bresenham Clock Gen 2 */
					/* 3=Bresenham Clock Gen 3 */
					/* If IAR_TYPE_M=Unix Timer: */
					/* 1=Unix Timer */
#define H2_IAR_ACCESS_SELECT	0x0080	/* 1=read 0=write */
#define H2_IAR_PARAM		0x000C	/* Parameter Select */
#define H2_IAR_RB_INDEX_M	0x0003	/* Read Back Index */
					/* 00:word0 */
					/* 01:word1 */
					/* 10:word2 */
					/* 11:word3 */
/*
 * HAL2 internal addressing
 *
 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
 * Indirect Data registers. Write the address to the Indirect Address register
 * to transfer the data.
 *
 * We define the H2IR_* to the read address and H2IW_* to the write address and
 * H2I_* to be fields in whatever register is referred to.
 *
 * When we write to indirect registers which are larger than one word (16 bit)
 * we have to fill more than one indirect register before writing. When we read
 * back however we have to read several times, each time with different Read
 * Back Indexes (there are defs for doing this easily).
 */

/*
 * Relay Control
 */
#define H2I_RELAY_C		0x9100
#define H2I_RELAY_C_STATE	0x01		/* state of RELAY pin signal */

/* DMA port enable */

#define H2I_DMA_PORT_EN		0x9104
#define H2I_DMA_PORT_EN_SY_IN	0x01		/* Synth_in DMA port */
#define H2I_DMA_PORT_EN_AESRX	0x02		/* AES receiver DMA port */
#define H2I_DMA_PORT_EN_AESTX	0x04		/* AES transmitter DMA port */
#define H2I_DMA_PORT_EN_CODECTX	0x08		/* CODEC transmit DMA port */
#define H2I_DMA_PORT_EN_CODECRX	0x10		/* CODEC receive DMA port */

#define H2I_DMA_END		0x9108 		/* global dma endian select */
#define H2I_DMA_END_SY_IN	0x01		/* Synth_in DMA port */
#define H2I_DMA_END_AESRX	0x02		/* AES receiver DMA port */
#define H2I_DMA_END_AESTX	0x04		/* AES transmitter DMA port */
#define H2I_DMA_END_CODECTX	0x08		/* CODEC transmit DMA port */
#define H2I_DMA_END_CODECRX	0x10		/* CODEC receive DMA port */
						/* 0=b_end 1=l_end */

#define H2I_DMA_DRV		0x910C  	/* global PBUS DMA enable */

#define H2I_SYNTH_C		0x1104		/* Synth DMA control */

#define H2I_AESRX_C		0x1204	 	/* AES RX dma control */
#define H2I_AESRX_C_TS_EN	0x20		/* timestamp enable */
#define H2I_AESRX_C_TS_FMT	0x40		/* timestamp format */
#define H2I_AESRX_C_NAUDIO	0x80		/* PBUS DMA data format */

/* AESRX CTL, 16 bit */

#define H2I_AESTX_C		0x1304		/* AES TX DMA control */
#define H2I_AESTX_C_CLKID_SHIFT	3		/* Bresenham Clock Gen 1-3 */
#define H2I_AESTX_C_CLKID_M	0x18
#define H2I_AESTX_C_DATAT_SHIFT	8		/* 1=mono 2=stereo (3=quad) */
#define H2I_AESTX_C_DATAT_M	0x300

/* CODEC registers. Specification calls them DAC_CTRL and ADC_CTRL, but this
 * is braindamaged. It doesn't explain their meaning. */

#define H2I_CODEC_A_C1		0x1404 		/* CODEC_A DMA control, 16 bit */
#define H2I_CODEC_A_C2		0x1408		/* CODEC_A DMA control, 32 bit */
#define H2I_CODEC_B_C1		0x1504 		/* CODEC_B DMA control, 16 bit */
#define H2I_CODEC_B_C2		0x1508		/* CODEC_B DMA control, 32 bit */

/* Bits in CTL1 register */

#define H2I_C1_DMA_SHIFT	0		/* DMA channel */
#define H2I_C1_DMA_M		0x7
#define H2I_C1_CLKID_SHIFT	3		/* Bresenham Clock Gen 1-3 */
#define H2I_C1_CLKID_M		0x18
#define H2I_C1_DATAT_SHIFT	8		/* 1=mono 2=stereo (3=quad) */
#define H2I_C1_DATAT_M		0x300

/* Bits in CTL2 register */

#define H2I_C2_R_GAIN_SHIFT	0		/* right a/d input gain */	
#define H2I_C2_R_GAIN_M		0xf	
#define H2I_C2_L_GAIN_SHIFT	4		/* left a/d input gain */
#define H2I_C2_L_GAIN_M		0xf0
#define H2I_C2_R_SEL		0x100		/* right input select */
#define H2I_C2_L_SEL		0x200		/* left input select */
#define H2I_C2_MUTE		0x400		/* mute */
#define H2I_C2_DO1		0x00010000	/* digital output port bit 0 */
#define H2I_C2_DO2		0x00020000	/* digital output port bit 1 */
#define H2I_C2_R_ATT_SHIFT	18		/* right d/a output - */
#define H2I_C2_R_ATT_M		0x007c0000	/* attenuation */
#define H2I_C2_L_ATT_SHIFT	23		/* left d/a output - */
#define H2I_C2_L_ATT_M		0x0f800000	/* attenuation */

#define H2I_SYNTH_MAP_C		0x1104		/* synth dma handshake ctrl */

/* Clock generator 1 CTL 1, 16 bit */

#define H2I_BRES1_C1		0x2104 
#define H2I_BRES1_C1_SHIFT	0		/* 0=48.0 1=44.1 2=aes_rx */
#define H2I_BRES1_C1_M		0x03
				
/* Clock generator 1 CTL 2, 32 bit */

#define H2I_BRES1_C2		0x2108
#define H2I_BRES1_C2_INC_SHIFT	0		/* increment value */
#define H2I_BRES1_C2_INC_M	0xffff
#define H2I_BRES1_C2_MOD_SHIFT	16		/* modcontrol value */
#define H2I_BRES1_C2_MOD_M	0xffff0000	/* modctrl=0xffff&(modinc-1) */

/* Clock generator 2 CTL 1, 16 bit */

#define H2I_BRES2_C1		0x2204 
#define H2I_BRES2_C1_SHIFT	0		/* 0=48.0 1=44.1 2=aes_rx */
#define H2I_BRES2_C1_M		0x03
				
/* Clock generator 2 CTL 2, 32 bit */

#define H2I_BRES2_C2		0x2208
#define H2I_BRES2_C2_INC_SHIFT	0		/* increment value */
#define H2I_BRES2_C2_INC_M	0xffff
#define H2I_BRES2_C2_MOD_SHIFT	16		/* modcontrol value */
#define H2I_BRES2_C2_MOD_M	0xffff0000	/* modctrl=0xffff&(modinc-1) */

/* Clock generator 3 CTL 1, 16 bit */

#define H2I_BRES3_C1		0x2304 
#define H2I_BRES3_C1_SHIFT	0		/* 0=48.0 1=44.1 2=aes_rx */
#define H2I_BRES3_C1_M		0x03
				
/* Clock generator 3 CTL 2, 32 bit */

#define H2I_BRES3_C2		0x2308
#define H2I_BRES3_C2_INC_SHIFT	0		/* increment value */
#define H2I_BRES3_C2_INC_M	0xffff
#define H2I_BRES3_C2_MOD_SHIFT	16		/* modcontrol value */
#define H2I_BRES3_C2_MOD_M	0xffff0000	/* modctrl=0xffff&(modinc-1) */

/* Unix timer, 64 bit */

#define H2I_UTIME		0x3104
#define H2I_UTIME_0_LD		0xffff		/* microseconds, LSB's */
#define H2I_UTIME_1_LD0		0x0f		/* microseconds, MSB's */
#define H2I_UTIME_1_LD1		0xf0		/* tenths of microseconds */
#define H2I_UTIME_2_LD		0xffff		/* seconds, LSB's */
#define H2I_UTIME_3_LD		0xffff		/* seconds, MSB's */

typedef volatile u32 hal2_reg_t;

typedef struct stru_hal2_ctl_regs hal2_ctl_regs_t;
struct stru_hal2_ctl_regs {
	hal2_reg_t _unused0[4];
	hal2_reg_t isr;			/* 0x10 Status Register */
	hal2_reg_t _unused1[3];
	hal2_reg_t rev;			/* 0x20 Revision Register */
	hal2_reg_t _unused2[3];
	hal2_reg_t iar;			/* 0x30 Indirect Address Register */
	hal2_reg_t _unused3[3];
	hal2_reg_t idr0;		/* 0x40 Indirect Data Register 0 */
	hal2_reg_t _unused4[3];
	hal2_reg_t idr1;		/* 0x50 Indirect Data Register 1 */
	hal2_reg_t _unused5[3];
	hal2_reg_t idr2;		/* 0x60 Indirect Data Register 2 */
	hal2_reg_t _unused6[3];
	hal2_reg_t idr3;		/* 0x70 Indirect Data Register 3 */
};

typedef struct stru_hal2_aes_regs hal2_aes_regs_t;
struct stru_hal2_aes_regs {
	hal2_reg_t rx_stat[2];		/* Status registers */
	hal2_reg_t rx_cr[2];		/* Control registers */
	hal2_reg_t rx_ud[4];		/* User data window */
	hal2_reg_t rx_st[24];		/* Channel status data */
	
	hal2_reg_t tx_stat[1];		/* Status register */
	hal2_reg_t tx_cr[3];		/* Control registers */
	hal2_reg_t tx_ud[4];		/* User data window */
	hal2_reg_t tx_st[24];		/* Channel status data */
};

typedef struct stru_hal2_vol_regs hal2_vol_regs_t;
struct stru_hal2_vol_regs {
	hal2_reg_t right;		/* 0x00 Right volume */
	hal2_reg_t left;		/* 0x04 Left volume */
};

typedef struct stru_hal2_syn_regs hal2_syn_regs_t;
struct stru_hal2_syn_regs {
	hal2_reg_t _unused0[2];
	hal2_reg_t page;		/* DOC Page register */
	hal2_reg_t regsel;		/* DOC Register selection */
	hal2_reg_t dlow;		/* DOC Data low */
	hal2_reg_t dhigh;		/* DOC Data high */
	hal2_reg_t irq;			/* IRQ Status */
	hal2_reg_t dram;		/* DRAM Access */
};

/* HAL2 specific structures */

typedef struct stru_hal2_pbus hal2_pbus_t;
struct stru_hal2_pbus {
	struct hpc3_pbus_dmacregs *pbus;
	int pbusnr;
	unsigned int fifobeg;
	unsigned int fifoend;
	unsigned int highwater;

	unsigned long ctrl;		/* Current state of pbus->pbdma_ctrl */
};

typedef struct stru_hal2_binfo hal2_binfo_t;
typedef struct stru_hal2_buffer hal2_buf_t;
struct stru_hal2_binfo {
	volatile struct hpc_dma_desc desc;
	hal2_buf_t *next;		/* pointer to next buffer */
	int cnt;			/* bytes in buffer */
};
#define H2_BUFFER_SIZE	(PAGE_SIZE - \
		((sizeof(hal2_binfo_t) - 1) / 8 + 1) * 8)
struct stru_hal2_buffer {
	hal2_binfo_t info;
	char data[H2_BUFFER_SIZE] __attribute__((aligned(8)));
};

typedef struct stru_hal2_codec hal2_codec_t;
struct stru_hal2_codec {
	hal2_buf_t *head;
	hal2_buf_t *tail; 
	hal2_pbus_t pbus;
	unsigned int format;		/* Audio data format */
	int voices;			/* mono/stereo */
	unsigned int sample_rate;
	unsigned int master;		/* Master frequency */
	unsigned short mod;		/* MOD value */
	unsigned short inc;		/* INC value */

	wait_queue_head_t dma_wait;
	spinlock_t lock;
	struct semaphore sem;

	int usecount;			/* recording and playback are 
					 * independent */
};

#define H2_MIX_OUTPUT_ATT	0
#define H2_MIX_INPUT_GAIN	1
#define H2_MIXERS		2
typedef struct stru_hal2_mixer hal2_mixer_t;
struct stru_hal2_mixer {
	int modcnt;
	unsigned int volume[H2_MIXERS];
};

typedef struct stru_hal2_card hal2_card_t;
struct stru_hal2_card {
	int dev_dsp;			/* audio device */
	int dev_mixer;			/* mixer device */
	int dev_midi;			/* midi device */
	
	hal2_ctl_regs_t *ctl_regs;	/* HAL2 ctl registers */
	hal2_aes_regs_t *aes_regs;	/* HAL2 vol registers */
	hal2_vol_regs_t *vol_regs;	/* HAL2 aes registers */
	hal2_syn_regs_t *syn_regs;	/* HAL2 syn registers */

	hal2_codec_t dac;
	hal2_codec_t adc;
	hal2_mixer_t mixer;
};

#endif				/* __HAL2_H */

Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/Config.in,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- Config.in	2001/12/06 18:44:28	1.11
+++ Config.in	2002/01/28 21:00:02	1.12
@@ -43,11 +43,13 @@
 dep_tristate '  ESS Maestro, Maestro2, Maestro2E driver' CONFIG_SOUND_MAESTRO $CONFIG_SOUND
 dep_tristate '  ESS Maestro3/Allegro driver (EXPERIMENTAL)' CONFIG_SOUND_MAESTRO3 $CONFIG_SOUND $CONFIG_PCI $CONFIG_EXPERIMENTAL
 dep_tristate '  Intel ICH (i8xx) audio support' CONFIG_SOUND_ICH $CONFIG_PCI
+if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
+    dep_tristate '  IT8172G Sound' CONFIG_SOUND_IT8172 $CONFIG_SOUND
+fi
 dep_tristate '  RME Hammerfall (RME96XX) support' CONFIG_SOUND_RME96XX $CONFIG_SOUND $CONFIG_PCI $CONFIG_EXPERIMENTAL
 dep_tristate '  S3 SonicVibes' CONFIG_SOUND_SONICVIBES $CONFIG_SOUND
-if [ "$CONFIG_VISWS" = "y" ]; then
-    dep_tristate '  SGI Visual Workstation Sound' CONFIG_SOUND_VWSND $CONFIG_SOUND
-fi
+dep_tristate '  SGI Visual Workstation sound' CONFIG_SOUND_VWSND $CONFIG_SOUND $CONFIG_VISWS
+dep_tristate '  SGI HAL2 sound (EXPERIMENTAL)' CONFIG_SOUND_HAL2 $CONFIG_SOUND $CONFIG_SGI_IP22 $CONFIG_EXPERIMENTAL
 
 if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
     dep_tristate '  IT8172G Sound' CONFIG_SOUND_IT8172 $CONFIG_SOUND

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/sound/Makefile,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- Makefile	2001/11/26 19:34:31	1.11
+++ Makefile	2002/01/28 21:00:02	1.12
@@ -20,6 +20,7 @@
 
 # Please leave it as is, cause the link order is significant !
 
+obj-$(CONFIG_SOUND_HAL2)	+= hal2.o
 obj-$(CONFIG_SOUND_AEDSP16)	+= aedsp16.o
 obj-$(CONFIG_SOUND_PSS)		+= pss.o ad1848.o mpu401.o
 obj-$(CONFIG_SOUND_TRIX)	+= trix.o ad1848.o sb_lib.o uart401.o

[Linux-mips-commits]CVS: linux/include/asm-mips/sibyte swarm_ide.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv15560/include/asm-mips/sibyte

Added Files:
	swarm_ide.h 
Log Message:
Sync up rest of files.

--- NEW FILE: swarm_ide.h ---
/*
 * Copyright (C) 2001 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#ifndef _SWARM_IDE_H
#define _SWARM_IDE_H

#include <asm/sibyte/sb1250_int.h>

#define SWARM_IDE_BASE        (0xb00b0000-mips_io_port_base)
#define SWARM_IDE_REG(pcaddr) (SWARM_IDE_BASE + ((pcaddr)<<5))
#define SWARM_IDE_INT         (K_INT_GPIO_4)

extern ide_ideproc_t swarm_ideproc;

#define swarm_outb(val,port)							\
do {									\
	*(volatile u8 *)(mips_io_port_base + (port)) = val;	\
} while(0)

#define swarm_outw(val,port)							\
do {									\
	*(volatile u16 *)(mips_io_port_base + (port)) = val;	\
} while(0)

#define swarm_outl(val,port)							\
do {									\
	*(volatile u32 *)(mips_io_port_base + (port)) = val;\
} while(0)

static inline unsigned char swarm_inb(unsigned long port)
{
	return (*(volatile u8 *)(mips_io_port_base + port));
}

static inline unsigned short swarm_inw(unsigned long port)
{
	return (*(volatile u16 *)(mips_io_port_base + port));
}

static inline unsigned int swarm_inl(unsigned long port)
{
	return (*(volatile u32 *)(mips_io_port_base + port));
}


static inline void swarm_outsb(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		swarm_outb(*(u8 *)addr, port);
		addr++;
	}
}

static inline void swarm_insb(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u8 *)addr = swarm_inb(port);
		addr++;
	}
}

static inline void swarm_outsw(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		swarm_outw(*(u16 *)addr, port);
		addr += 2;
	}
}

static inline void swarm_insw(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u16 *)addr = swarm_inw(port);
		addr += 2;
	}
}

static inline void swarm_outsl(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		swarm_outl(*(u32 *)addr, port);
		addr += 4;
	}
}

static inline void swarm_insl(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u32 *)addr = swarm_inl(port);
		addr += 4;
	}
}

#endif

[Linux-mips-commits]CVS: linux/include/asm-mips/sgi sgihpc.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/sgi
In directory usw-pr-cvs1:/tmp/cvs-serv15444/include/asm-mips/sgi

Added Files:
	sgihpc.h 
Log Message:
Sync up rest of files.

--- NEW FILE: sgihpc.h ---
/*
 * sgihpc.h: Various HPC I/O controller defines.  The HPC is basically
 *           the approximate functional equivalent of the Sun SYSIO
 *           on SGI INDY machines.
 *
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1998 Ralf Baechle (ra...@gn...)
 */
#ifndef __ASM_SGI_SGIHPC_H
#define __ASM_SGI_SGIHPC_H

#include <asm/page.h>

extern int sgi_has_ioc2;	/* to know if we have older ioc1 or ioc2. */
extern int sgi_guiness;		/* GUINESS or FULLHOUSE machine. */
extern int sgi_boardid;		/* Board revision. */

/* An HPC dma descriptor. */
struct hpc_dma_desc {
	u32 pbuf;	/* physical address of data buffer */
	u32 cntinfo;	/* counter and info bits */
#define HPCDMA_EOX	0x80000000 /* last desc in chain for tx */
#define HPCDMA_EOR	0x80000000 /* last desc in chain for rx */
#define HPCDMA_EOXP	0x40000000 /* end of packet for tx */
#define HPCDMA_EORP	0x40000000 /* end of packet for rx */
#define HPCDMA_XIE	0x20000000 /* irq generated when at end of this desc */
#define HPCDMA_XIU	0x01000000 /* Tx buffer in use by CPU. */
#define HPCDMA_EIPC	0x00ff0000 /* SEEQ ethernet special xternal bytecount */
#define HPCDMA_ETXD	0x00008000 /* set to one by HPC when packet tx'd */
#define HPCDMA_OWN	0x00004000 /* Denotes ring buffer ownership on rx */
#define HPCDMA_BCNT	0x00003fff /* size in bytes of this dma buffer */

	u32 pnext;	/* paddr of next hpc_dma_desc if any */
};

typedef volatile u32 hpcreg;

/* HPC1 stuff. */

/* HPC3 stuff. */

/* The set of regs for each HPC3 pbus dma channel. */
struct hpc3_pbus_dmacregs {
	hpcreg pbdma_bptr;	/* pbus dma channel buffer ptr */
	hpcreg pbdma_dptr;	/* pbus dma channel desc ptr */
	char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg pbdma_ctrl;	/* pbus dma channel control register has 
				 * copletely different meaning for read 
				 * compared with write */
	/* read */
#define HPC3_PDMACTRL_INT	0x00000001 /* interrupt (cleared after read) */
#define HPC3_PDMACTRL_ISACT	0x00000002 /* channel active */
	/* write */
#define HPC3_PDMACTRL_SEL	0x00000002 /* little endian transfer */
#define HPC3_PDMACTRL_RCV	0x00000004 /* direction is receive */
#define HPC3_PDMACTRL_FLSH	0x00000008 /* enable flush for receive DMA */
#define HPC3_PDMACTRL_ACT	0x00000010 /* start dma transfer */
#define HPC3_PDMACTRL_LD	0x00000020 /* load enable for ACT */
#define HPC3_PDMACTRL_RT	0x00000040 /* Use realtime GIO bus servicing */
#define HPC3_PDMACTRL_HW	0x0000ff00 /* DMA High-water mark */
#define HPC3_PDMACTRL_FB	0x003f0000 /* Ptr to beginning of fifo */
#define HPC3_PDMACTRL_FE	0x3f000000 /* Ptr to end of fifo */

	char _unused2[PAGE_SIZE - (sizeof(hpcreg))]; /* padding */
};

/* The HPC3 scsi registers, this does not include external ones. */
struct hpc3_scsiregs {
	hpcreg cbptr;	/* current dma buffer ptr, diagnostic use only */
	hpcreg ndptr;	/* next dma descriptor ptr */
	char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg bcd;	/* byte count info */
#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */

	hpcreg ctrl;    /* control register */
#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */

	hpcreg gfptr;	/* current GIO fifo ptr */
	hpcreg dfptr;	/* current device fifo ptr */
	hpcreg dconfig;	/* DMA configuration register */
#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */

	hpcreg pconfig;	/* PIO configuration register */
#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */

	char _unused2[PAGE_SIZE - (6 * sizeof(hpcreg))]; /* padding */
};

/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
struct hpc3_ethregs {
	/* Receiver registers. */
	hpcreg rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
	hpcreg rx_ndptr;   /* next dma descriptor ptr */
	char _unused1[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg rx_bcd;	/* byte count info */
#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */

	hpcreg rx_ctrl;	/* control register */
#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
#define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
#define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
#define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
#define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */

	hpcreg rx_gfptr;	/* current GIO fifo ptr */
	hpcreg rx_dfptr;	/* current device fifo ptr */
	hpcreg _unused2;	/* padding */
	hpcreg rx_reset;	/* reset register */
#define HPC3_ERXRST_CRESET 0x1	/* Reset dma channel and external controller */
#define HPC3_ERXRST_CLRIRQ 0x2	/* Clear channel interrupt */
#define HPC3_ERXRST_LBACK  0x4	/* Enable diagnostic loopback mode of Seeq8003 */

	hpcreg rx_dconfig;	/* DMA configuration register */
#define HPC3_ERXDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
#define HPC3_ERXDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
#define HPC3_ERXDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
#define HPC3_ERXDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
#define HPC3_ERXDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
#define HPC3_ERXDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
#define HPC3_ERXDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
#define HPC3_ERXDCFG_PTO   0x30000 /* Programmed timeout value for above two */

	hpcreg rx_pconfig;	/* PIO configuration register */
#define HPC3_ERXPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_ERXPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_ERXPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_ERXPCFG_TST   0x1000 /* Diagnistic ram test feature bit */

	char _unused3[PAGE_SIZE - (8 * sizeof(hpcreg))]; /* padding */

	/* Transmitter registers. */
	hpcreg tx_cbptr;	/* current dma buffer ptr, diagnostic use only */
	hpcreg tx_ndptr;	/* next dma descriptor ptr */
	char _unused4[PAGE_SIZE - (2 * sizeof(hpcreg))]; /* padding */
	hpcreg tx_bcd;		/* byte count info */
#define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
#define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */
#define HPC3_ETXBCD_XIE     0x20000000 /* Interrupt cpu at end of cur desc */
#define HPC3_ETXBCD_EOP     0x40000000 /* Last byte of cur buf is end of packet */
#define HPC3_ETXBCD_EOX     0x80000000 /* This buf is the end of desc chain */

	hpcreg tx_ctrl;    /* control register */
#define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
#define HPC3_ETXCTRL_STAT4  0x00000010 /* Indicate late collision occurred */
#define HPC3_ETXCTRL_STAT75 0x000000e0 /* Rdonly irq status from seeq */
#define HPC3_ETXCTRL_ENDIAN 0x00000100 /* Dma channel endian mode, 1=little 0=big */
#define HPC3_ETXCTRL_ACTIVE 0x00000200 /* DMA tx channel is active */
#define HPC3_ETXCTRL_AMASK  0x00000400 /* Indicates ACTIVE inhibits PIO's */

	hpcreg tx_gfptr;	/* current GIO fifo ptr */
	hpcreg tx_dfptr;	/* current device fifo ptr */
	char _unused5[PAGE_SIZE - (4 * sizeof(hpcreg))]; /* padding */
};

struct hpc3_regs {
	/* First regs for the PBUS 8 dma channels. */
	struct hpc3_pbus_dmacregs pbdma[8];

	/* Now the HPC scsi registers, we get two scsi reg sets. */
	struct hpc3_scsiregs scsi_chan0, scsi_chan1;

	/* The SEEQ hpc3 ethernet dma/control registers. */
	struct hpc3_ethregs ethregs;

	/* Here are where the hpc3 fifo's can be directly accessed
	 * via PIO accesses.  Under normal operation we never stick
	 * our grubby paws in here so it's just padding.
	 */
	char _unused1[PAGE_SIZE * 24];

	/* HPC3 irq status regs.  Due to a peculiar bug you need to
	 * look at two different register addresses to get at all of
	 * the status bits.  The first reg can only reliably report
	 * bits 4:0 of the status, and the second reg can only
	 * reliably report bits 9:5 of the hpc3 irq status.  I told
	 * you it was a peculiar bug. ;-)
	 */
	hpcreg istat0;		/* Irq status, only bits <4:0> reliable. */

#define HPC3_ISTAT_PBIMASK	0x0ff	/* irq bits for pbus devs 0 --> 7 */
#define HPC3_ISTAT_SC0MASK	0x100	/* irq bit for scsi channel 0 */
#define HPC3_ISTAT_SC1MASK	0x200	/* irq bit for scsi channel 1 */

	hpcreg gio64_misc;	/* GIO64 misc control bits. */
#define HPC3_GIOMISC_ERTIME	0x1	/* Enable external timer real time. */
#define HPC3_GIOMISC_DENDIAN	0x2	/* dma descriptor endian, 1=lit 0=big */

	hpcreg eeprom_data;	/* EEPROM data reg. */
#define HPC3_EEPROM_EPROT	0x01	/* Protect register enable */
#define HPC3_EEPROM_CSEL	0x02	/* Chip select */
#define HPC3_EEPROM_ECLK	0x04	/* EEPROM clock */
#define HPC3_EEPROM_DATO	0x08	/* Data out */
#define HPC3_EEPROM_DATI	0x10	/* Data in */

	hpcreg istat1;		/* Irq status, only bits <9:5> reliable. */
	hpcreg gio64_estat;	/* GIO64 error interrupt status reg. */
#define HPC3_GIOESTAT_BLMASK	0x000ff	/* Bus lane where bad parity occurred */
#define HPC3_GIOESTAT_CTYPE	0x00100	/* Bus cycle type, 0=PIO 1=DMA */
#define HPC3_GIOESTAT_PIDMSK	0x3f700	/* DMA channel parity identifier */

	/* Now direct PIO per-HPC3 peripheral access to external regs. */
	char _unused2[0x13fec];	/* Trust me... */
	hpcreg scsi0_ext[256];	/* SCSI channel 0 external regs */
	char _unused3[0x07c00];	/* Trust me... */
	hpcreg scsi1_ext[256];	/* SCSI channel 1 external regs */
	char _unused4[0x07c00];	/* It'll only hurt a little... */

	/* Ethernet external registers. Noone use them so we need some 
	 * padding instead.
	 */
	char _unused5[0x04000]; /* It'll hurt a lot if you leave this out */

	/* Per-peripheral device external registers and dma/pio control. */
	hpcreg pbus_extregs[16][256];	/* 2nd indice indexes controller */
	hpcreg pbus_dmacfgs[8][128];	/* 2nd indice indexes controller */
#define HPC3_PIODCFG_D3R    0x00000001	/* Cycles to spend in D3 for reads */
#define HPC3_PIODCFG_D4R    0x0000001e	/* Cycles to spend in D4 for reads */
#define HPC3_PIODCFG_D5R    0x000001e0	/* Cycles to spend in D5 for reads */
#define HPC3_PIODCFG_D3W    0x00000200	/* Cycles to spend in D3 for writes */
#define HPC3_PIODCFG_D4W    0x00003c00	/* Cycles to spend in D4 for writes */
#define HPC3_PIODCFG_D5W    0x0003c000	/* Cycles to spend in D5 for writes */
#define HPC3_PIODCFG_HWORD  0x00040000	/* Enable 16-bit dma access mode */
#define HPC3_PIODCFG_EHI    0x00080000	/* Places halfwords on high 16 bits of bus */
#define HPC3_PIODCFG_RTIME  0x00200000	/* Make this device real time on GIO bus */
#define HPC3_PIODCFG_BURST  0x07c00000	/* 5 bit burst count for DMA device */
#define HPC3_PIODCFG_DRQLV  0x08000000	/* Use live pbus_dreq unsynchronized signal */

	hpcreg pbus_piocfgs[64][10];	/* 2nd indice indexes controller */
#define HPC3_PIOPCFG_RP2    0x00001	/* Cycles to spend in P2 state for reads */
#define HPC3_PIOPCFG_RP3    0x0001e	/* Cycles to spend in P3 state for reads */
#define HPC3_PIOPCFG_RP4    0x001e0	/* Cycles to spend in P4 state for reads */
#define HPC3_PIOPCFG_WP2    0x00200	/* Cycles to spend in P2 state for writes */
#define HPC3_PIOPCFG_WP3    0x03c00	/* Cycles to spend in P3 state for writes */
#define HPC3_PIOPCFG_WP4    0x3c000	/* Cycles to spend in P4 state for writes */
#define HPC3_PIOPCFG_HW     0x40000	/* Enable 16-bit PIO accesses */
#define HPC3_PIOPCFG_EHI    0x80000	/* Place even address bits in bits <15:8> */

	/* PBUS PROM control regs. */
	hpcreg pbus_promwe;	/* PROM write enable register */
#define HPC3_PROM_WENAB	    0x1	/* Enable writes to the PROM */

	char _unused6[0x800 - sizeof(hpcreg)];
	hpcreg pbus_promswap;	/* Chip select swap reg */
#define HPC3_PROM_SWAP      0x1	/* invert GIO addr bit to select prom0 or prom1 */

	char _unused7[0x800 - sizeof(hpcreg)];
	hpcreg pbus_gout;	/* PROM general purpose output reg */
#define HPC3_PROM_STAT      0x1	/* General purpose status bit in gout */

	char _unused8[0x1000 - sizeof(hpcreg)];
	hpcreg pbus_promram[16384];	/* 64k of PROM battery backed ram */
};

/* It is possible to have two HPC3's within the address space on
 * one machine, though only having one is more likely on an INDY.
 * Controller 0 lives at physical address 0x1fb80000 and the controller
 * 1 if present lives at address 0x1fb00000.
 */
extern struct hpc3_regs *hpc3c0, *hpc3c1;
#define HPC3_CHIP0_PBASE	0x1fb80000	/* physical */
#define HPC3_CHIP1_PBASE	0x1fb00000	/* physical */

/* Control and misc status information, these live in pbus channel 6. */
struct hpc3_miscregs {
	hpcreg pdata, pctrl, pstat, pdmactrl, pistat, pimask;
	hpcreg ptimer1, ptimer2, ptimer3, ptimer4;
	hpcreg _unused1[2];
	hpcreg ser1cmd, ser1data;
	hpcreg ser0cmd, ser0data;
	hpcreg kbdmouse0, kbdmouse1;
	hpcreg gcsel, genctrl, panel;
	hpcreg _unused2;
	hpcreg sysid;
	hpcreg _unused3;
	hpcreg read, _unused4;
	hpcreg dselect;
#define HPC3_DSELECT_SCLK10MHZ	0x00	/* use 10MHZ serial clock */
#define HPC3_DSELECT_ISDNB	0x01	/* enable isdn B */
#define HPC3_DSELECT_ISDNA	0x02	/* enable isdn A */
#define HPC3_DSELECT_LPR	0x04	/* use parallel DMA */
#define HPC3_DSELECT_SCLK667MHZ	0x10	/* use 6.67MHZ serial clock */
#define HPC3_DSELECT_SCLKEXT	0x20	/* use external serial clock */

	hpcreg _unused5;
	hpcreg write1;
#define HPC3_WRITE1_PRESET	0x01	/* 0=LPR_RESET, 1=NORMAL */
#define HPC3_WRITE1_KMRESET	0x02	/* 0=KBDMOUSE_RESET, 1=NORMAL */
#define HPC3_WRITE1_ERESET	0x04	/* 0=EISA_RESET, 1=NORMAL */
#define HPC3_WRITE1_GRESET	0x08	/* 0=MAGIC_GIO_RESET, 1=NORMAL */
#define HPC3_WRITE1_LC0OFF	0x10	/* turn led off (guiness=red, else green) */
#define HPC3_WRITE1_LC1OFF	0x20	/* turn led off (guiness=green, else amber) */

	hpcreg _unused6;
	hpcreg write2;
#define HPC3_WRITE2_NTHRESH	0x01	/* use 4.5db threshhold */
#define HPC3_WRITE2_TPSPEED	0x02	/* use 100ohm TP speed */
#define HPC3_WRITE2_EPSEL	0x04	/* force cable mode: 1=AUI 0=TP */
#define HPC3_WRITE2_EASEL	0x08	/* 1=autoselect 0=manual cable selection */
#define HPC3_WRITE2_U1AMODE	0x10	/* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_U0AMODE	0x20	/* 1=PC 0=MAC UART mode */
#define HPC3_WRITE2_MLO		0x40	/* 1=4.75V 0=+5V */
#define HPC3_WRITE2_MHI		0x80	/* 1=5.25V 0=+5V */
};
extern struct hpc3_miscregs *hpc3mregs;
#define HPC3_MREGS_PBASE	0x1fbd9800	/* physical */

/* We need software copies of these because they are write only. */
extern unsigned int sgi_hpc_write1, sgi_hpc_write2;

struct hpc_keyb {
#ifdef __MIPSEB__
	unsigned char _unused0[3];
	volatile unsigned char data;
	unsigned char _unused1[3];
	volatile unsigned char command;
#else
	volatile unsigned char data;
	unsigned char _unused0[3];
	volatile unsigned char command;
	unsigned char _unused1[3];
#endif
};

/* Indy RTC  */

/* The layout of registers for the INDY Dallas 1286 clock chipset. */
struct indy_clock {
	volatile unsigned int hsec;
	volatile unsigned int sec;
	volatile unsigned int min;
	volatile unsigned int malarm;
	volatile unsigned int hr;
	volatile unsigned int halarm;
	volatile unsigned int day;
	volatile unsigned int dalarm;
	volatile unsigned int date;
	volatile unsigned int month;
	volatile unsigned int year;
	volatile unsigned int cmd;
	volatile unsigned int whsec;
	volatile unsigned int wsec;
	volatile unsigned int _unused0[50];
};

#define INDY_CLOCK_REGS (KSEG1ADDR(0x1fbe0000))

extern void sgihpc_init(void);

#endif /* __ASM_SGI_SGIHPC_H */

[Linux-mips-commits]CVS: linux/include/asm-mips asm.h,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv14730

Modified Files:
	asm.h 
Log Message:
Use .pushsection / .popsection.  This means binutils 2.8 can no longer be used to build the MIPS kernel from now on.

Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/asm.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- asm.h	2001/11/19 17:30:16	1.4
+++ asm.h	2002/01/28 20:53:19	1.5
@@ -1,6 +1,4 @@
 /*
- * include/asm-mips/asm.h
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
@@ -124,20 +122,20 @@
 		TEXT(string)
 
 #define	TEXT(msg)                                       \
-		.data;                                  \
+		.pushsection .data;			\
 8:		.asciiz	msg;                            \
-		.previous;
+		.popsection;
 
 /*
  * Build text tables
  */
 #define TTABLE(string)                                  \
-		.text;                                  \
+		.pushsection .text;			\
 		.word	1f;                             \
 		.previous;                              \
 		.data;                                  \
 1:		.asciz	string;                         \
-		.previous
+		.popsection
 
 /*
  * MIPS IV pref instruction.

[Linux-mips-commits]CVS: linux/include/asm-mips system.h,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv14519

Modified Files:
	system.h 
Log Message:
Use ssnop in __cli to make code bulletproof against superscalar cpus.

Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/system.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- system.h	2001/12/12 16:18:36	1.6
+++ system.h	2002/01/28 20:52:33	1.7
@@ -53,16 +53,15 @@
 __asm__ (
 	".macro\t__cli\n\t"
 	".set\tpush\n\t"
-	".set\treorder\n\t"
 	".set\tnoat\n\t"
 	"mfc0\t$1,$12\n\t"
 	"ori\t$1,1\n\t"
 	"xori\t$1,1\n\t"
 	".set\tnoreorder\n\t"
 	"mtc0\t$1,$12\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
 	".set\tpop\n\t"
 	".endm");
 

[Linux-mips-commits]CVS: linux/drivers/scsi sgiwd93.c,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/scsi
In directory usw-pr-cvs1:/tmp/cvs-serv13934

Modified Files:
	sgiwd93.c 
Log Message:
64-bit fixlet.

Index: sgiwd93.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/scsi/sgiwd93.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- sgiwd93.c	2001/12/13 19:15:15	1.4
+++ sgiwd93.c	2002/01/28 20:50:26	1.5
@@ -39,7 +39,7 @@
 
 struct hpc_chunk {
 	struct hpc_dma_desc desc;
-	unsigned long padding;
+	u32 _padding;	/* align to quadword boundary */
 };
 
 struct Scsi_Host *sgiwd93_host = NULL;
@@ -142,10 +142,10 @@
 	/* Start up the HPC. */
 	hregs->ndptr = PHYSADDR(hdata->dma_bounce_buffer);
 	if(datainp) {
-		dma_cache_wback_inv((unsigned long) cmd->SCp.ptr, cmd->SCp.this_residual);
+		dma_cache_inv((unsigned long) cmd->SCp.ptr, cmd->SCp.this_residual);
 		hregs->ctrl = (HPC3_SCTRL_ACTIVE);
 	} else {
-		dma_cache_inv((unsigned long) cmd->SCp.ptr, cmd->SCp.this_residual);
+		dma_cache_wback_inv((unsigned long) cmd->SCp.ptr, cmd->SCp.this_residual);
 		hregs->ctrl = (HPC3_SCTRL_ACTIVE | HPC3_SCTRL_DIR);
 	}
 
@@ -237,9 +237,10 @@
 		return 0;
 	}
 	init_hpc_chain(buf);
-
-	regs.SASR = KSEG1ADDR (0x1fbc0003); /* HPC_SCSI_REG0 | 0x03 | KSEG1 */
-	regs.SCMD = KSEG1ADDR (0x1fbc0007);
+	
+	/* HPC_SCSI_REG0 | 0x03 | KSEG1 */
+	regs.SASR = (unsigned char*) KSEG1ADDR (0x1fbc0003);
+	regs.SCMD = (unsigned char*) KSEG1ADDR (0x1fbc0007);
 	wd33c93_init(sgiwd93_host, regs, dma_setup, dma_stop, WD33C93_FS_16_20);
 
 	hdata = (struct WD33C93_hostdata *)sgiwd93_host->hostdata;
@@ -273,8 +274,8 @@
 			init_hpc_chain(buf);
 
 			/* HPC_SCSI_REG1 | 0x03 | KSEG1 */
-			regs.SASR = KSEG1ADDR(0x1fbc8003);
-			regs.SCMD = KSEG1ADDR(0x1fbc8007);
+			regs.SASR = (unsigned char*) KSEG1ADDR(0x1fbc8003);
+			regs.SCMD = (unsigned char*) KSEG1ADDR(0x1fbc8007);
 			wd33c93_init(sgiwd93_host1, regs, dma_setup, dma_stop,
 			             WD33C93_FS_16_20);
 	

[Linux-mips-commits]CVS: linux/drivers/ide Makefile,1.3,1.4 ide-swarm.c,NONE,1.1 ide.c,NONE,1.1 Config.in,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/ide
In directory usw-pr-cvs1:/tmp/cvs-serv13243/drivers/ide

Modified Files:
	Config.in 
Added Files:
	Makefile ide-swarm.c ide.c 
Log Message:
Swarm IDE support.


--- NEW FILE: ide-swarm.c ---
/*
 * Copyright (C) 2001 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

/*  Derived loosely from ide-pmac.c, so:
 *  
 *  Copyright (C) 1998 Paul Mackerras.
 *  Copyright (C) 1995-1998 Mark Lord
 */
#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/ide.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/sibyte/sb1250_int.h>
#include <asm/sibyte/swarm_ide.h>

void __init swarm_ide_probe(void)
{
	int i;
	ide_hwif_t *hwif;
	/* 
	 * Find the first untaken slot in hwifs 
	 */
	for (i = 0; i < MAX_HWIFS; i++) {
		if (!ide_hwifs[i].io_ports[IDE_DATA_OFFSET]) {
			break;
		}
	}
	if (i == MAX_HWIFS) {
		printk("No space for SWARM onboard IDE driver in ide_hwifs[].  Not enabled.\n");
		return;
	}

	/* Set up our stuff */
	hwif = &ide_hwifs[i];
	hwif->hw.io_ports[IDE_DATA_OFFSET]    = SWARM_IDE_REG(0x1f0);
	hwif->hw.io_ports[IDE_ERROR_OFFSET]   = SWARM_IDE_REG(0x1f1);
	hwif->hw.io_ports[IDE_NSECTOR_OFFSET] = SWARM_IDE_REG(0x1f2);
	hwif->hw.io_ports[IDE_SECTOR_OFFSET]  = SWARM_IDE_REG(0x1f3);
	hwif->hw.io_ports[IDE_LCYL_OFFSET]    = SWARM_IDE_REG(0x1f4);
	hwif->hw.io_ports[IDE_HCYL_OFFSET]    = SWARM_IDE_REG(0x1f5);
	hwif->hw.io_ports[IDE_SELECT_OFFSET]  = SWARM_IDE_REG(0x1f6);
	hwif->hw.io_ports[IDE_STATUS_OFFSET]  = SWARM_IDE_REG(0x1f7);
	hwif->hw.io_ports[IDE_CONTROL_OFFSET] = SWARM_IDE_REG(0x3f6);
	hwif->hw.io_ports[IDE_IRQ_OFFSET]     = SWARM_IDE_REG(0x3f7);
//	hwif->hw->ack_intr                     = swarm_ide_ack_intr;
	hwif->hw.irq                          = SWARM_IDE_INT;
	hwif->ideproc                         = swarm_ideproc;

	memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
	hwif->irq = hwif->hw.irq;
	printk("SWARM onboard IDE configured as device %i\n", i);
}


--- NEW FILE: ide.c ---
/*
 *  linux/drivers/ide/ide.c		Version 6.31	June 9, 2000
 *
 *  Copyright (C) 1994-1998  Linus Torvalds & authors (see below)
 */

/*
 *  Mostly written by Mark Lord  <ml...@po...>
 *                and Gadi Oxman <ga...@ne...>
 *                and Andre Hedrick <an...@li...>
 *
 *  See linux/MAINTAINERS for address of current maintainer.
 *
 * This is the multiple IDE interface driver, as evolved from hd.c.
 * It supports up to MAX_HWIFS IDE interfaces, on one or more IRQs (usually 14 & 15).
 * There can be up to two drives per interface, as per the ATA-2 spec.
 *
 * Primary:    ide0, port 0x1f0; major=3;  hda is minor=0; hdb is minor=64
 * Secondary:  ide1, port 0x170; major=22; hdc is minor=0; hdd is minor=64
[...3757 lines suppressed...]

	for (index = 0; index < MAX_HWIFS; ++index) {
		ide_unregister(index);
#if defined(CONFIG_BLK_DEV_IDEDMA) && !defined(CONFIG_DMA_NONPCI)
		if (ide_hwifs[index].dma_base)
			(void) ide_release_dma(&ide_hwifs[index]);
#endif /* (CONFIG_BLK_DEV_IDEDMA) && !(CONFIG_DMA_NONPCI) */
	}

#ifdef CONFIG_PROC_FS
	proc_ide_destroy();
#endif
	devfs_unregister (ide_devfs_handle);
}

#else /* !MODULE */

__setup("", ide_setup);

#endif /* MODULE */

Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/ide/Config.in,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- Config.in	2001/12/03 17:31:27	1.6
+++ Config.in	2002/01/28 20:48:47	1.7
@@ -105,6 +105,9 @@
 	   define_bool CONFIG_BLK_DEV_IDEPCI $CONFIG_BLK_DEV_IDEDMA_PMAC
 	 fi
       fi
+      if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
+	 bool '  SWARM onboard IDE support' CONFIG_BLK_DEV_IDE_SWARM
+      fi
       if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
 	 dep_bool '    ICS IDE interface support' CONFIG_BLK_DEV_IDE_ICSIDE $CONFIG_ARCH_ACORN
 	 dep_bool '      ICS DMA support' CONFIG_BLK_DEV_IDEDMA_ICS $CONFIG_BLK_DEV_IDE_ICSIDE

[Linux-mips-commits]CVS: linux/drivers/char sb1250_duart.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv13243/drivers/char

Modified Files:
	sb1250_duart.c 
Log Message:
Swarm IDE support.

Index: sb1250_duart.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/sb1250_duart.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- sb1250_duart.c	2001/12/02 19:05:31	1.3
+++ sb1250_duart.c	2002/01/28 20:48:47	1.4
@@ -58,34 +58,6 @@
 #define DEFAULT_CFLAGS          (CS8 | B115200)
 
 
-#ifdef FORCED_INPUT
-static struct timer_list inp_timer;
-static unsigned char inp_cmds[] =
-"";
-"foo\n";
-"export LD_DEBUG=all\nfoo\n";
-
-static unsigned char *next_inp;
-struct tty_struct *stuff_char_tty;
-
-
-static void stuff_char(unsigned long arg) 
-{
-	int was_newline = 0;
-	tty_insert_flip_char(stuff_char_tty, *next_inp, 0);
-	tty_flip_buffer_push(stuff_char_tty);
-	if (*next_inp == '\n') {
-		was_newline = 1;
-	}
-	next_inp++;
-	del_timer(&inp_timer);
-	if (*next_inp) {
-		inp_timer.expires = jiffies + (was_newline?20:2);
-		add_timer(&inp_timer);
-	}
-}
-#endif
-
 /*
   Still not sure what the termios structures set up here are for, 
    but we have to supply pointers to them to register the tty driver
@@ -222,7 +194,8 @@
 			us->outp_count--;
 		} while ((get_status_reg(line) & M_DUART_TX_RDY) && us->outp_count);
 
-		if ((us->flags & SD_WRITE_WAKE) && (us->outp_count < (CONFIG_SB1250_DUART_OUTPUT_BUF_SIZE/2))) {
+		if (us->open && (us->flags & SD_WRITE_WAKE) &&
+		    (us->outp_count < (CONFIG_SB1250_DUART_OUTPUT_BUF_SIZE/2))) {
 			/* We told the discipline at one point that we had no space, so it went
 			   to sleep.  Wake it up when we hit half empty */
 			wake_up_interruptible(&us->tty->write_wait);
@@ -370,10 +343,10 @@
 	duart_mask_ints(line, M_DUART_IMR_TX);
 	spin_lock_irqsave(&us->outp_lock, flags);
 	us->outp_head = us->outp_tail = us->outp_count = 0;
-	spin_unlock_irqrestore(&us->outp_lock, flags);
 	if (us->flags & SD_WRITE_WAKE) {
 		wake_up_interruptible(&us->tty->write_wait);
 	}	
+	spin_unlock_irqrestore(&us->outp_lock, flags);
 }
 
 
@@ -683,7 +656,7 @@
 	sb1250_duart_driver.table            = duart_table;
 	sb1250_duart_driver.termios          = duart_termios;
 	sb1250_duart_driver.termios_locked   = duart_termios_locked;
-	
+
 	sb1250_duart_driver.open             = duart_open;
 	sb1250_duart_driver.close            = duart_close;
 	sb1250_duart_driver.write            = duart_write;
@@ -696,16 +669,22 @@
 	sb1250_duart_driver.stop             = duart_stop;
 	sb1250_duart_driver.start            = duart_start;
 	sb1250_duart_driver.wait_until_sent  = duart_wait_until_sent;
-	
-	sb1250_duart_callout_driver                = sb1250_duart_driver;
+
+	sb1250_duart_callout_driver          = sb1250_duart_driver;
+#ifdef CONFIG_DEVFS_FS
 	sb1250_duart_callout_driver.name     = "cua/%d";
+#else
+	sb1250_duart_callout_driver.name     = "cua";
+#endif
 	sb1250_duart_callout_driver.major    = TTYAUX_MAJOR;
-	sb1250_duart_callout_driver.subtype        = SERIAL_TYPE_CALLOUT;
-	
+	sb1250_duart_callout_driver.subtype  = SERIAL_TYPE_CALLOUT;
+
+	duart_mask_ints(0, 0xf);
 	if (request_irq(K_INT_UART_0, duart_int, 0, "uart0", &uart_states[0])) {
 		panic("Couldn't get uart0 interrupt line");
 	}
 #ifndef CONFIG_SIBYTE_SB1250_DUART_NO_PORT_1
+	duart_mask_ints(1, 0xf);
 	if (request_irq(K_INT_UART_1, duart_int, 0, "uart1", &uart_states[1])) {
 		panic("Couldn't get uart1 interrupt line");
 	}
@@ -731,7 +710,7 @@
 {
 	unsigned long flags;
 	int ret;
-	
+
 	save_flags(flags);
 	cli();
 	ret = tty_unregister_driver(&sb1250_duart_callout_driver);
@@ -744,11 +723,11 @@
 	}
 	free_irq(K_INT_UART_0, &uart_states[0]);
 	free_irq(K_INT_UART_1, &uart_states[1]);
-	
+
 	/* mask lines in the scd */
 	disable_irq(K_INT_UART_0);
 	disable_irq(K_INT_UART_1);
-	
+
 	restore_flags(flags);
 }
 
@@ -809,25 +788,18 @@
 }
 
 static struct console sb1250_ser_cons = {
-        "ttyS",
-        ser_console_write,       /* write */
-        NULL,                   /* read */
-        ser_console_device,      /* device */
-        ser_console_wait_key,    /* wait_key */
-        NULL,                   /* unblank */
-        ser_console_setup,       /* setup */
-        CON_PRINTBUFFER | CON_ENABLED,
-        -1,
-        0,
-        NULL
+	name:		"ttyS",
+	write:		ser_console_write,
+	device:		ser_console_device,
+	wait_key:	ser_console_wait_key,
+	setup:		ser_console_setup,
+	flags:		CON_PRINTBUFFER,
+	index:		-1,
 };
 
 void __init sb1250_serial_console_init(void)
 {
 	register_console(&sb1250_ser_cons);
-	
-	/*JDCXXX - this should be called from console_setup...but isn't.  Why? */
-	ser_console_setup(NULL, NULL);  
 }
 
 #endif /* CONFIG_SERIAL_CONSOLE */

[Linux-mips-commits]CVS: linux/include/asm-mips/sibyte sb1250_uart.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv13243/include/asm-mips/sibyte

Modified Files:
	sb1250_uart.h 
Log Message:
Swarm IDE support.

Index: sb1250_uart.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/sibyte/sb1250_uart.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sb1250_uart.h	2001/11/08 17:28:25	1.1
+++ sb1250_uart.h	2002/01/28 20:48:47	1.2
@@ -6,7 +6,7 @@
     *  This module contains constants and macros useful for 
     *  manipulating the SB1250's UARTs
     *
-    *  SB1250 specification level:  0.2
+    *  SB1250 specification level:  01/02/2002
     *  
     *  Author:  Mitch Lichtenberg (mi...@si...)
     *  
@@ -63,7 +63,7 @@
 
 
 #define M_DUART_PARITY_TYPE_EVEN    0x00
-#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(3)
+#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
 
 #define S_DUART_PARITY_MODE          3
 #define M_DUART_PARITY_MODE         _SB_MAKEMASK(2,S_DUART_PARITY_MODE)

[Linux-mips-commits]CVS: linux/include/asm-mips64 cacheops.h,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv8552/include/asm-mips64

Added Files:
	cacheops.h 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

--- NEW FILE: cacheops.h ---
/*
 * Cache operations for the cache instruction.
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * (C) Copyright 1996, 1997 by Ralf Baechle
 */
#ifndef	__ASM_MIPS_CACHEOPS_H
#define	__ASM_MIPS_CACHEOPS_H

/*
 * Cache Operations
 */
#define Index_Invalidate_I      0x00
#define Index_Writeback_Inv_D   0x01
#define Index_Invalidate_SI     0x02
#define Index_Writeback_Inv_SD  0x03
#define Index_Load_Tag_I	0x04
#define Index_Load_Tag_D	0x05
#define Index_Load_Tag_SI	0x06
#define Index_Load_Tag_SD	0x07
#define Index_Store_Tag_I	0x08
#define Index_Store_Tag_D	0x09
#define Index_Store_Tag_SI	0x0A
#define Index_Store_Tag_SD	0x0B
#define Create_Dirty_Excl_D	0x0d
#define Create_Dirty_Excl_SD	0x0f
#define Hit_Invalidate_I	0x10
#define Hit_Invalidate_D	0x11
#define Hit_Invalidate_SI	0x12
#define Hit_Invalidate_SD	0x13
#define Fill			0x14
#define Hit_Writeback_Inv_D	0x15
					/* 0x16 is unused */
#define Hit_Writeback_Inv_SD	0x17
#define Hit_Writeback_I		0x18
#define Hit_Writeback_D		0x19
					/* 0x1a is unused */
#define Hit_Writeback_SD	0x1b
					/* 0x1c is unused */
					/* 0x1e is unused */
#define Hit_Set_Virtual_SI	0x1e
#define Hit_Set_Virtual_SD	0x1f

#endif	/* __ASM_MIPS_CACHEOPS_H */

[Linux-mips-commits]CVS: linux/arch/mips64/kernel head.S,1.2,1.3 pci-dma.c,NONE,1.1

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv8552/arch/mips64/kernel

Added Files:
	head.S pci-dma.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.


--- NEW FILE: pci-dma.c ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000  Ani Joshi <aj...@un...>
 * Copyright (C) 2000  Ralf Baechle <ra...@gn...>
 * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
 */
#include <linux/types.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>

#include <asm/io.h>
#include <asm/addrspace.h>

void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
			   dma_addr_t * dma_handle)
{
	void *ret;
	int gfp = GFP_ATOMIC;

	if (hwdev != NULL && hwdev->dma_mask != 0xffffffff)
		gfp |= GFP_DMA;
	ret = (void *) __get_free_pages(gfp, get_order(size));

	if (ret != NULL) {
		memset(ret, 0, size);
#ifdef CONFIG_NONCOHERENT_IO
		dma_cache_wback_inv((unsigned long) ret, size);
		ret = KSEG1ADDR(ret);
#endif
		*dma_handle = __pa(ret);
		return ret;
	}
	return NULL;
}

void pci_free_consistent(struct pci_dev *hwdev, size_t size,
			 void *vaddr, dma_addr_t dma_handle)
{
	free_pages((unsigned long) KSEG0ADDR(vaddr), get_order(size));
}

[Linux-mips-commits]CVS: linux/arch/mips64/sgi-ip27 ip27-init.c,1.6,1.7

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/sgi-ip27

Modified Files:
	ip27-init.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: ip27-init.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/sgi-ip27/ip27-init.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- ip27-init.c	2001/12/17 18:31:14	1.6
+++ ip27-init.c	2002/01/28 20:31:57	1.7
@@ -438,7 +438,7 @@
 	start_secondary();
 }
 
-void allowboot(void)
+__init void allowboot(void)
 {
 	int		num_cpus = 0;
 	cpuid_t		cpu, mycpuid = getcpuid();
@@ -536,6 +536,17 @@
 	init_mfhi_war();
 #endif
 	smp_num_cpus = num_cpus;
+}
+
+void __init smp_boot_cpus(void)
+{
+	extern void allowboot(void);
+
+	init_new_context(current, &init_mm);
+	current->processor = 0;
+	init_idle();
+	smp_tune_scheduling();
+	allowboot();
 }
 
 #else /* CONFIG_SMP */

[Linux-mips-commits]CVS: linux/arch/mips64/kernel Makefile,1.3,1.4 i8259.c,1.1,1.2 irq.c,1.3,1.4 smp.c,1.12,1.13 traps.c,1.11,1.12

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/kernel

Modified Files:
	Makefile i8259.c irq.c smp.c traps.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- Makefile	2002/01/02 19:12:17	1.3
+++ Makefile	2002/01/28 20:31:57	1.4
@@ -13,7 +13,7 @@
 
 O_TARGET := kernel.o
 
-export-objs = irq.o mips64_ksyms.o smp.o
+export-objs = irq.o mips64_ksyms.o pci-dma.o smp.o
 
 obj-y	:= branch.o entry.o irq.o proc.o process.o ptrace.o r4k_cache.o \
 	   r4k_fpu.o r4k_genex.o r4k_switch.o r4k_tlb.o r4k_tlb_debug.o \
@@ -27,6 +27,10 @@
 obj-$(CONFIG_MIPS32_COMPAT)	+= linux32.o scall_o32.o signal32.o ioctl32.o
 obj-$(CONFIG_BINFMT_ELF32)	+= binfmt_elf32.o
 obj-$(CONFIG_SMP)		+= smp.o
+
+ifndef CONFIG_MAPPED_PCI_IO
+obj-y				+= pci-dma.o
+endif
 
 CFLAGS_r4k_genex.o := -P
 CFLAGS_r4k_tlb_glue.o := -P

Index: i8259.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/i8259.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- i8259.c	2002/01/02 19:13:41	1.1
+++ i8259.c	2002/01/28 20:31:57	1.2
@@ -29,7 +29,7 @@
  * moves to arch independent land
  */
 
-spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
+static spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED;
 
 static void end_8259A_irq (unsigned int irq)
 {

Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/irq.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- irq.c	2002/01/02 19:12:17	1.3
+++ irq.c	2002/01/28 20:31:57	1.4
@@ -20,7 +20,6 @@
 #include <linux/mm.h>
 #include <linux/random.h>
 #include <linux/sched.h>
-#include <linux/seq_file.h>
 
 #include <asm/atomic.h>
 #include <asm/system.h>
@@ -75,31 +74,32 @@
  * Generic, controller-independent functions:
  */
 
-int show_interrupts(struct seq_file *p, void *v)
+int get_irq_list(char *buf)
 {
 	struct irqaction * action;
+	char *p = buf;
 	int i;
 
-	seq_puts(p, "           ");
+	p += sprintf(p, "           ");
 	for (i=0; i < 1 /*smp_num_cpus*/; i++)
-		seq_printf(p, "CPU%d       ", i);
-	seq_putc(p, '\n');
+		p += sprintf(p, "CPU%d       ", i);
+	*p++ = '\n';
 
 	for (i = 0 ; i < NR_IRQS ; i++) {
 		action = irq_desc[i].action;
 		if (!action) 
 			continue;
-		seq_printf(p, "%3d: ",i);
-		seq_printf(p, "%10u ", kstat_irqs(i));
-		seq_printf(p, " %14s", irq_desc[i].handler->typename);
-		seq_printf(p, "  %s", action->name);
+		p += sprintf(p, "%3d: ",i);
+		p += sprintf(p, "%10u ", kstat_irqs(i));
+		p += sprintf(p, " %14s", irq_desc[i].handler->typename);
+		p += sprintf(p, "  %s", action->name);
 
 		for (action=action->next; action; action = action->next)
-			seq_printf(p, ", %s", action->name);
-		seq_putc(p, '\n');
+			p += sprintf(p, ", %s", action->name);
+		*p++ = '\n';
 	}
-	seq_printf(p, "ERR: %10lu\n", irq_err_count);
-	return 0;
+	p += sprintf(p, "ERR: %10lu\n", irq_err_count);
+	return p - buf;
 }
 
 #ifdef CONFIG_SMP

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/smp.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- smp.c	2002/01/02 19:12:17	1.12
+++ smp.c	2002/01/28 20:31:57	1.13
@@ -7,7 +7,6 @@
  * Copyright (C) 2000, 2001 Ralf Baechle
  * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
  */
-#include <linux/cache.h>
 #include <linux/delay.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -17,6 +16,7 @@
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/sched.h>
+#include <linux/cache.h>
 
 #include <asm/atomic.h>
 #include <asm/processor.h>
@@ -27,17 +27,23 @@
 #include <asm/irq.h>
 
 /* The 'big kernel lock' */
-static spinlock_t kernel_flag = SPIN_LOCK_UNLOCKED;
+spinlock_t kernel_flag __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
 int smp_threads_ready;	/* Not used */
 atomic_t smp_commenced = ATOMIC_INIT(0);
 struct cpuinfo_mips cpu_data[NR_CPUS];
+void (*volatile smp_cpu0_finalize)(void);
+
+// static atomic_t cpus_booted = ATOMIC_INIT(0);
+atomic_t cpus_booted = ATOMIC_INIT(0);
+
 int smp_num_cpus = 1;			/* Number that came online.  */
 cpumask_t cpu_online_map;		/* Bitmask of currently online CPUs */
 int __cpu_number_map[NR_CPUS];
 int __cpu_logical_map[NR_CPUS];
 cycles_t cacheflush_time;
 
-static void smp_tune_scheduling (void)
+// static void smp_tune_scheduling (void)
+void smp_tune_scheduling (void)
 {
 }
 
@@ -59,17 +65,6 @@
 	cpu_idle();
 }
 
-void __init smp_boot_cpus(void)
-{
-	extern void allowboot(void);
-
-	init_new_context(current, &init_mm);
-	current->processor = 0;
-	init_idle();
-	smp_tune_scheduling();
-	allowboot();
-}
-
 void __init smp_commence(void)
 {
 	wmb();
@@ -151,7 +146,9 @@
 	void (*func) (void *info) = call_data->func;
 	void *info = call_data->info;
 	int wait = call_data->wait;
+	int cpu = smp_processor_id();
 
+	irq_enter(cpu, 0);	/* XXX choose an irq number? */
 	/*
 	 * Notify initiating CPU that I've grabbed the data and am
 	 * about to execute the function.
@@ -167,15 +164,18 @@
 		mb();
 		atomic_inc(&call_data->finished);
 	}
+	irq_exit(cpu, 0);	/* XXX choose an irq number? */
 }
 
 static void stop_this_cpu(void *dummy)
 {
-	/*
-	 * Remove this CPU
-	 * XXX update this from 32-bit version
-	 */
-	for (;;);
+	int cpu = smp_processor_id();
+	if (cpu)
+		for (;;);		/* XXX Use halt like i386 */
+
+	/* XXXKW this isn't quite there yet */
+	while (!smp_cpu0_finalize) ;
+	smp_cpu0_finalize();
 }
 
 void smp_send_stop(void)

Index: traps.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/kernel/traps.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- traps.c	2002/01/04 17:39:11	1.11
+++ traps.c	2002/01/28 20:31:57	1.12
@@ -565,7 +565,7 @@
 {
 	extern char except_vec0;
 	extern char except_vec1_r10k;
-	extern char except_vec2_generic;
+	extern char except_vec2_generic, except_vec2_sb1;
 	extern char except_vec3_generic, except_vec3_r4000;
 	extern char except_vec4;
 	extern void bus_error_init(void);
@@ -609,14 +609,18 @@
 	 * Handling the following exceptions depends mostly of the cpu type
 	 */
 	switch(mips_cpu.cputype) {
-	case CPU_R10000:
-		/*
-		 * The R10000 is in most aspects similar to the R4400.  It
-		 * should get some special optimizations.
-		 */
-		write_32bit_cp0_register(CP0_FRAMEMASK, 0);
-		goto r4k;
+        case CPU_SB1:
+#ifdef CONFIG_SB1_CACHE_ERROR
+		/* Special cache error handler for SB1 */
+		memcpy((void *)(KSEG0 + 0x100), &except_vec2_sb1, 0x80);
+		memcpy((void *)(KSEG1 + 0x100), &except_vec2_sb1, 0x80);
+#endif
+		/* Enable timer interrupt and scd mapped interrupt */
+		clear_cp0_status(0xf000);
+		set_cp0_status(0xc00);
+		break;
 
+	case CPU_R10000:
 	case CPU_R4000MC:
 	case CPU_R4400MC:
 	case CPU_R4000SC:
@@ -628,7 +632,6 @@
 	case CPU_R4600:
 	case CPU_R5000:
 	case CPU_NEVADA:
-r4k:
 		/* Debug TLB refill handler.  */
 		memcpy((void *)KSEG0, &except_vec0, 0x80);
 		memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80);
@@ -664,7 +667,6 @@
 		 * handlers.
 		 */
 		bus_error_init();
-
 
 		set_except_vector(8, handle_sys);
 		set_except_vector(9, handle_bp);

[Linux-mips-commits]CVS: linux/arch/mips64/mm Makefile,NONE,1.1 c-sb1.c,NONE,1.1 pg-sb1.c,NONE,1.1 tlb-sb1.c,NONE,1.1 andes.c,1.8,1.9 fault.c,1.8,1.9 loadmmu.c,1.3,1.4 r4xx0.c,1.11,1.12 sb1.c,1.1,NONE

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64/mm
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64/mm

Modified Files:
	andes.c fault.c loadmmu.c r4xx0.c 
Added Files:
	Makefile c-sb1.c pg-sb1.c tlb-sb1.c 
Removed Files:
	sb1.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

--- NEW FILE: Makefile ---
#
# Makefile for the Linux/MIPS-specific parts of the memory manager.
#

O_TARGET := mm.o

export-objs			+= umap.o
obj-y				:= extable.o init.o fault.o loadmmu.o

obj-$(CONFIG_CPU_R4300)		+= r4xx0.o
obj-$(CONFIG_CPU_R4X00)		+= r4xx0.o
obj-$(CONFIG_CPU_R5000)		+= r4xx0.o
obj-$(CONFIG_CPU_NEVADA)	+= r4xx0.o
obj-$(CONFIG_CPU_R10000)	+= andes.o
obj-$(CONFIG_CPU_SB1)		+= pg-sb1.o c-sb1.o tlb-sb1.o

obj-$(CONFIG_SGI_IP22)		+= umap.o

include $(TOPDIR)/Rules.make

--- NEW FILE: c-sb1.c ---
/*
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1997, 2001 Ralf Baechle (ra...@gn...)
 * Copyright (C) 2000, 2001 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */ 

#include <linux/init.h>
#include <asm/mmu_context.h>
#include <asm/bootinfo.h>
#include <asm/cacheops.h>
#include <asm/cpu.h>

/* These are probed at ld_mmu time */
static unsigned int icache_size;
static unsigned int dcache_size;

static unsigned int icache_line_size;
static unsigned int dcache_line_size;

static unsigned int icache_index_mask;

static unsigned int icache_assoc;
static unsigned int dcache_assoc;

static unsigned int icache_sets;
static unsigned int dcache_sets;

/*
 * The dcache is fully coherent to the system, with one
 * big caveat:  the instruction stream.  In other words,
 * if we miss in the icache, and have dirty data in the
 * L1 dcache, then we'll go out to memory (or the L2) and
 * get the not-as-recent data.
 * 
 * So the only time we have to flush the dcache is when
 * we're flushing the icache.  Since the L2 is fully
 * coherent to everything, including I/O, we never have
 * to flush it
 */

static void sb1_flush_cache_all(void)
{
}

static void local_sb1___flush_cache_all(void)
{
	/*
	 * Haven't worried too much about speed here; given that we're flushing
	 * the icache, the time to invalidate is dwarfed by the time it's going
	 * to take to refill it.  Register usage:
	 * 
	 * $1 - moving cache index
	 * $2 - set count
	 */
	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     move   $1, %2         \n" /* Start at index 0 */
		"1:   cache  %3, 0($1)      \n" /* WB/Invalidate this index */
		"     daddiu  %1, %1, -1     \n" /* Decrement loop count */
		"     bnez   %1, 1b         \n" /* loop test */
		"      addu   $1, $1, %0    \n" /* Next address */
		".set pop                   \n"
		:
		: "r" (dcache_line_size), "r" (dcache_sets * dcache_assoc),
		  "r" (KSEG0), "i" (Index_Writeback_Inv_D));

	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set mips2                 \n"
		"sync                       \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
		"sync                       \n"
#endif
		".set pop                   \n");

	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     move   $1, %2         \n" /* Start at index 0 */
		"1:   cache  %3, 0($1)       \n" /* Invalidate this index */
		"     daddiu  %1, %1, -1     \n" /* Decrement loop count */
		"     bnez   %1, 1b         \n" /* loop test */
		"      addu   $1, $1, %0    \n" /* Next address */
		".set pop                   \n"
		:
		: "r" (icache_line_size), "r" (icache_sets * icache_assoc),
		  "r" (KSEG0), "i" (Index_Invalidate_I));
}

#ifdef CONFIG_SMP
extern void sb1___flush_cache_all_ipi(void *ignored);
asm("sb1___flush_cache_all_ipi = local_sb1___flush_cache_all");

static void sb1___flush_cache_all(void)
{
	smp_call_function(sb1___flush_cache_all_ipi, 0, 1, 1);
	local_sb1___flush_cache_all();
}
#else
extern void sb1___flush_cache_all(void);
asm("sb1___flush_cache_all = local_sb1___flush_cache_all");
#endif


/*
 * When flushing a range in the icache, we have to first writeback
 * the dcache for the same range, so new ifetches will see any
 * data that was dirty in the dcache.  Also, if the flush is very
 * large, just flush the whole cache rather than spinning in here
 * forever.  Fills from the (always coherent) L2 come in relatively
 * quickly.
 *
 * Also, at the moment we just hit-writeback the dcache instead
 * of writeback-invalidating it.  Not doing the invalidates
 * doesn't cost us anything, since we're coherent 
 *
 */

static void local_sb1_flush_icache_range(unsigned long start, unsigned long end)
{
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
	unsigned long flags;
	local_irq_save(flags);
#endif

	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     move   $1, %0         \n" 
		"1:                         \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
		".align 3                   \n"
		"     lw     $0,   0($1)    \n" /* Bug 1370, 1368            */
		"     sync                  \n"
		"     cache  0x15, 0($1)    \n" /* Hit-WB-inval this address */
#else
		"     cache  0x19, 0($1)    \n" /* Hit-WB this address */
#endif
		"     bne    $1, %1, 1b     \n" /* loop test */
		"      addu  $1, $1, %2     \n" /* next line */
		".set pop                   \n"
		:
		: "r" (start  & ~(dcache_line_size - 1)),
		  "r" ((end - 1) & ~(dcache_line_size - 1)),
		  "r" (dcache_line_size));
	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set mips2                 \n"
		"sync                       \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
		"sync                       \n"
#endif
		".set pop                   \n");
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
		local_irq_restore(flags);
#endif

	/* Guess what: these Kseg0 addressese aren't enough to let us figure
	 * out what may be in the cache under mapped Useg tags.  The situation
	 * is even worse, because bit 12 belongs to both the page number AND
	 * the cache index, which means the Kseg0 page number may have a
	 * different cache index than the Useg address.  For these two reasons,
	 * we have to flush the entire thing.  Since the Dcache is physically
	 * tagged, we *can* use hit operations.
	 */
	start = 0;
	end = icache_index_mask;

	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     move   $1, %0         \n" 
		".align 3                   \n"
		"1:   cache  0, (0<<13)($1) \n" /* Index-inval this address */
		"     cache  0, (1<<13)($1) \n" /* Index-inval this address */
		"     cache  0, (2<<13)($1) \n" /* Index-inval this address */
		"     cache  0, (3<<13)($1) \n" /* Index-inval this address */
		"     bne    $1, %1, 1b     \n" /* loop test */
		"      addu  $1, $1, %2     \n" /* next line */
		".set pop                   \n"
		:
		: "r" (start & ~(icache_line_size - 1)),
		  "r" ((end - 1) & ~(dcache_line_size - 1)),
		  "r" (icache_line_size));
}

#ifdef CONFIG_SMP
struct flush_icache_range_args {
	unsigned long start;
	unsigned long end;
};

static void sb1_flush_icache_range_ipi(void *info)
{
	struct flush_icache_range_args *args = info;

	local_sb1_flush_icache_range(args->start, args->end);
}

void sb1_flush_icache_range(unsigned long start, unsigned long end)
{
	struct flush_icache_range_args args;

	args.start = start;
	args.end = end;
	smp_call_function(sb1_flush_icache_range_ipi, &args, 1, 1);
	local_sb1_flush_icache_range(start, end);
}
#else
void sb1_flush_icache_range(unsigned long start, unsigned long end);
asm("sb1_flush_icache_range = local_sb1_flush_icache_range");
#endif

/*
 * If there's no context yet, or the page isn't executable, no icache flush
 * is needed
 */
static void sb1_flush_icache_page(struct vm_area_struct *vma, struct page *page)
{
	unsigned long addr;

	if ((vma->vm_mm->context == 0) || !(vma->vm_flags & VM_EXEC)) {
		return;
	}

	addr = (unsigned long)page_address(page);
	/*
	 * XXXKW addr is a Kseg0 address, whereas hidden higher up the call
	 * stack, we may really need to flush a Useg address.  Our Icache is
	 * virtually tagged, which means we have to be super conservative.
	 *  See comments in sb1_flush_icache_rage.
	 */
	sb1_flush_icache_range(addr, addr + PAGE_SIZE);
}

static inline void protected_flush_icache_line(unsigned long addr)
{
	__asm__ __volatile__(
		"    .set push                \n"
		"    .set noreorder           \n"
		"    .set mips4               \n"
		"1:  cache 0x10, (%0)         \n"
		"2:  .set pop                 \n"
		"    .section __ex_table,\"a\"\n"
		"     .word  1b, 2b          \n"
		"     .previous"
		:
		: "r" (addr));
}

static inline void protected_writeback_dcache_line(unsigned long addr)
{
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
	/* Have to be sure the TLB entry exists for the cache op, 
	   so we have to be sure that nothing happens in between the
	   lw and the cache op 
	*/
	unsigned long flags;
	local_irq_save(flags);
#endif
	__asm__ __volatile__(
		"    .set push                \n"
		"    .set noreorder           \n"
		"    .set mips4               \n"
		"1:                           \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
		"     lw    $0,   (%0)         \n"  
		"     sync                  \n"
		"     cache  0x15, 0(%0)    \n" /* Hit-WB-inval this address */
#else
		"     cache  0x19, 0(%0)    \n" /* Hit-WB this address */
#endif
		/* XXX: should be able to do this after both dcache cache
		   ops, but there's no guarantee that this will be inlined,
		   and the pass1 restriction checker can't detect syncs
		   following cache ops except in the following basic block.
		*/
		"     sync                    \n"
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS		/* Bug 1384 */			
		"     sync                    \n"
#endif
		"2:  .set pop                 \n"
		"    .section __ex_table,\"a\"\n"
		"     .word  1b, 2b          \n"
		"     .previous"
		:
		: "r" (addr));
#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS					
	local_irq_restore(flags);
#endif
}

/*
 * XXX - Still need to really understand this.  This is mostly just
 * derived from the r10k and r4k implementations, and seems to work
 * but things that "seem to work" when I don't understand *why* they
 * "seem to work" disturb me greatly...JDC
 */
static void local_sb1_flush_cache_sigtramp(unsigned long addr)
{
	unsigned long daddr, iaddr;
	
	daddr = addr & ~(dcache_line_size - 1);
	protected_writeback_dcache_line(daddr);
	protected_writeback_dcache_line(daddr + dcache_line_size);
	iaddr = addr & ~(icache_line_size - 1);
	protected_flush_icache_line(iaddr);
	protected_flush_icache_line(iaddr + icache_line_size);
}

#ifdef CONFIG_SMP
extern void sb1_flush_cache_sigtramp_ipi(void *ignored);
asm("sb1_flush_cache_sigtramp_ipi = local_sb1_flush_cache_sigtramp");

static void sb1_flush_cache_sigtramp(unsigned long addr)
{
	smp_call_function(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
	local_sb1_flush_cache_sigtramp(addr);
}
#else
void sb1_flush_cache_sigtramp(unsigned long addr);
asm("sb1_flush_cache_sigtramp = local_sb1_flush_cache_sigtramp");
#endif

static void sb1_flush_icache_all(void)
{
	/*
	 * Haven't worried too much about speed here; given that we're flushing
	 * the icache, the time to invalidate is dwarfed by the time it's going
	 * to take to refill it.  Register usage:
	 * 
	 * $1 - moving cache index
	 * $2 - set count
	 */
	__asm__ __volatile__ (
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     move   $1, %2         \n" /* Start at index 0 */
		"1:   cache  %3, 0($1)      \n" /* Invalidate this index */
		"     daddiu  %1, %1, -1     \n" /* Decrement loop count */
		"     bnez   %1, 1b         \n" /* loop test */
		"      addu   $1, $1, %0    \n" /* Next address */
		".set pop                   \n"
		:
		: "r" (icache_line_size), "r" (icache_sets * icache_assoc),
		  "r" (KSEG0), "i" (Index_Invalidate_I));
}

/*
 * Anything that just flushes dcache state can be ignored, as we're always
 * coherent in dcache space.  This is just a dummy function that all the
 * nop'ed routines point to
 */

static void sb1_nop(void)
{
}

/*
 * This only needs to make sure stores done up to this
 * point are visible to other agents outside the CPU.  Given 
 * the coherent nature of the ZBus, all that's required here is 
 * a sync to make sure the data gets out to the caches and is
 * visible to an arbitrary A Phase from an external agent 
 *   
 * Actually, I'm not even sure that's necessary; the semantics
 * of this function aren't clear.  If it's supposed to serve as
 * a memory barrier, this is needed.  If it's only meant to 
 * prevent data from being invisible to non-cpu memory accessors
 * for some indefinite period of time (e.g. in a non-coherent 
 * dcache) then this function would be a complete nop.
 */
static void sb1_flush_page_to_ram(struct page *page)
{
	__asm__ __volatile__(
		"     sync  \n"  /* Short pipe */
		:::"memory");	
}

/*
 *  Cache set values (from the mips64 spec)
 * 0 - 64
 * 1 - 128
 * 2 - 256
 * 3 - 512
 * 4 - 1024
 * 5 - 2048
 * 6 - 4096
 * 7 - Reserved
 */
  
static unsigned int decode_cache_sets(unsigned int config_field)
{
	if (config_field == 7) {
		/* JDCXXX - Find a graceful way to abort. */
		return 0;
	} 
	return (1<<(config_field + 6));
}

/*
 *  Cache line size values (from the mips64 spec)
 * 0 - No cache present.
 * 1 - 4 bytes
 * 2 - 8 bytes
 * 3 - 16 bytes
 * 4 - 32 bytes
 * 5 - 64 bytes
 * 6 - 128 bytes
 * 7 - Reserved
 */

static unsigned int decode_cache_line_size(unsigned int config_field)
{
	if (config_field == 0) {
		return 0;
	} else if (config_field == 7) {
		/* JDCXXX - Find a graceful way to abort. */
		return 0;
	} 
	return (1<<(config_field + 1));
}

/*
 * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs)
 *
 * 24:22 Icache sets per way
 * 21:19 Icache line size
 * 18:16 Icache Associativity
 * 15:13 Dcache sets per way
 * 12:10 Dcache line size
 * 9:7   Dcache Associativity
 */

static __init void probe_cache_sizes(void)
{
	u32 config1;

	config1 = read_mips32_cp0_config1();
	icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7);
	dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7);
	icache_sets = decode_cache_sets((config1 >> 22) & 0x7);
	dcache_sets = decode_cache_sets((config1 >> 13) & 0x7);
	icache_assoc = ((config1 >> 16) & 0x7) + 1;
	dcache_assoc = ((config1 >> 7) & 0x7) + 1;
	icache_size = icache_line_size * icache_sets * icache_assoc;
	dcache_size = dcache_line_size * dcache_sets * dcache_assoc;
	icache_index_mask = (icache_sets - 1) * icache_line_size;
}

/*
 * This is called from loadmmu.c.  We have to set up all the
 * memory management function pointers, as well as initialize
 * the caches and tlbs
 */
void ld_mmu_sb1(void)
{
	probe_cache_sizes();

	_clear_page = sb1_clear_page;
	_copy_page = sb1_copy_page;

	_flush_cache_all = sb1_flush_cache_all;
	___flush_cache_all = sb1___flush_cache_all;
	_flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop;
	_flush_cache_range = (void *) sb1_nop;
	_flush_page_to_ram = sb1_flush_page_to_ram;
	_flush_icache_page = sb1_flush_icache_page;
	_flush_icache_range = sb1_flush_icache_range;

	/* None of these are needed for the sb1 */
	_flush_cache_page = (void *) sb1_nop;

	_flush_cache_sigtramp = sb1_flush_cache_sigtramp;
	_flush_icache_all = sb1_flush_icache_all;

	change_cp0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW);
	flush_cache_all();
}

--- NEW FILE: pg-sb1.c ---
/*
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1997, 2001 Ralf Baechle (ra...@gn...)
 * Copyright (C) 2000 Sibyte
 * 
 * Written by Justin Carlson (ca...@si...)
 *
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */ 
#include <linux/config.h>
#include <asm/page.h>

#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
#define SB1_PREF_LOAD_STREAMED_HINT "0"
#define SB1_PREF_STORE_STREAMED_HINT "1"
#else
#define SB1_PREF_LOAD_STREAMED_HINT "4"
#define SB1_PREF_STORE_STREAMED_HINT "5"
#endif

/* These are the functions hooked by the memory management function pointers */
void sb1_clear_page(void *page)
{
	/* JDCXXX - This should be bottlenecked by the write buffer, but these
	   things tend to be mildly unpredictable...should check this on the
	   performance model */

	/* We prefetch 4 lines ahead.  We're also "cheating" slightly here...
	   since we know we're on an SB1, we force the assembler to take 
	   64-bit operands to speed things up */
	__asm__ __volatile__(
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     daddiu     $1, %0, %2  \n"  /* Calculate the end of the page to clear */
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ",  0(%0)  \n"  /* Prefetch the first 4 lines */
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ", 32(%0)  \n"  
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ", 64(%0)  \n"  
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ", 96(%0)  \n"  
		"1:   sd        $0,  0(%0)  \n"  /* Throw out a cacheline of 0's */
		"     sd        $0,  8(%0)  \n"
		"     sd        $0, 16(%0)  \n"
		"     sd        $0, 24(%0)  \n"
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ",128(%0)  \n"  /* Prefetch 4 lines ahead     */
		"     bne       $1, %0, 1b  \n"
		"     daddiu     %0, %0, 32  \n"  /* Next cacheline (This instruction better be short piped!) */
		".set pop                   \n"
		:"=r" (page)
		:"0" (page),
		 "I" (PAGE_SIZE-32)
		:"$1","memory");

}

void sb1_copy_page(void *to, void *from)
{

	/* This should be optimized in assembly...can't use ld/sd, though,
	 * because the top 32 bits could be nuked if we took an interrupt
	 * during the routine.	And this is not a good place to be cli()'ing 
	 */

	/* The pref's used here are using "streaming" hints, which cause the
	 * copied data to be kicked out of the cache sooner.  A page copy often
	 * ends up copying a lot more data than is commonly used, so this seems
	 * to make sense in terms of reducing cache pollution, but I've no real
	 * performance data to back this up
	 */

	__asm__ __volatile__(
		".set push                  \n"
		".set noreorder             \n"
		".set noat                  \n"
		".set mips4                 \n"
		"     daddiu     $1, %0, %4  \n"  /* Calculate the end of the page to copy */
		"     pref       " SB1_PREF_LOAD_STREAMED_HINT  ",  0(%0)  \n"  /* Prefetch the first 3 lines */
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ",  0(%1)  \n"  
		"     pref       " SB1_PREF_LOAD_STREAMED_HINT  ",  32(%0) \n"
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ",  32(%1) \n"  
		"     pref       " SB1_PREF_LOAD_STREAMED_HINT  ",  64(%0) \n"
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ",  64(%1) \n"  
		"1:   lw        $2,  0(%0)  \n"  /* Block copy a cacheline */
		"     lw        $3,  4(%0)  \n"
		"     lw        $4,  8(%0)  \n"
		"     lw        $5, 12(%0)  \n"
		"     lw        $6, 16(%0)  \n"
		"     lw        $7, 20(%0)  \n"
		"     lw        $8, 24(%0)  \n"
		"     lw        $9, 28(%0)  \n"
		"     pref       " SB1_PREF_LOAD_STREAMED_HINT  ", 96(%0)  \n"  /* Prefetch ahead         */
		"     pref       " SB1_PREF_STORE_STREAMED_HINT ", 96(%1)  \n"
		"     sw        $2,  0(%1)  \n"  
		"     sw        $3,  4(%1)  \n"
		"     sw        $4,  8(%1)  \n"
		"     sw        $5, 12(%1)  \n"
		"     sw        $6, 16(%1)  \n"
		"     sw        $7, 20(%1)  \n"
		"     sw        $8, 24(%1)  \n"
		"     sw        $9, 28(%1)  \n"		
		"     daddiu     %1, %1, 32  \n"  /* Next cacheline */
		"     nop                   \n"  /* Force next add to short pipe */
		"     nop                   \n"  /* Force next add to short pipe */
		"     bne       $1, %0, 1b  \n"
		"     daddiu     %0, %0, 32  \n"  /* Next cacheline */
		".set pop                   \n" 
		:"=r" (to),
		"=r" (from)
		:
		"0" (from),
		"1" (to),
		"I" (PAGE_SIZE-32)
		:"$1","$2","$3","$4","$5","$6","$7","$8","$9","memory");
/*
	unsigned long *src = from;
	unsigned long *dest = to;
	unsigned long *target = (unsigned long *) (((unsigned long)src) + PAGE_SIZE);
	while (src != target) {
		*dest++ = *src++;
	}
*/
}

--- NEW FILE: tlb-sb1.c ---
/*
 * Copyright (C) 1996 David S. Miller (dm...@en...)
 * Copyright (C) 1997, 2001 Ralf Baechle (ra...@gn...)
 * Copyright (C) 2000, 2001 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */ 
#include <asm/mmu_context.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>

/* Dump the current entry* and pagemask registers */
static inline void dump_cur_tlb_regs(void)
{
	unsigned int entryhihi, entryhilo, entrylo0hi, entrylo0lo, entrylo1hi;
	unsigned int entrylo1lo, pagemask;

	__asm__ __volatile__ (
		".set push             \n"
		".set noreorder        \n"
		"#.set mips64           \n"
		".set mips4            \n"
		".set noat             \n"
		"     tlbr             \n"
		"     dmfc0  $1, $10   \n"
		"     dsrl32 %0, $1, 0 \n"
		"     sra    %1, $1, 0 \n"
		"     dmfc0  $1, $2    \n"
		"     dsrl32 %2, $1, 0 \n"
		"     sra    %3, $1, 0 \n"
		"     dmfc0  $1, $3    \n"
		"     dsrl32 %4, $1, 0 \n"
		"     sra    %5, $1, 0 \n"
		"     mfc0   %6, $5    \n"
		".set pop              \n"
		: "=r" (entryhihi),
		"=r" (entryhilo),
		"=r" (entrylo0hi),
		"=r" (entrylo0lo),
		"=r" (entrylo1hi),
		"=r" (entrylo1lo),
		"=r" (pagemask));
	printk("%08X%08X %08X%08X %08X%08X %08X",
	       entryhihi, entryhilo,
	       entrylo0hi, entrylo0lo,
	       entrylo1hi, entrylo1lo,
	       pagemask);
}

void sb1_dump_tlb(void)
{
	int entry;
	printk("Current TLB registers state:\n"
	       "      EntryHi       EntryLo0          EntryLo1     PageMask  Index\n"
	       "--------------------------------------------------------------------\n");
	dump_cur_tlb_regs();
	printk(" %08X\n", read_32bit_cp0_register(CP0_INDEX));
	printk("\n\nFull TLB Dump:"
	       "Idx      EntryHi       EntryLo0          EntryLo1     PageMask\n"
	       "--------------------------------------------------------------\n");
	for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
		set_index(entry);
		printk("\n%02i ", entry);
		__asm__ __volatile__ (
			".set push             \n"
			"#.set mips64           \n"
			".set mips4           \n"
			"     tlbr             \n"
			".set pop              \n");
		dump_cur_tlb_regs();
	}
	printk("\n");
}

void local_flush_tlb_all(void)
{
	unsigned long flags;
	unsigned long old_ctx;
	int entry;

	__save_and_cli(flags);
	/* Save old context and create impossible VPN2 value */
	old_ctx = (get_entryhi() & 0xff);
	set_entrylo0(0);
	set_entrylo1(0);
	for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
		set_entryhi(KSEG0 + (PAGE_SIZE << 1) * entry);
		set_index(entry);
		tlb_write_indexed();
	}
	set_entryhi(old_ctx);
	__restore_flags(flags);	
}


/*
 * Use a bogus region of memory (starting at 0) to sanitize the TLB's.  
 * Use increments of the maximum page size (16MB), and check for duplicate
 * entries before doing a given write.  Then, when we're safe from collisions
 * with the firmware, go back and give all the entries invalid addresses with
 * the normal flush routine.
 */
void sb1_sanitize_tlb(void)
{
	int entry;
	long addr = 0;

	long inc = 1<<24;  /* 16MB */
	/* Save old context and create impossible VPN2 value */
	set_entrylo0(0);
	set_entrylo1(0);
	for (entry = 0; entry < mips_cpu.tlbsize; entry++) {
		do {
			addr += inc;
			set_entryhi(addr);
			tlb_probe();
		} while ((int)(get_index()) >= 0);
		set_index(entry);
		tlb_write_indexed();
	}
	/* Now that we know we're safe from collisions, we can safely flush
	   the TLB with the "normal" routine. */
	local_flush_tlb_all();
}


void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
                      unsigned long end)
{
	unsigned long flags;
	int cpu;

	__save_and_cli(flags);
	cpu = smp_processor_id();
	if(CPU_CONTEXT(cpu, mm) != 0) {
		int size;
		size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
		size = (size + 1) >> 1;
		if(size <= (mips_cpu.tlbsize/2)) {
			int oldpid = (get_entryhi() & 0xff);
			int newpid = (CPU_CONTEXT(cpu, mm) & 0xff);

			start &= (PAGE_MASK << 1);
			end += ((PAGE_SIZE << 1) - 1);
			end &= (PAGE_MASK << 1);
			while(start < end) {
				int idx;

				set_entryhi(start | newpid);
				start += (PAGE_SIZE << 1);
				tlb_probe();
				idx = get_index();
				set_entrylo0(0);
				set_entrylo1(0);
				set_entryhi(KSEG0 + (idx << (PAGE_SHIFT+1)));
				if(idx < 0)
					continue;
				tlb_write_indexed();
			}
			set_entryhi(oldpid);
		} else {
			get_new_mmu_context(mm, cpu);
			if (mm == current->active_mm)
				set_entryhi(CPU_CONTEXT(cpu, mm) & 0xff);
		}
	}
	__restore_flags(flags);
}

void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
{
	unsigned long flags;

#ifdef CONFIG_SMP
	/*
	 * This variable is eliminated from CPU_CONTEXT() if SMP isn't defined,
	 * so conditional it to get rid of silly "unused variable" compiler
	 * complaints
	 */
	int cpu = smp_processor_id();
#endif

	__save_and_cli(flags);
	if (CPU_CONTEXT(cpu, vma->vm_mm) != 0) {
		int oldpid, newpid, idx;
#ifdef DEBUG_TLB
		printk("[tlbpage<%d,%08lx>]", CPU_CONTEXT(cpu, vma->vm_mm), page);
#endif
		newpid = (CPU_CONTEXT(cpu, vma->vm_mm) & 0xff);
		page &= (PAGE_MASK << 1);
		oldpid = (get_entryhi() & 0xff);
		set_entryhi	(page | newpid);
		tlb_probe();
		idx = get_index();
		set_entrylo0(0);
		set_entrylo1(0);
		if(idx < 0)
			goto finish;
		/* Make sure all entries differ. */  
		set_entryhi(KSEG0+(idx<<(PAGE_SHIFT+1)));
		tlb_write_indexed();
	finish:
		set_entryhi(oldpid);
	}
	__restore_flags(flags);
}


/* All entries common to a mm share an asid.  To effectively flush
   these entries, we just bump the asid. */
void local_flush_tlb_mm(struct mm_struct *mm)
{
	unsigned long flags;
	int cpu;
	__save_and_cli(flags);
	cpu = smp_processor_id();
	if (CPU_CONTEXT(cpu, mm) != 0) {
		get_new_mmu_context(mm, smp_processor_id());
		if (mm == current->active_mm) {
			set_entryhi(CPU_CONTEXT(cpu, mm) & 0xff);
		}
	}
	__restore_flags(flags);
}

/* Stolen from mips32 routines */

void sb1_update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
                      pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;

	/*
	 * Handle debugger faulting in for debugee.
	 */
	if (current->active_mm != vma->vm_mm)
		return;

	__save_and_cli(flags);


	pid = get_entryhi() & 0xff;

#ifdef DEBUG_TLB
	if((pid != (CPU_CONTEXT(cpu, vma->vm_mm) & 0xff)) || (CPU_CONTEXT(cpu, vma->vm_mm) == 0)) {
		printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n",
		       (int) (CPU_CONTEXT(cpu, vma->vm_mm) & 0xff), pid);
	}
#endif

	address &= (PAGE_MASK << 1);
	set_entryhi(address | (pid));
	pgdp = pgd_offset(vma->vm_mm, address);
	tlb_probe();
	pmdp = pmd_offset(pgdp, address);
	idx = get_index();
	ptep = pte_offset(pmdp, address);
	set_entrylo0(pte_val(*ptep++) >> 6);
	set_entrylo1(pte_val(*ptep) >> 6);
	set_entryhi(address | (pid));
	if(idx < 0) {
		tlb_write_random();
	} else {
		tlb_write_indexed();
	}
	set_entryhi(pid);
	__restore_flags(flags);
}

/*
 * This is called from loadmmu.c.  We have to set up all the
 * memory management function pointers, as well as initialize
 * the caches and tlbs
 */
void sb1_tlb_init(void)
{
	u32 config1;

	config1 = read_mips32_cp0_config1();
	mips_cpu.tlbsize = ((config1 >> 25) & 0x3f) + 1;

	/*
	 * We don't know what state the firmware left the TLB's in, so this is
	 * the ultra-conservative way to flush the TLB's and avoid machine
	 * check exceptions due to duplicate TLB entries 
	 */
	sb1_sanitize_tlb();
	_update_mmu_cache = sb1_update_mmu_cache;
}

Index: andes.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/andes.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- andes.c	2001/11/20 17:57:32	1.8
+++ andes.c	2002/01/28 20:31:57	1.9
@@ -358,7 +358,7 @@
 			while(1);
 	}
     
-	update_mmu_cache = andes_update_mmu_cache;
+	_update_mmu_cache = andes_update_mmu_cache;
 
 	_show_regs = andes_show_regs;
 
@@ -372,9 +372,10 @@
 	 *     be set for 4kb pages.
 	 */
 	write_32bit_cp0_register(CP0_PAGEMASK, PM_4K);
+	write_32bit_cp0_register(CP0_FRAMEMASK, 0);
 
         /* From this point on the ARC firmware is dead.  */
 	local_flush_tlb_all();
 
-        /* Did I tell you that ARC SUCKS?  */
+	/* Did I tell you that ARC SUCKS?  */
 }

Index: fault.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/fault.c,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- fault.c	2001/12/07 19:28:38	1.8
+++ fault.c	2002/01/28 20:31:57	1.9
@@ -115,7 +115,7 @@
 	 * only copy the information from the master page table,
 	 * nothing more.
 	 */
-	if (address >= TASK_SIZE)
+	if (address >= VMALLOC_START)
 		goto vmalloc_fault;
 
 	info.si_code = SEGV_MAPERR;

Index: loadmmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/loadmmu.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- loadmmu.c	2001/11/26 17:17:26	1.3
+++ loadmmu.c	2002/01/28 20:31:57	1.4
@@ -24,14 +24,19 @@
 void (*_copy_page)(void * to, void * from);
 
 /* Cache operations. */
+void (*_flush_cache_all)(void);
+void (*___flush_cache_all)(void);
 void (*_flush_cache_mm)(struct mm_struct *mm);
 void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
                            unsigned long end);
 void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+void (*_flush_cache_sigtramp)(unsigned long addr);
+void (*_flush_icache_range)(unsigned long start, unsigned long end);
+void (*_flush_icache_page)(struct vm_area_struct *vma, struct page *page);
 void (*_flush_page_to_ram)(struct page * page);
+void (*_flush_icache_all)(void);
 
 /* MIPS specific cache operations */
-void (*_flush_cache_sigtramp)(unsigned long addr);
 void (*_flush_cache_l2)(void);
 void (*_flush_cache_l1)(void);
 
@@ -42,8 +47,8 @@
 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 
 /* Miscellaneous. */
-void (*update_mmu_cache)(struct vm_area_struct * vma,
-			 unsigned long address, pte_t pte);
+void (*_update_mmu_cache)(struct vm_area_struct * vma,
+	unsigned long address, pte_t pte);
 
 void (*_show_regs)(struct pt_regs *);
 

Index: r4xx0.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/mm/r4xx0.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- r4xx0.c	2001/11/30 18:34:10	1.11
+++ r4xx0.c	2002/01/28 20:31:57	1.12
@@ -2388,7 +2388,7 @@
 
 	_flush_cache_l2 = r4k_flush_cache_l2;
 
-	update_mmu_cache = r4k_update_mmu_cache;
+	_update_mmu_cache = r4k_update_mmu_cache;
 
 	_show_regs = r4k_show_regs;
 

--- sb1.c DELETED ---

[Linux-mips-commits]CVS: linux/arch/mips64 Makefile,1.7,1.8 config.in,1.12,1.13 defconfig,1.13,1.14

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips64
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips64

Modified Files:
	Makefile config.in defconfig 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/Makefile,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- Makefile	2002/01/02 19:12:17	1.7
+++ Makefile	2002/01/28 20:31:57	1.8
@@ -46,28 +46,25 @@
 # CPU-dependent compiler/assembler options for optimization.
 #
 ifdef CONFIG_CPU_R4300
-CFLAGS		:= $(CFLAGS) -mcpu=r4300 -mips3
+CFLAGS		+= -mcpu=r4300 -mips3
 endif
 ifdef CONFIG_CPU_R4X00
-CFLAGS		:= $(CFLAGS) -mcpu=r4600 -mips3
+CFLAGS		+= -mcpu=r4600 -mips3
 endif
 ifdef CONFIG_CPU_R5000
-CFLAGS		:= $(CFLAGS) -mcpu=r8000 -mips4
+CFLAGS		+= -mcpu=r8000 -mips4
 endif
 ifdef CONFIG_CPU_NEVADA
-CFLAGS		:= $(CFLAGS) -mcpu=r8000 -mips3 -mmad
+CFLAGS		+= -mcpu=r8000 -mips3 -mmad
 endif
 ifdef CONFIG_CPU_R8000
-CFLAGS		:= $(CFLAGS) -mcpu=r8000 -mips4
+CFLAGS		+= -mcpu=r8000 -mips4
 endif
 ifdef CONFIG_CPU_R10000
-CFLAGS		:= $(CFLAGS) -mcpu=r8000 -mips4
+CFLAGS		+= -mcpu=r8000 -mips4
 endif
 ifdef CONFIG_CPU_SB1
-GCCFLAGS	+= -mcpu=sb1 -mips2 -Wa,--trap
-ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
-MODFLAGS	+= -msb1-pass1-workarounds
-endif
+CFLAGS		+= -mcpu=r8000 -mips4
 endif
 
 ifdef CONFIG_MIPS_FPU_EMULATOR
@@ -127,6 +124,31 @@
 # 16kb aligned or the handling of the current variable will break.
 #
 LOADADDR	+= 0x80002000
+endif
+
+#
+# Sibyte SB1250 SOC
+#
+ifdef CONFIG_SIBYTE_SB1250
+# This is a LIB so that it links at the end, and initcalls are later
+# the sequence; but it is built as an object so that modules don't get
+# removed (as happens, even if they have __initcall/module_init)
+LIBS          += arch/mips/sibyte/sb1250/sb1250.o
+SUBDIRS       += arch/mips/sibyte/sb1250 
+endif
+
+#
+# Sibyte SWARM board
+#
+ifdef CONFIG_SB1_CACHE_ERROR
+LIBS          += arch/mips/sibyte/sb1/sb1kern.a
+SUBDIRS       += arch/mips/sibyte/sb1
+endif
+
+ifdef CONFIG_SIBYTE_SWARM
+LIBS          += arch/mips/sibyte/swarm/sbswarm.a
+SUBDIRS       += arch/mips/sibyte/swarm
+LOADADDR      += 0x80100000
 endif
 
 #

Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/config.in,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- config.in	2002/01/02 19:12:17	1.12
+++ config.in	2002/01/28 20:31:57	1.13
@@ -24,6 +24,20 @@
    bool '  Support for SGI-IP32 (O2)' CONFIG_SGI_IP32
 fi
 bool '  Support for SiByte SWARM board' CONFIG_SIBYTE_SWARM
+   if [ "$CONFIG_SIBYTE_SB1250" = "y" ]; then
+      bool '  Support for SB1250 onchip PCI controller' CONFIG_PCI
+      bool '  Support for SB1250 profiling - SB1/SCD perf counters' CONFIG_SIBYTE_SB1250_PROF
+      bool '  Support for BCM1250 profiling using trace buffer' CONFIG_BCM1250_TBPROF
+   bool '  Remote debugging (kgdb over UART 1)' CONFIG_REMOTE_DEBUG
+   bool '  Support for SiByte SWARM board' CONFIG_SIBYTE_SWARM
+   if [ "$CONFIG_SIBYTE_SWARM" = "y" ]; then
+      bool '    Running under simulation' CONFIG_SIMULATION
+      bool '    Configure for L3proc Demo' CONFIG_L3DEMO
+      int '      Maximum memory chunks' CONFIG_SIBYTE_SWARM_MAX_MEM_REGIONS 16
+      bool '      Multi-Processing support' CONFIG_SMP
+   fi
+fi
+
 
 if [ "$CONFIG_SGI_IP27" = "y" ]; then
    bool '  IP27 N-Mode' CONFIG_SGI_SN0_N_MODE
@@ -92,7 +106,7 @@
    define_bool CONFIG_PC_KEYB y
    define_bool CONFIG_PCI y
    #define_bool CONFIG_BOARD_SCACHE y
-   define_bool CONFIG_MAPPED_PCI_IO y
+   define_bool CONFIG_MAPPED_PCI_IO n
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_ARC_MEMORY y
    define_int CONFIG_L1_CACHE_SHIFT 5
@@ -132,6 +146,12 @@
 	 R10000 CONFIG_CPU_R10000		\
 	 SB1   CONFIG_CPU_SB1" R4x00
 endmenu
+
+if [ "$CONFIG_CPU_SB1" = "y" ]; then
+   bool '  Workarounds for pass 1 sb1 bugs' CONFIG_SB1_PASS_1_WORKAROUNDS
+   bool '  Support for SB1 Cache Error handler' CONFIG_SB1_CACHE_ERROR
+   define_bool CONFIG_VTAG_ICACHE y
+fi
 
 define_bool CONFIG_CPU_HAS_LLSC y
 define_bool CONFIG_CPU_HAS_LLDSCD y

Index: defconfig
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips64/defconfig,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- defconfig	2001/12/05 19:49:28	1.13
+++ defconfig	2002/01/28 20:31:57	1.14
@@ -1,6 +1,8 @@
 #
 # Automatically generated make config: don't edit
 #
+CONFIG_MIPS=y
+CONFIG_MIPS64=y
 
 #
 # Code maturity level options
@@ -110,8 +112,6 @@
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-CONFIG_NETLINK=y
-CONFIG_RTNETLINK=y
 CONFIG_NETLINK_DEV=y
 # CONFIG_NETFILTER is not set
 # CONFIG_FILTER is not set

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/swarm cfe_api.c,1.1,1.2 cfe_api.h,1.1,1.2 smp.c,1.4,1.5 time.c,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/sibyte/swarm

Modified Files:
	cfe_api.c cfe_api.h smp.c time.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: cfe_api.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/cfe_api.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- cfe_api.c	2001/11/08 17:42:08	1.1
+++ cfe_api.c	2002/01/28 20:31:57	1.2
@@ -253,7 +253,7 @@
 	return xiocb.xiocb_status;
 }
 
-int cfe_enummem(long idx, unsigned long *addr, unsigned long *size, long *type)
+int cfe_enummem(long idx, unsigned long long *addr, unsigned long long *size, long *type)
 {
 	cfe_xiocb_t xiocb;
 	xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
@@ -369,8 +369,18 @@
 
 void cfe_console_print(char *str)
 {
+	int len = strlen(str);
+	int res;
+
 	if (cfe_console_handle != -1) {
 		cfe_write(cfe_console_handle, str, strlen(str));
+		do {
+			res = cfe_writeblk(cfe_console_handle, 0, str, len);
+			if (res < 0)
+				break;
+			str += res;
+			len -= res;
+		} while (len);
 	}
 }
 

Index: cfe_api.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/cfe_api.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- cfe_api.h	2001/11/08 17:42:08	1.1
+++ cfe_api.h	2002/01/28 20:31:57	1.2
@@ -46,7 +46,7 @@
 int cfe_ioctl(int handle,unsigned int ioctlnum,unsigned char *buffer,int length,int *retlen);
 int cfe_inpstat(int handle);
 int cfe_enumenv(int idx,char *name,int namelen,char *val,int vallen);
-int cfe_enummem(long idx, unsigned long *addr, unsigned long *size, long *type);
+int cfe_enummem(long idx, unsigned long long *addr, unsigned long long *size, long *type);
 int cfe_setenv(char *name,char *val);
 int cfe_getenv(char *name,char *dest,int destlen);
 long long cfe_getticks(void);

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/smp.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- smp.c	2001/12/17 18:48:28	1.4
+++ smp.c	2002/01/28 20:31:57	1.5
@@ -18,14 +18,19 @@
 
 #include <linux/config.h>
 #include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm/sibyte/sb1250.h>
 #include <asm/sibyte/sb1250_regs.h>
 #include <asm/sibyte/sb1250_int.h>
 #include <asm/mipsregs.h>
+#include <asm/mmu_context.h>
+
 #include "cfe_xiocb.h"
 #include "cfe_api.h"
 
-
-
 extern void asmlinkage smp_bootstrap(void);
 
 /* Boot all other cpus in the system, initialize them, and
@@ -68,4 +73,79 @@
 void prom_smp_finish(void)
 {
 	sb1250_smp_finish();
+}
+
+/*
+ * XXX This is really halfway portable code and halfway system specific code.
+ */
+extern atomic_t cpus_booted;
+
+void __init smp_boot_cpus(void)
+{
+	int i;
+
+	smp_num_cpus = prom_setup_smp();
+	init_new_context(current, &init_mm);
+	current->processor = 0;
+	cpu_data[0].udelay_val = loops_per_jiffy;
+	cpu_data[0].asid_cache = ASID_FIRST_VERSION;
+	CPUMASK_CLRALL(cpu_online_map);
+	CPUMASK_SETB(cpu_online_map, 0);
+	atomic_set(&cpus_booted, 1);  /* Master CPU is already booted... */
+	init_idle();
+	for (i = 1; i < smp_num_cpus; i++) {
+		struct task_struct *p;
+		struct pt_regs regs;
+		printk("Starting CPU %d... ", i);
+
+		/* Spawn a new process normally.  Grab a pointer to
+		   its task struct so we can mess with it */
+		do_fork(CLONE_VM|CLONE_PID, 0, &regs, 0);
+		p = init_task.prev_task;
+
+		/* Schedule the first task manually */
+		p->processor = i;
+		p->cpus_runnable = 1 << i; /* we schedule the first task manually */
+
+		/* Attach to the address space of init_task. */
+		atomic_inc(&init_mm.mm_count);
+		p->active_mm = &init_mm;
+		init_tasks[i] = p;
+
+		del_from_runqueue(p);
+		unhash_process(p);
+
+		prom_boot_secondary(i,
+				    (unsigned long)p + KERNEL_STACK_SIZE - 32,
+				    (unsigned long)p);
+
+#if 0
+		/* This is copied from the ip-27 code in the mips64 tree */
+
+		struct task_struct *p;
+
+		/*
+		 * The following code is purely to make sure
+		 * Linux can schedule processes on this slave.
+		 */
+		kernel_thread(0, NULL, CLONE_PID);
+		p = init_task.prev_task;
+		sprintf(p->comm, "%s%d", "Idle", i);
+		init_tasks[i] = p;
+		p->processor = i;
+		p->cpus_runnable = 1 << i; /* we schedule the first task manually */
+		del_from_runqueue(p);
+		unhash_process(p);
+		/* Attach to the address space of init_task. */
+		atomic_inc(&init_mm.mm_count);
+		p->active_mm = &init_mm;
+		prom_boot_secondary(i, 
+				    (unsigned long)p + KERNEL_STACK_SIZE - 32,
+				    (unsigned long)p);
+#endif
+	}
+
+	/* Wait for everyone to come up */
+	while (atomic_read(&cpus_booted) != smp_num_cpus);
+	smp_threads_ready = 1;
 }

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/swarm/time.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- time.c	2001/11/08 17:42:08	1.1
+++ time.c	2002/01/28 20:31:57	1.2
@@ -22,8 +22,6 @@
  * track of here is what time of day we think it is.  And we don't
  * really even do a good job of that...
  */
-
-
 #include <linux/init.h>
 #include <linux/time.h>
 #include <linux/sched.h>
@@ -36,9 +34,6 @@
 #include <asm/sibyte/sb1250_regs.h>
 #include <asm/sibyte/sb1250_smbus.h>
 
-static unsigned long long sec_bias = 0;
-static unsigned int usec_bias = 0;
-
 extern rwlock_t xtime_lock;
 
 /* Xicor 1241 definitions */
@@ -219,7 +214,7 @@
 /*
  *  Bring up the timer at 100 Hz.  
  */
-void __init time_init(void)
+void __init swarm_time_init(void)
 {
 	unsigned int flags;
 	int status;
@@ -243,26 +238,4 @@
 		xtime.tv_usec = 0;
 		write_unlock_irqrestore(&xtime_lock, flags);
 	}
-}
-
-void do_settimeofday(struct timeval *tv)
-{
-	unsigned long saved_jiffies;
-	unsigned long flags;
-	saved_jiffies = jiffies;
-	write_lock_irqsave(&xtime_lock, flags);
-	sec_bias = (saved_jiffies/HZ) - tv->tv_sec;
-	usec_bias = ((saved_jiffies%HZ)*(1000000/HZ)) - tv->tv_usec;
-	write_unlock_irqrestore(&xtime_lock, flags);
-}
-
-void do_gettimeofday(struct timeval *tv)
-{
-	unsigned long saved_jiffies;
-	unsigned long flags;
-	saved_jiffies = jiffies;
-	read_lock_irqsave(&xtime_lock, flags);
-	tv->tv_sec = sec_bias + (saved_jiffies/HZ);
-	tv->tv_usec = usec_bias + ((saved_jiffies%HZ) * (1000000/HZ));
-	read_unlock_irqrestore(&xtime_lock, flags);
 }

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1 cache_error.c,NONE,1.1 Makefile,1.2,1.3 cache_err_handler.S,1.2,1.3

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/sibyte/sb1

Modified Files:
	Makefile cache_err_handler.S 
Added Files:
	cache_error.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

--- NEW FILE: cache_error.c ---
/*
 * Copyright (C) 2001 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#include <linux/kernel.h>
#include <asm/mipsregs.h>

/* SB1 definitions */
#define CP0_ERRCTL_RECOVERABLE (1 << 31)
#define CP0_ERRCTL_DCACHE      (1 << 30)
#define CP0_ERRCTL_ICACHE      (1 << 29)
#define CP0_ERRCTL_MULTIBUS    (1 << 23)
#define CP0_ERRCTL_MC_TLB      (1 << 15)
#define CP0_ERRCTL_MC_TIMEOUT  (1 << 14)

#define CP0_CERRI_TAG_PARITY   (1 << 29)
#define CP0_CERRI_DATA_PARITY  (1 << 28)
#define CP0_CERRI_EXTERNAL     (1 << 26)
#define CP0_CERRI_CACHE_IDX    (0xff << 5)

#define CP0_CERRD_MULTIPLE     (1 << 31)
#define CP0_CERRD_TAG_STATE    (1 << 30)
#define CP0_CERRD_TAG_ADDRESS  (1 << 29)
#define CP0_CERRD_DATA_SBE     (1 << 28)
#define CP0_CERRD_DATA_DBE     (1 << 27)
#define CP0_CERRD_EXTERNAL     (1 << 26)
#define CP0_CERRD_LOAD         (1 << 25)
#define CP0_CERRD_STORE        (1 << 24)
#define CP0_CERRD_FILLWB       (1 << 23)
#define CP0_CERRD_COHERENCY    (1 << 22)
#define CP0_CERRD_DUPTAG       (1 << 21)
#define CP0_CERRD_CACHE_IDX    (0xff << 5)

asmlinkage void sb1_cache_error(void)
{
	unsigned int errctl, cerr_i, cerr_d, cerr_dpa;
	unsigned int eepc;

	eepc = read_32bit_cp0_register(CP0_ERROREPC);
	__asm__ __volatile__ (
		".set push\n"
		"#.set mips64\n"
		".set mips4\n"
		".word 0x4001D000; move %0, $1; # mfc0 %0, $26, 0\n"
		".word 0x4001D800; move %1, $1; # mfc0 %1, $27, 0\n"
		".word 0x4001D801; move %2, $1; # mfc0 %2, $27, 1\n"
		".word 0x4001D803; move %3, $1; # mfc0 %3, $27, 3\n"
		".set pop\n"
		: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), "=r" (cerr_dpa));

	printk("Cache error exception:\n");
	printk(" cp0_errorepc == %08x\n", eepc);
	printk(" cp0_errctl   == %08x\n", errctl);
	if (errctl & CP0_ERRCTL_DCACHE) {
		printk(" cp0_cerr_d   == %08x\n", cerr_d);
		printk(" cp0_cerr_dpa == %08x\n", cerr_dpa);
	}
	if (errctl & CP0_ERRCTL_ICACHE) {
		printk(" cp0_cerr_i   == %08x\n", cerr_i);
	}

	panic("Can't handle the cache error!");
}

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/Makefile,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- Makefile	2001/11/29 17:18:37	1.2
+++ Makefile	2002/01/28 20:31:57	1.3
@@ -5,6 +5,6 @@
 
 L_TARGET = sb1kern.a
 
-obj-$(CONFIG_SB1_CACHE_ERROR) += cache_err_handler.o 
+obj-$(CONFIG_SB1_CACHE_ERROR) += cache_err_handler.o cache_error.o
 
 include $(TOPDIR)/Rules.make

Index: cache_err_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1/cache_err_handler.S,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- cache_err_handler.S	2002/01/04 18:04:53	1.2
+++ cache_err_handler.S	2002/01/28 20:31:57	1.3
@@ -16,59 +16,70 @@
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
 
-#include <linux/config.h>
-#include <linux/threads.h>
-
 #include <asm/asm.h>
-#include <asm/cacheops.h>
-#include <asm/current.h>
-#include <asm/offset.h>
-#include <asm/processor.h>
 #include <asm/regdef.h>
-#include <asm/cachectl.h>
 #include <asm/mipsregs.h>
-#include <asm/stackframe.h>
 
 	.text
-	/* Special Cache Error handler for SB1 for now*/
+	/* Special Cache Error handler for SB1 for now */
 	LEAF(except_vec2_sb1)
 	.set	noat
-	.set    mips0
+	.set	mips0
 	/*
-	 * This is a very bad place to be.  Our cache error
-	 * detection has triggered.  If we have write-back data
-	 * in the cache, we may not be able to recover.  As a
-	 * first-order desperate measure, turn off KSEG0 cacheing.
+	 * This is a very bad place to be.  Our cache error detection has
+	 * triggered.  If we have write-back data in the cache, we may not be
+	 * able to recover.  As a first-order desperate measure, turn off KSEG0
+	 * cacheing.
 	 */
-        .set    push
-        .set    mips64
-        .set    reorder
-        # look for signature of spurious CErr
-        mfc0    k1,$26,0
-        lui     k0,0x4000
-        bne     k0,k1,real_cerr
-        mfc0    k1,$27,1
-        lui     k0,0xffe0
-        and     k1,k0,k1
-        lui     k0,0x0200
-        bne     k0,k1,real_cerr
-        # clear/unlock the registers
-        mtc0    zero,$26,0
-        mtc0    zero,$27,1
-        eret
+	.set	push
+	#.set	mips64
+	.set	mips4
+	.set	reorder
+	# look for signature of spurious CErr
+	mfc0	k1, $26				# mfc0	k1, $26, 0
+	# check if error was recoverable
+	# XXXKW - count them
+	bltz	k1,leave_cerr
+	 nop
+#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
+	# look for signature of spurious CErr
+	lui	k0, 0x4000
+	bne	k0, k1, real_cerr
+	.word	0x401Bd801			# mfc0	k1, $27, 1
+	lui	k0, 0xffe0
+	and	k1, k0, k1
+	lui	k0, 0x0200
+	bne	k0, k1, real_cerr
+	 nop
+#else
+	j	real_cerr
+	 nop
+#endif
+	# XXXKW - count spurious errors
+leave_cerr:
+	# clear/unlock the registers
+	mtc0	zero, $26			# mtc0	zero, $26, 0
+	mtc0	zero, $27			# mtc0	zero, $27, 0
+	.word	0x4080d801			# mtc0	zero, $27, 1
+	.word	0x4080d803			# mtc0	zero, $27, 3
+	eret
 
-        # XXXXPK -  this is a real error.  set the LEDs and spin for now
 real_cerr:
-        lui     k0,0xb00A
-        li      k1,'C'
-        sb      k1,56(k0)
-        li      k1,'E'
-        sb      k1,48(k0)
-        li      k1,'R'
-        sb      k1,40(k0)
-        li      k1,'R'
-        sb      k1,32(k0)
-2:
-        b       2b
-        .set    pop
+	mfc0	k0,CP0_CONFIG
+	li	k1,~CONF_CM_CMASK
+	and	k0,k0,k1
+	ori	k0,k0,CONF_CM_UNCACHED
+	mtc0	k0,CP0_CONFIG
+	/* Give it a few cycles to sink in... */
+	sll     zero, zero, 0x1			# ssnop
+	sll     zero, zero, 0x1			# ssnop
+	sll     zero, zero, 0x1			# ssnop
+	sll     zero, zero, 0x1			# ssnop
+	sll     zero, zero, 0x1			# ssnop
+	sll     zero, zero, 0x1			# ssnop
+
+	j	sb1_cache_error
+	 nop
+
+	.set	pop
 	END(except_vec2_sb1)

[Linux-mips-commits]CVS: linux/arch/mips/sibyte/sb1250 Makefile,1.4,1.5 irq_handler.S,1.4,1.5

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/sibyte/sb1250

Modified Files:
	Makefile irq_handler.S 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/Makefile,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- Makefile	2001/11/21 22:07:56	1.4
+++ Makefile	2002/01/28 20:31:57	1.5
@@ -5,10 +5,11 @@
 
 O_TARGET := sb1250.o
 
-obj-y := setup.o irq.o irq_handler.o time.o lib_hssubr.o
+obj-y := setup.o irq.o irq_handler.o time.o
 
-obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_SMP) += smp.o
-obj-$(CONFIG_BCM1250_TBPROF) += bcm1250_tbprof.o
+obj-$(CONFIG_PCI)		+= pci.o
+obj-$(CONFIG_SMP)		+= smp.o
+obj-$(CONFIG_BCM1250_TBPROF)	+= bcm1250_tbprof.o
+obj-$(CONFIG_MIPS32)		+= lib_hssubr.o
 
 include $(TOPDIR)/Rules.make

Index: irq_handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/sibyte/sb1250/irq_handler.S,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq_handler.S	2001/12/02 19:05:30	1.4
+++ irq_handler.S	2002/01/28 20:31:57	1.5
@@ -17,7 +17,7 @@
  */
  
 /*
- *  sb1250_handle_int() is the routine that is actually called when an interrupt
+ * sb1250_handle_int() is the routine that is actually called when an interrupt
  * occurs.  It is installed as the exception vector handler in init_IRQ() in
  * arch/mips/sibyte/sb1250/irq.c
  *
@@ -48,10 +48,11 @@
  */
  
 	.text
-	.set    push
+	.set	push
 	.set	noreorder
 	.set	noat
-	.set    mips64
+	#.set	mips64
+	.set	mips4
 	.align	5
 	NESTED(sb1250_irq_handler, PT_SIZE, sp)
 	SAVE_ALL
@@ -59,34 +60,34 @@
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
 	/* Set compare to count to silence count/compare timer interrupts */
-	mfc0	 t1, CP0_COUNT
-	mtc0	 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
+	mfc0	t1, CP0_COUNT
+	mtc0	t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
 #endif
 	/* Read cause */
-	mfc0     s0, CP0_CAUSE
+	mfc0	s0, CP0_CAUSE
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
 	/* Cpu performance counter interrupt is routed to IP[7] */
-	andi	 t1, s0, CAUSEF_IP7
-	beqz	 t1, 0f
-	 srl	 t1, s0, (CAUSEB_BD-2)  /* Shift BD bit to bit 2 */
-	and	 t1, t1, 0x4	/* mask to get just BD bit */
-	mfc0	 a0, CP0_EPC
-	jal	 sbprof_cpu_intr
-	 addu	 a0, a0, t1	/* a0 = EPC + (BD ? 4 :	0) */
+	andi	t1, s0, CAUSEF_IP7
+	beqz	t1, 0f
+	 srl	t1, s0, (CAUSEB_BD-2)  /* Shift BD bit to bit 2 */
+	and	t1, t1, 0x4		/* mask to get just BD bit */
+	mfc0	a0, CP0_EPC
+	jal	sbprof_cpu_intr
+	 addu	a0, a0, t1		/* a0 = EPC + (BD ? 4 :	0) */
 	j	ret_from_irq
 	 nop				# delay slot
 0:
 #endif
 	/* Timer interrupt is routed to IP[4] */
-	andi     t1, s0, CAUSEF_IP4
-	beqz     t1, 1f
+	andi	t1, s0, CAUSEF_IP4
+	beqz	t1, 1f
 	 nop
-	jal      sb1250_timer_interrupt
-	 move    a0, sp  /* Pass the registers along */
+	jal	sb1250_timer_interrupt
+	 move	a0, sp			/* Pass the registers along */
 	j	ret_from_irq
 	 nop				# delay slot
-1:	
+1:
 
 #ifdef CONFIG_SMP
 	/* Mailbox interrupt is routed to IP[3] */
@@ -108,15 +109,16 @@
 	 * Default...we've hit an IP[2] interrupt, which means we've got to
 	 * check the 1250 interrupt registers to figure out what to do
 	 */
-	la       v0, KSEG1 + A_IMR_CPU0_BASE
-	ld       s0, R_IMR_INTERRUPT_STATUS_BASE(v0)		/* read IP[2] status */
+	la	v0, KSEG1 + A_IMR_CPU0_BASE
+	ld	s0, R_IMR_INTERRUPT_STATUS_BASE(v0)	/* read IP[2] status */
 
-	beqz     s0, 4f         /* No interrupts.  Return */
+	beqz	s0, 4f		/* No interrupts.  Return */
 	 move	a1, sp
 
-3:	dclz     s1, s0         /* Find the next interrupt */
-	dsubu    a0, zero, s1
-	daddiu   a0, a0, 63     
+3:	#dclz	s1, s0		/* Find the next interrupt */
+	.word   0x72118824	# dclz s1, s0
+	dsubu	a0, zero, s1
+	daddiu	a0, a0, 63     
 	jal	 do_IRQ
 	 nop
 

[Linux-mips-commits]CVS: linux/arch/mips/mips-boards/malta malta_int.c,1.5,1.6

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mips-boards/malta
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/mips-boards/malta

Modified Files:
	malta_int.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: malta_int.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mips-boards/malta/malta_int.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- malta_int.c	2001/12/11 18:25:20	1.5
+++ malta_int.c	2002/01/28 20:31:57	1.6
@@ -50,18 +50,6 @@
 	GT_READ(GT_PCI0_IACK_OFS, irq);
 	irq &= 0xFF;
 
-	/*  
-	 * IRQ7 is used to detect spurious interrupts.  The interrupt
-	 * acknowledge cycle returns IRQ7, if no interrupts is requested.  We
-	 * can differentiate between this situation and a "normal" IRQ7 by
-	 * reading the ISR.
-	 */
-	if (irq == 7) {
-		outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR, PIIX4_ICTLR1_OCW3);
-		if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7)))
-		        return;    /* Spurious interrupt. */
-	}
-
 	do_IRQ(irq, regs);
 }
 

[Linux-mips-commits]CVS: linux/arch/mips/mips-boards/generic Makefile,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mips-boards/generic
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/mips-boards/generic

Modified Files:
	Makefile 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mips-boards/generic/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile	2002/01/02 19:12:16	1.1
+++ Makefile	2002/01/28 20:31:56	1.2
@@ -30,8 +30,9 @@
 
 O_TARGET := mipsboards.o
 
-obj-y				:= mipsIRQ.o pci.o reset.o display.o init.o \
+obj-y				:= mipsIRQ.o reset.o display.o init.o \
 				   memory.o printf.o cmdline.o time.o
+obj-$(CONFIG_PCI)		+= pci.o
 obj-$(CONFIG_REMOTE_DEBUG)	+= gdb_hook.o
 
 include $(TOPDIR)/Rules.make

[Linux-mips-commits]CVS: linux/arch/mips/mips-boards/atlas atlas_setup.c,1.3,1.4

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/mips-boards/atlas
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/mips-boards/atlas

Modified Files:
	atlas_setup.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: atlas_setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mips-boards/atlas/atlas_setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- atlas_setup.c	2001/12/12 18:30:53	1.3
+++ atlas_setup.c	2002/01/28 20:31:56	1.4
@@ -28,8 +28,9 @@
 #include <asm/irq.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
-#include <asm/gt64120.h>
 #include <asm/mips-boards/atlasint.h>
+#include <asm/gt64120.h>
+#include <asm/time.h>
 
 #if defined(CONFIG_SERIAL_CONSOLE) || defined(CONFIG_PROM_CONSOLE)
 extern void console_setup(char *, int *);
@@ -52,6 +53,12 @@
 	return "MIPS Atlas";
 }
 
+void __init bus_error_init(void)
+{
+}
+
+extern void mips_time_init(void);
+
 void __init atlas_setup(void)
 {
 #ifdef CONFIG_REMOTE_DEBUG
@@ -115,6 +122,7 @@
 		mips_cpu.options &= ~MIPS_CPU_FPU;
 
 	rtc_ops = &atlas_rtc_ops;
+	board_time_init = mips_time_init;
 
 	mips_reboot_setup();
 }

[Linux-mips-commits]CVS: linux/arch/mips/kernel Makefile,1.18,1.19 smp.c,1.12,1.13

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv7656/arch/mips/kernel

Modified Files:
	Makefile smp.c 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/Makefile,v
retrieving revision 1.18
retrieving revision 1.19
diff -u -d -r1.18 -r1.19
--- Makefile	2002/01/19 21:17:35	1.18
+++ Makefile	2002/01/28 20:31:56	1.19
@@ -60,13 +60,13 @@
 obj-$(CONFIG_BINFMT_IRIX)	+= irixelf.o irixioctl.o irixsig.o sysirix.o \
 				   irixinv.o
 obj-$(CONFIG_REMOTE_DEBUG)	+= gdb-low.o gdb-stub.o 
-obj-$(CONFIG_PCI)		+= pci-dma.o
 obj-$(CONFIG_PROC_FS)		+= proc.o
 
-ifdef CONFIG_PCI
-obj-$(CONFIG_NEW_PCI)          += pci.o
-obj-$(CONFIG_PCI_AUTO)         += pci_auto.o
+obj-$(CONFIG_NEW_PCI)		+= pci.o
+ifndef CONFIG_MAPPED_PCI_IO
+obj-y				+= pci-dma.o
 endif
+obj-$(CONFIG_PCI_AUTO)		+= pci_auto.o
 
 entry.o: entry.S
 head.o: head.S

Index: smp.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/smp.c,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- smp.c	2002/01/02 20:42:11	1.12
+++ smp.c	2002/01/28 20:31:56	1.13
@@ -46,9 +46,10 @@
 int smp_num_cpus = 1;			/* Number that came online.  */
 cpumask_t cpu_online_map;		/* Bitmask of currently online CPUs */
 struct cpuinfo_mips cpu_data[NR_CPUS];
-void (*volatile smp_cpu0_finalize)(void) = NULL;
+void (*volatile smp_cpu0_finalize)(void);
 
-static atomic_t cpus_booted = ATOMIC_INIT(0);
+// static atomic_t cpus_booted = ATOMIC_INIT(0);
+atomic_t cpus_booted = ATOMIC_INIT(0);
 
 
 /* These are defined by the board-specific code. */
@@ -106,76 +107,6 @@
 	return 0;
 }
 
-void __init smp_boot_cpus(void)
-{
-	int i;
-
-	smp_num_cpus = prom_setup_smp();
-	init_new_context(current, &init_mm);
-	current->processor = 0;
-	cpu_data[0].udelay_val = loops_per_jiffy;
-	cpu_data[0].asid_cache = ASID_FIRST_VERSION;
-	CPUMASK_CLRALL(cpu_online_map);
-	CPUMASK_SETB(cpu_online_map, 0);
-	atomic_set(&cpus_booted, 1);  /* Master CPU is already booted... */
-	init_idle();
-	for (i = 1; i < smp_num_cpus; i++) {
-		struct task_struct *p;
-		struct pt_regs regs;
-		printk("Starting CPU %d... ", i);
-
-		/* Spawn a new process normally.  Grab a pointer to
-		   its task struct so we can mess with it */
-		do_fork(CLONE_VM|CLONE_PID, 0, &regs, 0);
-		p = init_task.prev_task;
-
-		/* Schedule the first task manually */
-		p->processor = i;
-		p->cpus_runnable = 1 << i; /* we schedule the first task manually */
-
-		/* Attach to the address space of init_task. */
-		atomic_inc(&init_mm.mm_count);
-		p->active_mm = &init_mm;
-		init_tasks[i] = p;
-
-		del_from_runqueue(p);
-		unhash_process(p);
-
-		prom_boot_secondary(i,
-				    (unsigned long)p + KERNEL_STACK_SIZE - 32,
-				    (unsigned long)p);
-
-#if 0
-		/* This is copied from the ip-27 code in the mips64 tree */
-
-		struct task_struct *p;
-
-		/*
-		 * The following code is purely to make sure
-		 * Linux can schedule processes on this slave.
-		 */
-		kernel_thread(0, NULL, CLONE_PID);
-		p = init_task.prev_task;
-		sprintf(p->comm, "%s%d", "Idle", i);
-		init_tasks[i] = p;
-		p->processor = i;
-		p->cpus_runnable = 1 << i; /* we schedule the first task manually */
-		del_from_runqueue(p);
-		unhash_process(p);
-		/* Attach to the address space of init_task. */
-		atomic_inc(&init_mm.mm_count);
-		p->active_mm = &init_mm;
-		prom_boot_secondary(i, 
-				    (unsigned long)p + KERNEL_STACK_SIZE - 32,
-				    (unsigned long)p);
-#endif
-	}
-
-	/* Wait for everyone to come up */
-	while (atomic_read(&cpus_booted) != smp_num_cpus);
-	smp_threads_ready = 1;
-}
-
 void __init smp_commence(void)
 {
 	/* Not sure what to do here yet */
@@ -238,7 +169,9 @@
 	void (*func) (void *info) = call_data->func;
 	void *info = call_data->info;
 	int wait = call_data->wait;
+	int cpu = smp_processor_id();
 
+	irq_enter(cpu, 0);	/* XXX choose an irq number? */
 	/*
 	 * Notify initiating CPU that I've grabbed the data
 	 * and am about to execute the function
@@ -254,6 +187,7 @@
 		mb();
 		atomic_inc(&call_data->finished);
 	}
+	irq_exit(cpu, 0);	/* XXX choose an irq number? */
 }
 
 static void stop_this_cpu(void *dummy)

[Linux-mips-commits]CVS: linux/include/asm-mips64/sibyte sb1250_io.h,NONE,1.1 swarm_ide.h,NONE,1.1 sb1250.h,1.1,1.2 sb1250_uart.h,1.1,1.2

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64/sibyte
In directory usw-pr-cvs1:/tmp/cvs-serv7656/include/asm-mips64/sibyte

Modified Files:
	sb1250.h sb1250_uart.h 
Added Files:
	sb1250_io.h swarm_ide.h 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

--- NEW FILE: sb1250_io.h ---
/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 Ralf Baechle
 * Copyright (C) 2000 Silicon Graphics, Inc.
 */
#ifndef _ASM_SGI_IO_H
#define _ASM_SGI_IO_H

#include <asm/addrspace.h>

#define IO_SPACE_BASE K1BASE

/* For Indigo2.  */
#define IO_SPACE_LIMIT 0xffff

/* XXX ISA specific functions go here here.  */

#endif /* _ASM_SGI_IO_H */

--- NEW FILE: swarm_ide.h ---
/*
 * Copyright (C) 2001 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 * 
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 */

#ifndef _SWARM_IDE_H
#define _SWARM_IDE_H

#include <asm/sibyte/sb1250_int.h>

#define SWARM_IDE_BASE        (0xb00b0000-mips_io_port_base)
#define SWARM_IDE_REG(pcaddr) (SWARM_IDE_BASE + ((pcaddr)<<5))
#define SWARM_IDE_INT         (K_INT_GPIO_4)

extern ide_ideproc_t swarm_ideproc;

#define swarm_outb(val,port)							\
do {									\
	*(volatile u8 *)(mips_io_port_base + (port)) = val;	\
} while(0)

#define swarm_outw(val,port)							\
do {									\
	*(volatile u16 *)(mips_io_port_base + (port)) = val;	\
} while(0)

#define swarm_outl(val,port)							\
do {									\
	*(volatile u32 *)(mips_io_port_base + (port)) = val;\
} while(0)

static inline unsigned char swarm_inb(unsigned long port)
{
	return (*(volatile u8 *)(mips_io_port_base + port));
}

static inline unsigned short swarm_inw(unsigned long port)
{
	return (*(volatile u16 *)(mips_io_port_base + port));
}

static inline unsigned int swarm_inl(unsigned long port)
{
	return (*(volatile u32 *)(mips_io_port_base + port));
}


static inline void swarm_outsb(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		swarm_outb(*(u8 *)addr, port);
		addr++;
	}
}

static inline void swarm_insb(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u8 *)addr = swarm_inb(port);
		addr++;
	}
}

static inline void swarm_outsw(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		swarm_outw(*(u16 *)addr, port);
		addr += 2;
	}
}

static inline void swarm_insw(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u16 *)addr = swarm_inw(port);
		addr += 2;
	}
}

static inline void swarm_outsl(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		swarm_outl(*(u32 *)addr, port);
		addr += 4;
	}
}

static inline void swarm_insl(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u32 *)addr = swarm_inl(port);
		addr += 4;
	}
}

#endif

Index: sb1250.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sibyte/sb1250.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sb1250.h	2001/11/08 17:28:25	1.1
+++ sb1250.h	2002/01/28 20:32:06	1.2
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2001 Broadcom Corporation
+ * Copyright (C) 2000, 2001 Broadcom Corporation
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -16,6 +16,14 @@
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
 
+#ifndef _ASM_SIBYTE_SB1250_H
+#define _ASM_SIBYTE_SB1250_H
+
+extern void sb1250_time_init(void);
 extern void sb1250_mask_irq(int cpu, int irq);
 extern void sb1250_unmask_irq(int cpu, int irq);
-extern void sb1250_time_init(void);
+extern void sb1250_smp_finish(void);
+
+#define IO_SPACE_BASE 0xa0000000UL
+
+#endif

Index: sb1250_uart.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/sibyte/sb1250_uart.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- sb1250_uart.h	2001/11/08 17:28:25	1.1
+++ sb1250_uart.h	2002/01/28 20:32:06	1.2
@@ -6,7 +6,7 @@
     *  This module contains constants and macros useful for 
     *  manipulating the SB1250's UARTs
     *
-    *  SB1250 specification level:  0.2
+    *  SB1250 specification level:  01/02/2002
     *  
     *  Author:  Mitch Lichtenberg (mi...@si...)
     *  
@@ -63,7 +63,7 @@
 
 
 #define M_DUART_PARITY_TYPE_EVEN    0x00
-#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(3)
+#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
 
 #define S_DUART_PARITY_MODE          3
 #define M_DUART_PARITY_MODE         _SB_MAKEMASK(2,S_DUART_PARITY_MODE)

[Linux-mips-commits]CVS: linux/include/asm-mips64 asm.h,1.7,1.8 io.h,1.12,1.13 mipsregs.h,1.8,1.9 mmu_context.h,1.3,1.4 page.h,1.5,1.6 pci.h,1.9,1.10 pgtable.h,1.7,1.8 scatterlist.h,1.1,1.2 system.h,1.7,1.8

[James S. <jsi...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips64
In directory usw-pr-cvs1:/tmp/cvs-serv7656/include/asm-mips64

Modified Files:
	asm.h io.h mipsregs.h mmu_context.h page.h pci.h pgtable.h 
	scatterlist.h system.h 
Log Message:
Big overhaul of 64-bit kernel along the lines of what we already have for the 64-bit kernel just more radical.

Index: asm.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/asm.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- asm.h	2001/11/19 17:30:16	1.7
+++ asm.h	2002/01/28 20:32:05	1.8
@@ -105,20 +105,20 @@
 		TEXT(string)
 
 #define	TEXT(msg)                                       \
-		.data;                                  \
+		.pushsection .data;			\
 8:		.asciiz	msg;                            \
-		.previous;
+		.popsection;
 
 /*
  * Build text tables
  */
 #define TTABLE(string)                                  \
-		.text;                                  \
+		.pushsection .text;			\
 		.word	1f;                             \
 		.previous;                              \
 		.data;                                  \
 1:		.asciz	string;                         \
-		.previous
+		.popsection
 
 /*
  * MIPS IV pref instruction.

Index: io.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/io.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- io.h	2002/01/02 19:12:18	1.12
+++ io.h	2002/01/28 20:32:05	1.13
@@ -34,6 +34,10 @@
 #include <asm/ip32/io.h>
 #endif
 
+#ifdef CONFIG_SIBYTE_SB1250
+#include <asm/sibyte/sb1250_io.h>
+#endif
+
 extern unsigned long bus_to_baddr[256];
 
 /*
@@ -63,6 +67,8 @@
  * Change "struct page" to physical address.
  */
 #define page_to_phys(page)	PHYSADDR(page_address(page))
+
+typedef unsigned long phys_t;
 
 /*
  * On MIPS, we have the whole physical address space mapped at all

Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mipsregs.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -d -r1.8 -r1.9
--- mipsregs.h	2001/12/02 19:05:32	1.8
+++ mipsregs.h	2002/01/28 20:32:05	1.9
@@ -383,7 +383,7 @@
  * R10000 performance counter definitions.
  *
  * FIXME: The R10000 performance counter opens a nice way to implement CPU
- *        time accounting with a precision of one cycle.  I don't have
+ *        time accounting with a precission of one cycle.  I don't have
  *        R10000 silicon but just a manual, so ...
  */
 
@@ -448,7 +448,7 @@
         __res;})
 
 #define read_64bit_cp0_register(source)                         \
-({ int __res;                                                   \
+({ unsigned long __res;                                         \
         __asm__ __volatile__(                                   \
         ".set\tmips3\n\t"                                       \
         "dmfc0\t%0,"STR(source)"\n\t"                           \

Index: mmu_context.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/mmu_context.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mmu_context.h	2001/11/19 17:35:09	1.3
+++ mmu_context.h	2002/01/28 20:32:05	1.4
@@ -14,6 +14,7 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/pgalloc.h>
+#include <asm/pgtable.h>
 
 /*
  * For the fast tlb miss handlers, we currently keep a per cpu array
@@ -57,6 +58,7 @@
 	unsigned long asid = ASID_CACHE(cpu);
 
 	if (! ((asid += ASID_INC) & ASID_MASK) ) {
+		flush_icache_all();
 		local_flush_tlb_all();	/* start new asid cycle */
 		if (!asid)		/* fix version if needed */
 			asid = ASID_FIRST_VERSION;

Index: page.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/page.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- page.h	2002/01/02 17:08:26	1.5
+++ page.h	2002/01/28 20:32:05	1.6
@@ -23,6 +23,13 @@
 #define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); *(int *)0=0; } while (0)
 #define PAGE_BUG(page) do {  BUG(); } while (0)
 
+/*
+ * Prototypes for clear_page / copy_page variants with processor dependant
+ * optimizations.
+ */
+void sb1_clear_page(void * page);
+void sb1_copy_page(void * to, void * from);
+
 extern void (*_clear_page)(void * page);
 extern void (*_copy_page)(void * to, void * from);
 
@@ -57,8 +64,8 @@
 	size = (size-1) >> (PAGE_SHIFT-1);
 	order = -1;
 	do {
-		size >>= 1;
-		order++;
+       		size >>= 1;
+       		order++;
 	} while (size);
 	return order;
 }
@@ -81,6 +88,9 @@
 #define PAGE_OFFSET	0x9800000000000000UL
 #endif
 #if defined(CONFIG_SGI_IP27)
+#define PAGE_OFFSET	0xa800000000000000UL
+#endif
+#if defined(CONFIG_SIBYTE_SB1250)
 #define PAGE_OFFSET	0xa800000000000000UL
 #endif
 

Index: pci.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pci.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- pci.h	2002/01/02 19:12:18	1.9
+++ pci.h	2002/01/28 20:32:05	1.10
@@ -181,9 +181,7 @@
 static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
 			     int nents, int direction)
 {
-#ifdef CONFIG_NONCOHERENT_IO
 	int i;
-#endif
 
 	if (direction == PCI_DMA_NONE)
 		BUG();
@@ -193,7 +191,7 @@
 #ifdef CONFIG_NONCOHERENT_IO
 		dma_cache_wback_inv((unsigned long)sg->address, sg->length);
 #endif
-		sg->address = (char *)(bus_to_baddr[hwdev->bus->number] | __pa(sg->address));
+		sg->dma_address = (char *)(__pa(sg->address));
 	}
 
 	return nents;

Index: pgtable.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/pgtable.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- pgtable.h	2002/01/02 18:02:57	1.7
+++ pgtable.h	2002/01/28 20:32:05	1.8
@@ -27,13 +27,27 @@
  *  - flush_cache_range(mm, start, end) flushes a range of pages
  *  - flush_page_to_ram(page) write back kernel page to ram
  */
+extern void (*_flush_cache_all)(void);
+extern void (*___flush_cache_all)(void);
 extern void (*_flush_cache_mm)(struct mm_struct *mm);
 extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
-                                 unsigned long end);
-extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
+	unsigned long end);
+extern void (*_flush_cache_page)(struct vm_area_struct *vma,
+	unsigned long page);
 extern void (*_flush_page_to_ram)(struct page * page);
+extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
+extern void (*_flush_icache_page)(struct vm_area_struct *vma,
+	struct page *page);
+extern void (*_flush_cache_sigtramp)(unsigned long addr);
+extern void (*_flush_icache_all)(void);
 
-#define flush_cache_all()		do { } while(0)
+/* These suck ...  */
+extern void (*_flush_cache_l2)(void);
+extern void (*_flush_cache_l1)(void);
+
+
+#define flush_cache_all()		_flush_cache_all()
+#define __flush_cache_all()		___flush_cache_all()
 #define flush_dcache_page(page)		do { } while (0)
 
 #ifndef CONFIG_CPU_R10000
@@ -73,15 +87,13 @@
 } while (0)
 #endif /* !CONFIG_CPU_R10000 */
 
-/*
- * The foll cache flushing routines are MIPS specific.
- * flush_cache_l2 is needed only during initialization.
- */
-extern void (*_flush_cache_sigtramp)(unsigned long addr);
-extern void (*_flush_cache_l2)(void);
-extern void (*_flush_cache_l1)(void);
-
 #define flush_cache_sigtramp(addr)	_flush_cache_sigtramp(addr)
+#ifdef CONFIG_VTAG_ICACHE
+#define flush_icache_all()		_flush_icache_all()
+#else
+#define flush_icache_all()		do { } while(0)
+#endif
+
 #define flush_cache_l2()		_flush_cache_l2()
 #define flush_cache_l1()		_flush_cache_l1()
 
@@ -529,8 +541,9 @@
 extern pgd_t swapper_pg_dir[1024];
 extern void paging_init(void);
 
-extern void (*update_mmu_cache)(struct vm_area_struct *vma,
-				unsigned long address, pte_t pte);
+extern void (*_update_mmu_cache)(struct vm_area_struct *vma,
+	unsigned long address, pte_t pte);
+#define update_mmu_cache(vma, address, pte) _update_mmu_cache(vma, address, pte)
 
 /*
  * Non-present pages:  high 24 bits are offset, next 8 bits type,

Index: scatterlist.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/scatterlist.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- scatterlist.h	2002/01/02 19:12:18	1.1
+++ scatterlist.h	2002/01/28 20:32:05	1.2
@@ -4,17 +4,16 @@
 struct scatterlist {
 	char *  address;	/* Location data is to be transferred to */
 	struct page *page;
-	unsigned int offset;
 	unsigned int length;
 
-	__u32 dvma_address;
+	__u32 dma_address;
 };
 
 struct mmu_sglist {
         char *addr;
         char *__dont_touch;
         unsigned int len;
-        __u32 dvma_addr;
+        __u32 dma_addr;
 };
 
 #define ISA_DMA_THRESHOLD (0x00ffffffUL)

Index: system.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips64/system.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -d -r1.7 -r1.8
--- system.h	2001/12/12 16:19:19	1.7
+++ system.h	2002/01/28 20:32:05	1.8
@@ -56,9 +56,9 @@
 	"xori\t$1,1\n\t"
 	".set\tnoreorder\n\t"
 	"mtc0\t$1,$12\n\t"
-	"nop\n\t"
-	"nop\n\t"
-	"nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
+	"sll\t$0, $0, 1\t\t\t# nop\n\t"
 	".set\tpop\n\t"
 	".endm");