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From: Paul M. <le...@us...> - 2002-01-22 22:08:15
|
Update of /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/common In directory usw-pr-cvs1:/tmp/cvs-serv5255/ddb5xxx/common Modified Files: prom.c Log Message: Get rid of hardcoded ip=bootp. Index: prom.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/ddb5xxx/common/prom.c,v retrieving revision 1.4 retrieving revision 1.5 diff -u -d -r1.4 -r1.5 --- prom.c 2001/12/12 18:30:52 1.4 +++ prom.c 2002/01/22 22:08:12 1.5 @@ -52,9 +52,6 @@ strcat(arcs_cmdline, " "); } - /* by default all these boards use dhcp/nfs root fs */ - strcat(arcs_cmdline, "ip=bootp"); - mips_machgroup = MACH_GROUP_NEC_DDB; #if defined(CONFIG_DDB5074) |
|
From: Paul M. <le...@us...> - 2002-01-22 22:02:55
|
Update of /cvsroot/linux-mips/linux/net/ipv4 In directory usw-pr-cvs1:/tmp/cvs-serv3361 Modified Files: ipconfig.c Log Message: Default to autoconfig by default.. Index: ipconfig.c =================================================================== RCS file: /cvsroot/linux-mips/linux/net/ipv4/ipconfig.c,v retrieving revision 1.1 retrieving revision 1.2 diff -u -d -r1.1 -r1.2 --- ipconfig.c 2002/01/22 22:01:55 1.1 +++ ipconfig.c 2002/01/22 22:02:53 1.2 @@ -101,7 +101,7 @@ */ int ic_set_manually __initdata = 0; /* IPconfig parameters set manually */ -int ic_enable __initdata = 0; /* IP config enabled? */ +int ic_enable __initdata = 1; /* IP config enabled? */ /* Protocol choice */ int ic_proto_enabled __initdata = 0 |
|
From: Paul M. <le...@us...> - 2002-01-22 22:01:57
|
Update of /cvsroot/linux-mips/linux/net/ipv4
In directory usw-pr-cvs1:/tmp/cvs-serv3180
Added Files:
ipconfig.c
Log Message:
Add stock ipconfig.c from 2.4.17..
--- NEW FILE: ipconfig.c ---
/*
* $Id: ipconfig.c,v 1.1 2002/01/22 22:01:55 lethal Exp $
*
* Automatic Configuration of IP -- use DHCP, BOOTP, RARP, or
* user-supplied information to configure own IP address and routes.
*
* Copyright (C) 1996-1998 Martin Mares <mj...@at...>
*
* Derived from network configuration code in fs/nfs/nfsroot.c,
* originally Copyright (C) 1995, 1996 Gero Kuhlmann and me.
*
* BOOTP rewritten to construct and analyse packets itself instead
* of misusing the IP layer. num_bugs_causing_wrong_arp_replies--;
* -- MJ, December 1998
*
* Fixed ip_auto_config_setup calling at startup in the new "Linker Magic"
* initialization scheme.
* - Arnaldo Carvalho de Melo <ac...@co...>, 08/11/1999
*
[...1330 lines suppressed...]
break;
case 6:
ic_proto_name(ip);
break;
}
}
ip = cp;
num++;
}
return 1;
}
static int __init nfsaddrs_config_setup(char *addrs)
{
return ip_auto_config_setup(addrs);
}
__setup("ip=", ip_auto_config_setup);
__setup("nfsaddrs=", nfsaddrs_config_setup);
|
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From: Paul M. <le...@us...> - 2002-01-22 22:01:34
|
Update of /cvsroot/linux-mips/linux/net/ipv4 In directory usw-pr-cvs1:/tmp/cvs-serv3082/net/ipv4 Log Message: Directory /cvsroot/linux-mips/linux/net/ipv4 added to the repository |
|
From: Paul M. <le...@us...> - 2002-01-22 22:01:28
|
Update of /cvsroot/linux-mips/linux/net In directory usw-pr-cvs1:/tmp/cvs-serv3041/net Log Message: Directory /cvsroot/linux-mips/linux/net added to the repository |
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From: Paul M. <le...@Ch...> - 2002-01-21 16:10:42
|
On Mon, Jan 21, 2002 at 02:28:47PM +0100, Dirk Behme wrote: > >=20 > > Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common > > ... > > Added Files: > > ... vrc4173.c >=20 > I think the 4173 is not "common" for the VR4122, so a better place for th= is > file would be the "eagle" directory? >=20 It's fully supported alongside the Vr4122 and the Vr4131. In order to link = it in for the Vr4131, it needs to reside in the common directory.. The Eagle a= nd the BE-300 are two ports in CVS that currently support the Vrc4173. Regards, --=20 Paul Mundt <le...@ch...> |
|
From: Dirk B. <dir...@de...> - 2002-01-21 13:29:13
|
Paul Mundt wrote: > > Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common > ... > Added Files: > ... vrc4173.c I think the 4173 is not "common" for the VR4122, so a better place for this file would be the "eagle" directory? Dirk -- dir...@de... |
|
From: Paul M. <le...@us...> - 2002-01-20 03:26:10
|
Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv20377
Modified Files:
vr41xxwdt.c
Log Message:
Vr41xx WDT update. (This was actually done about a month ago, just forgot to
check it in..).
Index: vr41xxwdt.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/vr41xxwdt.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- vr41xxwdt.c 2001/10/30 17:53:17 1.3
+++ vr41xxwdt.c 2002/01/20 03:26:07 1.4
@@ -19,7 +19,6 @@
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/notifier.h>
-#include <linux/smp_lock.h>
#include <linux/ioport.h>
#include <linux/fs.h>
@@ -41,16 +40,21 @@
* the userspace daemon. A heartbeat value 2x that of the timer overflow
* period should be suffecient.
*/
-#define DSUTMRINTRVL (jiffies + (HZ * nsecs))/* DSU Timer Interval */
-#define DSUHEARTBEAT (DSUTMRINTRVL * 2) /* Next Heartbeat */
-static int vr41xx_wdt_is_open = 0;
+/* DSU Timer Interval */
+#define DSUTMRINTRVL (jiffies + (HZ * nsecs))
+
+/* Next heartbeat */
+#define DSUHEARTBEAT (DSUTMRINTRVL * heartbeat_multiplier)
+
+static unsigned long vr41xx_wdt_is_open = 0;
static struct watchdog_info vr41xx_wdt_info;
static struct timer_list timer;
static unsigned long next_heartbeat;
static unsigned int nsecs = 7; /* Default overflow period */
+static unsigned int heartbeat_multiplier = 2;
/**
* vr41xx_wdt_start - Start the Watchdog
@@ -70,13 +74,13 @@
add_timer(&timer);
/* Clear the counter */
- writew(0x01, VR41XX_DSUCLRREG);
+ *(volatile unsigned int *)VR41XX_DSUCLRREG = 1;
/* Set the overflow period (in seconds) */
- writew(nsecs, VR41XX_DSUSETREG);
+ *(volatile unsigned int *)VR41XX_DSUSETREG = nsecs;
/* Turn on the watchdog */
- writew(0x01, VR41XX_DSUCNTREG);
+ *(volatile unsigned int *)VR41XX_DUSCNTREG = 1;
}
/**
@@ -89,10 +93,10 @@
del_timer(&timer);
/* Clear the counter */
- writew(0x01, VR41XX_DSUCLRREG);
+ *(volatile unsigned int *)VR41XX_DSUCLRREG = 1;
/* Turn off the watchdog */
- writew(0x00, VR41XX_DSUCNTREG);
+ *(volatile unsigned int *)VR41XX_DSUCNTREG = 0;
}
/**
@@ -106,7 +110,7 @@
{
if (time_before(jiffies, next_heartbeat)) {
/* Clear overflow counter */
- writew(0x01, VR41XX_DSUCLRREG);
+ *(volatile unsigned int *)VR41XX_DSUCLRREG = 1;
/* Update timer */
timer.expires = DSUTMRINTRVL;
@@ -126,10 +130,9 @@
{
switch (MINOR(inode->i_rdev)) {
case WATCHDOG_MINOR:
- if (vr41xx_wdt_is_open)
+ if (test_and_set_bit(0, &vr41xx_wdt_is_open))
return -EBUSY;
- vr41xx_wdt_is_open = 1;
vr41xx_wdt_start();
break;
@@ -150,17 +153,13 @@
*/
static int vr41xx_wdt_close(struct inode *inode, struct file *file)
{
- lock_kernel();
-
if (MINOR(inode->i_rdev) == WATCHDOG_MINOR) {
#ifndef CONFIG_WATCHDOG_NOWAYOUT
vr41xx_wdt_stop();
#endif
- vr41xx_wdt_is_open = 0;
+ clear_bit(0, &vr41xx_wdt_is_open);
}
- unlock_kernel();
-
return 0;
}
@@ -338,6 +337,8 @@
MODULE_DESCRIPTION("NEC VR41xx watchdog driver");
MODULE_PARM(nsecs, "i");
MODULE_PARM_DESC(nsecs, "Number of seconds for overflow period. (1 - 15 seconds).");
+MODULE_PARM(heartbeat_multiplier, "i");
+MODULE_PARM_DESC(heartbeat_multiplier, "Heartbeat multiplier (next heartbeat = overflow period * multiplier). Defaults to 2.");
MODULE_LICENSE("GPL");
module_init(vr41xx_wdt_init);
|
|
From: Paul M. <le...@us...> - 2002-01-20 03:22:16
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv19905 Added Files: defconfig-casio-be300 Log Message: Add a defconfig for the casio be-300 --- NEW FILE: defconfig-casio-be300 --- # # Automatically generated by make menuconfig: don't edit # CONFIG_MIPS=y CONFIG_MIPS32=y # # Code maturity level options # CONFIG_EXPERIMENTAL=y # # Machine selection # # CONFIG_ACER_PICA_61 is not set # CONFIG_ALGOR_P4032 is not set # CONFIG_BAGET_MIPS is not set # CONFIG_COBALT_MICRO_SERVER is not set # CONFIG_DECSTATION is not set # CONFIG_DDB5074 is not set # CONFIG_NEC_EAGLE is not set # CONFIG_NEC_KORVA is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set # CONFIG_SIBYTE_SB1250 is not set # CONFIG_PS2 is not set CONFIG_CASIO_BE300=y # CONFIG_CASIO_E15 is not set # CONFIG_VADEM_CLIO_1000 is not set # CONFIG_NEC_MOBILEPRO_780 is not set # CONFIG_IDT_79S334 is not set # CONFIG_IDT_79EB355 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set # CONFIG_DDB5477 is not set # CONFIG_NEC_OSPREY is not set # CONFIG_OLIVETTI_M700 is not set # CONFIG_SGI_IP22 is not set # CONFIG_SNI_RM200_PCI is not set # CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set # CONFIG_MIPS_PB1500 is not set # CONFIG_TOSHIBA_JMR3927 is not set # CONFIG_HP_LASERJET is not set # CONFIG_HIGHMEM is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set # CONFIG_MCA is not set # CONFIG_SBUS is not set CONFIG_CPU_VR41XX=y CONFIG_VR4122=y CONFIG_VR4131=y CONFIG_NEW_IRQ=y CONFIG_NEW_TIME_C=y CONFIG_VR4122_TIME_C=y CONFIG_NONCOHERENT_IO=y CONFIG_DUMMY_KEYB=y CONFIG_PCI=y CONFIG_NEW_PCI=y CONFIG_PCI_AUTO=y # CONFIG_ISA is not set # CONFIG_EISA is not set # # Loadable module support # # CONFIG_MODULES is not set # # CPU selection # # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set CONFIG_CPU_VR41XX=y # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5900 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_SR7100 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_RC32300 is not set # CONFIG_CPU_ADVANCED is not set # CONFIG_CPU_HAS_LLSC is not set # CONFIG_CPU_HAS_LLDSCD is not set # CONFIG_CPU_HAS_WB is not set # # General setup # CONFIG_CPU_LITTLE_ENDIAN=y # CONFIG_CPU_R5900_CONTEXT is not set CONFIG_VR4131_CACHE_FIX=y CONFIG_KCORE_ELF=y CONFIG_ELF_KERNEL=y # CONFIG_BINFMT_AOUT is not set CONFIG_BINFMT_ELF=y # CONFIG_BINFMT_MISC is not set # CONFIG_CPU_FREQ is not set # CONFIG_NET is not set # CONFIG_PCI_NAMES is not set # CONFIG_HOTPLUG is not set # CONFIG_PCMCIA is not set # CONFIG_HOTPLUG_PCI is not set # CONFIG_SYSVIPC is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_SYSCTL is not set # # Memory Technology Devices (MTD) # # CONFIG_MTD is not set # # Parallel port support # # CONFIG_PARPORT is not set # # Block devices # # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_DEV_XD is not set # CONFIG_PARIDE is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_BLK_DEV_INITRD is not set # # Multi-device support (RAID and LVM) # # CONFIG_MD is not set # CONFIG_BLK_DEV_MD is not set # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID5 is not set # CONFIG_MD_MULTIPATH is not set # CONFIG_BLK_DEV_LVM is not set # # Telephony Support # # CONFIG_PHONE is not set # CONFIG_PHONE_IXJ is not set # CONFIG_PHONE_IXJ_PCMCIA is not set # # ATA/IDE/MFM/RLL support # # CONFIG_IDE is not set # CONFIG_BLK_DEV_IDE_MODES is not set # CONFIG_BLK_DEV_HD is not set # # SCSI support # # CONFIG_SCSI is not set # # I2O device support # # CONFIG_I2O is not set # CONFIG_I2O_PCI is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set # # Amateur Radio support # # CONFIG_HAMRADIO is not set # # ISDN subsystem # # # Old CD-ROM drivers (not SCSI, not IDE) # # CONFIG_CD_NO_IDESCSI is not set # # Character devices # CONFIG_VT=y CONFIG_VT_CONSOLE=y # CONFIG_SERIAL is not set # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_VRC4173=y # CONFIG_VRC4173_PS2U is not set # CONFIG_VRC4173_PIU is not set CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 # # I2C support # # CONFIG_I2C is not set # # Mice # # CONFIG_BUSMOUSE is not set CONFIG_MOUSE=y CONFIG_PSMOUSE=y # CONFIG_82C710_MOUSE is not set # CONFIG_PC110_PAD is not set # # Joysticks # # CONFIG_INPUT_GAMEPORT is not set # CONFIG_QIC02_TAPE is not set # # Watchdog Cards # # CONFIG_WATCHDOG is not set # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set # CONFIG_MIPS_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # # Ftape, the floppy tape device driver # # CONFIG_FTAPE is not set # CONFIG_AGP is not set # CONFIG_DRM is not set # # Multimedia devices # # CONFIG_VIDEO_DEV is not set # # File systems # # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set # CONFIG_REISERFS_PROC_INFO is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EXT3_FS is not set # CONFIG_JBD is not set # CONFIG_JBD_DEBUG is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS_FS is not set # CONFIG_JFFS2_FS is not set # CONFIG_CRAMFS is not set # CONFIG_TMPFS is not set # CONFIG_RAMFS is not set # CONFIG_ISO9660_FS is not set # CONFIG_JOLIET is not set # CONFIG_ZISOFS is not set # CONFIG_MINIX_FS is not set # CONFIG_VXFS_FS is not set # CONFIG_NTFS_FS is not set # CONFIG_NTFS_RW is not set # CONFIG_HPFS_FS is not set CONFIG_PROC_FS=y # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set # CONFIG_DEVPTS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set # CONFIG_EXT2_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UDF_FS is not set # CONFIG_UDF_RW is not set # CONFIG_UFS_FS is not set # CONFIG_UFS_FS_WRITE is not set # CONFIG_NCPFS_NLS is not set # CONFIG_SMB_FS is not set # CONFIG_ZISOFS_FS is not set # CONFIG_ZLIB_FS_INFLATE is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set # CONFIG_OSF_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y # CONFIG_BSD_DISKLABEL is not set # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_SMB_NLS is not set # CONFIG_NLS is not set # # Console drivers # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set # # Frame-buffer support # # CONFIG_FB is not set # # Sound # # CONFIG_SOUND is not set # # USB support # # CONFIG_USB is not set # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set # CONFIG_USB_OHCI is not set # CONFIG_USB_AUDIO is not set # CONFIG_USB_BLUETOOTH is not set # CONFIG_USB_STORAGE is not set # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_DPCM is not set # CONFIG_USB_STORAGE_HP8200e is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_DC2XX is not set # CONFIG_USB_MDC800 is not set # CONFIG_USB_SCANNER is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USB_HPUSBSCSI is not set # CONFIG_USB_USS720 is not set # # USB Serial Converter support # # CONFIG_USB_SERIAL is not set # CONFIG_USB_SERIAL_GENERIC is not set # CONFIG_USB_SERIAL_BELKIN is not set # CONFIG_USB_SERIAL_WHITEHEAT is not set # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set # CONFIG_USB_SERIAL_EMPEG is not set # CONFIG_USB_SERIAL_FTDI_SIO is not set # CONFIG_USB_SERIAL_VISOR is not set # CONFIG_USB_SERIAL_IR is not set # CONFIG_USB_SERIAL_EDGEPORT is not set # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set # CONFIG_USB_SERIAL_KEYSPAN is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set # CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set # CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set # CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set # CONFIG_USB_SERIAL_MCT_U232 is not set # CONFIG_USB_SERIAL_PL2303 is not set # CONFIG_USB_SERIAL_CYBERJACK is not set # CONFIG_USB_SERIAL_XIRCOM is not set # CONFIG_USB_SERIAL_OMNINET is not set # CONFIG_USB_RIO500 is not set # # Input core support # # CONFIG_INPUT is not set # CONFIG_INPUT_KEYBDEV is not set # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # # Kernel hacking # CONFIG_CROSSCOMPILE=y # CONFIG_REMOTE_DEBUG is not set # CONFIG_GDB_CONSOLE is not set # CONFIG_DEBUG is not set # CONFIG_MAGIC_SYSRQ is not set # CONFIG_MIPS_UNCACHED is not set |
|
From: Paul M. <le...@us...> - 2002-01-20 03:18:34
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4131/casio-be300
In directory usw-pr-cvs1:/tmp/cvs-serv19235
Modified Files:
Makefile
Added Files:
pci_fixup.c
Log Message:
Add some dummy PCI fixup routines. Fill these in later.
--- NEW FILE: pci_fixup.c ---
/*
* arch/mips/vr4131/casio-be300/pci_fixup.c
*
* PCI fixup routines for the Casio Cassiopeia BE-300
*
* Copyright (C) 2002 Paul Mundt <le...@ch...>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <asm/vrc4173.h>
#include <asm/vr41xx.h>
#include <asm/pci_channel.h>
struct pci_channel mips_pci_channels[] = {
{ 0, }
};
void __init pcibios_fixup_resources(struct pci_dev *pdev)
{
}
void __init pcibios_fixup(void)
{
}
void __init pcibios_fixup_irqs(void)
{
}
unsigned int pcibios_assign_all_busses(void)
{
return 0;
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4131/casio-be300/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 2002/01/18 21:22:22 1.1
+++ Makefile 2002/01/20 03:18:30 1.2
@@ -15,4 +15,6 @@
obj-y := prom.o setup.o
+obj-$(CONFIG_PCI) += pci_fixup.o
+
include $(TOPDIR)/Rules.make
|
|
From: Paul M. <le...@us...> - 2002-01-19 21:17:39
|
Update of /cvsroot/linux-mips/linux/arch/mips In directory usw-pr-cvs1:/tmp/cvs-serv11561/arch/mips Modified Files: Makefile config.in Log Message: Commited Jason Gunthorpe's SR7100 patch, after cleaning it up some.. still not too happy with the ret_from_irq_sr7100.. Index: Makefile =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v retrieving revision 1.38 retrieving revision 1.39 diff -u -d -r1.38 -r1.39 --- Makefile 2002/01/18 21:22:07 1.38 +++ Makefile 2002/01/19 21:17:35 1.39 @@ -101,6 +101,9 @@ MODFLAGS += -msb1-pass1-workarounds endif endif +ifdef CONFIG_CPU_SR7100 +GCCFLAGS += -mcpu=r5000 -mips2 -Wa,--trap +endif GCCFLAGS += -pipe Index: config.in =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v retrieving revision 1.81 retrieving revision 1.82 diff -u -d -r1.81 -r1.82 --- config.in 2002/01/19 01:35:17 1.81 +++ config.in 2002/01/19 21:17:35 1.82 @@ -474,6 +474,7 @@ R5432 CONFIG_CPU_R5432 \ R5900 CONFIG_CPU_R5900 \ RM7000 CONFIG_CPU_RM7000 \ + SR7100 CONFIG_CPU_SR7100 \ R52xx CONFIG_CPU_NEVADA \ R10000 CONFIG_CPU_R10000 \ SB1 CONFIG_CPU_SB1 \ |
|
From: Paul M. <le...@us...> - 2002-01-19 21:17:38
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv11561/arch/mips/mm
Modified Files:
Makefile loadmmu.c
Added Files:
c-sr7100.c
Log Message:
Commited Jason Gunthorpe's SR7100 patch, after cleaning it up some.. still not
too happy with the ret_from_irq_sr7100..
--- NEW FILE: c-sr7100.c ---
/*
Jason Gunthorpe <jg...@yo...>
Copyright (C) 2002 YottaYotta. Inc.
Based on c-mips32:
Kevin D. Kissell, ke...@mi... and Carsten Langgaard, car...@mi...
Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
This file is subject to the terms and conditions of the GNU General Public
License. See the file "COPYING" in the main directory of this archive
for more details.
Sandcraft SR7100 cache routines.
The SR7100 is a MIPS64 compatible CPU with 4 caches:
* 4 way 32K primary ICache - virtually indexed/physically tagged
* 4 way 32K primary DCache - virtually indexed/physically tagged
* 8 way 512K secondary cache - physically indexed/taged
* 8 way up to 16M tertiary cache - physically indexed/taged (and off chip)
ICache and DCache do not have any sort of snooping. Unlike the RM7k,
the virtual index is 13 bits, and we use a 4k page size. This means you
can have cache aliasing effects, so they have to be treated as virtually
tagged. (unless that can be solved elsewhere, should investigate)
Note that on this chip all the _SD type cache ops (ie Hit_Writeback_Inv_SD)
are really just _S. This is in line with what the MIPS64 spec permits.
Also, the line size of the tertiary cache is really the block size. The
line size is always 32 bytes. The chip can tag partial blocks and the cache
op instructions work on those partial blocks too.
See ./Documentation/cachetlb.txt
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/bcache.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/mmu_context.h>
#undef DEBUG_CACHE
/* Primary cache parameters. */
int icache_size, dcache_size; /* Size in bytes */
int ic_lsize, dc_lsize; /* LineSize in bytes */
/* Secondary cache parameters. */
unsigned int scache_size, sc_lsize; /* Again, in bytes */
/* tertiary cache (if present) parameters. */
unsigned int tcache_size, tc_lsize; /* Again, in bytes */
#include <asm/cacheops.h>
#include <asm/mips32_cache.h>
// Unique to the SR7100
#define Index_Invalidate_T 0x2
#define Hit_Invalidate_T 0x16
static inline void blast_tcache(void)
{
unsigned long start = KSEG0;
unsigned long end = KSEG0 + tcache_size;
// Could use flash invalidate perhaps..
while(start < end)
{
cache_unroll(start,Index_Invalidate_T);
start += tc_lsize;
}
}
static inline void flush_tcache_line(unsigned long addr)
{
__asm__ __volatile__
(
".set noreorder\n\t"
".set mips3\n\t"
"cache %1, (%0)\n\t"
".set mips0\n\t"
".set reorder"
:
: "r" (addr),
"i" (Hit_Invalidate_T));
}
/*
* Dummy cache handling routines for machines without boardcaches
*/
static void no_sc_noop(void) {}
static struct bcache_ops no_sc_ops = {
(void *)no_sc_noop, (void *)no_sc_noop,
(void *)no_sc_noop, (void *)no_sc_noop
};
struct bcache_ops *bcops = &no_sc_ops;
// Clean all virtually indexed caches
static inline void sr7100_flush_cache_all_pc(void)
{
unsigned long flags;
__save_and_cli(flags);
blast_dcache(); blast_icache();
__restore_flags(flags);
}
// This clears all caches. It is only used from a syscall..
static inline void sr7100_nuke_caches(void)
{
unsigned long flags;
__save_and_cli(flags);
blast_dcache(); blast_icache(); blast_scache();
if (tcache_size != 0)
blast_tcache();
__restore_flags(flags);
}
/* This is called to clean out a virtual mapping. We only need to flush the
I and D caches since the other two are physically tagged */
static void sr7100_flush_cache_range_pc(struct mm_struct *mm,
unsigned long start,
unsigned long end)
{
if(mm->context != 0) {
unsigned long flags;
#ifdef DEBUG_CACHE
printk("crange[%d,%08lx,%08lx]", (int)mm->context, start, end);
#endif
__save_and_cli(flags);
blast_dcache(); blast_icache();
__restore_flags(flags);
}
}
/*
* On architectures like the Sparc, we could get rid of lines in
* the cache created only by a certain context, but on the MIPS
* (and actually certain Sparc's) we cannot.
* Again, only clean the virtually tagged cache.
*/
static void sr7100_flush_cache_mm_pc(struct mm_struct *mm)
{
if(mm->context != 0) {
#ifdef DEBUG_CACHE
printk("cmm[%d]", (int)mm->context);
#endif
sr7100_flush_cache_all_pc();
}
}
static void sr7100_flush_cache_page_pc(struct vm_area_struct *vma,
unsigned long page)
{
struct mm_struct *mm = vma->vm_mm;
unsigned long flags;
pgd_t *pgdp;
pmd_t *pmdp;
pte_t *ptep;
/*
* If ownes no valid ASID yet, cannot possibly have gotten
* this page into the cache.
*/
if (mm->context == 0)
return;
#ifdef DEBUG_CACHE
printk("cpage[%d,%08lx]", (int)mm->context, page);
#endif
__save_and_cli(flags);
page &= PAGE_MASK;
pgdp = pgd_offset(mm, page);
pmdp = pmd_offset(pgdp, page);
ptep = pte_offset(pmdp, page);
/*
* If the page isn't marked valid, the page cannot possibly be
* in the cache.
*/
if (!(pte_val(*ptep) & _PAGE_VALID))
goto out;
/*
* Doing flushes for another ASID than the current one is
* too difficult since Mips32 caches do a TLB translation
* for every cache flush operation. So we do indexed flushes
* in that case, which doesn't overly flush the cache too much.
*/
if (mm == current->active_mm) {
blast_dcache_page(page);
} else {
/* Do indexed flush, too much work to get the (possible)
* tlb refills to work correctly.
*/
page = (KSEG0 + (page & (dcache_size - 1)));
blast_dcache_page_indexed(page);
}
out:
__restore_flags(flags);
}
/* If the addresses passed to these routines are valid, they are
* either:
*
* 1) In KSEG0, so we can do a direct flush of the page.
* 2) In KSEG2, and since every process can translate those
* addresses all the time in kernel mode we can do a direct
* flush.
* 3) In KSEG1, no flush necessary.
*/
static void sr7100_flush_page_to_ram_pc(struct page *page)
{
blast_dcache_page((unsigned long)page_address(page));
}
/* I-Cache and D-Cache are seperate and virtually tagged, these need to
flush them */
static void sr7100_flush_icache_range(unsigned long start, unsigned long end)
{
flush_cache_all(); // only does i and d, probably excessive
}
static void sr7100_flush_icache_page(struct vm_area_struct *vma,
struct page *page)
{
int address;
if (!(vma->vm_flags & VM_EXEC))
return;
address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1));
blast_icache_page_indexed(address);
}
/* Writeback and invalidate the primary cache dcache before DMA.
See asm-mips/io.h
*/
static void sr7100_dma_cache_wback_inv_sc(unsigned long addr,
unsigned long size)
{
unsigned long end, a;
if (size >= scache_size) {
sr7100_nuke_caches();
return;
}
a = addr & ~(sc_lsize - 1);
end = (addr + size) & ~(sc_lsize - 1);
while (1) {
flush_dcache_line(a);
flush_scache_line(a); // Hit_Writeback_Inv_SD
if (a == end) break;
a += sc_lsize;
}
}
static void sr7100_dma_cache_wback_inv_tc(unsigned long addr,
unsigned long size)
{
unsigned long end, a;
a = addr & ~(sc_lsize - 1);
end = (addr + size) & ~(sc_lsize - 1);
while (1) {
flush_dcache_line(a);
flush_scache_line(a); // Hit_Writeback_Inv_SD
flush_tcache_line(a); // Hit_Invalidate_T
if (a == end) break;
a += sc_lsize;
}
}
/* It is kind of silly to writeback for the inv case.. Oh well */
static void sr7100_dma_cache_inv_sc(unsigned long addr, unsigned long size)
{
unsigned long end, a;
if (size >= scache_size) {
sr7100_nuke_caches();
return;
}
a = addr & ~(sc_lsize - 1);
end = (addr + size) & ~(sc_lsize - 1);
while (1) {
flush_dcache_line(a);
flush_scache_line(a); // Hit_Writeback_Inv_SD
if (a == end) break;
a += sc_lsize;
}
}
static void sr7100_dma_cache_inv_tc(unsigned long addr, unsigned long size)
{
unsigned long end, a;
a = addr & ~(sc_lsize - 1);
end = (addr + size) & ~(sc_lsize - 1);
while (1) {
flush_dcache_line(a);
flush_scache_line(a); // Hit_Writeback_Inv_SD
flush_tcache_line(a); // Hit_Invalidate_T
if (a == end) break;
a += sc_lsize;
}
}
static void sr7100_dma_cache_wback(unsigned long addr, unsigned long size)
{
panic("sr7100_dma_cache_wback called - should not happen.");
}
/*
* While we're protected against bad userland addresses we don't care
* very much about what happens in that case. Usually a segmentation
* fault will dump the process later on anyway ...
*/
static void sr7100_flush_cache_sigtramp(unsigned long addr)
{
protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
protected_flush_icache_line(addr & ~(ic_lsize - 1));
}
/* Detect and size the various caches. */
static void __init probe_icache(unsigned long config,unsigned long config1)
{
unsigned int lsize;
config1 = read_mips32_cp0_config1();
if ((lsize = ((config1 >> 19) & 7)))
mips_cpu.icache.linesz = 2 << lsize;
else
mips_cpu.icache.linesz = lsize;
mips_cpu.icache.sets = 64 << ((config1 >> 22) & 7);
mips_cpu.icache.ways = 1 + ((config1 >> 16) & 7);
ic_lsize = mips_cpu.icache.linesz;
icache_size = mips_cpu.icache.sets * mips_cpu.icache.ways *
ic_lsize;
printk("Primary instruction cache %dkb, linesize %d bytes (%d ways)\n",
icache_size >> 10, ic_lsize, mips_cpu.icache.ways);
}
static void __init probe_dcache(unsigned long config,unsigned long config1)
{
unsigned int lsize;
if ((lsize = ((config1 >> 10) & 7)))
mips_cpu.dcache.linesz = 2 << lsize;
else
mips_cpu.dcache.linesz = lsize;
mips_cpu.dcache.sets = 64 << ((config1 >> 13) & 7);
mips_cpu.dcache.ways = 1 + ((config1 >> 7) & 7);
dc_lsize = mips_cpu.dcache.linesz;
dcache_size =
mips_cpu.dcache.sets * mips_cpu.dcache.ways
* dc_lsize;
printk("Primary data cache %dkb, linesize %d bytes (%d ways)\n",
dcache_size >> 10, dc_lsize, mips_cpu.dcache.ways);
}
static void __init probe_scache(unsigned long config,unsigned long config2)
{
unsigned int lsize;
if ((lsize = ((config2 >> 4) & 7)))
mips_cpu.scache.linesz = 2 << lsize;
else
mips_cpu.scache.linesz = lsize;
mips_cpu.scache.sets = 64 << ((config2 >> 8) & 7);
mips_cpu.scache.ways = 1 + ((config2 >> 0) & 7);
sc_lsize = mips_cpu.scache.linesz;
scache_size = mips_cpu.scache.sets * mips_cpu.scache.ways * sc_lsize;
printk("Secondary cache %dK, linesize %d bytes (%d ways)\n",
scache_size >> 10, sc_lsize, mips_cpu.scache.ways);
}
static void __init probe_tcache(unsigned long config,unsigned long config2)
{
unsigned int lsize;
/* Firmware or prom_init is required to configure the size of the
tertiary cache in config2 and set the TE bit in config2 to signal
the external SRAM chips are present. */
if ((config2 & (1<<28)) == 0)
return;
if ((lsize = ((config2 >> 20) & 7)))
mips_cpu.tcache.linesz = 2 << lsize;
else
mips_cpu.tcache.linesz = lsize;
mips_cpu.tcache.sets = 64 << ((config2 >> 24) & 7);
mips_cpu.tcache.ways = 1 + ((config2 >> 16) & 7);
tc_lsize = mips_cpu.tcache.linesz;
tcache_size = mips_cpu.tcache.sets * mips_cpu.tcache.ways * tc_lsize;
printk("Tertiary cache %dK, linesize %d bytes, blocksize %d "
"bytes (%d ways)\n",
tcache_size >> 10, sc_lsize, tc_lsize, mips_cpu.tcache.ways);
}
static void __init setup_scache_funcs(void)
{
_flush_cache_all = sr7100_flush_cache_all_pc;
___flush_cache_all = sr7100_nuke_caches;
_flush_cache_mm = sr7100_flush_cache_mm_pc;
_flush_cache_range = sr7100_flush_cache_range_pc;
_flush_cache_page = sr7100_flush_cache_page_pc;
_flush_page_to_ram = sr7100_flush_page_to_ram_pc;
_clear_page = (void *)mips32_clear_page_sc;
_copy_page = (void *)mips32_copy_page_sc;
_flush_icache_page = sr7100_flush_icache_page;
if (tcache_size == 0)
{
_dma_cache_wback_inv = sr7100_dma_cache_wback_inv_sc;
_dma_cache_inv = sr7100_dma_cache_inv_sc;
}
else
{
_dma_cache_wback_inv = sr7100_dma_cache_wback_inv_tc;
_dma_cache_inv = sr7100_dma_cache_inv_tc;
}
_dma_cache_wback = sr7100_dma_cache_wback;
}
/* This implements the cache intialization stuff from the SR7100 guide. After
this all the caches will be empty and ready to run. It must be run from
uncached space. */
static void __init clear_enable_caches(unsigned long config)
{
config = (config & (~CONF_CM_CMASK)) | CONF_CM_CACHABLE_NONCOHERENT;
/* Primary cache init (7.1.1)
SR71000 Primary Cache initialization of 4-way, 32 Kbyte line I/D
caches. */
__asm__ __volatile__
(
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips64\n"
// Enable KSEG0 caching
" mtc0 %0, $16\n"
/* It is recommended that parity be disabled during cache
initialization. */
" mfc0 $1, $12\n" // Read CP0 Status Register.
" li $2, 0x00010000\n" // DE Bit.
" or $2, $1, $2\n"
" mtc0 $2, $12\n" // Disable Parity.
" ori $3, %1, 0x1FE0\n" // 256 sets.
" mtc0 $0, $28\n" // Set CP0 Tag_Lo Register
"1:\n"
" cache 8, 0x0000($3)\n" // Index_Store_Tag_I
" cache 8, 0x2000($3)\n" // Index_Store_Tag_I
" cache 8, 0x4000($3)\n" // Index_Store_Tag_I
" cache 8, 0x6000($3)\n" // Index_Store_Tag_I
" cache 9, 0x0000($3)\n" // Index_Store_Tag_D
" cache 9, 0x2000($3)\n" // Index_Store_Tag_D
" cache 9, 0x4000($3)\n" // Index_Store_Tag_D
" cache 9, 0x6000($3)\n" // Index_Store_Tag_D
" bne $3, %1, 1b\n"
" addiu $3, $3, -0x0020\n" // 32 byte cache line
" mtc0 $1, $12\n" // Put original back in Status Register.
".set pop\n"
:
: "r"(config), "r"(KSEG0)
: "$1","$2","$3");
// Fixme: use settings from config register not hardwired
/* Secondary and tertiary flash invalidate (7.5.18)
This code fragment, invalidates (also disables), and
restores (re-enables) the secondary and tertiary caches.
Ensure system is operating in uncached space. */
__asm__ __volatile__
(
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips64\n"
" sync\n" // flush core pipeline
" lw $2, 0(%0)\n" // flush pending accesses
" bne $2, $2, 1f\n" // prevent I-fetches
" nop\n"
"1: mfc0 $1, $16, 2\n" // save current Config2
" li $2, 0x20002000\n" // set flash invalidation bits
" or $2, $1, $2\n"
" mtc0 $2, $16, 2\n" // invalidate & disable caches
" mtc0 $1, $16, 2\n" // restore Config2
".set pop\n"
:
: "r"(KSEG1)
: "$1","$2");
}
void __init ld_mmu_sr7100(void)
{
unsigned long config = read_32bit_cp0_registerx(CP0_CONFIG,0);
unsigned long config1 = read_32bit_cp0_registerx(CP0_CONFIG,1);
unsigned long config2 = read_32bit_cp0_registerx(CP0_CONFIG,2);
void (*kseg1_cec)(unsigned long config) = (void *)KSEG1ADDR(&clear_enable_caches);
// Should never happen
if (!(config & (1 << 31)) || !(config1 & (1 << 31)))
panic("sr7100 does not have necessary config registers");
/* We should be uncached for this.. If the firmware has enabled
the cache it may have dirty data and we really need to flush
it before doing a mass invalidate, on the other hand if the
cache has not been inited flushing it could corrupt ram.. */
if ((config & CONF_CM_CMASK) != CONF_CM_UNCACHED)
{
printk("Turning off cache.\n");
change_cp0_config(CONF_CM_CMASK,CONF_CM_UNCACHED);
// flush core pipeline
__asm__ __volatile__ (" sync\n");
sr7100_flush_cache_all_pc();
// Was the secondary cached turned on?
if ((config2 & (1<<12)) != 0)
blast_scache();
// Tertiary is write through so it is safe
}
probe_icache(config,config1);
probe_dcache(config,config1);
probe_scache(config,config2);
probe_tcache(config,config2);
setup_scache_funcs();
// Make sure the the secondary cache is turned on (always present)
write_32bit_cp0_registerx(CP0_CONFIG,2,config2 | (1<<12));
#ifndef CONFIG_MIPS_UNCACHED
kseg1_cec(config);
#endif
_flush_cache_sigtramp = sr7100_flush_cache_sigtramp;
_flush_icache_range = sr7100_flush_icache_range;
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/Makefile,v
retrieving revision 1.13
retrieving revision 1.14
diff -u -d -r1.13 -r1.14
--- Makefile 2002/01/18 21:22:17 1.13
+++ Makefile 2002/01/19 21:17:35 1.14
@@ -30,6 +30,7 @@
obj-$(CONFIG_CPU_R10000) += pg-andes.o c-andes.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_MIPS32) += pg-mips32.o c-mips32.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_MIPS64) += pg-mips32.o c-mips32.o tlb-r4k.o tlbex-r4k.o
+obj-$(CONFIG_CPU_SR7100) += pg-mips32.o c-sr7100.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_SB1) += pg-sb1.o c-sb1.o tlb-sb1.o tlbex-r4k.o
obj-$(CONFIG_CPU_RC32300) += pg-rc32300.o c-r4k.o tlb-r4k.o tlbex-r4k.o
Index: loadmmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/loadmmu.c,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- loadmmu.c 2002/01/15 00:34:07 1.11
+++ loadmmu.c 2002/01/19 21:17:35 1.12
@@ -61,6 +61,7 @@
extern void ld_mmu_andes(void);
extern void ld_mmu_sb1(void);
extern void ld_mmu_mips32(void);
+extern void ld_mmu_sr7100(void);
extern void r3k_tlb_init(void);
extern void r4k_tlb_init(void);
extern void sb1_tlb_init(void);
@@ -89,6 +90,10 @@
#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
ld_mmu_mips32();
+ r4k_tlb_init();
+#endif
+#if defined(CONFIG_CPU_SR7100)
+ ld_mmu_sr7100();
r4k_tlb_init();
#endif
} else switch(mips_cpu.cputype) {
|
|
From: Paul M. <le...@us...> - 2002-01-19 21:17:38
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv11561/include/asm-mips
Modified Files:
cpu.h mipsregs.h processor.h
Log Message:
Commited Jason Gunthorpe's SR7100 patch, after cleaning it up some.. still not
too happy with the ret_from_irq_sr7100..
Index: cpu.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/cpu.h,v
retrieving revision 1.20
retrieving revision 1.21
diff -u -d -r1.20 -r1.21
--- cpu.h 2002/01/15 00:34:07 1.20
+++ cpu.h 2002/01/19 21:17:35 1.21
@@ -29,6 +29,7 @@
#define PRID_COMP_BROADCOM 0x020000
#define PRID_COMP_ALCHEMY 0x030000
#define PRID_COMP_SIBYTE 0x040000
+#define PRID_COMP_SANDCRAFT 0x050000
/*
* Assigned values for the product ID register. In order to detect a
@@ -79,6 +80,12 @@
#define PRID_IMP_SB1 0x0100
/*
+ * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
+ */
+
+#define PRID_IMP_SR7100 0x0400
+
+/*
* Definitions for 7:0 on legacy processors
*/
@@ -130,7 +137,7 @@
CPU_R5000A, CPU_R4640, CPU_NEVADA, CPU_RM7000, CPU_R5432, CPU_4KC,
CPU_5KC, CPU_R4310, CPU_SB1, CPU_TX3912, CPU_TX3922, CPU_TX3927,
CPU_AU1000, CPU_4KEC, CPU_4KSC, CPU_VR41XX, CPU_R5500, CPU_TX49XX,
- CPU_TX39XX, CPU_R5900, CPU_AU1500, CPU_RC32300, CPU_LAST
+ CPU_TX39XX, CPU_R5900, CPU_AU1500, CPU_RC32300, CPU_SR7100, CPU_LAST
};
#endif
Index: mipsregs.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/mipsregs.h,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- mipsregs.h 2002/01/02 18:10:40 1.14
+++ mipsregs.h 2002/01/19 21:17:35 1.15
@@ -493,6 +493,26 @@
".set\tmips0" \
: : "r" (value))
+#define read_32bit_cp0_registerx(source,sel) \
+({ int __res; \
+ __asm__ __volatile__( \
+ ".set\tpush\n\t" \
+ ".set\treorder\n\t" \
+ ".set\tmips64\n\t" \
+ "mfc0\t%0,"STR(source)","STR(sel)"\n\t" \
+ ".set\tmips0\n\t" \
+ ".set\tpop" \
+ : "=r" (__res)); \
+ __res;})
+
+#define write_32bit_cp0_registerx(register,sel,value) \
+ __asm__ __volatile__( \
+ ".set\tmips64\n\t" \
+ "mtc0\t%0,"STR(register)","STR(sel)"\n\t" \
+ ".set\tmips0\n\t" \
+ "nop" \
+ : : "r" (value));
+
/*
* This should be changed when we get a compiler that support the MIPS32 ISA.
*/
Index: processor.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/processor.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -d -r1.11 -r1.12
--- processor.h 2002/01/02 19:58:02 1.11
+++ processor.h 2002/01/19 21:17:35 1.12
@@ -43,6 +43,7 @@
extern void r3081_wait(void);
extern void r39xx_wait(void);
extern void r4k_wait(void);
+extern void sr7100_wait(void);
extern struct cpuinfo_mips cpu_data[];
extern unsigned int vced_count, vcei_count;
|
|
From: Paul M. <le...@us...> - 2002-01-19 21:17:38
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel
In directory usw-pr-cvs1:/tmp/cvs-serv11561/arch/mips/kernel
Modified Files:
Makefile entry.S setup.c
Log Message:
Commited Jason Gunthorpe's SR7100 patch, after cleaning it up some.. still not
too happy with the ret_from_irq_sr7100..
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/Makefile,v
retrieving revision 1.17
retrieving revision 1.18
diff -u -d -r1.17 -r1.18
--- Makefile 2002/01/15 00:34:06 1.17
+++ Makefile 2002/01/19 21:17:35 1.18
@@ -40,6 +40,7 @@
obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_MIPS32) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_MIPS64) += r4k_fpu.o r4k_switch.o
+obj-$(CONFIG_CPU_SR7100) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_SMP) += smp.o
Index: entry.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/entry.S,v
retrieving revision 1.14
retrieving revision 1.15
diff -u -d -r1.14 -r1.15
--- entry.S 2001/12/10 17:46:47 1.14
+++ entry.S 2002/01/19 21:17:35 1.15
@@ -50,7 +50,29 @@
lw t0, PT_STATUS(sp) # returning to kernel mode?
andi t0, t0, KU_USER
bnez t0, ret_from_sys_call
+EXPORT(ret_from_irq_sr7100)
j restore_all
+
+/* SR7100 Errata: The wait instruction that does not advance EPC. The solution
+ is to check if epc is pointing at a wait instruction and if so, skip it.
+ This must be after ret_from_irq. The setup code will nop out the jump above
+ so we fall through. wait instructions are only fixed if they are in the
+ kernel */
+#ifdef CONFIG_CPU_SR7100
+ // Fetch EPC
+ lw t0,PT_EPC(sp)
+
+ // Is the instruction a wait?
+ li t2,0x42000000
+ lw t1,0(t0)
+ ori t2,t2,0x20
+ bne t1,t2,restore_all
+
+ // Yep, go to the next instruction
+ addu t1,t0,4
+ sw t1,PT_EPC(sp)
+ j restore_all
+#endif
reschedule: jal schedule
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v
retrieving revision 1.47
retrieving revision 1.48
diff -u -d -r1.47 -r1.48
--- setup.c 2002/01/18 21:22:15 1.47
+++ setup.c 2002/01/19 21:17:35 1.48
@@ -46,6 +46,7 @@
#ifndef CONFIG_SMP
struct cpuinfo_mips cpu_data[1];
#endif
+#include <asm/cacheops.h>
/*
* Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -121,6 +122,7 @@
extern void SetUpBootInfo(void);
extern void loadmmu(void);
extern asmlinkage void start_kernel(void);
+extern asmlinkage void ret_from_irq_sr7100(void);
extern void prom_init(int, char **, char **, int *);
static struct resource code_resource = { "Kernel code" };
@@ -153,6 +155,10 @@
cpu_wait = r4k_wait;
printk(" available.\n");
break;
+ case CPU_SR7100:
+ cpu_wait = sr7100_wait;
+ printk(" errata work around.\n");
+ break;
default:
printk(" unavailable.\n");
break;
@@ -536,6 +542,20 @@
break;
}
break;
+ case PRID_COMP_SANDCRAFT:
+ mips_cpu.cputype = CPU_UNKNOWN;
+ switch (mips_cpu.processor_id & 0xff00) {
+ case PRID_IMP_SR7100:
+ mips_cpu.cputype = CPU_SR7100;
+ mips_cpu.isa_level = MIPS_CPU_ISA_M64;
+ mips_cpu.options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
+ MIPS_CPU_4KTLB | MIPS_CPU_FPU |
+ MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
+ MIPS_CPU_MCHECK;
+ mips_cpu.scache.ways = 8;
+ break;
+ }
+ break;
default:
mips_cpu.cputype = CPU_UNKNOWN;
}
@@ -1062,6 +1082,41 @@
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
+}
+
+/*
+ * Fix the sr7100 wait errata. We have a special ret_from_irq that is executed
+ * when a jump is converted to a nop. Before we wait we do that conversion.
+ * This engages the code that detects the errata. This way we don't loose any
+ * speed in the normal case. Though it does make the timing race with wait
+ * longer..
+ */
+void sr7100_wait(void)
+{
+ u32 *jump = ((u32 *)&ret_from_irq_sr7100);
+
+ __asm__ __volatile__ (
+ ".set push\n\t"
+ ".set noat\n\t"
+ ".set noreorder\n\t"
+ ".set mips3\n\t"
+ "lw $1,0(%0)\n\t"
+ "sw $0,0(%0)\n\t"
+
+ // No snoopy i/d cache..
+ "cache %1,0(%0)\n\t"
+ "cache %2,0(%0)\n\t"
+
+ "wait\n\t"
+ "sw $1,0(%0)\n\t"
+
+ "cache %1,0(%0)\n\t"
+ "cache %2,0(%0)\n\t"
+
+ ".set pop\n\t"
+ :
+ : "r" (jump), "i" (Hit_Writeback_D), "i" (Hit_Invalidate_I)
+ : "$1");
}
int __init fpu_disable(char *s)
|
|
From: Steve L. <slo...@us...> - 2002-01-19 01:47:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv2097
Modified Files:
setup.c
Log Message:
Added initial ramdisk support.
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- setup.c 2002/01/17 21:07:24 1.4
+++ setup.c 2002/01/19 01:47:29 1.5
@@ -52,6 +52,11 @@
extern void __init rc32334_pcibridge_init(void);
#endif
+#ifdef CONFIG_BLK_DEV_INITRD
+extern unsigned long initrd_start, initrd_end;
+extern void * __rd_start, * __rd_end;
+#endif
+
int idtprintf(const char *fmt, ...)
{
@@ -224,6 +229,12 @@
// clear out any wired entries
write_32bit_cp0_register(CP0_WIRED, 0);
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
+ initrd_start = (unsigned long)&__rd_start;
+ initrd_end = (unsigned long)&__rd_end;
+#endif
#if 0
printk(__FUNCTION__ ": CPU_PORT_WIDTH = 0x%08x\n",
|
|
From: Steve L. <slo...@us...> - 2002-01-19 01:35:20
|
Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv31221/include/asm-mips
Modified Files:
serial.h
Log Message:
Added CONFIG_CPU_RC32334 and CONFIG_CPU_RC32355 so code can distinguish
between RC32300 core and extended features of above cpu's.
Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/serial.h,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -d -r1.10 -r1.11
--- serial.h 2002/01/17 21:06:46 1.10
+++ serial.h 2002/01/19 01:35:17 1.11
@@ -159,7 +159,7 @@
#define AU1000_SERIAL_PORT_DEFNS
#endif
-#ifdef CONFIG_CPU_RC32300
+#ifdef CONFIG_IDT_79S334
#include <asm/rc32300/rc32300.h>
#define RC32300_SERIAL_PORT_DEFNS \
{ baud_base: RC32300_BASE_BAUD, \
|
|
From: Steve L. <slo...@us...> - 2002-01-19 01:35:20
|
Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/common In directory usw-pr-cvs1:/tmp/cvs-serv31221/arch/mips/rc32300/common Modified Files: reset.c Log Message: Added CONFIG_CPU_RC32334 and CONFIG_CPU_RC32355 so code can distinguish between RC32300 core and extended features of above cpu's. Index: reset.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/reset.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -d -r1.3 -r1.4 --- reset.c 2002/01/17 21:07:24 1.3 +++ reset.c 2002/01/19 01:35:17 1.4 @@ -44,7 +44,7 @@ flush_cache_all(); write_32bit_cp0_register(CP0_WIRED, 0); -#ifdef CONFIG_IDT_79S334 +#ifdef CONFIG_CPU_RC32334 // Trigger the WatchDog Timer (Timer 3) to warm reset outl(0, TIMER0_CNTL + 3*TIMER_REG_OFFSET); outl(0xd8, CPU_IP_BUSERR_CNTL); |
|
From: Steve L. <slo...@us...> - 2002-01-19 01:35:20
|
Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv31221/arch/mips/rc32300/79S334
Modified Files:
irq.c
Log Message:
Added CONFIG_CPU_RC32334 and CONFIG_CPU_RC32355 so code can distinguish
between RC32300 core and extended features of above cpu's.
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/irq.c,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -d -r1.6 -r1.7
--- irq.c 2002/01/17 21:07:24 1.6
+++ irq.c 2002/01/19 01:35:17 1.7
@@ -316,7 +316,7 @@
}
static struct hw_interrupt_type rc32300_irq_type = {
- "RC32300",
+ "RC32334",
startup_irq,
shutdown_irq,
rc32300_enable_irq,
|
|
From: Steve L. <slo...@us...> - 2002-01-19 01:35:19
|
Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv31221/arch/mips
Modified Files:
config.in
Log Message:
Added CONFIG_CPU_RC32334 and CONFIG_CPU_RC32355 so code can distinguish
between RC32300 core and extended features of above cpu's.
Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.80
retrieving revision 1.81
diff -u -d -r1.80 -r1.81
--- config.in 2002/01/18 21:22:11 1.80
+++ config.in 2002/01/19 01:35:17 1.81
@@ -320,6 +320,7 @@
define_int MAX_HWIFS 1
fi
if [ "$CONFIG_IDT_79S334" = "y" ]; then
+ define_bool CONFIG_CPU_RC32334 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_PCI y
@@ -332,6 +333,7 @@
fi
if [ "$CONFIG_IDT_79EB355" = "y" ]; then
+ define_bool CONFIG_CPU_RC32355 y
define_bool CONFIG_NEW_IRQ y
define_bool CONFIG_NEW_TIME_C y
define_bool CONFIG_PCI y
|
|
From: Paul M. <le...@us...> - 2002-01-18 21:27:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/mm
In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/mm
Modified Files:
Makefile
Added Files:
pg-vr4131.c
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.
--- NEW FILE: pg-vr4131.c ---
/*
* arch/mips/mm/pg-vr4131.c
*
* MMU/Cache routines for early revisions of the NEC Vr4131 processor.
*
* Copyright (C) 2001, 2002 Paul Mundt <le...@ch...>
* Copyright (C) 2001 NEC Electronics
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/cacheops.h>
/*
* Zero an entire page on Vr4131 processor. Basically a simple unrolled loop
* should do the job but we want more performance by saving memory bus
* bandwidth. We have five flavours of the routine available for:
*
* - 16byte cachelines and no second level cache
* - 32byte cachelines second level cache
* - a version which handles the buggy R4600 v1.x
* - a version which handles the buggy R4600 v2.0
* - Finally a last version without fancy cache games for the SC and MC
* versions of R4000 and R4400.
*/
void r4k_clear_page_d16(void *page)
{
unsigned long reg1;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips3\n\t"
"mfc0 %1,$16\n\t"
"nop\n\t"
"mtc0\t$0,$28\n\t"
"mtc0\t$0,$29\n\t"
"nop\n\t"
"daddiu\t$1,%0,%3\n"
"1:\tcache\t0x09,(%0)\n\t"
"cache\t%4,(%0)\n\t"
"sd\t$0,(%0)\n\t"
"sd\t$0,8(%0)\n\t"
"cache\t0x09,(%0)\n\t"
"cache\t0x09,16(%0)\n\t"
"cache\t%4,16(%0)\n\t"
"sd\t$0,16(%0)\n\t"
"sd\t$0,24(%0)\n\t"
"daddiu\t%0,64\n\t"
"cache\t0x09,16(%0)\n\t"
"cache\t0x09,-32(%0)\n\t"
"cache\t%4,-32(%0)\n\t"
"sd\t$0,-32(%0)\n\t"
"sd\t$0,-24(%0)\n\t"
"cache\t0x09,-32(%0)\n\t"
"cache\t0x09,-16(%0)\n\t"
"cache\t%4,-16(%0)\n\t"
"sd\t$0,-16(%0)\n\t"
"sd\t$0,-8(%0)\n\t"
"cache\t0x09,-16(%0)\n\t"
"nop\n\t"
"bne\t$1,%0,1b\n\t"
"nop\n\t"
"mtc0 %1,$16\n\t"
"nop\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
:"=r" (page), "=&r" (reg1)
:"0" (page),
"I" (PAGE_SIZE),
"i" (Index_Writeback_Inv_D)
:"$1", "memory");
}
void r4k_copy_page_d16(void *to, void *from)
{
unsigned long dummy1, dummy2;
unsigned long reg1, reg2, reg3, reg4;
__asm__ __volatile__(
".set\tnoreorder\n\t"
".set\tnoat\n\t"
".set\tmips3\n\t"
"daddiu\t$1,%0,%8\n"
"1:\tcache\t%9,(%0)\n\t"
"lw\t%2,(%1)\n\t"
"lw\t%3,4(%1)\n\t"
"lw\t%4,8(%1)\n\t"
"lw\t%5,12(%1)\n\t"
"sw\t%2,(%0)\n\t"
"sw\t%3,4(%0)\n\t"
"sw\t%4,8(%0)\n\t"
"sw\t%5,12(%0)\n\t"
"cache\t%9,16(%0)\n\t"
"lw\t%2,16(%1)\n\t"
"lw\t%3,20(%1)\n\t"
"lw\t%4,24(%1)\n\t"
"lw\t%5,28(%1)\n\t"
"sw\t%2,16(%0)\n\t"
"sw\t%3,20(%0)\n\t"
"sw\t%4,24(%0)\n\t"
"sw\t%5,28(%0)\n\t"
"cache\t%9,32(%0)\n\t"
"daddiu\t%0,64\n\t"
"daddiu\t%1,64\n\t"
"lw\t%2,-32(%1)\n\t"
"lw\t%3,-28(%1)\n\t"
"lw\t%4,-24(%1)\n\t"
"lw\t%5,-20(%1)\n\t"
"sw\t%2,-32(%0)\n\t"
"sw\t%3,-28(%0)\n\t"
"sw\t%4,-24(%0)\n\t"
"sw\t%5,-20(%0)\n\t"
"cache\t%9,-16(%0)\n\t"
"lw\t%2,-16(%1)\n\t"
"lw\t%3,-12(%1)\n\t"
"lw\t%4,-8(%1)\n\t"
"lw\t%5,-4(%1)\n\t"
"sw\t%2,-16(%0)\n\t"
"sw\t%3,-12(%0)\n\t"
"sw\t%4,-8(%0)\n\t"
"bne\t$1,%0,1b\n\t"
"sw\t%5,-4(%0)\n\t"
".set\tmips0\n\t"
".set\tat\n\t"
".set\treorder"
:"=r" (dummy1), "=r" (dummy2),
"=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
:"0" (to), "1" (from),
"I" (PAGE_SIZE),
"i" (Index_Writeback_Inv_D));
}
void r4k_clear_page_d32(void *page)
{
}
void r4k_clear_page_r4600_v1(void *page)
{
}
void r4k_clear_page_r4600_v2(void *page)
{
}
void r4k_clear_page_s16(void *page)
{
}
void r4k_clear_page_s32(void *page)
{
}
void r4k_clear_page_s64(void *page)
{
}
void r4k_clear_page_s128(void *page)
{
}
void r4k_copy_page_d32(void *to, void *from)
{
}
void r4k_copy_page_r4600_v1(void *to, void *from)
{
}
void r4k_copy_page_r4600_v2(void *to, void *from)
{
}
void r4k_copy_page_s16(void *to, void *from)
{
}
void r4k_copy_page_s32(void *to, void *from)
{
}
void r4k_copy_page_s64(void *to, void *from)
{
}
void r4k_copy_page_s128(void *to, void *from)
{
}
void pgd_init(unsigned long page)
{
unsigned long *p = (unsigned long *)page;
int i;
for (i = 0; i < USER_PTRS_PER_PGD; i += 8) {
p[i + 0] = (unsigned long)invalid_pte_table;
p[i + 1] = (unsigned long)invalid_pte_table;
p[i + 2] = (unsigned long)invalid_pte_table;
p[i + 3] = (unsigned long)invalid_pte_table;
p[i + 4] = (unsigned long)invalid_pte_table;
p[i + 5] = (unsigned long)invalid_pte_table;
p[i + 6] = (unsigned long)invalid_pte_table;
p[i + 7] = (unsigned long)invalid_pte_table;
}
}
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/mm/Makefile,v
retrieving revision 1.12
retrieving revision 1.13
diff -u -d -r1.12 -r1.13
--- Makefile 2002/01/15 00:34:07 1.12
+++ Makefile 2002/01/18 21:22:17 1.13
@@ -22,7 +22,6 @@
obj-$(CONFIG_CPU_TX49XX) += pg-r4k.o c-tx49.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_R4300) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_R4X00) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
-obj-$(CONFIG_CPU_VR41XX) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_R5000) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_R5900) += pg-r5900.o c-r5900.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_NEVADA) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
@@ -33,6 +32,12 @@
obj-$(CONFIG_CPU_MIPS64) += pg-mips32.o c-mips32.o tlb-r4k.o tlbex-r4k.o
obj-$(CONFIG_CPU_SB1) += pg-sb1.o c-sb1.o tlb-sb1.o tlbex-r4k.o
obj-$(CONFIG_CPU_RC32300) += pg-rc32300.o c-r4k.o tlb-r4k.o tlbex-r4k.o
+
+ifdef CONFIG_VR4131_CACHE_FIX
+obj-$(CONFIG_CPU_VR41XX) += pg-vr4131.o c-r4k.o tlb-r4k.o tlbex-r4k.o
+else
+obj-$(CONFIG_CPU_VR41XX) += pg-r4k.o c-r4k.o tlb-r4k.o tlbex-r4k.o
+endif
obj-$(CONFIG_SGI_IP22) += umap.o
obj-$(CONFIG_BAGET_MIPS) += umap.o
|
|
From: Paul M. <le...@us...> - 2002-01-18 21:27:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/kernel In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/kernel Modified Files: setup.c Log Message: NEC Vr4122/Vr4131/Vrc4173 updates. Index: setup.c =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/kernel/setup.c,v retrieving revision 1.46 retrieving revision 1.47 diff -u -d -r1.46 -r1.47 --- setup.c 2002/01/15 00:34:06 1.46 +++ setup.c 2002/01/18 21:22:15 1.47 @@ -700,7 +700,8 @@ void swarm_setup(void); void hp_setup(void); void idt_setup(void); - + void casio_be300_setup(void); + unsigned long bootmap_size; unsigned long start_pfn, max_pfn, first_usable_pfn; #ifdef CONFIG_BLK_DEV_INITRD @@ -814,6 +815,11 @@ #ifdef CONFIG_NEC_MOBILEPRO_780 case MACH_GROUP_NEC_VR41XX: nec_mobilepro_setup(); + break; +#endif +#ifdef CONFIG_CASIO_BE300 + case MACH_GROUP_NEC_VR41XX: + casio_be300_setup(); break; #endif #ifdef CONFIG_MIPS_EV96100 |
|
From: Paul M. <le...@us...> - 2002-01-18 21:27:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/common
In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/vr4122/common
Modified Files:
Makefile cmu.c icu.c int-handler.S time.c
Added Files:
pci_ops.c vrc4173.c
Removed Files:
pci.c
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.
--- NEW FILE: pci_ops.c ---
/*
* BRIEF MODULE DESCRIPTION
* NEC VR4122 PCIU specific PCI support.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/types.h>
#include <asm/io.h>
#include <asm/vr4122/vr4122.h>
static inline int vr4122_pci_config_access(struct pci_dev *dev, int where)
{
unsigned char bus = dev->bus->number;
unsigned char dev_fn = dev->devfn;
if (bus == 0) {
/*
* Type 0 configuration
*/
if (PCI_SLOT(dev_fn) < 11 || PCI_SLOT(dev_fn) > 31 || where > 255)
return -1;
writel((1UL << PCI_SLOT(dev_fn))|
(PCI_FUNC(dev_fn) << 8) |
(where & 0xfc),
VR4122_PCICONFAREG);
}
else {
/*
* Type 1 configuration
*/
if (bus > 255 || PCI_SLOT(dev_fn) > 31 || where > 255)
return -1;
writel((bus << 16) |
(dev_fn << 8) |
(where & 0xfc) |
1UL,
VR4122_PCICONFAREG);
}
return 0;
}
static int vr4122_pci_read_config_byte(struct pci_dev *dev, int where, u8 *val)
{
u32 data;
*val = 0xff;
if (vr4122_pci_config_access(dev, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
data = readl(VR4122_PCICONFDREG);
*val = (u8)(data >> ((where & 3) << 3));
return PCIBIOS_SUCCESSFUL;
}
static int vr4122_pci_read_config_word(struct pci_dev *dev, int where, u16 *val)
{
u32 data;
*val = 0xffff;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (vr4122_pci_config_access(dev, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
data = readl(VR4122_PCICONFDREG);
*val = (u16)(data >> ((where & 2) << 3));
return PCIBIOS_SUCCESSFUL;
}
static int vr4122_pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
{
*val = 0xffffffff;
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (vr4122_pci_config_access(dev, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
*val = readl(VR4122_PCICONFDREG);
return PCIBIOS_SUCCESSFUL;
}
static int vr4122_pci_write_config_byte(struct pci_dev *dev, int where, u8 val)
{
u32 data;
int shift;
if (vr4122_pci_config_access(dev, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
data = readl(VR4122_PCICONFDREG);
shift = (where & 3) << 3;
data &= ~(0xff << shift);
data |= (((u32)val) << shift);
writel(data, VR4122_PCICONFDREG);
return PCIBIOS_SUCCESSFUL;
}
static int vr4122_pci_write_config_word(struct pci_dev *dev, int where, u16 val)
{
u32 data;
int shift;
if (where & 1)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (vr4122_pci_config_access(dev, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
data = readl(VR4122_PCICONFDREG);
shift = (where & 2) << 3;
data &= ~(0xffff << shift);
data |= (((u32)val) << shift);
writel(data, VR4122_PCICONFDREG);
return PCIBIOS_SUCCESSFUL;
}
static int vr4122_pci_write_config_dword(struct pci_dev *dev, int where, u32 val)
{
if (where & 3)
return PCIBIOS_BAD_REGISTER_NUMBER;
if (vr4122_pci_config_access(dev, where) < 0)
return PCIBIOS_DEVICE_NOT_FOUND;
writel(val, VR4122_PCICONFDREG);
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops vr4122_pci_ops = {
vr4122_pci_read_config_byte,
vr4122_pci_read_config_word,
vr4122_pci_read_config_dword,
vr4122_pci_write_config_byte,
vr4122_pci_write_config_word,
vr4122_pci_write_config_dword
};
#endif /* CONFIG_PCI */
--- NEW FILE: vrc4173.c ---
/*
* BRIEF MODULE DESCRIPTION
* Setup for NEC VRC4173.
*
* Copyright 2001,2002 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/module.h>
#include <asm/pci_channel.h>
#include <asm/vr4122/eagle.h>
#include <asm/vrc4173.h>
extern int early_read_config_byte(struct pci_channel *hose, int top_bus, int bus,
int devfn, int offset, u8 *val);
extern int early_read_config_word(struct pci_channel *hose, int top_bus, int bus,
int devfn, int offset, u16 *val);
extern int early_read_config_dword(struct pci_channel *hose, int top_bus, int bus,
int devfn, int offset, u32 *val);
extern int early_write_config_byte(struct pci_channel *hose, int top_bus, int bus,
int devfn, int offset, u8 val);
extern int early_write_config_word(struct pci_channel *hose, int top_bus, int bus,
int devfn, int offset, u16 val);
extern int early_write_config_dword(struct pci_channel *hose, int top_bus, int bus,
int devfn, int offset, u32 val);
struct pci_dev *vrc4173_pci_dev = NULL;
EXPORT_SYMBOL(vrc4173_pci_dev);
unsigned long vrc4173_io_port_base = 0;
EXPORT_SYMBOL(vrc4173_io_port_base);
void __init vrc4173_bcu_init(void)
{
struct pci_channel *hose;
int top_bus;
int current_bus;
u32 pci_devfn, cmdstat, base;
u16 vid, did, cmu_mask;
hose = mips_pci_channels;
top_bus = 0;
current_bus = 0;
for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
early_read_config_word(hose, top_bus, current_bus, pci_devfn,
PCI_VENDOR_ID, &vid);
if (vid != PCI_VENDOR_ID_NEC)
continue;
early_read_config_word(hose, top_bus, current_bus, pci_devfn,
PCI_DEVICE_ID, &did);
if (did != PCI_DEVICE_ID_NEC_VRC4173_BCU)
continue;
/*
* Initialized NEC VRC4173 Bus Control Unit
*/
early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_COMMAND, &cmdstat);
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER);
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_LATENCY_TIMER, 0x80);
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_BASE_ADDRESS_0, VR4122_PCI_IO_START);
early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
PCI_BASE_ADDRESS_0, &base);
base &= PCI_BASE_ADDRESS_IO_MASK;
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_VRC4173_BUSCNT, VRC4173_BUSCNT_POSTON);
/* CARDU1 IDSEL = AD12, CARDU2 IDSEL = AD13 */
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
PCI_VRC4173_IDSELNUM, 0);
outw(VRC4173_CMUCLKMSK_MSK48MOSC, base + VRC4173_CMUCLKMSK);
cmu_mask = inw(base + VRC4173_CMUCLKMSK);
cmu_mask |= VRC4173_CMUCLKMSK_MSK48MPIN;
outw(cmu_mask, base + VRC4173_CMUCLKMSK);
outw(0x000f, base + VRC4173_CMUSRST);
cmu_mask = inw(base + VRC4173_CMUCLKMSK);
#ifdef CONFIG_USB_OHCI
cmu_mask |= (VRC4173_CMUCLKMSK_MSK48MUSB | VRC4173_CMUCLKMSK_MSKUSB);
#endif
#ifdef CONFIG_PCMCIA
cmu_mask |= (VRC4173_CMUCLKMSK_MSKCARD1 | VRC4173_CMUCLKMSK_MSKCARD2);
#endif
#ifdef CONFIG_SOUND
cmu_mask |= VRC4173_CMUCLKMSK_MSKAC97;
#endif
outw(cmu_mask, base + VRC4173_CMUCLKMSK);
cmu_mask = inw(base + VRC4173_CMUCLKMSK); /* dummy read */
outw(0x0000, base + VRC4173_CMUSRST);
}
}
#endif
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- Makefile 2001/10/08 21:50:42 1.3
+++ Makefile 2002/01/18 21:22:17 1.4
@@ -1,5 +1,5 @@
#
-# Copyright 2001 MontaVista Software Inc.
+# Copyright 2001,2002 MontaVista Software Inc.
# Author: Yoichi Yuasa
# yy...@mv... or so...@mv...
#
@@ -19,10 +19,12 @@
O_TARGET := vr4122.o
-export-objs := serial.o
-obj-y := cmu.o icu.o int-handler.o reset.o time.o
+export-objs := vrc4173.o
+obj-y := cmu.o icu.o int-handler.o reset.o
-obj-$(CONFIG_PCI) += pci.o
+obj-$(CONFIG_VR4122_TIME_C) += time.o
+obj-$(CONFIG_PCI) += pci_ops.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
+obj-$(CONFIG_VRC4173) += vrc4173.o
include $(TOPDIR)/Rules.make
Index: cmu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/cmu.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- cmu.c 2001/09/22 04:27:15 1.1
+++ cmu.c 2002/01/18 21:22:18 1.2
@@ -1,8 +1,8 @@
/*
* BRIEF MODULE DESCRIPTION
- * NEC Vr4122 Clock Mask Unit routines.
+ * NEC VR4122 Clock Mask Unit routines.
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001,2002 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
@@ -26,15 +26,12 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include <linux/init.h>
-#include <linux/kernel.h>
#include <linux/spinlock.h>
-#include <linux/interrupt.h>
#include <asm/io.h>
#include <asm/vr4122/vr4122.h>
-spinlock_t vr4122_cmu_lock = SPIN_LOCK_UNLOCKED;
+rwlock_t vr4122_cmu_lock = RW_LOCK_UNLOCKED;
void vr4122_clock_supply(unsigned short mask)
{
Index: icu.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/icu.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- icu.c 2001/12/14 18:26:22 1.2
+++ icu.c 2002/01/18 21:22:19 1.3
@@ -1,8 +1,8 @@
/*
* BRIEF MODULE DESCRIPTION
- * Interrupt dispatcher for NEC Vr4122 Interrupt Control Unit.
+ * Interrupt dispatcher for NEC VR4122 Interrupt Control Unit.
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001,2002 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
@@ -26,16 +26,47 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/config.h>
+#include <linux/pci.h>
+
#include <asm/io.h>
#include <asm/types.h>
#include <asm/vr4122/vr4122.h>
+#ifdef CONFIG_VRC4173
+#include <asm/vrc4173.h>
+#endif
extern unsigned int do_IRQ(int irq, struct pt_regs *regs);
+#ifdef CONFIG_VRC4173
+
+void vrc4173_icu_irqdispatch(struct pt_regs *regs)
+{
+ u16 pend, mask;
+ int i;
+
+ pend = vrc4173_inw(VRC4173_SYSINT1REG);
+ mask = vrc4173_inw(VRC4173_MSYSINT1REG);
+
+ pend &= mask;
+
+ if (pend) {
+ for (i = 0; i < 16; i++) {
+ if (pend & 0x0001) {
+ do_IRQ(VRC4173_IRQ_BASE + i, regs);
+ return;
+ }
+ pend >>= 1;
+ }
+ }
+}
+
+#endif
+
static void giuint_irqdispatch(struct pt_regs *regs)
{
u16 pendl, pendh, maskl, maskh;
- int i = 0;
+ int i;
pendl = readw(VR4122_GIUINTLREG);
pendh = readw(VR4122_GIUINTHREG);
@@ -48,7 +79,13 @@
if (pendl) {
for (i = 0; i < 16; i++) {
if (pendl & 0x0001) {
- do_IRQ(VR4122_GIUINTL_IRQ_BASE + i, regs);
+#ifdef CONFIG_VRC4173
+ if (vrc4173_pci_dev &&
+ (vrc4173_pci_dev->irq == (VR4122_GIUINTL_IRQ_BASE + i)))
+ vrc4173_icu_irqdispatch(regs);
+ else
+#endif
+ do_IRQ(VR4122_GIUINTL_IRQ_BASE + i, regs);
return;
}
pendl >>= 1;
@@ -65,7 +102,7 @@
}
}
-asmlinkage void int0_icu_irqdispatch(struct pt_regs *regs)
+asmlinkage void icu_irqdispatch(struct pt_regs *regs)
{
u16 pend1, pend2, mask1, mask2;
int i;
Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/int-handler.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- int-handler.S 2001/10/08 21:50:42 1.1
+++ int-handler.S 2002/01/18 21:22:19 1.2
@@ -1,6 +1,6 @@
/*
* BRIEF MODULE DESCRIPTION
- * Interrupt dispatcher for NEC Vr4122 CPU core.
+ * Interrupt dispatcher for NEC VR4122 CPU core.
*
* Copyright 2001 MontaVista Software Inc.
* Author Yoichi Yuasa
@@ -82,7 +82,7 @@
andi t1, t0, CAUSEF_IP2 # check for IP2
beqz t1, 3f
move a0, sp
- jal int0_icu_irqdispatch
+ jal icu_irqdispatch
nop
j ret_from_irq
nop
Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/common/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c 2002/01/15 17:09:57 1.3
+++ time.c 2002/01/18 21:22:19 1.4
@@ -1,8 +1,8 @@
/*
* BRIEF MODULE DESCRIPTION
- * NEC Vr4122 RTC Unit routines.
+ * NEC VR4122 RTC Unit routines.
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001,2002 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
@@ -26,14 +26,14 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/interrupt.h>
+#include <linux/irq.h>
#include <linux/spinlock.h>
#include <asm/io.h>
#include <asm/param.h>
#include <asm/time.h>
#include <asm/vr4122/vr4122.h>
-
-extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
spinlock_t vr4122_rtc_lock = SPIN_LOCK_UNLOCKED;
--- pci.c DELETED ---
|
|
From: Paul M. <le...@us...> - 2002-01-18 21:27:32
|
Update of /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle
In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/vr4122/eagle
Modified Files:
Makefile irq.c prom.c setup.c
Added Files:
pci_fixup.c
Removed Files:
pci.c
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.
--- NEW FILE: pci_fixup.c ---
/*
* BRIEF MODULE DESCRIPTION
* NEC Eagle Board specific PCI fixups.
*
* Copyright 2001 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/config.h>
#ifdef CONFIG_PCI
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/pci_channel.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
#ifdef CONFIG_VRC4173
#include <asm/vrc4173.h>
#endif
#define DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...)
#endif
static struct resource vr4122_pci_io_resource = {
"PCI I/O space",
VR4122_PCI_IO_START,
VR4122_PCI_IO_END,
IORESOURCE_IO
};
static struct resource vr4122_pci_mem_resource = {
"PCI memory space",
VR4122_PCI_MEM_START,
VR4122_PCI_MEM_END,
IORESOURCE_MEM
};
extern struct pci_ops vr4122_pci_ops;
struct pci_channel mips_pci_channels[] = {
{&vr4122_pci_ops, &vr4122_pci_io_resource, &vr4122_pci_mem_resource, 0, 256},
{NULL, NULL, NULL, 0, 0}
};
void __init pcibios_fixup_resources(struct pci_dev *dev)
{
}
void __init pcibios_fixup(void)
{
}
void __init pcibios_fixup_irqs(void)
{
struct pci_dev *dev;
unsigned int devnum;
pci_for_each_dev(dev) {
dev->irq = VR4122_IRQ_PCI;
switch (dev->vendor) {
#ifdef CONFIG_VRC4173
case PCI_VENDOR_ID_NEC:
switch (dev->device) {
case PCI_DEVICE_ID_NEC_VRC4173_BCU:
dev->irq = VR4122_IRQ_VRC4173;
break;
case PCI_DEVICE_ID_NEC_VRC5477_AC97:
dev->irq = VRC4173_IRQ_AC97;
break;
case PCI_DEVICE_ID_NEC_VRC4173_CARDU:
devnum = dev->devfn >> 3;
if (devnum == 12)
dev->irq = VRC4173_IRQ_PCMCIA1;
if (devnum == 13)
dev->irq = VRC4173_IRQ_PCMCIA2;
break;
case PCI_DEVICE_ID_NEC_VRC4173_USB:
dev->irq = VRC4173_IRQ_USB;
break;
}
break;
#endif
case PCI_VENDOR_ID_MEDIAQ:
if (dev->device == PCI_DEVICE_ID_MEDIAQ_MQ200)
dev->irq = VR4122_IRQ_MQ200;
break;
case PCI_VENDOR_ID_AMD:
if (dev->device == PCI_DEVICE_ID_AMD_LANCE ||
dev->device == PCI_DEVICE_ID_AMD_LANCE_HOME)
dev->irq = VR4122_IRQ_LANCE;
break;
}
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
}
unsigned int pcibios_assign_all_busses(void)
{
return 0;
}
#endif
Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 2001/09/22 04:27:15 1.1
+++ Makefile 2002/01/18 21:22:19 1.2
@@ -1,5 +1,5 @@
#
-# Copyright 2001 MontaVista Software Inc.
+# Copyright 2001,2002 MontaVista Software Inc.
# Author: Yoichi Yuasa
# yy...@mv... or so...@mv...
#
@@ -19,6 +19,8 @@
all: eagle.o
-obj-y := irq.o pci.o prom.o setup.o
+obj-y := irq.o prom.o setup.o
+
+obj-$(CONFIG_PCI) += pci_fixup.o
include $(TOPDIR)/Rules.make
Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq.c 2002/01/02 18:19:35 1.4
+++ irq.c 2002/01/18 21:22:20 1.5
@@ -2,7 +2,7 @@
* BRIEF MODULE DESCRIPTION
* NEC Eagle interrupt routines.
*
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001,2002 MontaVista Software Inc.
* Author: Yoichi Yuasa
* yy...@mv... or so...@mv...
*
@@ -26,17 +26,16 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include <linux/delay.h>
#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/irq.h>
#include <linux/interrupt.h>
-#include <linux/kernel.h>
#include <asm/io.h>
#include <asm/mipsregs.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
+#ifdef CONFIG_VRC4173
+#include <asm/vrc4173.h>
+#endif
#ifdef CONFIG_REMOTE_DEBUG
extern void set_debug_traps(void);
@@ -44,6 +43,7 @@
#endif
extern asmlinkage void vr4122_handle_int(void);
+extern void __init init_generic_irq(void);
static void enable_cpucore_irq(unsigned int irq)
{
@@ -61,8 +61,8 @@
return 0; /* never anything pending */
}
-#define shutdown_cpucore_irq disable_cpucore_irq
-#define mask_and_ack_cpucore_irq disable_cpucore_irq
+#define shutdown_cpucore_irq disable_cpucore_irq
+#define ack_cpucore_irq disable_cpucore_irq
static void end_cpucore_irq(unsigned int irq)
{
@@ -76,7 +76,7 @@
shutdown_cpucore_irq,
enable_cpucore_irq,
disable_cpucore_irq,
- mask_and_ack_cpucore_irq,
+ ack_cpucore_irq,
end_cpucore_irq,
NULL
};
@@ -88,7 +88,7 @@
unsigned short val;
val = readw(VR4122_MSYSINT1REG);
- val |= (u16)1 << (irq - 8);
+ val |= (u16)1 << (irq - VR4122_SYSINT1_IRQ_BASE);
writew(val, VR4122_MSYSINT1REG);
}
@@ -97,7 +97,7 @@
unsigned short val;
val = readw(VR4122_MSYSINT1REG);
- val &= ~((u16)1 << (irq - 8));
+ val &= ~((u16)1 << (irq - VR4122_SYSINT1_IRQ_BASE));
writew(val, VR4122_MSYSINT1REG);
}
@@ -107,8 +107,8 @@
return 0; /* never anything pending */
}
-#define shutdown_sysint1_irq disable_sysint1_irq
-#define mask_and_ack_sysint1_irq disable_sysint1_irq
+#define shutdown_sysint1_irq disable_sysint1_irq
+#define ack_sysint1_irq disable_sysint1_irq
static void end_sysint1_irq(unsigned int irq)
{
@@ -122,7 +122,7 @@
shutdown_sysint1_irq,
enable_sysint1_irq,
disable_sysint1_irq,
- mask_and_ack_sysint1_irq,
+ ack_sysint1_irq,
end_sysint1_irq,
NULL
};
@@ -135,11 +135,11 @@
if (irq == VR4122_IRQ_DSIU) {
val = readw(VR4122_MDSIUINTREG);
- val |= 0x0800;
+ val |= VR4122_DSIUINTREG_INTDSIU;
writew(val, VR4122_MDSIUINTREG);
}
val = readw(VR4122_MSYSINT2REG);
- val |= (u16)1 << (irq - 24);
+ val |= (u16)1 << (irq - VR4122_SYSINT2_IRQ_BASE);
writew(val, VR4122_MSYSINT2REG);
}
@@ -151,7 +151,7 @@
writew(0, VR4122_MDSIUINTREG);
}
val = readw(VR4122_MSYSINT2REG);
- val &= ~((u16)1 << (irq - 24));
+ val &= ~((u16)1 << (irq - VR4122_SYSINT2_IRQ_BASE));
writew(val, VR4122_MSYSINT2REG);
}
@@ -161,8 +161,8 @@
return 0; /* never anything pending */
}
-#define shutdown_sysint2_irq disable_sysint2_irq
-#define mask_and_ack_sysint2_irq disable_sysint2_irq
+#define shutdown_sysint2_irq disable_sysint2_irq
+#define ack_sysint2_irq disable_sysint2_irq
static void end_sysint2_irq(unsigned int irq)
{
@@ -176,7 +176,7 @@
shutdown_sysint2_irq,
enable_sysint2_irq,
disable_sysint2_irq,
- mask_and_ack_sysint2_irq,
+ ack_sysint2_irq,
end_sysint2_irq,
NULL
};
@@ -187,13 +187,13 @@
{
unsigned short val, mask;
- if (irq == VR4122_IRQ_ETHR) {
+ if (irq == VR4122_IRQ_LANCE) {
val = readb(NEC_EAGLE_PCIINTMSKREG);
val |= NEC_EAGLE_PCIINTMSK_MSKLANINT;
writeb(val, NEC_EAGLE_PCIINTMSKREG);
}
- mask = (u16)1 << (irq - 40);
+ mask = (u16)1 << (irq - VR4122_GIUINTL_IRQ_BASE);
writew(mask, VR4122_GIUINTSTATL);
val = readw(VR4122_MGIUINTLREG);
@@ -209,13 +209,13 @@
{
unsigned short val, mask;
- if (irq == VR4122_IRQ_ETHR) {
+ if (irq == VR4122_IRQ_LANCE) {
val = readb(NEC_EAGLE_PCIINTMSKREG);
val &= ~NEC_EAGLE_PCIINTMSK_MSKLANINT;
writeb(val, NEC_EAGLE_PCIINTMSKREG);
}
- mask = (u16)1 << (irq - 40);
+ mask = (u16)1 << (irq - VR4122_GIUINTL_IRQ_BASE);
val = readw(VR4122_GIUINTENL);
val &= ~mask;
writew(val, VR4122_GIUINTENL);
@@ -233,8 +233,8 @@
return 0; /* never anything pending */
}
-#define shutdown_giuintl_irq disable_giuintl_irq
-#define mask_and_ack_giuintl_irq disable_giuintl_irq
+#define shutdown_giuintl_irq disable_giuintl_irq
+#define ack_giuintl_irq disable_giuintl_irq
static void end_giuintl_irq(unsigned int irq)
{
@@ -248,7 +248,7 @@
shutdown_giuintl_irq,
enable_giuintl_irq,
disable_giuintl_irq,
- mask_and_ack_giuintl_irq,
+ ack_giuintl_irq,
end_giuintl_irq,
NULL
};
@@ -259,7 +259,7 @@
{
unsigned short val, mask;
- mask = (u16)1 << (irq - 56);
+ mask = (u16)1 << (irq - VR4122_GIUINTH_IRQ_BASE);
writew(mask, VR4122_GIUINTSTATH);
val = readw(VR4122_MGIUINTHREG);
@@ -275,7 +275,7 @@
{
unsigned short val, mask;
- mask = (u16)1 << (irq - 56);
+ mask = (u16)1 << (irq - VR4122_GIUINTH_IRQ_BASE);
val= readw(VR4122_GIUINTENH);
val &= ~mask;
writew(val, VR4122_GIUINTENH);
@@ -293,8 +293,8 @@
return 0; /* never anything pending */
}
-#define shutdown_giuinth_irq disable_giuinth_irq
-#define mask_and_ack_giuinth_irq disable_giuinth_irq
+#define shutdown_giuinth_irq disable_giuinth_irq
+#define ack_giuinth_irq disable_giuinth_irq
static void end_giuinth_irq(unsigned int irq)
{
@@ -308,15 +308,65 @@
shutdown_giuinth_irq,
enable_giuinth_irq,
disable_giuinth_irq,
- mask_and_ack_giuinth_irq,
+ ack_giuinth_irq,
end_giuinth_irq,
NULL
};
/*=======================================================================*/
-void __init init_vr4122_icu_irqs(void)
+#ifdef CONFIG_VRC4173
+
+static void enable_vrc4173_sysint1_irq(unsigned int irq)
+{
+ u16 val;
+
+ val = vrc4173_inw(VRC4173_MSYSINT1REG);
+ val |= (u16)1 << (irq - VRC4173_IRQ_BASE);
+ vrc4173_outw(val, VRC4173_MSYSINT1REG);
+}
+
+static void disable_vrc4173_sysint1_irq(unsigned int irq)
+{
+ u16 val;
+
+ val = vrc4173_inw(VRC4173_MSYSINT1REG);
+ val &= ~((u16)1 << (irq - VRC4173_IRQ_BASE));
+ vrc4173_outw(val, VRC4173_MSYSINT1REG);
+}
+
+static unsigned int startup_vrc4173_sysint1_irq(unsigned int irq)
{
+ enable_vrc4173_sysint1_irq(irq);
+ return 0; /* never anything pending */
+}
+
+#define shutdown_vrc4173_sysint1_irq disable_vrc4173_sysint1_irq
+#define ack_vrc4173_sysint1_irq disable_vrc4173_sysint1_irq
+
+static void end_vrc4173_sysint1_irq(unsigned int irq)
+{
+ if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+ enable_vrc4173_sysint1_irq(irq);
+}
+
+static struct hw_interrupt_type vrc4173_sysint1_irq_type = {
+ "VRC4173 SYSINT1",
+ startup_vrc4173_sysint1_irq,
+ shutdown_vrc4173_sysint1_irq,
+ enable_vrc4173_sysint1_irq,
+ disable_vrc4173_sysint1_irq,
+ ack_vrc4173_sysint1_irq,
+ end_vrc4173_sysint1_irq,
+ NULL
+};
+
+#endif
+
+/*=======================================================================*/
+
+static void __init init_eagle_irq(void)
+{
int i;
/* Default all ICU IRQs to off ... */
@@ -343,19 +393,21 @@
barrier();
for (i = 0; i < NR_IRQS; i++) {
- irq_desc[i].status = IRQ_DISABLED;
- irq_desc[i].action = 0;
- irq_desc[i].depth = 1;
- if (i < 8)
+ if (i < VR4122_SYSINT1_IRQ_BASE)
irq_desc[i].handler = &cpucore_irq_type;
- else if (i < 24)
+ else if (i < VR4122_SYSINT2_IRQ_BASE)
irq_desc[i].handler = &sysint1_irq_type;
- else if (i < 40)
+ else if (i < VR4122_GIUINTL_IRQ_BASE)
irq_desc[i].handler = &sysint2_irq_type;
- else if (i < 56)
+ else if (i < VR4122_GIUINTH_IRQ_BASE)
irq_desc[i].handler = &giuintl_irq_type;
- else if (i < 72)
+ else if (i < VR4122_IRQ_LAST)
irq_desc[i].handler = &giuinth_irq_type;
+#ifdef CONFIG_VRC4173
+ else if (i < VRC4173_IRQ_LAST)
+ irq_desc[i].handler = &vrc4173_sysint1_irq_type;
+#endif
+
}
}
@@ -368,7 +420,7 @@
memset(irq_desc, 0, sizeof(irq_desc));
init_generic_irq();
- init_vr4122_icu_irqs();
+ init_eagle_irq();
setup_irq(VR4122_IRQ_INT0, &cascade);
setup_irq(VR4122_IRQ_GIU, &cascade);
Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle/prom.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- prom.c 2001/12/12 18:45:47 1.4
+++ prom.c 2002/01/18 21:22:21 1.5
@@ -39,6 +39,10 @@
return "NEC_Vr41xx Eagle";
}
+void __init bus_error_init(void)
+{
+}
+
/* Do basic initialization */
void __init prom_init(int argc, char **argv,
unsigned long magic, int *prom_vec)
@@ -73,6 +77,9 @@
break;
case 64:
add_memory_region(0, 64 << 20, BOOT_MEM_RAM);
+ break;
+ case 128:
+ add_memory_region(0, 128 << 20, BOOT_MEM_RAM);
break;
default:
panic("Memory size error");
Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/vr4122/eagle/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c 2002/01/02 19:12:17 1.3
+++ setup.c 2002/01/18 21:22:21 1.4
@@ -26,17 +26,27 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-
+#include <linux/config.h>
#include <linux/init.h>
#include <linux/console.h>
+#include <linux/ioport.h>
+#include <linux/ide.h>
-#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/reboot.h>
#include <asm/time.h>
#include <asm/vr4122/vr4122.h>
#include <asm/vr4122/eagle.h>
+#define VR4122_HAS_CLKSPEEDREG_BUG
+
+#define MAX_PCI_CLOCK 33333333
+
+#ifdef CONFIG_BLK_DEV_INITRD
+extern unsigned long initrd_start, initrd_end;
+extern void * __rd_start, * __rd_end;
+#endif
+
extern void vr4122_restart(char *command);
extern void vr4122_halt(void);
extern void vr4122_power_off(void);
@@ -44,29 +54,107 @@
extern void vr4122_time_init(void);
extern void vr4122_timer_setup(struct irqaction *irq);
-void __init bus_error_init(void)
+#ifdef CONFIG_BLK_DEV_IDE
+extern struct ide_ops std_ide_ops;
+#endif
+
+#ifdef CONFIG_VRC4173
+extern void vrc4173_bcu_init(void);
+#endif
+
+static void __init vr4122_siu_init(void)
{
+ u16 val;
+
+ /* Select RS-232C */
+ val = readw(VR4122_SIUIRSEL);
+ val &= ~VR4122_SIUIRSEL_SIRSEL;
+ writew(val, VR4122_SIUIRSEL);
+
+ /* Supply DSIU and SIU clock */
+ vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSIU);
+ vr4122_clock_supply(VR4122_CMUCLKMSK_MSKDSIU);
+ vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSSIU);
}
+static void __init vr4122_pciu_init(unsigned long vtclock)
+{
+ u32 n;
+
+ /* Enable PCI clock */
+ vr4122_clock_supply(VR4122_CMUCLKMSK_MSKPCIU);
+ for (n = 0; n < 10000; n++);
+
+ /* Set master memory & I/O windows */
+ writel(0x100f9010, VR4122_PCIMMAW1REG);
+ writel(0x140fd014, VR4122_PCIMMAW2REG);
+ writel(0x160fd000, VR4122_PCIMIOAWREG);
+
+ /* Set target memory windows */
+ writel(0x00081000, VR4122_PCITAW1REG);
+ writel(0x00000000, VR4122_PCIMBA1REG);
+ writel(0x00000000, VR4122_PCITAW2REG);
+ writel(0x00000000, VR4122_PCIMAILBAREG);
+
+ /* Clear bus error */
+ n = readl(VR4122_BUSERRADREG);
+
+ /* Select PCI clock */
+ if (vtclock < MAX_PCI_CLOCK)
+ writel(0x00000002, VR4122_PCICLKSELREG);
+ else if ((vtclock / 2) < MAX_PCI_CLOCK)
+ writel(0x00000000, VR4122_PCICLKSELREG);
+ else if ((vtclock / 4) < MAX_PCI_CLOCK)
+ writel(0x00000001, VR4122_PCICLKSELREG);
+ else
+ printk(KERN_INFO "Warning: PCI Clock is over 33MHz.\n");
+
+ writel(100, VR4122_PCITRDYVREG);
+ writel(0x00008004, VR4122_PCICACHELSREG);
+ for (n = 0; n < 10000; n++);
+
+ writel(0x00000004, VR4122_PCIENREG);
+ writel(0x00000147, VR4122_PCICOMMANDREG);
+}
+
void __init nec_eagle_setup(void)
{
- unsigned long clock;
- unsigned short val;
+ unsigned long clock, vtclock;
+ u16 val;
val = readw(VR4122_CLKSPEEDREG);
- clock = (18432000 * 98) / (val & 0x1f);
+ clock = (18432000 * 98) / (val & 0x001f);
printk("PClock: %ldHz\n", clock);
- clock = clock / ((val & 0x700) >> 8);
- printk("VTClock: %ldHz\n", clock);
+#ifdef VR4122_HAS_CLKSPEEDREG_BUG
+ if ((val & 0x0700) == 0x0100) {
+ u16 div;
+ div = readw(VR4122_PMUTCLKDIVREG);
+ if ((div & 0x0007) == 0x0002)
+ val = (val & ~0x0700) | 0x0200;
+ }
+#endif
+ vtclock = clock / ((val & 0x0700) >> 8);
+ printk("VTClock: %ldHz\n", vtclock);
- clock = clock / (2 << ((val & 0x1000) >> 12));
+ clock = vtclock / (2 << ((val & 0x1000) >> 12));
printk("TClock: %ldHz\n", clock);
mips_counter_frequency = clock / 4;
+ isa_slot_offset = VR4122_ISA_IO_BASE;
set_io_port_base(VR4122_IO_PORT_BASE);
+ ioport_resource.start = 0;
+ ioport_resource.end = VR4122_PCI_IO_SIZE;
+ iomem_resource.start = VR4122_PCI_MEM_BASE;
+ iomem_resource.end = VR4122_PCI_MEM_BASE + VR4122_PCI_MEM_SIZE;
+#ifdef CONFIG_BLK_DEV_INITRD
+ ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
+ initrd_start = (unsigned long)&__rd_start;
+ initrd_end = (unsigned long)&__rd_end;
+#endif
+
_machine_restart = vr4122_restart;
_machine_halt = vr4122_halt;
_machine_power_off = vr4122_power_off;
@@ -78,13 +166,14 @@
conswitchp = &dummy_con;
#endif
- /* Select RS-232C */
- val = readw(VR4122_SIUIRSEL);
- val &= ~VR4122_SIUIRSEL_SIRSEL;
- writew(val, VR4122_SIUIRSEL);
+#ifdef CONFIG_BLK_DEV_IDE
+ ide_ops = &std_ide_ops;
+#endif
- /* Supply DSIU and SIU clock */
- vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSIU);
- vr4122_clock_supply(VR4122_CMUCLKMSK_MSKDSIU);
- vr4122_clock_supply(VR4122_CMUCLKMSK_MSKSSIU);
+ vr4122_siu_init();
+ vr4122_pciu_init(vtclock);
+
+#ifdef CONFIG_VRC4173
+ vrc4173_bcu_init();
+#endif
}
--- pci.c DELETED ---
|
|
From: Paul M. <le...@us...> - 2002-01-18 21:27:31
|
Update of /cvsroot/linux-mips/linux/Documentation In directory usw-pr-cvs1:/tmp/cvs-serv8327/Documentation Modified Files: Configure.help Log Message: NEC Vr4122/Vr4131/Vrc4173 updates. Index: Configure.help =================================================================== RCS file: /cvsroot/linux-mips/linux/Documentation/Configure.help,v retrieving revision 1.9 retrieving revision 1.10 diff -u -d -r1.9 -r1.10 --- Configure.help 2002/01/05 20:35:10 1.9 +++ Configure.help 2002/01/18 21:22:02 1.10 @@ -2247,6 +2247,14 @@ byte order. These modes require different kernels. Say Y if your machine is little endian, N if it's a big endian machine. +Enable Vr4131 cache fixes for early rev processors +CONFIG_VR4131_CACHE_FIX + Early revisions of the NEC Vr4131 processor (just about everything + prior to rev 2.2) have problems with illegal write backs occuring when + executing things like Index_Store_Tag, Hit_Writeback_Invalidate, and + Create_Dirty_Exclusive for the D-cache. Saying Y here will link in an + alternate set of MMU/Cache routines as a workaround. + Use power LED as a heartbeat CONFIG_HEARTBEAT Use the power-on LED on your machine as a load meter. The exact |
|
From: Paul M. <le...@us...> - 2002-01-18 21:27:31
|
Update of /cvsroot/linux-mips/linux/arch/mips/configs In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/configs Modified Files: defconfig-eagle Log Message: NEC Vr4122/Vr4131/Vrc4173 updates. Index: defconfig-eagle =================================================================== RCS file: /cvsroot/linux-mips/linux/arch/mips/configs/defconfig-eagle,v retrieving revision 1.11 retrieving revision 1.12 diff -u -d -r1.11 -r1.12 --- defconfig-eagle 2001/11/27 23:31:02 1.11 +++ defconfig-eagle 2002/01/18 21:22:14 1.12 @@ -19,16 +19,17 @@ # CONFIG_DDB5074 is not set CONFIG_NEC_EAGLE=y CONFIG_NEC_EAGLE_MEM_SIZE=64 -# CONFIG_NEC_KORVA is not set # CONFIG_MIPS_EV96100 is not set # CONFIG_MIPS_EV64120 is not set # CONFIG_MIPS_ATLAS is not set # CONFIG_MIPS_MALTA is not set # CONFIG_NINO is not set +# CONFIG_MIPS_LXPB20K is not set # CONFIG_SIBYTE_SB1250 is not set # CONFIG_PS2 is not set # CONFIG_CASIO_BE300 is not set # CONFIG_VADEM_CLIO_1000 is not set +# CONFIG_NEC_MOBILEPRO_780 is not set # CONFIG_MIPS_MAGNUM_4000 is not set # CONFIG_MOMENCO_OCELOT is not set # CONFIG_DDB5476 is not set @@ -40,20 +41,23 @@ # CONFIG_MIPS_ITE8172 is not set # CONFIG_MIPS_IVR is not set # CONFIG_MIPS_PB1000 is not set -# CONFIG_HP_LASERJET is not set +# CONFIG_MIPS_PB1500 is not set # CONFIG_TOSHIBA_JMR3927 is not set +# CONFIG_HP_LASERJET is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set +CONFIG_GENERIC_ISA_DMA=y # CONFIG_MCA is not set # CONFIG_SBUS is not set CONFIG_CPU_VR41XX=y CONFIG_VR4122=y -CONFIG_VRC4173=y CONFIG_NEW_IRQ=y CONFIG_NEW_TIME_C=y +CONFIG_VR4122_TIME_C=y CONFIG_NONCOHERENT_IO=y -CONFIG_DUMMY_KEYB=y CONFIG_PCI=y +CONFIG_NEW_PCI=y +CONFIG_PCI_AUTO=y # CONFIG_ISA is not set # CONFIG_EISA is not set # CONFIG_I8259 is not set @@ -61,17 +65,20 @@ # # Loadable module support # -# CONFIG_MODULES is not set +CONFIG_MODULES=y +# CONFIG_MODVERSIONS is not set +CONFIG_KMOD=y # # CPU selection # # CONFIG_CPU_R3000 is not set +# CONFIG_CPU_LX45XXX is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_R6000 is not set -# CONFIG_CPU_VR41XX is not set +CONFIG_CPU_VR41XX=y # CONFIG_CPU_R4300 is not set -CONFIG_CPU_R4X00=y +# CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set @@ -83,9 +90,9 @@ # CONFIG_CPU_MIPS32 is not set # CONFIG_CPU_MIPS64 is not set # CONFIG_CPU_ADVANCED is not set -CONFIG_CPU_HAS_LLSC=y +# CONFIG_CPU_HAS_LLSC is not set +# CONFIG_CPU_HAS_LLDSCD is not set # CONFIG_CPU_HAS_WB is not set -CONFIG_CPU_HAS_LLDSCD=y # # General setup @@ -98,8 +105,23 @@ # CONFIG_BINFMT_MISC is not set CONFIG_NET=y # CONFIG_PCI_NAMES is not set -# CONFIG_HOTPLUG is not set -# CONFIG_PCMCIA is not set +CONFIG_HOTPLUG=y + +# +# PCMCIA/CardBus support +# +CONFIG_PCMCIA=y +CONFIG_CARDBUS=y +# CONFIG_I82092 is not set +# CONFIG_I82365 is not set +# CONFIG_TCIC is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set +# CONFIG_HOTPLUG_PCI_COMPAQ is not set +# CONFIG_HOTPLUG_PCI_COMPAQ_NVRAM is not set CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y @@ -123,9 +145,10 @@ # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=4096 # CONFIG_BLK_DEV_INITRD is not set # @@ -144,13 +167,13 @@ # Networking options # CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK is not set +CONFIG_PACKET_MMAP=y +CONFIG_NETLINK_DEV=y # CONFIG_NETFILTER is not set # CONFIG_FILTER is not set CONFIG_UNIX=y CONFIG_INET=y -# CONFIG_IP_MULTICAST is not set +CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_PNP=y # CONFIG_IP_PNP_DHCP is not set @@ -158,6 +181,8 @@ # CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set # CONFIG_INET_ECN is not set # CONFIG_SYN_COOKIES is not set # CONFIG_IPV6 is not set @@ -196,9 +221,80 @@ # # ATA/IDE/MFM/RLL support # -# CONFIG_IDE is not set -# CONFIG_BLK_DEV_IDE_MODES is not set +CONFIG_IDE=y + +# +# IDE, ATA and ATAPI Block devices +# +CONFIG_BLK_DEV_IDE=y + +# +# Please see Documentation/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_HD_IDE is not set # CONFIG_BLK_DEV_HD is not set +CONFIG_BLK_DEV_IDEDISK=y +CONFIG_IDEDISK_MULTI_MODE=y +# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set +# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set +# CONFIG_BLK_DEV_IDEDISK_IBM is not set +# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set +# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set +# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set +# CONFIG_BLK_DEV_IDEDISK_WD is not set +# CONFIG_BLK_DEV_COMMERIAL is not set +# CONFIG_BLK_DEV_TIVO is not set +# CONFIG_BLK_DEV_IDECS is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_BLK_DEV_IDEFLOPPY is not set +# CONFIG_BLK_DEV_IDESCSI is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_BLK_DEV_CMD640 is not set +# CONFIG_BLK_DEV_CMD640_ENHANCED is not set +# CONFIG_BLK_DEV_ISAPNP is not set +# CONFIG_BLK_DEV_RZ1000 is not set +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_SHARE_IRQ=y +# CONFIG_BLK_DEV_IDEDMA_PCI is not set +# CONFIG_BLK_DEV_ADMA is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +# CONFIG_IDEDMA_PCI_AUTO is not set +# CONFIG_BLK_DEV_IDEDMA is not set +# CONFIG_IDEDMA_PCI_WIP is not set +# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_AEC62XX_TUNING is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_WDC_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_AMD74XX_OVERRIDE is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_CY82C693 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT34X is not set +# CONFIG_HPT34X_AUTODMA is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_OPTI621 is not set +# CONFIG_BLK_DEV_PDC202XX is not set +# CONFIG_PDC202XX_BURST is not set +# CONFIG_PDC202XX_FORCE is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIS5513 is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_IDE_CHIPSETS is not set +# CONFIG_IDEDMA_AUTO is not set +# CONFIG_DMA_NONPCI is not set +# CONFIG_BLK_DEV_IDE_MODES is not set +# CONFIG_BLK_DEV_ATARAID is not set +# CONFIG_BLK_DEV_ATARAID_PDC is not set +# CONFIG_BLK_DEV_ATARAID_HPT is not set # # SCSI support @@ -228,6 +324,7 @@ # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_ETHERTAP is not set # # Ethernet (10 or 100Mbit) @@ -251,9 +348,9 @@ # CONFIG_APRICOT is not set # CONFIG_CS89x0 is not set # CONFIG_TULIP is not set +# CONFIG_TC35815 is not set # CONFIG_DE4X5 is not set # CONFIG_DGRS is not set -# CONFIG_TC35815 is not set # CONFIG_DM9102 is not set # CONFIG_EEPRO100 is not set # CONFIG_LNE390 is not set @@ -272,6 +369,7 @@ # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set +# CONFIG_VIA_RHINE_MMIO is not set # CONFIG_WINBOND_840 is not set # CONFIG_LAN_SAA9730 is not set # CONFIG_NET_POCKET is not set @@ -311,6 +409,11 @@ # CONFIG_WAN is not set # +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# # Amateur Radio support # # CONFIG_HAMRADIO is not set @@ -339,6 +442,9 @@ # CONFIG_SERIAL_CONSOLE is not set # CONFIG_SERIAL_EXTENDED is not set # CONFIG_SERIAL_NONSTANDARD is not set +CONFIG_VRC4173=y +CONFIG_VRC4173_PS2U=y +CONFIG_VRC4173_PIU=y CONFIG_UNIX98_PTYS=y CONFIG_UNIX98_PTY_COUNT=256 @@ -351,20 +457,45 @@ # Mice # # CONFIG_BUSMOUSE is not set -# CONFIG_MOUSE is not set +CONFIG_MOUSE=y +CONFIG_PSMOUSE=y +# CONFIG_82C710_MOUSE is not set +# CONFIG_PC110_PAD is not set # # Joysticks # # CONFIG_INPUT_GAMEPORT is not set - -# -# Input core support is needed for gameports -# +# CONFIG_INPUT_NS558 is not set +# CONFIG_INPUT_LIGHTNING is not set +# CONFIG_INPUT_PCIGAME is not set +# CONFIG_INPUT_CS461X is not set +# CONFIG_INPUT_EMU10K1 is not set +# CONFIG_INPUT_SERIO is not set +# CONFIG_INPUT_SERPORT is not set # -# Input core support is needed for joysticks +# Joysticks # +# CONFIG_INPUT_ANALOG is not set +# CONFIG_INPUT_A3D is not set +# CONFIG_INPUT_ADI is not set +# CONFIG_INPUT_COBRA is not set +# CONFIG_INPUT_GF2K is not set +# CONFIG_INPUT_GRIP is not set +# CONFIG_INPUT_INTERACT is not set +# CONFIG_INPUT_TMDC is not set +# CONFIG_INPUT_SIDEWINDER is not set +# CONFIG_INPUT_IFORCE_USB is not set +# CONFIG_INPUT_IFORCE_232 is not set +# CONFIG_INPUT_WARRIOR is not set +# CONFIG_INPUT_MAGELLAN is not set +# CONFIG_INPUT_SPACEORB is not set +# CONFIG_INPUT_SPACEBALL is not set +# CONFIG_INPUT_STINGER is not set +# CONFIG_INPUT_DB9 is not set +# CONFIG_INPUT_GAMECON is not set +# CONFIG_INPUT_TURBOGRAFX is not set # CONFIG_QIC02_TAPE is not set # @@ -374,6 +505,7 @@ # CONFIG_INTEL_RNG is not set # CONFIG_NVRAM is not set # CONFIG_RTC is not set +# CONFIG_MIPS_RTC is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set @@ -386,6 +518,11 @@ # CONFIG_DRM is not set # +# PCMCIA character devices +# +# CONFIG_PCMCIA_SERIAL_CS is not set + +# # Multimedia devices # # CONFIG_VIDEO_DEV is not set @@ -398,11 +535,15 @@ CONFIG_AUTOFS4_FS=y # CONFIG_REISERFS_FS is not set # CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set # CONFIG_ADFS_FS is not set # CONFIG_ADFS_FS_RW is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_BFS_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_JBD is not set +# CONFIG_JBD_DEBUG is not set # CONFIG_FAT_FS is not set # CONFIG_MSDOS_FS is not set # CONFIG_UMSDOS_FS is not set @@ -425,7 +566,7 @@ # CONFIG_DEVFS_FS is not set # CONFIG_DEVFS_MOUNT is not set # CONFIG_DEVFS_DEBUG is not set -# CONFIG_DEVPTS_FS is not set +CONFIG_DEVPTS_FS=y # CONFIG_QNX4FS_FS is not set # CONFIG_QNX4FS_RW is not set # CONFIG_ROMFS_FS is not set @@ -440,13 +581,15 @@ # Network File Systems # # CONFIG_CODA_FS is not set +# CONFIG_INTERMEZZO_FS is not set CONFIG_NFS_FS=y -# CONFIG_NFS_V3 is not set +CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_NFSD=y -# CONFIG_NFSD_V3 is not set +CONFIG_NFSD_V3=y CONFIG_SUNRPC=y CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y # CONFIG_SMB_FS is not set # CONFIG_NCP_FS is not set # CONFIG_NCPFS_PACKET_SIGNING is not set @@ -495,6 +638,7 @@ # CONFIG_FB_RIVA is not set # CONFIG_FB_CLGEN is not set # CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_E1355 is not set CONFIG_FB_MQ200=y @@ -507,15 +651,15 @@ # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_E1356 is not set # CONFIG_FB_IT8181 is not set -CONFIG_FB_VIRTUAL=y +# CONFIG_FB_VIRTUAL is not set CONFIG_FBCON_ADVANCED=y # CONFIG_FBCON_MFB is not set # CONFIG_FBCON_CFB2 is not set # CONFIG_FBCON_CFB4 is not set -# CONFIG_FBCON_CFB8 is not set +CONFIG_FBCON_CFB8=y CONFIG_FBCON_CFB16=y -# CONFIG_FBCON_CFB24 is not set -# CONFIG_FBCON_CFB32 is not set +CONFIG_FBCON_CFB24=y +CONFIG_FBCON_CFB32=y # CONFIG_FBCON_AFB is not set # CONFIG_FBCON_ILBM is not set # CONFIG_FBCON_IPLAN2P2 is not set @@ -543,14 +687,23 @@ # # USB support # -# CONFIG_USB is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set # +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_BANDWIDTH=y +CONFIG_USB_LONG_TIMEOUT=y + +# # USB Controllers # # CONFIG_USB_UHCI is not set # CONFIG_USB_UHCI_ALT is not set -# CONFIG_USB_OHCI is not set +CONFIG_USB_OHCI=y +# CONFIG_USB_NON_PCI_OHCI is not set # # USB Device Class drivers @@ -572,10 +725,9 @@ # # USB Human Interface Devices (HID) # - -# -# Input core support is needed for USB HID -# +CONFIG_USB_HID=y +# CONFIG_USB_HIDDEV is not set +# CONFIG_USB_WACOM is not set # # USB Imaging devices @@ -645,9 +797,11 @@ # # Input core support # -# CONFIG_INPUT is not set -# CONFIG_INPUT_KEYBDEV is not set -# CONFIG_INPUT_MOUSEDEV is not set +CONFIG_INPUT=y +CONFIG_INPUT_KEYBDEV=y +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set |
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