linux-mips-commits — CVS Commit Patches

[Linux-mips-commits]CVS: linux/arch/mips Makefile,1.37,1.38 config.in,1.79,1.80

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips
In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips

Modified Files:
	Makefile config.in 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/Makefile,v
retrieving revision 1.37
retrieving revision 1.38
diff -u -d -r1.37 -r1.38
--- Makefile	2002/01/15 18:01:25	1.37
+++ Makefile	2002/01/18 21:22:07	1.38
@@ -442,6 +442,19 @@
 endif                                                        
 
 #
+# Casio Cassiopeia BE-300 (Vr4131)
+#
+ifdef CONFIG_CASIO_BE300
+SUBDIRS       += arch/mips/vr4122/common \
+                 arch/mips/vr4131/common \
+		 arch/mips/vr4131/casio-be300
+LIBS          += arch/mips/vr4122/common/vr4122.o \
+                 arch/mips/vr4131/common/vr4131.o \
+		 arch/mips/vr4131/casio-be300/casio-be300.o
+LOADADDR      += 0x80001000
+endif
+
+#
 # Choosing incompatible machines durings configuration will result in
 # error messages during linking.  Select a default linkscript if
 # none has been choosen above.

Index: config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/config.in,v
retrieving revision 1.79
retrieving revision 1.80
diff -u -d -r1.79 -r1.80
--- config.in	2002/01/15 18:01:26	1.79
+++ config.in	2002/01/18 21:22:11	1.80
@@ -23,7 +23,7 @@
    bool 'Support for NEC DDB Vrc-5074 (EXPERIMENTAL)' CONFIG_DDB5074
    bool 'Support for NEC Eagle board (EXPERIMENTAL)' CONFIG_NEC_EAGLE
    if [ "$CONFIG_NEC_EAGLE" = "y" ]; then
-      int '   Memory size' CONFIG_NEC_EAGLE_MEM_SIZE 32
+      int '   Memory size' CONFIG_NEC_EAGLE_MEM_SIZE 64
    fi
    bool 'Support for NEC Korva/Markham board (EXPERIMENTAL)' CONFIG_NEC_KORVA
    if [ "$CONFIG_NEC_KORVA" = "y" ]; then
@@ -258,12 +258,13 @@
 if [ "$CONFIG_NEC_EAGLE" = "y" ]; then
    define_bool CONFIG_CPU_VR41XX y
    define_bool CONFIG_VR4122 y
-   define_bool CONFIG_VRC4173 y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_VR4122_TIME_C y
    define_bool CONFIG_NONCOHERENT_IO y
-   define_bool CONFIG_DUMMY_KEYB y
    define_bool CONFIG_PCI y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_PCI_AUTO y
 fi
 if [ "$CONFIG_NEC_KORVA" = "y" ]; then
    define_bool CONFIG_CPU_VR41XX y
@@ -394,19 +395,16 @@
 fi
 if [ "$CONFIG_CASIO_BE300" = "y" ]; then
    define_bool CONFIG_CPU_VR41XX y
-   #
-   # Note that the VR4131 is pin compliant with the VR4122,
-   # leave both specified for now to attempt and reduce code
-   # duplication as much as possible. -Lethal
-   #
    define_bool CONFIG_VR4122 y
    define_bool CONFIG_VR4131 y
-   define_bool CONFIG_VRC4173 y
    define_bool CONFIG_NEW_IRQ y
    define_bool CONFIG_NEW_TIME_C y
+   define_bool CONFIG_VR4122_TIME_C y
    define_bool CONFIG_NONCOHERENT_IO y
    define_bool CONFIG_DUMMY_KEYB y
    define_bool CONFIG_PCI y
+   define_bool CONFIG_NEW_PCI y
+   define_bool CONFIG_PCI_AUTO y
 fi
 if [ "$CONFIG_CASIO_E15" = "y" ]; then
    define_bool CONFIG_CPU_VR41XX y
@@ -526,12 +524,16 @@
      "$CONFIG_NINO" = "y" -o
      "$CONFIG_VR4111" = "y"   -o   \
      "$CONFIG_VR4121" = "y"   -o  \
+     "$CONFIG_VR4122" = "y"   -o  \
      "$CONFIG_NEC_KORVA" = "y" ]; then
    define_bool CONFIG_CPU_LITTLE_ENDIAN y
 else
    bool 'Generate little endian code' CONFIG_CPU_LITTLE_ENDIAN
 fi
 
+dep_bool '  Enable R5900 specific context' CONFIG_CPU_R5900_CONTEXT $CONFIG_PS2
+dep_bool '  Enable Vr4131 cache fixes for early rev processors' CONFIG_VR4131_CACHE_FIX $CONFIG_VR4131
+
 if [ "$CONFIG_TOSHIBA_JMR3927" = "y" ]; then
    bool 'DS1742 BRAM/RTC support' CONFIG_RTC_DS1742
 fi                             
@@ -736,10 +738,6 @@
 
 if [ "$CONFIG_SGI_IP22" = "y" ]; then
    source drivers/sgi/Config.in
-fi
-
-if [ "$CONFIG_PS2" = "y" ]; then
-   bool '  Enable R5900 specific context' CONFIG_CPU_R5900_CONTEXT
 fi
 
 source drivers/usb/Config.in

[Linux-mips-commits]CVS: linux/include/asm-mips/vr4122 eagle.h,1.1,1.2 vr4122.h,1.3,1.4

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/vr4122
In directory usw-pr-cvs1:/tmp/cvs-serv8327/include/asm-mips/vr4122

Modified Files:
	eagle.h vr4122.h 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



Index: eagle.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4122/eagle.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- eagle.h	2001/09/22 04:27:16	1.1
+++ eagle.h	2002/01/18 21:22:23	1.2
@@ -32,25 +32,23 @@
 #define __ASM_NEC_EAGLE_H
 
 /*
- * Memory Mapping
+ * Board specific address mapping
  */
-#define VR4122_EXTERNAL_IO_BZSE		0x0a000000
-#define VR4122_EXTERNAL_IO_SIZE		0x04000000
-
-#define VR4122_INTERNAL_IO_BASE		0x0f000000
-#define VR4122_INTERNAL_IO_SIZE		0x01000000
-
 #define VR4122_PCI_MEM_BASE		0x10000000
 #define VR4122_PCI_MEM_SIZE		0x06000000
 
 #define VR4122_PCI_IO_BASE		0x16000000
 #define VR4122_PCI_IO_SIZE		0x02000000
 
-#define VR4122_ROM_BASE			0x1c000000
-#define VR4122_ROM_SIZE			0x04000000
+#define VR4122_PCI_IO_START		0x01000000
+#define VR4122_PCI_IO_END		0x01ffffff
 
-#define VR4122_IO_PORT_BASE		KSEG1ADDR(VR4122_PCI_IO_BASE)
+#define VR4122_PCI_MEM_START		0x12000000
+#define VR4122_PCI_MEM_END		0x15ffffff
 
+#define VR4122_ISA_IO_BASE		KSEG1ADDR(VR4122_EXTERNAL_IO_BASE)
+
+#define VR4122_IO_PORT_BASE		KSEG1ADDR(VR4122_PCI_IO_BASE)
 
 /*
  * Interrupt Number
@@ -59,7 +57,7 @@
 #define VR4122_IRQ_MQ200		VR4122_IRQ_GPIO4
 #define VR4122_IRQ_FPGA			VR4122_IRQ_GPIO5
 #define VR4122_IRQ_PCI			VR4122_IRQ_GPIO5
-#define VR4122_IRQ_ETHR			VR4122_IRQ_GPIO5
+#define VR4122_IRQ_LANCE		VR4122_IRQ_GPIO5
 #define VR4122_IRQ_SIO			VR4122_IRQ_GPIO8
 #define VR4122_IRQ_DCD			VR4122_IRQ_GPIO15
 

Index: vr4122.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/vr4122/vr4122.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- vr4122.h	2001/10/29 08:20:55	1.3
+++ vr4122.h	2002/01/18 21:22:23	1.4
@@ -15,6 +15,25 @@
 #include <asm/io.h>
 #endif
 
+/*
+ * Physical Address Space
+ */
+#define VR4122_DRAM_BASE	0x00000000
+#define VR4122_DRAM_SIZE	0x08000000
+
+#define VR4122_EXTERNAL_IO_BASE	0x0a000000
+#define VR4122_EXTERNAL_IO_SIZE	0x04000000
+
+#define VR4122_INTERNAL_IO_BASE	0x0f000000
+#define VR4122_INTERNAL_IO_SIZE	0x01000000
+
+#define VR4122_PCI_BASE		0x10000000
+#define VR4122_PCI_SIZE		0x08000000
+
+#define VR4122_ROM_BASE		0x18000000
+#define VR4122_ROM_SIZE		0x08000000
+
+
 /* CPU interrupts */
 #define VR4122_IRQ_SW1       0  /* IP0 - Software interrupt */
 #define VR4122_IRQ_SW2       1  /* IP1 - Software interrupt */
@@ -92,6 +111,7 @@
 #define VR4122_IRQ_GPIO29    69
 #define VR4122_IRQ_GPIO30    70
 #define VR4122_IRQ_GPIO31    71
+#define VR4122_IRQ_LAST      72
 
 /* Alternative to above GPIO IRQ defines */
 #define VR4122_IRQ_GPIO(pin) ((VR4122_IRQ_GPIO0)ADDR((pin))
@@ -193,6 +213,8 @@
 #define VR4122_MSCUINTREG	KSEG1ADDR(0x0F0000B4)	/* Level 2 mask SCU interrupt register */
 #define VR4122_MCSIINTREG	KSEG1ADDR(0x0F0000B6)	/* Level 2 mask CSI interrupt register */
 
+/* DSIU interrupt register */
+#define VR4122_DSIUINTREG_INTDSIU	0x0800
 
 /* Power Management Unit (PMU) */
 #define VR4122_PMUINTREG	KSEG1ADDR(0x0F0000C0)	/* PMU Status Register */

[Linux-mips-commits]CVS: linux/arch/mips/vr4131/common Makefile,NONE,1.1 irq.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4131/common
In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/vr4131/common

Added Files:
	Makefile irq.c 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



--- NEW FILE: Makefile ---
#
# Makefile for the NEC Vr4131 CPU, generic files.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(CFLAGS) $< -o $*.s
.S.o:
	$(CC) $(CFLAGS) -c $< -o $*.o

O_TARGET := vr4131.o

obj-y := irq.o

include $(TOPDIR)/Rules.make

--- NEW FILE: irq.c ---
/*
 * arch/mips/vr4131/common/irq.c
 *
 * Interrupt routines for the NEC Vr4131
 *
 * Copyright (C) 2002 Paul Mundt <le...@ch...>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/config.h>

#include <asm/irq.h>
#include <asm/gdb-stub.h>
#include <asm/vr41xx.h>

extern asmlinkage void vr4122_handle_int(void);

/* 
 * FIXME: Finish implementing .. just a place holder
 * for now, to keep gcc happy
 */
void __init init_IRQ(void)
{
	init_generic_irq();

	set_except_vector(0, vr4122_handle_int);

#ifdef CONFIG_REMOTE_DEBUG
	set_debug_traps();
	breakpoint();
#endif
}

[Linux-mips-commits]CVS: linux/arch/mips/vr4131/casio-be300 Makefile,NONE,1.1 prom.c,NONE,1.1 setup.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4131/casio-be300
In directory usw-pr-cvs1:/tmp/cvs-serv8327/arch/mips/vr4131/casio-be300

Added Files:
	Makefile prom.c setup.c 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



--- NEW FILE: Makefile ---
#
# Makefile for the Casio Cassiopeia BE-300 specific parts of the kernel
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#

.S.s:
	$(CPP) $(AFLAGS) $< -o $@
.S.o:
	$(CC) $(AFLAGS) -c $< -o $@

O_TARGET := casio-be300.o

obj-y	 := prom.o setup.o

include $(TOPDIR)/Rules.make

--- NEW FILE: prom.c ---
/*
 * arch/mips/vr4131/casio-be300/prom.c
 *
 * PROM library initialization routines for the Casio Cassiopeia BE-300
 *
 * Copyright (C) 2002 Paul Mundt <le...@ch...>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/kernel.h>
#include <linux/string.h>

#include <asm/bootinfo.h>
#include <asm/addrspace.h>
#include <asm/vr41xx.h>

char arcs_cmdline[CL_SIZE];

const char *get_system_type(void)
{
	return "NEC_Vr41xx Casio Cassiopeia BE-300";
}

void __init prom_init(int argc, char **argv, char **envp)
{
	int i;

	for (i = 1; i < argc; i++) {
		strcat(arcs_cmdline, argv[i]);

		if (i < (argc - 1))
			strcat(arcs_cmdline, " ");
	}

	mips_machgroup = MACH_GROUP_NEC_VR41XX;
	mips_machtype = MACH_CASIO_BE300;

	add_memory_region(0, PAGE_ALIGN((16 << 20) - PAGE_SIZE), BOOT_MEM_RAM);
}

void __init prom_free_prom_memory(void)
{
}


--- NEW FILE: setup.c ---
/*
 * arch/mips/vr4131/casio-be300/setup.c
 *
 * Setup routines for the Casio Cassiopeia BE-300
 *
 * Copyright (C) 2002 Paul Mundt <le...@ch...>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */
#include <linux/init.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/console.h>

#include <asm/vr41xx.h>
#include <asm/reboot.h>
#include <asm/time.h>

extern void vr4122_restart(char *command);
extern void vr4122_halt(void);
extern void vr4122_power_off(void);

extern void vr4122_time_init(void);
extern void vr4122_timer_setup(struct irqaction *irq);

void __init bus_error_init(void)
{
}

void __init casio_be300_setup(void)
{
	_machine_restart = vr4122_restart;
	_machine_halt = vr4122_halt;
	_machine_power_off = vr4122_power_off;

	board_time_init = vr4122_time_init;
	board_timer_setup = vr4122_timer_setup;

#ifdef CONFIG_FB
	conswitchp = &dummy_con;
#endif
}

[Linux-mips-commits]CVS: linux/drivers/pcmcia nec.h,NONE,1.1 yenta.c,NONE,1.1

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/pcmcia
In directory usw-pr-cvs1:/tmp/cvs-serv8327/drivers/pcmcia

Added Files:
	nec.h yenta.c 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



--- NEW FILE: nec.h ---
/*
 * BRIEF MODULE DESCRIPTION
 *      Include file for NEC PCMCIA controller.
 *
 * Copyright 2001 MontaVista Software Inc.
 *		so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#ifndef _LINUX_NEC_H
#define _LINUX_NEC_H

static int nec_open(pci_socket_t *socket)
{
	return 0;
}

static struct pci_socket_ops nec_ops = {
	nec_open,
	yenta_close,
	yenta_init,
	yenta_suspend,
	yenta_get_status,
	yenta_get_socket,
	yenta_set_socket,
	yenta_get_io_map,
	yenta_set_io_map,
	yenta_get_mem_map,
	yenta_set_mem_map,
	yenta_proc_setup
};

#endif /* _LINUX_NEC_H */

--- NEW FILE: yenta.c ---
/*
 * Regular lowlevel cardbus driver ("yenta")
 *
 * (C) Copyright 1999, 2000 Linus Torvalds
 */
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/module.h>

#include <pcmcia/version.h>
#include <pcmcia/cs_types.h>
#include <pcmcia/ss.h>
#include <pcmcia/cs.h>

#include <asm/io.h>

#include "yenta.h"
#include "i82365.h"

#if 0
#define DEBUG(x,args...)	printk(__FUNCTION__ ": " x,##args)
#else
#define DEBUG(x,args...)
#endif

/* Don't ask.. */
#define to_cycles(ns)	((ns)/120)
#define to_ns(cycles)	((cycles)*120)

/*
 * Generate easy-to-use ways of reading a cardbus sockets
 * regular memory space ("cb_xxx"), configuration space
 * ("config_xxx") and compatibility space ("exca_xxxx")
 */
static inline u32 cb_readl(pci_socket_t *socket, unsigned reg)
{
	u32 val = readl(socket->base + reg);
	DEBUG("%p %04x %08x\n", socket, reg, val);
	return val;
}

static inline void cb_writel(pci_socket_t *socket, unsigned reg, u32 val)
{
	DEBUG("%p %04x %08x\n", socket, reg, val);
	writel(val, socket->base + reg);
}

static inline u8 config_readb(pci_socket_t *socket, unsigned offset)
{
	u8 val;
	pci_read_config_byte(socket->dev, offset, &val);
	DEBUG("%p %04x %02x\n", socket, offset, val);
	return val;
}

static inline u16 config_readw(pci_socket_t *socket, unsigned offset)
{
	u16 val;
	pci_read_config_word(socket->dev, offset, &val);
	DEBUG("%p %04x %04x\n", socket, offset, val);
	return val;
}

static inline u32 config_readl(pci_socket_t *socket, unsigned offset)
{
	u32 val;
	pci_read_config_dword(socket->dev, offset, &val);
	DEBUG("%p %04x %08x\n", socket, offset, val);
	return val;
}

static inline void config_writeb(pci_socket_t *socket, unsigned offset, u8 val)
{
	DEBUG("%p %04x %02x\n", socket, offset, val);
	pci_write_config_byte(socket->dev, offset, val);
}

static inline void config_writew(pci_socket_t *socket, unsigned offset, u16 val)
{
	DEBUG("%p %04x %04x\n", socket, offset, val);
	pci_write_config_word(socket->dev, offset, val);
}

static inline void config_writel(pci_socket_t *socket, unsigned offset, u32 val)
{
	DEBUG("%p %04x %08x\n", socket, offset, val);
	pci_write_config_dword(socket->dev, offset, val);
}

static inline u8 exca_readb(pci_socket_t *socket, unsigned reg)
{
	u8 val = readb(socket->base + 0x800 + reg);
	DEBUG("%p %04x %02x\n", socket, reg, val);
	return val;
}

static inline u8 exca_readw(pci_socket_t *socket, unsigned reg)
{
	u16 val;
	val = readb(socket->base + 0x800 + reg);
	val |= readb(socket->base + 0x800 + reg + 1) << 8;
	DEBUG("%p %04x %04x\n", socket, reg, val);
	return val;
}

static inline void exca_writeb(pci_socket_t *socket, unsigned reg, u8 val)
{
	DEBUG("%p %04x %02x\n", socket, reg, val);
	writeb(val, socket->base + 0x800 + reg);
}

static void exca_writew(pci_socket_t *socket, unsigned reg, u16 val)
{
	DEBUG("%p %04x %04x\n", socket, reg, val);
	writeb(val, socket->base + 0x800 + reg);
	writeb(val >> 8, socket->base + 0x800 + reg + 1);
}

/*
 * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
 * on what kind of card is inserted..
 */
static int yenta_get_status(pci_socket_t *socket, unsigned int *value)
{
	unsigned int val;
	u32 state = cb_readl(socket, CB_SOCKET_STATE);

	val  = (state & CB_3VCARD) ? SS_3VCARD : 0;
	val |= (state & CB_XVCARD) ? SS_XVCARD : 0;
	val |= (state & (CB_CDETECT1 | CB_CDETECT2 | CB_5VCARD | CB_3VCARD
			 | CB_XVCARD | CB_YVCARD)) ? 0 : SS_PENDING;

	if (state & CB_CBCARD) {
		val |= SS_CARDBUS;	
		val |= (state & CB_CARDSTS) ? SS_STSCHG : 0;
		val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT;
		val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0;
	} else {
		u8 status = exca_readb(socket, I365_STATUS);
		val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
		if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
			val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
		} else {
			val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
			val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
		}
		val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
		val |= (status & I365_CS_READY) ? SS_READY : 0;
		val |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
	}

	*value = val;
	return 0;
}

static int yenta_Vcc_power(u32 control)
{
	switch (control & CB_SC_VCC_MASK) {
	case CB_SC_VCC_5V: return 50;
	case CB_SC_VCC_3V: return 33;
	default: return 0;
	}
}

static int yenta_Vpp_power(u32 control)
{
	switch (control & CB_SC_VPP_MASK) {
	case CB_SC_VPP_12V: return 120;
	case CB_SC_VPP_5V: return 50;
	case CB_SC_VPP_3V: return 33;
	default: return 0;
	}
}

static int yenta_get_socket(pci_socket_t *socket, socket_state_t *state)
{
	u8 reg;
	u32 control;

	control = cb_readl(socket, CB_SOCKET_CONTROL);

	state->Vcc = yenta_Vcc_power(control);
	state->Vpp = yenta_Vpp_power(control);
	state->io_irq = socket->io_irq;

	if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
		u16 bridge = config_readw(socket, CB_BRIDGE_CONTROL);
		if (bridge & CB_BRIDGE_CRST)
			state->flags |= SS_RESET;
		return 0;
	}

	/* 16-bit card state.. */
	reg = exca_readb(socket, I365_POWER);
	state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
	state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;

	reg = exca_readb(socket, I365_INTCTL);
	state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
	state->flags |= (reg & I365_PC_IOCARD) ? SS_IOCARD : 0;

	reg = exca_readb(socket, I365_CSCINT);
	state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
	if (state->flags & SS_IOCARD) {
		state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
	} else {
		state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
		state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
		state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
	}

	return 0;
}

static void yenta_set_power(pci_socket_t *socket, socket_state_t *state)
{
	u32 reg = 0;	/* CB_SC_STPCLK? */
	switch (state->Vcc) {
	case 33: reg = CB_SC_VCC_3V; break;
	case 50: reg = CB_SC_VCC_5V; break;
	default: reg = 0; break;
	}
	switch (state->Vpp) {
	case 33:  reg |= CB_SC_VPP_3V; break;
	case 50:  reg |= CB_SC_VPP_5V; break;
	case 120: reg |= CB_SC_VPP_12V; break;
	}
	if (reg != cb_readl(socket, CB_SOCKET_CONTROL))
		cb_writel(socket, CB_SOCKET_CONTROL, reg);
}

static int yenta_set_socket(pci_socket_t *socket, socket_state_t *state)
{
	u16 bridge;

	if (state->flags & SS_DEBOUNCED) {
		/* The insertion debounce period has ended.  Clear any pending insertion events */
		socket->events &= ~SS_DETECT;
		state->flags &= ~SS_DEBOUNCED;		/* SS_DEBOUNCED is oneshot */
	}
	yenta_set_power(socket, state);
	socket->io_irq = state->io_irq;
	bridge = config_readw(socket, CB_BRIDGE_CONTROL) & ~(CB_BRIDGE_CRST | CB_BRIDGE_INTR);
	if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
		u8 intr;
		bridge |= (state->flags & SS_RESET) ? CB_BRIDGE_CRST : 0;

		/* ISA interrupt control? */
		intr = exca_readb(socket, I365_INTCTL);
		intr = (intr & ~0xf);
		if (!socket->cb_irq) {
			intr |= state->io_irq;
			bridge |= CB_BRIDGE_INTR;
		}
		exca_writeb(socket, I365_INTCTL, intr);
	}  else {
		u8 reg;

		reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA);
		reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
		reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
		if (state->io_irq != socket->cb_irq) {
			reg |= state->io_irq;
			bridge |= CB_BRIDGE_INTR;
		}
		exca_writeb(socket, I365_INTCTL, reg);

		reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK);
		reg |= I365_PWR_NORESET;
		if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
		if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
		if (exca_readb(socket, I365_POWER) != reg)
			exca_writeb(socket, I365_POWER, reg);

		/* CSC interrupt: no ISA irq for CSC */
		reg = I365_CSC_DETECT;
		if (state->flags & SS_IOCARD) {
			if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
		} else {
			if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
			if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
			if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
		}
		exca_writeb(socket, I365_CSCINT, reg);
		exca_readb(socket, I365_CSC);
	}
	config_writew(socket, CB_BRIDGE_CONTROL, bridge);
	/* Socket event mask: get card insert/remove events.. */
	cb_writel(socket, CB_SOCKET_EVENT, -1);
	cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
	return 0;
}

static int yenta_get_io_map(pci_socket_t *socket, struct pccard_io_map *io)
{
	int map;
	unsigned char ioctl, addr;

	map = io->map;
	if (map > 1)
		return -EINVAL;

	io->start = exca_readw(socket, I365_IO(map)+I365_W_START);
	io->stop = exca_readw(socket, I365_IO(map)+I365_W_STOP);

	ioctl = exca_readb(socket, I365_IOCTL);
	addr = exca_readb(socket, I365_ADDRWIN);
	io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
	io->flags  = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
	io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
	io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
	io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;

	return 0;
}

static int yenta_set_io_map(pci_socket_t *socket, struct pccard_io_map *io)
{
	int map;
	unsigned char ioctl, addr, enable;

	map = io->map;

	if (map > 1)
		return -EINVAL;

	enable = I365_ENA_IO(map);
	addr = exca_readb(socket, I365_ADDRWIN);

	/* Disable the window before changing it.. */
	if (addr & enable) {
		addr &= ~enable;
		exca_writeb(socket, I365_ADDRWIN, addr);
	}

	exca_writew(socket, I365_IO(map)+I365_W_START, io->start);
	exca_writew(socket, I365_IO(map)+I365_W_STOP, io->stop);

	ioctl = exca_readb(socket, I365_IOCTL) & ~I365_IOCTL_MASK(map);
	if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
	if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
	if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
	exca_writeb(socket, I365_IOCTL, ioctl);

	if (io->flags & MAP_ACTIVE)
		exca_writeb(socket, I365_ADDRWIN, addr | enable);
	return 0;
}

static int yenta_get_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem)
{
	int map;
	unsigned char addr;
	unsigned int start, stop, page, offset;

	map = mem->map;
	if (map > 4)
		return -EINVAL;

	addr = exca_readb(socket, I365_ADDRWIN);
	mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;

	start = exca_readw(socket, I365_MEM(map) + I365_W_START);
	mem->flags |= (start & I365_MEM_16BIT) ? MAP_16BIT : 0;
	mem->flags |= (start & I365_MEM_0WS) ? MAP_0WS : 0;
	start = (start & 0x0fff) << 12;

	stop = exca_readw(socket, I365_MEM(map) + I365_W_STOP);
	mem->speed = to_ns(stop >> 14);
	stop = ((stop & 0x0fff) << 12) + 0x0fff;

	offset = exca_readw(socket, I365_MEM(map) + I365_W_OFF);
	mem->flags |= (offset & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
	mem->flags |= (offset & I365_MEM_REG) ? MAP_ATTRIB : 0;
	offset = ((offset & 0x3fff) << 12) + start;
	mem->card_start = offset & 0x3ffffff;

	page = exca_readb(socket, CB_MEM_PAGE(map)) << 24;
	mem->sys_start = start + page;
	mem->sys_stop = start + page;

	return 0;
}

static int yenta_set_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem)
{
	int map;
	unsigned char addr, enable;
	unsigned int start, stop, card_start;
	unsigned short word;

	map = mem->map;
	start = mem->sys_start;
	stop = mem->sys_stop;
	card_start = mem->card_start;

	if (map > 4 || start > stop || ((start ^ stop) >> 24) ||
	    (card_start >> 26) || mem->speed > 1000)
		return -EINVAL;

	enable = I365_ENA_MEM(map);
	addr = exca_readb(socket, I365_ADDRWIN);
	if (addr & enable) {
		addr &= ~enable;
		exca_writeb(socket, I365_ADDRWIN, addr);
	}

	exca_writeb(socket, CB_MEM_PAGE(map), start >> 24);

	word = (start >> 12) & 0x0fff;
	if (mem->flags & MAP_16BIT)
		word |= I365_MEM_16BIT;
	if (mem->flags & MAP_0WS)
		word |= I365_MEM_0WS;
	exca_writew(socket, I365_MEM(map) + I365_W_START, word);

	word = (stop >> 12) & 0x0fff;
	switch (to_cycles(mem->speed)) {
		case 0: break;
		case 1:  word |= I365_MEM_WS0; break;
		case 2:  word |= I365_MEM_WS1; break;
		default: word |= I365_MEM_WS1 | I365_MEM_WS0; break;
	}
	exca_writew(socket, I365_MEM(map) + I365_W_STOP, word);

	word = ((card_start - start) >> 12) & 0x3fff;
	if (mem->flags & MAP_WRPROT)
		word |= I365_MEM_WRPROT;
	if (mem->flags & MAP_ATTRIB)
		word |= I365_MEM_REG;
	exca_writew(socket, I365_MEM(map) + I365_W_OFF, word);

	if (mem->flags & MAP_ACTIVE)
		exca_writeb(socket, I365_ADDRWIN, addr | enable);
	return 0;
}

static void yenta_proc_setup(pci_socket_t *socket, struct proc_dir_entry *base)
{
	/* Not done yet */
}

static unsigned int yenta_events(pci_socket_t *socket)
{
	u8 csc;
	u32 cb_event;
	unsigned int events;

	/* Clear interrupt status for the event */
	cb_event = cb_readl(socket, CB_SOCKET_EVENT);
	cb_writel(socket, CB_SOCKET_EVENT, cb_event);

	csc = exca_readb(socket, I365_CSC);

	events = (cb_event & (CB_CD1EVENT | CB_CD2EVENT)) ? SS_DETECT : 0 ;
	events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
	if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
		events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
	} else {
		events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
		events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
		events |= (csc & I365_CSC_READY) ? SS_READY : 0;
	}
	return events;
}


static void yenta_bh(void *data)
{
	pci_socket_t *socket = data;
	unsigned int events;

	spin_lock_irq(&socket->event_lock);
	events = socket->events;
	socket->events = 0;
	spin_unlock_irq(&socket->event_lock);
	if (socket->handler)
		socket->handler(socket->info, events);
}

static void yenta_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned int events;
	pci_socket_t *socket = (pci_socket_t *) dev_id;

	events = yenta_events(socket);
	if (events) {
		spin_lock(&socket->event_lock);
		socket->events |= events;
		spin_unlock(&socket->event_lock);
		schedule_task(&socket->tq_task);
	}
}

static void yenta_interrupt_wrapper(unsigned long data)
{
	pci_socket_t *socket = (pci_socket_t *) data;

	yenta_interrupt(0, (void *)socket, NULL);
	socket->poll_timer.expires = jiffies + HZ;
	add_timer(&socket->poll_timer);
}

/*
 * Only probe "regular" interrupts, don't
 * touch dangerous spots like the mouse irq,
 * because there are mice that apparently
 * get really confused if they get fondled
 * too intimately.
 *
 * Default to 11, 10, 9, 7, 6, 5, 4, 3.
 */
static u32 isa_interrupts = 0x0ef8;

static unsigned int yenta_probe_irq(pci_socket_t *socket, u32 isa_irq_mask)
{
	int i;
	unsigned long val;
	u16 bridge_ctrl;
	u32 mask;

	/* Set up ISA irq routing to probe the ISA irqs.. */
	bridge_ctrl = config_readw(socket, CB_BRIDGE_CONTROL);
	if (!(bridge_ctrl & CB_BRIDGE_INTR)) {
		bridge_ctrl |= CB_BRIDGE_INTR;
		config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl);
	}

	/*
	 * Probe for usable interrupts using the force
	 * register to generate bogus card status events.
	 */
	cb_writel(socket, CB_SOCKET_EVENT, -1);
	cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
	exca_writeb(socket, I365_CSCINT, 0);
	val = probe_irq_on() & isa_irq_mask;
	for (i = 1; i < 16; i++) {
		if (!((val >> i) & 1))
			continue;
		exca_writeb(socket, I365_CSCINT, I365_CSC_STSCHG | (i << 4));
		cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
		udelay(100);
		cb_writel(socket, CB_SOCKET_EVENT, -1);
	}
	cb_writel(socket, CB_SOCKET_MASK, 0);
	exca_writeb(socket, I365_CSCINT, 0);
	
	mask = probe_irq_mask(val) & 0xffff;

	bridge_ctrl &= ~CB_BRIDGE_INTR;
	config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl);

	return mask;
}

/*
 * Set static data that doesn't need re-initializing..
 */
static void yenta_get_socket_capabilities(pci_socket_t *socket, u32 isa_irq_mask)
{
	socket->cap.features |= SS_CAP_PAGE_REGS | SS_CAP_PCCARD | SS_CAP_CARDBUS;
	socket->cap.map_size = 0x1000;
	socket->cap.pci_irq = socket->cb_irq;
	socket->cap.irq_mask = yenta_probe_irq(socket, isa_irq_mask);
	socket->cap.cb_dev = socket->dev;
	socket->cap.bus = NULL;

	printk("Yenta IRQ list %04x, PCI irq%d\n", socket->cap.irq_mask, socket->cb_irq);
}

extern void cardbus_register(pci_socket_t *socket);

/*
 * 'Bottom half' for the yenta_open routine. Allocate the interrupt line
 *  and register the socket with the upper layers.
 */
static void yenta_open_bh(void * data)
{
	pci_socket_t * socket = (pci_socket_t *) data;

	/* It's OK to overwrite this now */
	socket->tq_task.routine = yenta_bh;

	if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, SA_SHIRQ, socket->dev->name, socket)) {
		/* No IRQ or request_irq failed. Poll */
		socket->cb_irq = 0; /* But zero is a valid IRQ number. */
		socket->poll_timer.function = yenta_interrupt_wrapper;
		socket->poll_timer.data = (unsigned long)socket;
		socket->poll_timer.expires = jiffies + HZ;
		add_timer(&socket->poll_timer);
	}

	/* Figure out what the dang thing can do for the PCMCIA layer... */
	yenta_get_socket_capabilities(socket, isa_interrupts);
	printk("Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));

	/* Register it with the pcmcia layer.. */
	cardbus_register(socket);

	MOD_DEC_USE_COUNT;
}

static void yenta_clear_maps(pci_socket_t *socket)
{
	int i;
	pccard_io_map io = { 0, 0, 0, 0, 1 };
	pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };

	mem.sys_stop = 0x0fff;
	yenta_set_socket(socket, &dead_socket);
	for (i = 0; i < 2; i++) {
		io.map = i;
		yenta_set_io_map(socket, &io);
	}
	for (i = 0; i < 5; i++) {
		mem.map = i;
		yenta_set_mem_map(socket, &mem);
	}
}

/*
 * Initialize the standard cardbus registers
 */
static void yenta_config_init(pci_socket_t *socket)
{
	u16 bridge;
	struct pci_dev *dev = socket->dev;

	pci_set_power_state(socket->dev, 0);

	config_writel(socket, CB_LEGACY_MODE_BASE, 0);
	config_writel(socket, PCI_BASE_ADDRESS_0, dev->resource[0].start);
	config_writew(socket, PCI_COMMAND,
			PCI_COMMAND_IO |
			PCI_COMMAND_MEMORY |
			PCI_COMMAND_MASTER |
			PCI_COMMAND_WAIT);

	/* MAGIC NUMBERS! Fixme */
	config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4);
	config_writeb(socket, PCI_LATENCY_TIMER, 168);
	config_writel(socket, PCI_PRIMARY_BUS,
		(176 << 24) |			   /* sec. latency timer */
		(dev->subordinate->subordinate << 16) | /* subordinate bus */
		(dev->subordinate->secondary << 8) |  /* secondary bus */
		dev->subordinate->primary);		   /* primary bus */

	/*
	 * Set up the bridging state:
	 *  - enable write posting.
	 *  - memory window 0 prefetchable, window 1 non-prefetchable
	 *  - PCI interrupts enabled if a PCI interrupt exists..
	 */
	bridge = config_readw(socket, CB_BRIDGE_CONTROL);
	bridge &= ~(CB_BRIDGE_CRST | CB_BRIDGE_PREFETCH1 | CB_BRIDGE_INTR | CB_BRIDGE_ISAEN | CB_BRIDGE_VGAEN);
	bridge |= CB_BRIDGE_PREFETCH0 | CB_BRIDGE_POSTEN;
	if (!socket->cb_irq)
		bridge |= CB_BRIDGE_INTR;
	config_writew(socket, CB_BRIDGE_CONTROL, bridge);

	exca_writeb(socket, I365_GBLCTL, 0x00);
	exca_writeb(socket, I365_GENCTL, 0x00);

	/* Redo card voltage interrogation */
	cb_writel(socket, CB_SOCKET_FORCE, CB_CVSTEST);
}

/* Called at resume and initialization events */
static int yenta_init(pci_socket_t *socket)
{
	yenta_config_init(socket);
	yenta_clear_maps(socket);

	/* Re-enable interrupts */
	cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
	return 0;
}

static int yenta_suspend(pci_socket_t *socket)
{
	yenta_set_socket(socket, &dead_socket);

	/* Disable interrupts */
	cb_writel(socket, CB_SOCKET_MASK, 0x0);

	/*
	 * This does not work currently. The controller
	 * loses too much information during D3 to come up
	 * cleanly. We should probably fix yenta_init()
	 * to update all the critical registers, notably
	 * the IO and MEM bridging region data.. That is
	 * something that pci_set_power_state() should
	 * probably know about bridges anyway.
	 *
	pci_set_power_state(socket->dev, 3);
	 */

	return 0;
}

static void yenta_allocate_res(pci_socket_t *socket, int nr, unsigned type)
{
	struct pci_bus *bus;
	struct resource *root, *res;
	u32 start, end;
	u32 align, size, min, max;
	unsigned offset;
	unsigned mask;

	/* The granularity of the memory limit is 4kB, on IO it's 4 bytes */
	mask = ~0xfff;
	if (type & IORESOURCE_IO)
		mask = ~3;

	offset = 0x1c + 8*nr;
	bus = socket->dev->subordinate;
	res = socket->dev->resource + PCI_BRIDGE_RESOURCES + nr;
	res->name = bus->name;
	res->flags = type;
	res->start = 0;
	res->end = 0;
	root = pci_find_parent_resource(socket->dev, res);

	if (!root)
		return;

	start = config_readl(socket, offset) & mask;
	end = config_readl(socket, offset+4) | ~mask;
	if (start && end > start) {
		res->start = start;
		res->end = end;
		request_resource(root, res);
		return;
	}

	align = size = 4*1024*1024;
	min = PCIBIOS_MIN_MEM; max = ~0U;
	if (type & IORESOURCE_IO) {
		align = 1024;
		size = 256;
		min = 0x4000;
		max = 0xffff;
	}
		
	if (allocate_resource(root, res, size, min, max, align, NULL, NULL) < 0)
		return;

	config_writel(socket, offset, res->start);
	config_writel(socket, offset+4, res->end);
}

/*
 * Allocate the bridge mappings for the device..
 */
static void yenta_allocate_resources(pci_socket_t *socket)
{
	yenta_allocate_res(socket, 0, IORESOURCE_MEM|IORESOURCE_PREFETCH);
	yenta_allocate_res(socket, 1, IORESOURCE_MEM);
	yenta_allocate_res(socket, 2, IORESOURCE_IO);
	yenta_allocate_res(socket, 3, IORESOURCE_IO);	/* PCI isn't clever enough to use this one yet */
}

/*
 * Close it down - release our resources and go home..
 */
static void yenta_close(pci_socket_t *sock)
{
	/* Disable all events so we don't die in an IRQ storm */
	cb_writel(sock, CB_SOCKET_MASK, 0x0);
	exca_writeb(sock, I365_CSCINT, 0);

	if (sock->cb_irq)
		free_irq(sock->cb_irq, sock);
	else
		del_timer_sync(&sock->poll_timer);

	if (sock->base)
		iounmap(sock->base);
}

#include "ti113x.h"
#include "ricoh.h"
#include "nec.h"

/*
 * Different cardbus controllers have slightly different
 * initialization sequences etc details. List them here..
 */
#define PD(x,y) PCI_VENDOR_ID_##x, PCI_DEVICE_ID_##x##_##y
static struct cardbus_override_struct {
	unsigned short vendor;
	unsigned short device;
	struct pci_socket_ops *op;
} cardbus_override[] = {
	{ PD(TI,1130),	&ti113x_ops },
	{ PD(TI,1031),	&ti_ops },
	{ PD(TI,1131),	&ti113x_ops },
	{ PD(TI,1250),	&ti1250_ops },
	{ PD(TI,1220),	&ti_ops },
	{ PD(TI,1221),	&ti_ops },
	{ PD(TI,1210),	&ti_ops },
	{ PD(TI,1450),	&ti_ops },
	{ PD(TI,1225),	&ti_ops },
	{ PD(TI,1251A),	&ti_ops },
	{ PD(TI,1211),	&ti_ops },
	{ PD(TI,1251B),	&ti_ops },
	{ PD(TI,1410),	&ti_ops },
	{ PD(TI,1420),	&ti_ops },
	{ PD(TI,4410),	&ti_ops },
	{ PD(TI,4451),	&ti_ops },

	{ PD(RICOH,RL5C465), &ricoh_ops },
	{ PD(RICOH,RL5C466), &ricoh_ops },
	{ PD(RICOH,RL5C475), &ricoh_ops },
	{ PD(RICOH,RL5C476), &ricoh_ops },
	{ PD(RICOH,RL5C478), &ricoh_ops },

	{ PD(NEC,VRC4173_CARDU), &nec_ops }
};

#define NR_OVERRIDES (sizeof(cardbus_override)/sizeof(struct cardbus_override_struct))

/*
 * Initialize a cardbus controller. Make sure we have a usable
 * interrupt, and that we can map the cardbus area. Fill in the
 * socket information structure..
 */
static int yenta_open(pci_socket_t *socket)
{
	int i;
	struct pci_dev *dev = socket->dev;

	/*
	 * Do some basic sanity checking..
	 */
	if (pci_enable_device(dev))
		return -1;
	if (!pci_resource_start(dev, 0)) {
		printk("No cardbus resource!\n");
		return -1;
	}

	/*
	 * Ok, start setup.. Map the cardbus registers,
	 * and request the IRQ.
	 */
	socket->base = ioremap(pci_resource_start(dev, 0), 0x1000);
	if (!socket->base)
		return -1;

	yenta_config_init(socket);

	/* Disable all events */
	cb_writel(socket, CB_SOCKET_MASK, 0x0);

	/* Set up the bridge regions.. */
	yenta_allocate_resources(socket);

	socket->cb_irq = dev->irq;

	/* Do we have special options for the device? */
	for (i = 0; i < NR_OVERRIDES; i++) {
		struct cardbus_override_struct *d = cardbus_override+i;
		if (dev->vendor == d->vendor && dev->device == d->device) {
			socket->op = d->op;
			if (d->op->open) {
				int retval = d->op->open(socket);
				if (retval < 0)
					return retval;
			}
		}
	}

	/* Get the PCMCIA kernel thread to complete the
	   initialisation later. We can't do this here,
	   because, er, because Linus says so :)
	*/
	socket->tq_task.routine = yenta_open_bh;
	socket->tq_task.data = socket;

	MOD_INC_USE_COUNT;
	schedule_task(&socket->tq_task);

	return 0;
}

/*
 * Standard plain cardbus - no frills, no extensions
 */
struct pci_socket_ops yenta_operations = {
	yenta_open,
	yenta_close,
	yenta_init,
	yenta_suspend,
	yenta_get_status,
	yenta_get_socket,
	yenta_set_socket,
	yenta_get_io_map,
	yenta_set_io_map,
	yenta_get_mem_map,
	yenta_set_mem_map,
	yenta_proc_setup
};
EXPORT_SYMBOL(yenta_operations);
MODULE_LICENSE("GPL");

[Linux-mips-commits]CVS: linux/drivers/char vrc4173-bcu.c,NONE,1.1 vrc4173-piu.c,NONE,1.1 vrc4173-ps2u.c,NONE,1.1 Config.in,1.29,1.30 Makefile,1.24,1.25

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/char
In directory usw-pr-cvs1:/tmp/cvs-serv8327/drivers/char

Modified Files:
	Config.in Makefile 
Added Files:
	vrc4173-bcu.c vrc4173-piu.c vrc4173-ps2u.c 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



--- NEW FILE: vrc4173-bcu.c ---
/*
 * BRIEF MODULE DESCRIPTION
 *	NEC VRC4173 BCU support.
 *
 * Copyright 2001,2002 MontaVista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/types.h>

#include <asm/vrc4173.h>

static struct pci_device_id vrc4173_bcu_table[] __devinitdata = {
	{ PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_VRC4173_BCU,
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
	{ 0, }
};

static rwlock_t vrc4173_cmu_lock = RW_LOCK_UNLOCKED;

void vrc4173_clock_supply(u16 mask)
{
	unsigned long flags;
	u16 val;

	write_lock_irqsave(&vrc4173_cmu_lock, flags);
	val = vrc4173_inw(VRC4173_CMUCLKMSK);
	val |= mask;
	vrc4173_outw(val, VRC4173_CMUCLKMSK);
	write_unlock_irqrestore(&vrc4173_cmu_lock, flags);
}

void vrc4173_clock_mask(u16 mask)
{
	unsigned long flags;
	u16 val;

	write_lock_irqsave(&vrc4173_cmu_lock, flags);
	val = vrc4173_inw(VRC4173_CMUCLKMSK);
	val &= ~mask;
	vrc4173_outw(val, VRC4173_CMUCLKMSK);
	write_unlock_irqrestore(&vrc4173_cmu_lock, flags);

}

static __devinit void init_vrc4173_irq(void)
{
	vrc4173_outw(0, VRC4173_MSYSINT1REG);
	vrc4173_outw(0, VRC4173_MPIUINTREG);
	vrc4173_outw(0, VRC4173_MAIUINTREG);
	vrc4173_outw(0, VRC4173_MKIUINTREG);
	vrc4173_outw(0, VRC4173_MGIULINTREG);
	vrc4173_outw(0, VRC4173_MGIUHINTREG);

	vrc4173_outw(0, VRC4173_GIUINTENL);
	vrc4173_outw(0, VRC4173_GIUINTENH);

	vrc4173_outw(0xffff, VRC4173_GIUINTSTATL);
	vrc4173_outw(0xffff, VRC4173_GIUINTSTATH);
}

static struct irqaction cascade = {
	no_action, 0, 0, "cascade", NULL, NULL
};

static int __devinit vrc4173_bcu_probe(struct pci_dev *pdev,
                                       const struct pci_device_id *ent)
{
	unsigned long base, flags;
	int err = 0;

	printk(KERN_INFO "vrc4173_bcu_probe: found device %#08x.%#08x\n",
	       ent->vendor, ent->device);

	if ((err = pci_enable_device(pdev)) < 0) {
		printk(KERN_ERR "vrc4173_bcu.c: failed to enable device -- err=%d\n",
		       err);
		return err;
	}

	pci_set_master(pdev);

	base = pci_resource_start(pdev, 0);
	if (!base) {
		printk(KERN_ERR "No PCI I/O resources, aborting\n");
		return -ENODEV;
	}

	if (!base || (((flags = pci_resource_flags(pdev, 0)) & IORESOURCE_IO) == 0)) {
		printk(KERN_ERR "No PCI I/O resources, aborting\n");
		return -ENODEV;
	}

	if (setup_irq(pdev->irq, &cascade)) {
		printk(KERN_ERR "No IRQ resources, aborting\n");
		return -ENODEV;
	}


	if (pci_request_regions(pdev, "NEC VRC4173 BCU")) {
		printk(KERN_ERR "No PCI resources, aborting\n");
		return -ENODEV;
	}

	set_vrc4173_io_port_base(base);
	printk(KERN_INFO "    ioaddr=%#08lx resource_flags=%#08lx\n", base, flags);
	printk(KERN_INFO "NEC VRC4173 BCU at 0x%#08lx IRQ cascade %d\n", base, pdev->irq);

	init_vrc4173_irq();

	vrc4173_pci_dev = pdev;
	if (!vrc4173_pci_dev) {
		printk(KERN_ERR "No PCI device resources, aborting\n");
		return -ENODEV;
	}


	return 0;
}

static struct pci_driver vrc4173_bcu_driver = {
	name:		"NEC VRC4173 BCU",
	probe:		vrc4173_bcu_probe,
	remove:		NULL,
	id_table:	vrc4173_bcu_table,
};

static int __devinit vrc4173_bcu_init(void)
{
	int err;

	if ((err = pci_module_init(&vrc4173_bcu_driver)) < 0)
		return err;

	return 0;
}

static void __devexit vrc4173_bcu_exit(void)
{
	vrc4173_pci_dev = NULL;

	pci_unregister_driver(&vrc4173_bcu_driver);
}

module_init(vrc4173_bcu_init);
module_exit(vrc4173_bcu_exit);

--- NEW FILE: vrc4173-piu.c ---
/*
 * linux/drivers/char/vrc4173_tpanel.c
 *
 * Driver for NEC Vrc4173 PIU module.
 *
 * Copyright (C) 2000 Michael R. McDonald
 * Copyright (C) 2001 Montavista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * The touch panel code originally came from arch/mips/vr41xx/tpanel.c
 *
 */

#include <linux/sched.h>
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/miscdevice.h>
#include <linux/random.h>

#include <asm/io.h>
#include <asm/vr4122/vr4122.h>
#ifdef CONFIG_NEC_EAGLE
#include <asm/vr4122/eagle.h>
#endif
#include <asm/vrc4173.h>

/* BUFFSIZE can be increased, but it must be a power of 2 */
#define BUFFSIZE 128

struct tpanel_status {
    unsigned int	buffer[BUFFSIZE];
    unsigned char	head;
    unsigned char	tail;
    unsigned char	lostflag;
    unsigned char	lastcontact;
    wait_queue_head_t 	wait;
    struct fasync_struct *fasyncptr;
    int			active;
};

static struct tpanel_status tpanel;

spinlock_t vrc4173_piu_lock = SPIN_LOCK_UNLOCKED;
static unsigned int data_full = 0;

void vrc4173_piu_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned int data1 = 0, data2 = 0;
	unsigned short intreg, pendown;
	unsigned short xm = 0, xp = 0, ym = 0, yp = 0, z = 0;
	unsigned char head;

	intreg = vrc4173_inw(VRC4173_PIUINTREG) & VRC4173_PIUINTREG_MASK;

	if (intreg & VRC4173_PIUINTREG_PENCHG)
		vrc4173_outw(VRC4173_PIUINTREG_PENCHG, VRC4173_PIUINTREG);

	pendown = vrc4173_inw(VRC4173_PIUCNTREG);
        pendown &= VRC4173_PIUCNTREG_PENSTC;
        if (pendown)
                data1 |= 0x40000000;
        tpanel.lastcontact = pendown >> 13;

	/*
	 * PADCMD and PADADP shouldn't happen
	 */
	if (intreg & (VRC4173_PIUINTREG_PADCMD | VRC4173_PIUINTREG_PADADP)) {
		vrc4173_outw(VRC4173_PIUINTREG_PADCMD | VRC4173_PIUINTREG_PADADP, VRC4173_PIUINTREG);
	}

	/*
	 * PADDLOST interrupt: A/D data timeout
	 */
	if (intreg & VRC4173_PIUINTREG_PADDLOST) {
		tpanel.lostflag = 1;
		vrc4173_outw(VRC4173_PIUINTREG_PADDLOST, VRC4173_PIUINTREG);
	}

	if (intreg & VRC4173_PIUINTREG_PADPAGE1) {
		xm = vrc4173_inw(VRC4173_PIUPB10REG);
		xp = vrc4173_inw(VRC4173_PIUPB11REG);
		ym = vrc4173_inw(VRC4173_PIUPB12REG);
		yp = vrc4173_inw(VRC4173_PIUPB13REG);
		z = vrc4173_inw(VRC4173_PIUPB14REG);
		if ((xm & 0x8000) && (xp & 0x8000) &&
		    (ym & 0x8000) && (yp & 0x8000) && (z & 0x8000)) {
			data1 |= 0x80000000;
			tpanel.lostflag = 0;
		}
		xm &= 0x0fff;
		xp &= 0x0fff;
		ym &= 0x0fff;
		yp &= 0x0fff;
		z &= 0x0fff;

		vrc4173_outw(VRC4173_PIUINTREG_PADPAGE1, VRC4173_PIUINTREG);
	}
	if (intreg & VRC4173_PIUINTREG_PADPAGE0) {
		if ((intreg & (VRC4173_PIUINTREG_PADPAGE1 | VRC4173_PIUINTREG_OVP)) !=
		    (VRC4173_PIUINTREG_PADPAGE1 | VRC4173_PIUINTREG_OVP)) {
			xm = vrc4173_inw(VRC4173_PIUPB00REG);
			xp = vrc4173_inw(VRC4173_PIUPB01REG);
			ym = vrc4173_inw(VRC4173_PIUPB02REG);
			yp = vrc4173_inw(VRC4173_PIUPB03REG);
			z = vrc4173_inw(VRC4173_PIUPB04REG);
			if ((xm & 0x8000) && (xp & 0x8000) &&
			    (ym & 0x8000) && (yp & 0x8000) &&
			    (z & 0x8000)) {
				data1 |= 0x80000000;
				tpanel.lostflag = 0;
			}
			xm &= 0x0fff;
			xp &= 0x0fff;
			ym &= 0x0fff;
			yp &= 0x0fff;
			z &= 0x0fff;
		}

		vrc4173_outw(VRC4173_PIUINTREG_PADPAGE0, VRC4173_PIUINTREG);
	}
	if (intreg & VRC4173_PIUINTREG_OVP)
		vrc4173_outw(VRC4173_PIUINTREG_OVP, VRC4173_PIUINTREG);

	if (tpanel.lostflag) {
		data1 = 0x10000000;
		data2 = 0;
	}
	else {
		data1 |= (xp << 16) | (xm << 4) | (yp >> 8);
		data2 = (yp << 24) | (ym << 12) | z;
	}

	head = tpanel.head;
	tpanel.buffer[tpanel.head++] = data1 | data_full;
	tpanel.buffer[tpanel.head++] = data2;
	tpanel.head &= (BUFFSIZE - 1);
	data_full = 0;
	if (tpanel.head == tpanel.tail) {
		tpanel.head = head;
		data_full = 0x20000000;
	}
	tpanel.lostflag = 0;

	if (data1) {
		add_mouse_randomness(data1);
		if (data2)
			add_mouse_randomness(data2);
		wake_up_interruptible(&tpanel.wait);
		if (tpanel.fasyncptr)
			kill_fasync(&tpanel.fasyncptr, SIGIO, POLL_IN);
	}
	vrc4173_outw(0x0326, VRC4173_PIUCNTREG);
	barrier();
}

static int fasync_tpanel(int fd, struct file *filp, int on)
{
	int retval;

	retval = fasync_helper(fd, filp, on, &tpanel.fasyncptr);
	if (retval < 0)
		return retval;

	return 0;
}

static int close_tpanel(struct inode * inode, struct file * file)
{
	fasync_tpanel(-1, file, 0);
	if (--tpanel.active)
		return 0;

	/* set for standby */
	vrc4173_outw(0, VRC4173_MPIUINTREG);
	vrc4173_outw(0, VRC4173_PIUCNTREG);
	vrc4173_clock_mask(VRC4173_CMUCLKMSK_MSKPIU);

	return 0;
}

static int open_tpanel(struct inode * inode, struct file * file)
{
	u16 val;

	if (tpanel.active++)
		return 0;

	val = vrc4173_inw(VRC4173_SELECTREG);
	val &= ~VRC4173_SELECTREG_SEL3;
	vrc4173_outw(val, VRC4173_SELECTREG);

	vrc4173_outw(0, VRC4173_MPIUINTREG);

	/* Clear any pending interrputs */
	vrc4173_outw(0x007d, VRC4173_PIUINTREG);

	/* Supply TClock for PIU */
	vrc4173_clock_supply(VRC4173_CMUCLKMSK_MSKPIU);

	while (((vrc4173_inw(VRC4173_PIUCNTREG) >> 10) & 0x7) !=
	       VRC4173_PIUCNTREG_STATE_DISABLE)
		;
    
	/* Set PIU outputs as active and change to standby mode */
	val = vrc4173_inw(VRC4173_PIUCNTREG);
	val |= VRC4173_PIUCNTREG_PIUPWR;
	vrc4173_outw(val, VRC4173_PIUCNTREG);

	while (((vrc4173_inw(VRC4173_PIUCNTREG) >> 10) & 0x7) !=
	       VRC4173_PIUCNTREG_STATE_STANDBY)
		;
    
	tpanel.tail = tpanel.head;
	tpanel.lastcontact = 0;

	vrc4173_outw(0x007d, VRC4173_PIUINTREG);	/* clear any pending ints */

	vrc4173_outw(333, VRC4173_PIUSIVLREG);	/* set interval to .01 sec default */
	vrc4173_outw(25, VRC4173_PIUSTBLREG);
	vrc4173_outw(1<<12, VRC4173_PIUCMDREG);
	barrier();

	vrc4173_outw(0x007d, VRC4173_MPIUINTREG);	/* unmask interrupts */
	barrier();

	/* autoscan, sequence enabled */
	vrc4173_outw(0x0326, VRC4173_PIUCNTREG);

	return 0;
}

/*
 *  Read touch panel data.
 *
 *  Data format:
 *  unsigned short status: bit 15 = xyz data valid (0 means contact state only)
 *                         bit 14 = pen contact state (1 means contact)
 *                         bit 13 = soft data lost flag: if this is 1, this data
 *                                  is valid (if bit 15 is 1), but data was lost
 *                                  between this point and the previous point
 *                                  due to a buffer overrun in the driver
 *                         bit 12 = hard data lost flag: if this is 1, this point
 *                                  is valid (if bit 15 is 1), but data was lost
 *                                  between this point and the previous point
 *                                  due to hardware error
 *                         bits 11-8 = reserved
 *                         bits 7-0 = count of how many data packet lost, if hard
 *                                    or soft error is falgged
 *  unsigned short x+ raw data (if status:15 = 1)
 *  unsigned short x- raw data (if status:15 = 1)
 *  unsigned short y+ raw data (if status:15 = 1)
 *  unsigned short y- raw data (if status:15 = 1)
 *  unsigned short z (pressure) raw data (if status:15 = 1)
 *
 *  x+, x-, y+, and y- are limited to range 0-1023 for this hardware.  Each +/-
 *  pair is somewhat redundant: the + value can be used as is, but using the
 *  difference (eg. (x+) - (x-)) will produce a more accurate result.  Further
 *  manipulation and/or statistical analysis may be required for best accuracy.
 *
 *  No calibration is done on the driver side, that is expected to be done on
 *  the user side.
 */

#define TPANEL_DATA_SIZE	12

static ssize_t read_tpanel(struct file * file, char * buffer, size_t count,
                           loff_t *ppos)
{
	unsigned int data1, data2;
	unsigned long flags;
	size_t retcnt = 0;

	if (count < TPANEL_DATA_SIZE)
		return -EINVAL;

	/*
	 * We need to access the circular buffer atomic to
	 * anything else that will read or write it
	 */
	save_and_cli(flags);

	while (tpanel.head == tpanel.tail) {
		if (file->f_flags & O_NONBLOCK) {
			restore_flags(flags);
			return -EAGAIN;
		}
		interruptible_sleep_on(&tpanel.wait);

		/* sleep_on will sti for us */
		if (signal_pending(current))
			return -ERESTARTSYS;
		save_and_cli(flags);
	}
	do {
		data1 = tpanel.buffer[tpanel.tail++];
		data2 = tpanel.buffer[tpanel.tail++];
		tpanel.tail &= BUFFSIZE - 1;

		restore_flags(flags);

		if (!access_ok(VERIFY_WRITE, buffer, TPANEL_DATA_SIZE))
			return -EFAULT;

		__put_user(((data1 >> 16) & 0xf000), (short*)(buffer + retcnt));
		__put_user(((data1 >> 16) & 0x0fff), (short*)(buffer + retcnt + 2));
		__put_user(((data1 >> 4) & 0x0fff), (short*)(buffer + retcnt + 4));
		__put_user((((data1 << 8) | (data2 >> 24)) & 0x0fff),
		           (short*)(buffer + retcnt + 6));
		__put_user(((data2 >> 12) & 0x0fff), (short*)(buffer + retcnt + 8));
		__put_user((data2 & 0x0fff), (short*)(buffer + retcnt + 10));

		retcnt += TPANEL_DATA_SIZE;
		if (retcnt > count - TPANEL_DATA_SIZE)
			return retcnt;

		save_and_cli(flags);
	} while (tpanel.head != tpanel.tail);

	restore_flags(flags);

	return retcnt;
}

static unsigned int poll_tpanel(struct file *file, poll_table * wait)
{
	unsigned long flags;
	int comp;

	poll_wait(file, &tpanel.wait, wait);

	read_lock_irqsave(&vrc4173_piu_lock, flags);
	comp = (tpanel.head != tpanel.tail);
	read_unlock_irqrestore(&vrc4173_piu_lock, flags);

	if (comp)
		return POLLIN | POLLRDNORM;

	return 0;
}

static int ioctl_tpanel(struct inode * inode, struct file * file,
			unsigned int cmd, unsigned long arg)
{
	switch (cmd) {
	default:
		return -EINVAL;
	}
}

struct file_operations vrc4173_tpanel_fops = {
	read:		read_tpanel,
	poll:		poll_tpanel,
	ioctl:		ioctl_tpanel,
	open:		open_tpanel,
	release:	close_tpanel,
	fasync:		fasync_tpanel,
};

static struct miscdevice vrc4173_tpanel = {
	11, "vrc4173tpanel", &vrc4173_tpanel_fops
};

int __init vrc4173_tpanel_init(void)
{
	tpanel.active = 0;
	tpanel.head = tpanel.tail = 0;
	init_waitqueue_head(&tpanel.wait);
	tpanel.fasyncptr = NULL;

	printk("Touch panel initialized.\n");

	if (misc_register(&vrc4173_tpanel) != 0) {
		printk("NEC VRC4173: misc device register failed\n");
		return -EBUSY;
	}

	if (request_irq(VRC4173_IRQ_PIU, vrc4173_piu_interrupt, 0,
	                "NEC VRC4173 PIU", (void *)&vrc4173_tpanel) != 0) {
		printk("NEC VRC4173 PIU: irq=%d busy\n", VRC4173_IRQ_PIU);
		return -EBUSY;
	}

	return 0;
}

--- NEW FILE: vrc4173-ps2u.c ---
/*
 * linux/drivers/char/vrc4173_keyb.c
 *
 * Driver for keyboard of NEC Vrc4173 PS2U 
 *
 * Copyright (C) 2000 Michael R. McDonald
 * Copyright 2001,2002 MontaVista Software Inc.
 * Author: Yoichi Yuasa
 *		yy...@mv... or so...@mv...
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * The PS/2 code originally came from drivers/char/pc_keyb.c
 *
 */
#include <linux/config.h>
#include <linux/init.h>
#include <linux/module.h>

#include <linux/spinlock.h>
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/tty.h>
#include <linux/mm.h>
#include <linux/signal.h>
#include <linux/kbd_ll.h>
#include <linux/delay.h>
#include <linux/random.h>
#include <linux/poll.h>
#include <linux/miscdevice.h>
#include <linux/slab.h>
#include <linux/kbd_kern.h>
#include <linux/smp_lock.h>
#include <linux/kd.h>
#include <linux/pm.h>

#include <asm/keyboard.h>
#include <asm/bitops.h>
#include <asm/uaccess.h>
#include <asm/irq.h>
#include <asm/system.h>

#include <asm/io.h>
//#include <asm/vr4122/vr4122.h>
#include <asm/vrc4173.h>

#define CHANNEL_KEYBOARD	1	/* PS2CH1 */
#define CHANNEL_MOUSE		2	/* PS2CH2 */

/* Some configuration switches are present in the include file... */

#include <linux/pc_keyb.h>

/* Simple translation table for the SysRq keys */

#ifdef CONFIG_MAGIC_SYSRQ
unsigned char kbd_sysrq_xlate[128] =
	"\000\0331234567890-=\177\t"			/* 0x00 - 0x0f */
	"qwertyuiop[]\r\000as"				/* 0x10 - 0x1f */
	"dfghjkl;'`\000\\zxcv"				/* 0x20 - 0x2f */
	"bnm,./\000*\000 \000\201\202\203\204\205"	/* 0x30 - 0x3f */
	"\206\207\210\211\212\000\000789-456+1"		/* 0x40 - 0x4f */
	"230\177\000\000\213\214\000\000\000\000\000\000\000\000\000\000"
							/* 0x50 - 0x5f */
	"\r\000/";					/* 0x60 - 0x6f */
#endif

#ifdef CONFIG_PSMOUSE
static void aux_write_ack(int val);
static void __aux_write_ack(int val);
static int aux_reconnect = 0;
#endif

static spinlock_t vrc4173_ps2u_lock = SPIN_LOCK_UNLOCKED;

#ifdef CONFIG_PSMOUSE
/*
 *	PS/2 Auxiliary Device
 */

static int __devinit psaux_init(void);

#define AUX_RECONNECT1 0xaa	/* scancode1 when ps2 device is plugged (back) in */
#define AUX_RECONNECT2 0x00	/* scancode2 when ps2 device is plugged (back) in */
 
static struct aux_queue *queue;	/* Mouse data buffer. */
static int aux_count;
/* used when we send commands to the mouse that expect an ACK. */
static unsigned char mouse_reply_expected;

#define AUX_INTS_OFF (KBD_MODE_KCC | KBD_MODE_DISABLE_MOUSE | KBD_MODE_SYS | KBD_MODE_KBD_INT)
#define AUX_INTS_ON  (KBD_MODE_KCC | KBD_MODE_SYS | KBD_MODE_MOUSE_INT | KBD_MODE_KBD_INT)

#define MAX_RETRIES	60		/* some aux operations take long time*/
#endif /* CONFIG_PSMOUSE */

static unsigned short wait_for_input(int channel)  
{ 
	long timeout = KBD_INIT_TIMEOUT;
	unsigned short offset;

	offset = (channel == 1) ? 0x0000 : 0x0020;
	do {
//		printk("wait: 0x%04x\n", vrc4173_inw(VRC4173_PS2CH1CTRL + offset));
		if (vrc4173_inw(VRC4173_PS2CH1CTRL + offset) & VRC4173_PS2CTRL_REMT)
			return vrc4173_inw(VRC4173_PS2CH1DATA + offset);
		mdelay(1);
	} while (--timeout);
	return -1;
}

static void send_data(int channel, unsigned short data)
{
	long timeout = KBD_INIT_TIMEOUT;
	unsigned short offset, val;

	offset = (channel == 1) ? 0x0000 : 0x0020;

	spin_lock_irq(&vrc4173_ps2u_lock);
	/* Disable PS/2 interface */
	val = vrc4173_inw(VRC4173_PS2CH1CTRL + offset);
	val |= VRC4173_PS2CTRL_PS2EN;
	vrc4173_outw(val, VRC4173_PS2CH1CTRL + offset);

	/* Wait more than 100usec */
	udelay(110);

	/* All receiving data is read */
	while (vrc4173_inw(VRC4173_PS2CH1CTRL + offset) & VRC4173_PS2CTRL_REMT) {
		val = vrc4173_inw(VRC4173_PS2CH1DATA + offset);
	}

	/* Set a send data */
	vrc4173_outw(data, VRC4173_PS2CH1DATA + offset);

	/* Wait more than 100usec */
	udelay(110);

	/* Enable PS/2 interface */
	val = vrc4173_inw(VRC4173_PS2CH1CTRL + offset);
	val &= ~VRC4173_PS2CTRL_PS2EN;
	vrc4173_outw(val, VRC4173_PS2CH1CTRL + offset);

	while (--timeout &&
	       (vrc4173_inw(VRC4173_PS2CH1CTRL + offset) & VRC4173_PS2CTRL_TEMT))
	       udelay(10);

	if (timeout <= 0)
		printk("PS/2 data transmitting timeout\n");

	spin_unlock_irq(&vrc4173_ps2u_lock);
}

static unsigned char kbd_exists = 1;

void kbd_leds(unsigned char leds)
{
	if (vrc4173_pci_dev) {
		if (kbd_exists) {
			send_data(CHANNEL_KEYBOARD, KBD_CMD_SET_LEDS);
			send_data(CHANNEL_KEYBOARD, leds);
			/* re-enable kbd if any errors */
			send_data(CHANNEL_KEYBOARD, KBD_CMD_ENABLE);
			kbd_exists = 0;
		}
	}
}

int kbd_setkeycode(unsigned int scancode, unsigned int keycode)
{
	return (scancode == keycode) ? 0 : -EINVAL;
}

int kbd_getkeycode(unsigned int scancode)
{
	return scancode;
}

int kbd_translate(unsigned char scancode, unsigned char *keycode,
		        char raw_mode)
{
	*keycode = scancode;
	return 1;
}

char kbd_unexpected_up(unsigned char keycode)
{
	return 0x80;
}

/* AT scancodes to XT scanodes translation table from drivers/char/q40_keyb.c */
unsigned static char at2xt[256] = {
/*  0,   1,   2,   3,   4,   5,   6,   7,   8,   9,   a,   b,   c,   d,   e,   f, */
  0x00,0x43,0x00,0x3f,0x3d,0x3b,0x3c,0x58,0x00,0x44,0x42,0x40,0x3e,0x0f,0x29,0x00,
  0x00,0x38,0x2a,0x00,0x1d,0x10,0x02,0x00,0x00,0x00,0x2c,0x1f,0x1e,0x11,0x03,0x00,
  0x00,0x2e,0x2d,0x20,0x12,0x05,0x04,0x00,0x21,0x39,0x2f,0x21,0x14,0x13,0x06,0x00,
  0x00,0x31,0x30,0x23,0x22,0x15,0x07,0x00,0x24,0x00,0x32,0x24,0x16,0x08,0x09,0x00,
  0x00,0x33,0x25,0x17,0x18,0x0b,0x0a,0x00,0x00,0x34,0x35,0x26,0x27,0x19,0x0c,0x00,
  0x00,0x00,0x28,0x00,0x1a,0x0d,0x00,0x00,0x3a,0x36,0x1c,0x1b,0x00,0x2b,0x00,0x00,
  0x00,0x56,0x00,0x00,0x00,0x00,0x0e,0x00,0x00,0x4f,0x00,0x4b,0x47,0x00,0x00,0x00,
  0x52,0x53,0x50,0x4c,0x4d,0x48,0x01,0x45,0x57,0x4e,0x51,0x4a,0x37,0x49,0x46,0x00,
  0x00,0x00,0x00,0x41,0x37,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
};

int kbd_startup_reset __initdata = 1;

  /* for "kbd-reset" cmdline param */
  static int __init kbd_reset_setup(char *str)
{
	kbd_startup_reset = 1;
	return 1;
}

__setup("kbd-reset", kbd_reset_setup);

static void keyboard_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned short status = vrc4173_inw(VRC4173_PS2CH1CTRL);
	unsigned int work = 10000;
	static int down = 1;

	spin_lock_irq(&vrc4173_ps2u_lock);
	while ((--work > 0) && (status & VRC4173_PS2CTRL_REMT)) {
		unsigned char scancode;

		scancode = vrc4173_inw(VRC4173_PS2CH1DATA) & 0x00ff;
#ifdef CONFIG_VT
		kbd_exists = 1;
		if (scancode == 0x00f0)
			down = 0;
		else {
			handle_scancode(at2xt[scancode], down);
			down = 1;
		}
#endif
		tasklet_schedule(&keyboard_tasklet);

		status = vrc4173_inw(VRC4173_PS2CH1CTRL);
	}
	spin_unlock_irq(&vrc4173_ps2u_lock);
}

static char __init *initialize_kbd(void)
{
	unsigned short status;
	int channel = CHANNEL_KEYBOARD;

	/* Reset PS2U */
	vrc4173_outw(VRC4173_PS2RST_PS2RST, VRC4173_PS2CH1RST);
	udelay(10);

	/* Supply TClock for PS/2 unit channel 1 */
	vrc4173_clock_supply(VRC4173_CMUCLKMSK_MSKPS2CH1);
	udelay(10);

	/* Enable the PS/2 keyboard interface */
	vrc4173_outw(0, VRC4173_PS2CH1CTRL);
    
	/*
	 * Reset keyboard. If the read times out
	 * then the assumption is that no keyboard is
	 * plugged into the machine.
	 * This defaults the keyboard to scan-code set 2.
	 *
	 * Set up to try again if the keyboard asks for RESEND.
	 */
	do {
		send_data(channel, KBD_CMD_RESET);
		status = wait_for_input(channel);
		if (status == KBD_REPLY_ACK)
			break;
		if (status != KBD_REPLY_RESEND)
			return "Keyboard reset failed, no ACK";
	} while (1);

	if (wait_for_input(channel) != KBD_REPLY_POR)
		return "Keyboard reset failed, no POR";

	/*
	 * Set keyboard controller mode. During this, the keyboard should be
	 * in the disabled state.
	 *
	 * Set up to try again if the keyboard asks for RESEND.
	 */
	do {
		send_data(channel, KBD_CMD_DISABLE);
		status = wait_for_input(channel);
		if (status == KBD_REPLY_ACK)
			break;
		if (status != KBD_REPLY_RESEND)
			return "Disable keyboard: no ACK";
	} while (1);

	send_data(channel, KBD_CCMD_WRITE_MODE);
	send_data(channel, KBD_MODE_KBD_INT |
	                   KBD_MODE_SYS |
			   KBD_MODE_DISABLE_MOUSE |
			   KBD_MODE_KCC);

	/* ibm powerpc portables need this to use scan-code set 1 -- Cort */
	send_data(channel, KBD_CCMD_READ_MODE);
	if (!(wait_for_input(channel) & KBD_MODE_KCC)) {
		/*
		 * If the controller does not support conversion,
		 * Set the keyboard to scan-code set 1.
		 */
		send_data(channel, 0xF0);
		wait_for_input(channel);
		send_data(channel, 0x01);
		wait_for_input(channel);
	}

	send_data(channel, KBD_CMD_ENABLE);
	if (wait_for_input(channel) != KBD_REPLY_ACK)
		return "Enable keyboard: no ACK";

	/*
	 * Finally, set the typematic rate to maximum.
	 */
	send_data(channel, KBD_CMD_SET_RATE);
	if (wait_for_input(channel) != KBD_REPLY_ACK)
		return "Set rate: no ACK";
	send_data(channel, 0x00);
	if (wait_for_input(channel) != KBD_REPLY_ACK)
		return "Set rate: no ACK (0x00)";

	vrc4173_outw(VRC4173_PS2CTRL_RVEN | VRC4173_PS2CTRL_INTEN, VRC4173_PS2CH1CTRL);

	return NULL; /* success */
}

void  __init kbd_init_hw(void)
{
	/* Now nothing to do. */
}

static int __devinit vrc4173_ps2u_init(void)
{
	unsigned short val;
	int retval;

	val = vrc4173_inw(VRC4173_SELECTREG);
	val |= VRC4173_SELECTREG_SEL2;
	vrc4173_outw(val, VRC4173_SELECTREG);

	if (kbd_startup_reset) {
		char *msg = initialize_kbd();
		if (msg) {
			printk(KERN_WARNING "initialize_kbd: %s\n", msg);
			return -ENODEV;
		}
	}

#ifdef CONFIG_PSMOUSE
	psaux_init();
#endif

	retval = request_irq(VRC4173_IRQ_PS2CH1, keyboard_interrupt, 0,
	                     "NEC VRC4173 PS2CH1", NULL);
	if (retval) {
		printk("NEC VRC4173 PS2CH1: irq=%d busy\n", VRC4173_IRQ_PS2CH1);
		return retval;
	}

	return 0;
}

#if defined CONFIG_PSMOUSE

static int __init aux_reconnect_setup (char *str)
{
	        aux_reconnect = 1;
		        return 1;
}

__setup("psaux-reconnect", aux_reconnect_setup);

static inline void handle_mouse_event(unsigned char scancode)
{
	static unsigned char prev_code;
	if (mouse_reply_expected) {
		if (scancode == AUX_ACK) {
			mouse_reply_expected--;
			return;
		}
		mouse_reply_expected = 0;
	}
	else if(scancode == AUX_RECONNECT2 && prev_code == AUX_RECONNECT1
	        && aux_reconnect) {
		printk (KERN_INFO "PS/2 mouse reconnect detected\n");
		queue->head = queue->tail = 0;  /* Flush input queue */
		__aux_write_ack(AUX_ENABLE_DEV);  /* ping the mouse :) */
		return;
	}

	prev_code = scancode;
	add_mouse_randomness(scancode);
	if (aux_count) {
		int head = queue->head;

		queue->buf[head] = scancode;
		head = (head + 1) & (AUX_BUF_SIZE-1);
		if (head != queue->tail) {
			queue->head = head;
			kill_fasync(&queue->fasync, SIGIO, POLL_IN);
			wake_up_interruptible(&queue->proc_list);
		}
	}
}

static void mouse_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
	unsigned char scancode;

	while (vrc4173_inw(VRC4173_PS2CH2CTRL) & VRC4173_PS2CTRL_REMT) {
		scancode = (unsigned char)vrc4173_inw(VRC4173_PS2CH2DATA);
		handle_mouse_event(scancode);
	}
}

/*
 * Send a byte to the mouse
 */
static void aux_write_dev(int val)
{
	unsigned long flags;

	spin_lock_irqsave(&vrc4173_ps2u_lock, flags);
	send_data(CHANNEL_MOUSE, val);
	spin_unlock_irqrestore(&vrc4173_ps2u_lock, flags);
}

/*
 * Send a byte to the mouse & handle returned ack
 */
static void __aux_write_ack(int val)
{
	send_data(CHANNEL_MOUSE, val);
	/* we expect an ACK in response. */
	mouse_reply_expected++;
	wait_for_input(CHANNEL_MOUSE);
}

static void aux_write_ack(int val)
{
	unsigned long flags;

	spin_lock_irqsave(&vrc4173_ps2u_lock, flags);
	__aux_write_ack(val);
	spin_unlock_irqrestore(&vrc4173_ps2u_lock, flags);
}

static unsigned char get_from_queue(void)
{
	unsigned char result;
	unsigned long flags;

	spin_lock_irqsave(&vrc4173_ps2u_lock, flags);
	result = queue->buf[queue->tail];
	queue->tail = (queue->tail + 1) & (AUX_BUF_SIZE-1);
	spin_unlock_irqrestore(&vrc4173_ps2u_lock, flags);
	return result;
}

static inline int queue_empty(void)
{
	return queue->head == queue->tail;
}

static int fasync_aux(int fd, struct file *filp, int on)
{
	int retval;

	retval = fasync_helper(fd, filp, on, &queue->fasync);
	if (retval < 0)
		return retval;
	return 0;
}

/*
 * Random magic cookie for the aux device
 */
#define AUX_DEV ((void *)queue)

static int release_aux(struct inode * inode, struct file * file)
{
	unsigned short dummy;

	lock_kernel();
	fasync_aux(-1, file, 0);
	if (--aux_count) {
		unlock_kernel();
		return 0;
	}
	vrc4173_outw(VRC4173_PS2CTRL_PS2EN, AUX_INTS_OFF); /* Disable controller */
	udelay(150);

	/* drain the FIFO */
	while (vrc4173_inw(VRC4173_PS2CH2CTRL) & VRC4173_PS2CTRL_REMT) {
		dummy = vrc4173_inw(VRC4173_PS2CH2DATA);
	}
	free_irq(VRC4173_IRQ_PS2CH2, AUX_DEV);
	vrc4173_clock_mask(VRC4173_CMUCLKMSK_MSKPS2CH2);
	unlock_kernel();
	return 0;
}

/*
 * Install interrupt handler.
 * Enable auxiliary device.
 */

static int open_aux(struct inode * inode, struct file * file)
{
	if (aux_count++) {
		return 0;
	}
	queue->head = queue->tail = 0;		/* Flush input queue */
	if (request_irq(VRC4173_IRQ_PS2CH2, mouse_interrupt, 0,
	                "NEC VRC4173 PS2CH2", AUX_DEV)) {
		aux_count--;
		return -EBUSY;
	}

	/* Supply TClock to PS2CH2 */
	vrc4173_clock_supply(VRC4173_CMUCLKMSK_MSKPS2CH2);
	udelay(10);

	vrc4173_outw(0, VRC4173_PS2CH2CTRL);	/* Enable the auxiliary port 
						   on conntoller. */

	aux_write_ack(AUX_ENABLE_DEV); /* Enable aux device */
	vrc4173_outw(VRC4173_PS2CTRL_INTEN, VRC4173_PS2CH2CTRL); /* Enable conntoller
								    interrupts */

	mdelay(2);

	send_data(CHANNEL_MOUSE, KBD_CMD_ENABLE); /* try to workaround toshiba4030cdt problem */

	return 0;
}

/*
 * Put bytes from input queue to buffer.
 */

static ssize_t read_aux(struct file * file, char * buffer,
			size_t count, loff_t *ppos)
{
	DECLARE_WAITQUEUE(wait, current);
	ssize_t i = count;
	unsigned char c;

	if (queue_empty()) {
		if (file->f_flags & O_NONBLOCK)
			return -EAGAIN;
		add_wait_queue(&queue->proc_list, &wait);
repeat:
		set_current_state(TASK_INTERRUPTIBLE);
		if (queue_empty() && !signal_pending(current)) {
			schedule();
			goto repeat;
		}
		current->state = TASK_RUNNING;
		remove_wait_queue(&queue->proc_list, &wait);
	}
	while (i > 0 && !queue_empty()) {
		c = get_from_queue();
		put_user(c, buffer++);
		i--;
	}
	if (count-i) {
		file->f_dentry->d_inode->i_atime = CURRENT_TIME;
		return count-i;
	}
	if (signal_pending(current))
		return -ERESTARTSYS;
	return 0;
}

/*
 * Write to the aux device.
 */

static ssize_t write_aux(struct file * file, const char * buffer,
			 size_t count, loff_t *ppos)
{
	ssize_t retval = 0;

	if (count) {
		ssize_t written = 0;

		if (count > 32)
			count = 32; /* Limit to 32 bytes. */
		do {
			char c;
			get_user(c, buffer++);
			aux_write_dev(c);
			written++;
		} while (--count);
		retval = -EIO;
		if (written) {
			retval = written;
			file->f_dentry->d_inode->i_mtime = CURRENT_TIME;
		}
	}

	return retval;
}

/* No kernel lock held - fine */
static unsigned int aux_poll(struct file *file, poll_table * wait)
{
	poll_wait(file, &queue->proc_list, wait);
	if (!queue_empty())
		return POLLIN | POLLRDNORM;
	return 0;
}

struct file_operations psaux_fops = {
	read:		read_aux,
	write:		write_aux,
	poll:		aux_poll,
	open:		open_aux,
	release:	release_aux,
	fasync:		fasync_aux,
};

/*
 * Initialize driver.
 */
static struct miscdevice psaux_mouse = {
	PSMOUSE_MINOR, "psaux", &psaux_fops
};

static int __devinit psaux_init(void)
{
	unsigned short val;
	int retval;

	printk(KERN_INFO "Detected PS/2 Mouse Port.\n");

	if ((retval = misc_register(&psaux_mouse)))
		return retval;

	queue = (struct aux_queue *) kmalloc(sizeof(*queue), GFP_KERNEL);
	if (queue == NULL) {
		printk(KERN_ERR "psaux_init() out of memory\n");
		misc_deregister(&psaux_mouse);
		return -ENOMEM;
	}
	memset(queue, 0, sizeof(*queue));
	queue->head = queue->tail = 0;
	init_waitqueue_head(&queue->proc_list);

	val = vrc4173_inw(VRC4173_SELECTREG);
	val |= VRC4173_SELECTREG_SEL1;
	vrc4173_outw(val, VRC4173_SELECTREG);

#ifdef INITIALIZE_MOUSE
	/* Supply TClock to PS2CH2 */
	vrc4173_clock_supply(VRC4173_CMUCLKMSK_MSKPS2CH2);
	udelay(10);

	vrc4173_outw(0, VRC4173_PS2CH2CTRL);	/* Enable Aux. */
	aux_write_ack(AUX_SET_SAMPLE);
	aux_write_ack(100);			/* 100 samples/sec */
	aux_write_ack(AUX_SET_RES);
	aux_write_ack(3);			/* 8 counts per mm */
	aux_write_ack(AUX_SET_SCALE21);		/* 2:1 scaling */
#endif /* INITIALIZE_MOUSE */
	/* Disable aux device and controller interrupts */
	vrc4173_outw(VRC4173_PS2CTRL_PS2EN, VRC4173_PS2CH2CTRL);

	return 0;
}

#endif /* CONFIG_PSMOUSE */

module_init(vrc4173_ps2u_init);

Index: Config.in
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Config.in,v
retrieving revision 1.29
retrieving revision 1.30
diff -u -d -r1.29 -r1.30
--- Config.in	2001/12/02 19:05:31	1.29
+++ Config.in	2002/01/18 21:22:22	1.30
@@ -84,6 +84,13 @@
       fi
    fi
 fi
+if [ "$CONFIG_VR4122" = "y" -o "$CONFIG_VR4131" = "y" ]; then
+   bool 'NEC VRC4173 support' CONFIG_VRC4173
+   if [ "$CONFIG_VRC4173" != "n" ]; then
+     bool '    Enable PS/2 Unit Support' CONFIG_VRC4173_PS2U
+     bool '    Enable Touch Panel Interface Unit Support' CONFIG_VRC4173_PIU
+   fi
+fi
 if [ "$CONFIG_EXPERIMENTAL" = "y" -a "$CONFIG_ZORRO" = "y" ]; then
    tristate 'Commodore A2232 serial support (EXPERIMENTAL)' CONFIG_A2232
 fi

Index: Makefile
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/char/Makefile,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -d -r1.24 -r1.25
--- Makefile	2001/12/05 19:49:28	1.24
+++ Makefile	2002/01/18 21:22:23	1.25
@@ -116,6 +116,14 @@
   SERIAL   =
 endif
 
+ifeq ($(CONFIG_VRC4173),y)
+  ifeq ($(CONFIG_VRC4173_PS2U),y)
+    KEYBD    = vrc4173-ps2u.o
+  else
+    KEYBD    =
+  endif
+endif
+
 ifneq ($(CONFIG_SUN_SERIAL),)
   SERIAL   =
 endif
@@ -136,6 +144,8 @@
 obj-$(CONFIG_SERIAL_SA1100) += serial_sa1100.o
 obj-$(CONFIG_SERIAL_AMBA) += serial_amba.o
 obj-$(CONFIG_TS_AU1000_ADS7846) += au1000_ts.o
+obj-$(CONFIG_VRC4173) += vrc4173-bcu.o
+obj-$(CONFIG_VRC4173_PIU) += vrc4173-piu.o
 
 ifndef CONFIG_SUN_KEYBOARD
   obj-$(CONFIG_VT) += keyboard.o $(KEYMAP) $(KEYBD)

[Linux-mips-commits]CVS: linux/include/asm-mips vrc4173.h,NONE,1.1 bootinfo.h,1.24,1.25

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv8327/include/asm-mips

Modified Files:
	bootinfo.h 
Added Files:
	vrc4173.h 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



--- NEW FILE: vrc4173.h ---
/* $Id: vrc4173.h,v 1.1 2002/01/18 21:22:23 lethal Exp $
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2000 by Michael R. McDonald
 *
 * Copyright 2001 Montavista Software Inc.
 * Author: Yoichi Yuasa
 *              yy...@mv... or so...@mv...
 */
#ifndef __ASM_MIPS_VRC4173_H 
#define __ASM_MIPS_VRC4173_H 

#include <asm/addrspace.h>
#include <asm/io.h>


/*
 * Interrupts Number
 */
#define VRC4173_IRQ_BASE	72
#define VRC4173_IRQ_USB		(VRC4173_IRQ_BASE + 0)
#define VRC4173_IRQ_PCMCIA2	(VRC4173_IRQ_BASE + 1)
#define VRC4173_IRQ_PCMCIA1	(VRC4173_IRQ_BASE + 2)
#define VRC4173_IRQ_PS2CH2	(VRC4173_IRQ_BASE + 3)
#define VRC4173_IRQ_PS2CH1	(VRC4173_IRQ_BASE + 4)
#define VRC4173_IRQ_PIU		(VRC4173_IRQ_BASE + 5)
#define VRC4173_IRQ_AIU		(VRC4173_IRQ_BASE + 6)
#define VRC4173_IRQ_KIU		(VRC4173_IRQ_BASE + 7)
#define VRC4173_IRQ_GIU		(VRC4173_IRQ_BASE + 8)
#define VRC4173_IRQ_AC97	(VRC4173_IRQ_BASE + 9)
#define VRC4173_IRQ_AC97INT1	(VRC4173_IRQ_BASE + 10)
#define VRC4173_IRQ_DOZEPIU	(VRC4173_IRQ_BASE + 13)
#define VRC4173_IRQ_LAST	(VRC4173_IRQ_BASE + 16)


extern struct pci_dev *vrc4173_pci_dev;


/*
 * BCU I/O access
 */
extern unsigned long vrc4173_io_port_base;

#define set_vrc4173_io_port_base(base)	\
	do { vrc4173_io_port_base = mips_io_port_base + (base); } while (0)

#define vrc4173_outb(val,port)							\
do {										\
	*(volatile u8 *)(vrc4173_io_port_base + (port)) = __ioswab8(val);	\
} while(0)

#define vrc4173_outw(val,port)							\
do {										\
	*(volatile u16 *)(vrc4173_io_port_base + (port)) = __ioswab16(val);	\
} while(0)

#define vrc4173_outl(val,port)							\
do {										\
	*(volatile u32 *)(vrc4173_io_port_base + (port)) = __ioswab32(val);	\
} while(0)

#define vrc4173_outb_p(val,port)						\
do {										\
	*(volatile u8 *)(vrc4173_io_port_base + (port)) = __ioswab8(val);	\
	SLOW_DOWN_IO;								\
} while(0)

#define vrc4173_outw_p(val,port)						\
do {										\
	*(volatile u16 *)(vrc4173_io_port_base + (port)) = __ioswab16(val);	\
	SLOW_DOWN_IO;								\
} while(0)

#define vrc4173_outl_p(val,port)						\
do {										\
	*(volatile u32 *)(vrc4173_io_port_base + (port)) = __ioswab32(val);	\
	SLOW_DOWN_IO;								\
} while(0)

#define vrc4173_inb(port) (__ioswab8(*(volatile u8 *)(vrc4173_io_port_base + (port))))
#define vrc4173_inw(port) (__ioswab16(*(volatile u16 *)(vrc4173_io_port_base + (port))))
#define vrc4173_inl(port) (__ioswab32(*(volatile u32 *)(vrc4173_io_port_base + (port))))

#define vrc4173_inb_p(port)							\
({										\
 	u8 __val;								\
										\
	__val = *(volatile u8 *)(vrc4173_io_port_base + (port));		\
	SLOW_DOWN_IO;								\
	__ioswab8(__val);							\
})

#define vrc4173_inw_p(port)							\
({										\
 	u16 __val;								\
										\
	__val = *(volatile u16 *)(vrc4173_io_port_base + (port));		\
	SLOW_DOWN_IO;								\
	__ioswab16(__val);							\
})

#define vrc4173_inl_p(port)							\
({										\
 	u32 __val;								\
										\
	__val = *(volatile u32 *)(vrc4173_io_port_base + (port));		\
	SLOW_DOWN_IO;								\
	__ioswab32(__val);							\
})


static inline void vrc4173_outsb(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		vrc4173_outb(*(u8 *)addr, port);
		addr++;
	}
}

static inline void vrc4173_insb(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u8 *)addr = vrc4173_inb(port);
		addr++;
	}
}

static inline void vrc4173_outsw(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		vrc4173_outw(*(u16 *)addr, port);
		addr += 2;
	}
}

static inline void vrc4173_insw(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u16 *)addr = vrc4173_inw(port);
		addr += 2;
	}
}

static inline void vrc4173_outsl(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		vrc4173_outl(*(u32 *)addr, port);
		addr += 4;
	}
}

static inline void vrc4173_insl(unsigned long port, void *addr, unsigned int count)
{
	while (count--) {
		*(u32 *)addr = vrc4173_inl(port);
		addr += 4;
	}
}


/*
 * BCU PCI Configuration Registers
 */
#define PCI_VRC4173_BUSCNT		0x40
#define VRC4173_BUSCNT_POSTON		0x01

#define PCI_VRC4173_IDSELNUM		0x41
#define VRC4173_IDSELNUM_C1IDSEL	0x03
#define VRC4173_IDSELNUM_C2IDSEL	0x30


/*
 * DMA Address Unit (DMAAU)
 */
#define VRC4173_AIUIBALREG	0x000	/* AIU IN DMA Base Address Register Low */
#define VRC4173_AIUIBAHREG	0x002	/* AIU IN DMA Base Address Register High */
#define VRC4173_AIUIALREG	0x004	/* AIU IN DMA Address Register Low */
#define VRC4173_AIUIAHREG	0x006	/* AIU IN DMA Address Register High */
#define VRC4173_AIUOBALREG	0x008	/* AIU OUT DMA Base Address Register Low */
#define VRC4173_AIUOBAHREG	0x00A	/* AIU OUT DMA Base Address Register High */
#define VRC4173_AIUOALREG	0x00C	/* AIU OUT DMA Address Register Low */
#define VRC4173_AIUOAHREG	0x00E	/* AIU OUT DMA Address Register High */


/*
 * DMA Control Unit (DCU)
 */
#define VRC4173_DMARSTREG	0x020	/* DMA Reset Register */
#define VRC4173_DMAIDLEREG	0x022	/* DMA Sequencer Status Register */
#define VRC4173_DMASENREG	0x024	/* DMA Sequencer Enable Register */
#define VRC4173_DMAMSKREG	0x026	/* DMA Mask Register */
#define VRC4173_DMAREQREG	0x028	/* DMA Request Register */

/*
 * Clock Mask Unit (CMU)
 */
#ifndef _LANGUAGE_ASSEMBLY
extern void vrc4173_clock_supply(unsigned short mask);
extern void vrc4173_clock_mask(unsigned short mask);
#endif

#define VRC4173_CMUCLKMSK	0x040	/* CMU Clock Mask Register */
#define VRC4173_CMUCLKMSK_MSKPIU	0x0001
#define VRC4173_CMUCLKMSK_MSKKIU	0x0002
#define VRC4173_CMUCLKMSK_MSKAIU	0x0004
#define VRC4173_CMUCLKMSK_MSKPS2CH1	0x0008
#define VRC4173_CMUCLKMSK_MSKPS2CH2	0x0010
#define VRC4173_CMUCLKMSK_MSKUSB	0x0020
#define VRC4173_CMUCLKMSK_MSKCARD1	0x0040
#define VRC4173_CMUCLKMSK_MSKCARD2	0x0080
#define VRC4173_CMUCLKMSK_MSKAC97	0x0100
#define VRC4173_CMUCLKMSK_MSK48MUSB	0x0400
#define VRC4173_CMUCLKMSK_MSK48MPIN	0x0800
#define VRC4173_CMUCLKMSK_MSK48MOSC	0x1000

#define VRC4173_CMUSRST		0x042	/* CMU Soft Reset Register */
#define VRC4173_CMUSRST_USBRST		0x0001
#define VRC4173_CMUSRST_CARD1RST	0x0002
#define VRC4173_CMUSRST_CARD2RST	0x0004
#define VRC4173_CMUSRST_AC97RST		0x0008


/*
 * Interrupt Control Unit (ICU)
 */
#define VRC4173_SYSINT1REG	0x060	/* Level 1 System interrupt register 1 */
#define VRC4173_SYSINT1REG_DOZEPIUINTR	0x2000
#define VRC4173_SYSINT1REG_AC97INTR1	0x0400
#define VRC4173_SYSINT1REG_AC97INTR	0x0200
#define VRC4173_SYSINT1REG_GIUINTR	0x0100
#define VRC4173_SYSINT1REG_KIUINTR	0x0080
#define VRC4173_SYSINT1REG_AIUINTR	0x0040
#define VRC4173_SYSINT1REG_PIUINTR	0x0020
#define VRC4173_SYSINT1REG_PS2CH1INTR	0x0010
#define VRC4173_SYSINT1REG_PS2CH2INTR	0x0008
#define VRC4173_SYSINT1REG_PCMCIA1INTR	0x0004
#define VRC4173_SYSINT1REG_PCMCIA2INTR	0x0002
#define VRC4173_SYSINT1REG_USBINTR	0x0001


#define VRC4173_PIUINTREG_RO	0x062	/* Level 2 PIU interrupt register */
#define VRC4173_AIUINTREG	0x064	/* Level 2 AIU interrupt register */
#define VRC4173_KIUINTREG	0x066	/* Level 2 KIU interrupt register */
#define VRC4173_GIULINTREG	0x068	/* Level 2 GIU interrupt register Low */
#define VRC4173_GIUHINTREG	0x06A	/* Level 2 GIU interrupt register High */
#define VRC4173_MSYSINT1REG	0x06C	/* Level 1 mask system interrupt register 1 */
#define VRC4173_MPIUINTREG	0x06E	/* Level 2 mask PIU interrupt register */
#define VRC4173_MAIUINTREG	0x070	/* Level 2 mask AIU interrupt register */
#define VRC4173_MKIUINTREG	0x072	/* Level 2 mask KIU interrupt register */
#define VRC4173_MGIULINTREG	0x074	/* Level 2 mask GIU interrupt register Low */
#define VRC4173_MGIUHINTREG	0x076	/* Level 2 mask GIU interrupt register High */

/*
 * General Purpose I/O Unit (GIU)
 */
#define VRC4173_GIUDIRL		0x080	/* GPIO Input/Output Select Register L */
#define VRC4173_GIUDIRH		0x082	/* GPIO Input/Output Select Register H */
#define VRC4173_GIUPIODL	0x084	/* GPIO Port Input/Output Data Register L */
#define VRC4173_GIUPIODH	0x086	/* GPIO Port Input/Output Data Register H */
#define VRC4173_GIUINTSTATL	0x088	/* GPIO Interrupt Status Register L */
#define VRC4173_GIUINTSTATH	0x08A	/* GPIO Interrupt Status Register H */
#define VRC4173_GIUINTENL	0x08C	/* GPIO Interrupt Enable Register L */
#define VRC4173_GIUINTENH	0x08E	/* GPIO Interrupt Enable Register H */
#define VRC4173_GIUINTTYPL	0x090	/* GPIO Interrupt Type (Edge/Level) Select Register */
#define VRC4173_GIUINTTYPH	0x092	/* GPIO Interrupt Type (Edge/Level) Select Register */
#define VRC4173_GIUINTALSELL	0x094	/* GPIO Interrupt Active Level Select Register L */
#define VRC4173_GIUINTALSELH	0x096	/* GPIO Interrupt Active Level Select Register H */
#define VRC4173_GIUINTHTSELL	0x098	/* GPIO Interrupt Hold/Through Select Register L */
#define VRC4173_GIUINTHTSELH	0x09A	/* GPIO Interrupt Hold/Through Select Register H */
#define VRC4173_SELECTREG	0x09E	/* GPIO Port Output Data Enable Register */

#define VRC4173_SELECTREG_SEL0	0x0001
#define VRC4173_SELECTREG_SEL1	0x0002
#define VRC4173_SELECTREG_SEL2	0x0004
#define VRC4173_SELECTREG_SEL3	0x0008

#define VRC4173_GIUPIODH_GPIO20		0x0010
#define VRC4173_GIUPIODH_GPIO19		0x0008
#define VRC4173_GIUPIODH_GPIO18		0x0004
#define VRC4173_GIUPIODH_GPIO17		0x0002
#define VRC4173_GIUPIODH_GPIO16		0x0001
#define VRC4173_GIUPIODL_GPIO15		0x8000
#define VRC4173_GIUPIODL_GPIO14		0x4000
#define VRC4173_GIUPIODL_GPIO13		0x2000
#define VRC4173_GIUPIODL_GPIO12		0x1000
#define VRC4173_GIUPIODL_GPIO11		0x0800
#define VRC4173_GIUPIODL_GPIO10		0x0400
#define VRC4173_GIUPIODL_GPIO9		0x0200
#define VRC4173_GIUPIODL_GPIO8		0x0100
#define VRC4173_GIUPIODL_GPIO7		0x0080
#define VRC4173_GIUPIODL_GPIO6		0x0040
#define VRC4173_GIUPIODL_GPIO5		0x0020
#define VRC4173_GIUPIODL_GPIO4		0x0010
#define VRC4173_GIUPIODL_GPIO3		0x0008
#define VRC4173_GIUPIODL_GPIO2		0x0004
#define VRC4173_GIUPIODL_GPIO1		0x0002
#define VRC4173_GIUPIODL_GPIO0		0x0001


/*
 * Touch Panel Interface Unit (PIU)
 */
#define VRC4173_PIUCNTREG		0x0A2	/* PIU Control register (R/W) */
#define VRC4173_PIUCNTREG_PENSTC	0x2000
#define VRC4173_PIUCNTREG_PIUSEQEN	0x0004
#define VRC4173_PIUCNTREG_PIUPWR	0x0002
#define VRC4173_PIUCNTREG_PADRST	0x0001
#define VRC4173_PIUCNTREG_STATE_DISABLE		0
#define VRC4173_PIUCNTREG_STATE_STANDBY		1
#define VRC4173_PIUCNTREG_STATE_PORTSCAN	2
#define VRC4173_PIUCNTREG_STATE_WAITPEN		4
#define VRC4173_PIUCNTREG_STATE_PENSCAN		5
#define VRC4173_PIUCNTREG_STATE_NEXTSCAN	6
#define VRC4173_PIUCNTREG_STATE_CMDSCAN		7

#define VRC4173_PIUINTREG		0x0A4	/* PIU Interrupt cause register (R/W) */
#define VRC4173_PIUINTREG_OVP		0x8000
#define VRC4173_PIUINTREG_PADCMD	0x0040
#define VRC4173_PIUINTREG_PADADP	0x0020
#define VRC4173_PIUINTREG_PADPAGE1	0x0010
#define VRC4173_PIUINTREG_PADPAGE0	0x0008
#define VRC4173_PIUINTREG_PADDLOST	0x0004
#define VRC4173_PIUINTREG_PENCHG	0x0001
#define VRC4173_PIUINTREG_MASK		0x807d

#define VRC4173_PIUSIVLREG	0x0A6	/* PIU Data sampling interval register (R/W) */
#define VRC4173_PIUSTBLREG	0x0A8	/* PIU A/D converter start delay register (R/W) */
#define VRC4173_PIUCMDREG	0x0AA	/* PIU A/D command register (R/W) */
#define VRC4173_PIUASCNREG	0x0B0	/* PIU A/D port scan register (R/W) */
#define VRC4173_PIUAMSKREG	0x0B2	/* PIU A/D scan mask register (R/W) */
#define VRC4173_PIUCIVLREG	0x0BE	/* PIU Check interval register (R) */
#define VRC4173_PIUPB00REG	0x0C0	/* PIU Page 0 Buffer 0 register (R/W) */
#define VRC4173_PIUPB01REG	0x0C2	/* PIU Page 0 Buffer 1 register (R/W) */
#define VRC4173_PIUPB02REG	0x0C4	/* PIU Page 0 Buffer 2 register (R/W) */
#define VRC4173_PIUPB03REG	0x0C6	/* PIU Page 0 Buffer 3 register (R/W) */
#define VRC4173_PIUPB10REG	0x0C8	/* PIU Page 1 Buffer 0 register (R/W) */
#define VRC4173_PIUPB11REG	0x0CA	/* PIU Page 1 Buffer 1 register (R/W) */
#define VRC4173_PIUPB12REG	0x0CC	/* PIU Page 1 Buffer 2 register (R/W) */
#define VRC4173_PIUPB13REG	0x0CE	/* PIU Page 1 Buffer 3 register (R/W) */
#define VRC4173_PIUAB0REG	0x0D0	/* PIU A/D scan Buffer 0 register (R/W) */
#define VRC4173_PIUAB1REG	0x0D2	/* PIU A/D scan Buffer 1 register (R/W) */
#define VRC4173_PIUPB04REG	0x0DC	/* PIU Page 0 Buffer 4 register (R/W) */
#define VRC4173_PIUPB14REG	0x0DE	/* PIU Page 1 Buffer 4 register (R/W) */


/*
 * Audio Interface Unit (AIU)
 */
#define VRC4173_MDMADATREG	0x0E0	/* Mike DMA Data Register (R/W) */
#define VRC4173_SDMADATREG	0x0E2	/* Speaker DMA Data Register (R/W) */
#define VRC4173_SODATREG	0x0E6	/* Speaker Output Data Register (R/W) */
#define VRC4173_SCNTREG		0x0E8	/* Speaker Output Control Register (R/W) */
#define VRC4173_SCNVRREG	0x0EA	/* Speaker Conversion Rate Register (R/W) */
#define VRC4173_MIDATREG	0x0F0	/* Mike Input Data Register (R/W) */
#define VRC4173_MCNTREG		0x0F2	/* Mike Input Control Register (R/W) */
#define VRC4173_MCNVRREG	0x0F4	/* Mike Conversion Rate Register (R/W) */
#define VRC4173_DVALIDREG	0x0F8	/* Data Valid Register (R/W) */
#define VRC4173_SEQREG		0x0FA	/* Sequential Register (R/W) */
#define VRC4173_INTREG		0x0FC	/* Interrupt Register (R/W) */


/*
 * Keyboard Interface Unit (KIU) of the VRC4173
 */
#define VRC4173_KIUDAT0		0x100	/* KIU Data0 Register (R/W) */
#define VRC4173_KIUDAT1		0x102	/* KIU Data1 Register (R/W) */
#define VRC4173_KIUDAT2		0x104	/* KIU Data2 Register (R/W) */
#define VRC4173_KIUDAT3		0x106	/* KIU Data3 Register (R/W) */
#define VRC4173_KIUDAT4		0x108	/* KIU Data4 Register (R/W) */
#define VRC4173_KIUDAT5		0x10A	/* KIU Data5 Register (R/W) */
#define VRC4173_KIUSCANREP	0x110	/* KIU Scan/Repeat Register (R/W) */
#define VRC4173_KIUSCANREP_KEYEN	0x8000
#define VRC4173_KIUSCANREP_SCANSTP	0x0008
#define VRC4173_KIUSCANREP_SCANSTART	0x0004
#define VRC4173_KIUSCANREP_ATSTP	0x0002
#define VRC4173_KIUSCANREP_ATSCAN	0x0001
#define VRC4173_KIUSCANS	0x112	/* KIU Scan Status Register (R) */
#define VRC4173_KIUWKS		0x114	/* KIU Wait Keyscan Stable Register (R/W) */
#define VRC4173_KIUWKI		0x116	/* KIU Wait Keyscan Interval Register (R/W) */
#define VRC4173_KIUINT		0x118	/* KIU Interrupt Register (R/W) */
#define VRC4173_KIUINT_KDATLOST		0x0004
#define VRC4173_KIUINT_KDATRDY		0x0002
#define VRC4173_KIUINT_SCANINT		0x0001
#define VRC4173_KIURST		0x11A	/* KIU Reset Register (W) */
#define VRC4173_KIUGPEN		0x11C	/* KIU General Purpose Output Enable (R/W) */
#define VRC4173_SCANLINE	0x11E	/* KIU Scan Line Register (R/W) */


/*
 * PS/2 Unit (PS2U)
 */
#define VRC4173_PS2CH1DATA	0x120	/* PS2 Channel 1 Data Register (R/W) */
#define VRC4173_PS2CH1CTRL	0x122	/* PS2 Channel 1 Control Register (R/W) */
#define VRC4173_PS2CH1RST	0x124	/* PS2 Channel 1 Reset Register (R/W) */

#define VRC4173_PS2CH2DATA	0x140	/* PS2 Channel 2 Data Register (R/W) */
#define VRC4173_PS2CH2CTRL	0x142	/* PS2 Channel 2 Control Register (R/W) */
#define VRC4173_PS2CH2RST	0x144	/* PS2 Channel 2 Reset Register (R/W) */

#define VRC4173_PS2CTRL_REMT	0x0001
#define VRC4173_PS2CTRL_TEMT	0x0002
#define VRC4173_PS2CTRL_PS2EN	0x0004
#define VRC4173_PS2CTRL_INTEN	0x0008
#define VRC4173_PS2CTRL_RVEN	0x0010
#define VRC4173_PS2CTRL_PERR	0x0020

#define VRC4173_PS2RST_PS2RST	0x0001


/*
 * AC97 Unit (AC97U)
 */
#define VRC4173_AC97_INT_STATUS		0x000	/* Interrupt Clear/Status Register */
#define VRC4173_AC97_CODEC_WR		0x004	/* Codec Write Register */
#define VRC4173_AC97_CODEC_RD		0x008	/* Codec Read Register */
#define VRC4173_AC97_ACLINK_CTRL	0x01C	/* ACLINK Control Register */

#define VRC4173_AC97_CODEC_WR_RWC	(1<<23)	/* sets read/write command */
#define VRC4173_AC97_CODEC_WR_WRDY	(1<<31)	/* write ready */

#define VRC4173_AC97_CODEC_RD_RDRDY	(1<<30)	/* Read Data Ready */
#define VRC4173_AC97_CODEC_RD_DMASK	0xffff	/* Read Data Mask */

#define VRC4173_AC97_ACLINK_CTRL_SYNC_ON	(1<<30)	/* Codec sync bit */

#endif /* __ASM_MIPS_VRC4173_H */

Index: bootinfo.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/bootinfo.h,v
retrieving revision 1.24
retrieving revision 1.25
diff -u -d -r1.24 -r1.25
--- bootinfo.h	2002/01/15 17:08:43	1.24
+++ bootinfo.h	2002/01/18 21:22:23	1.25
@@ -171,6 +171,7 @@
 #define MACH_VADEM_CLIO_1000		3	/* Vadem Clio 1000 */
 #define MACH_NEC_MOBILEPRO_780		4	/* NEC MobilePro 780 PDA */
 #define MACH_CASIO_E15			5	/* Casio Cassiopeia E15 */
+#define MACH_CASIO_BE300		6	/* Casio Cassiopeia BE-300 */
 
 #define CL_SIZE			80
 

[Linux-mips-commits]CVS: linux/drivers/video mq200fb.c,1.3,1.4

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/drivers/video
In directory usw-pr-cvs1:/tmp/cvs-serv8327/drivers/video

Modified Files:
	mq200fb.c 
Log Message:
NEC Vr4122/Vr4131/Vrc4173 updates.



Index: mq200fb.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/drivers/video/mq200fb.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- mq200fb.c	2002/01/16 08:17:32	1.3
+++ mq200fb.c	2002/01/18 21:22:23	1.4
@@ -151,6 +151,8 @@
 	0 |		/* VERT_LCD_CRT		0x30000000	QView vert arrangement */
 	0 |		/* LCDCRT_POS_MASK	0x30000000	mask for QV orientation */
 	0		/* LCDCRT_POS_MASK	0x30000000	mask for QV orientation */
+#elif defined(CONFIG_NEC_EAGLE)
+	640, 480, 16, 60, 640*2, 0x00030003
 #else
 #if 0
 	800,		/* int	x;		x resolution */

[Linux-mips-commits]CVS: linux/arch/mips/vr4131/common - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4131/common
In directory usw-pr-cvs1:/tmp/cvs-serv7405/arch/mips/vr4131/common

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr4131/common added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr4131/casio-be300 - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4131/casio-be300
In directory usw-pr-cvs1:/tmp/cvs-serv7405/arch/mips/vr4131/casio-be300

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr4131/casio-be300 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/vr4131 - New directory

[Paul M. <le...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/vr4131
In directory usw-pr-cvs1:/tmp/cvs-serv7329/arch/mips/vr4131

Log Message:
Directory /cvsroot/linux-mips/linux/arch/mips/vr4131 added to the repository

[Linux-mips-commits]CVS: linux/arch/mips/rc32300/79S334 irq.c,1.5,1.6 pci_fixup.c,1.2,1.3 pci_ops.c,1.2,1.3 prom.c,1.3,1.4 setup.c,1.3,1.4

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv24611/79S334

Modified Files:
	irq.c pci_fixup.c pci_ops.c prom.c setup.c 
Log Message:
Changed include paths to reflect new location of RC32300 headers.


Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/irq.c,v
retrieving revision 1.5
retrieving revision 1.6
diff -u -d -r1.5 -r1.6
--- irq.c	2002/01/17 20:11:46	1.5
+++ irq.c	2002/01/17 21:07:24	1.6
@@ -45,7 +45,7 @@
 #include <asm/io.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 #undef DEBUG_IRQ
 #ifdef DEBUG_IRQ

Index: pci_fixup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_fixup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci_fixup.c	2002/01/15 23:58:00	1.2
+++ pci_fixup.c	2002/01/17 21:07:24	1.3
@@ -35,7 +35,7 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 void __init pcibios_fixup_resources(struct pci_dev *dev)
 {

Index: pci_ops.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/pci_ops.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci_ops.c	2002/01/15 23:58:00	1.2
+++ pci_ops.c	2002/01/17 21:07:24	1.3
@@ -37,7 +37,7 @@
 #include <linux/init.h>
 
 #include <asm/pci_channel.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1

Index: prom.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/prom.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- prom.c	2002/01/16 22:51:21	1.3
+++ prom.c	2002/01/17 21:07:24	1.4
@@ -44,7 +44,7 @@
 #include <linux/sched.h>
 #include <linux/bootmem.h>
 #include <linux/ioport.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 char arcs_cmdline[CL_SIZE];
 

Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- setup.c	2002/01/17 20:13:18	1.3
+++ setup.c	2002/01/17 21:07:24	1.4
@@ -37,7 +37,7 @@
 #include <asm/pgtable.h>
 #include <linux/mc146818rtc.h>	/* for rtc_ops, we fake the RTC */
 #include <asm/reboot.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 extern void (*board_time_init)(void);
 extern void (*board_timer_setup)(struct irqaction *irq);

[Linux-mips-commits]CVS: linux/arch/mips/rc32300/common dbg_io.c,1.3,1.4 idtdisplay.c,1.1,1.2 puts.c,1.4,1.5 reset.c,1.2,1.3 time.c,1.3,1.4

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/common
In directory usw-pr-cvs1:/tmp/cvs-serv24611/common

Modified Files:
	dbg_io.c idtdisplay.c puts.c reset.c time.c 
Log Message:
Changed include paths to reflect new location of RC32300 headers.


Index: dbg_io.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/dbg_io.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- dbg_io.c	2002/01/15 23:55:42	1.3
+++ dbg_io.c	2002/01/17 21:07:24	1.4
@@ -1,6 +1,6 @@
 
 #include <linux/config.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 #ifdef CONFIG_REMOTE_DEBUG
 

Index: idtdisplay.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/idtdisplay.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- idtdisplay.c	2002/01/17 03:08:48	1.1
+++ idtdisplay.c	2002/01/17 21:07:24	1.2
@@ -42,8 +42,8 @@
 #include <linux/errno.h>
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/rc32300.h>
-#include <asm/idtdisplay.h>
+#include <asm/rc32300/rc32300.h>
+#include <asm/rc32300/idtdisplay.h>
 
 
 /**

Index: puts.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/puts.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- puts.c	2002/01/15 23:55:43	1.4
+++ puts.c	2002/01/17 21:07:24	1.5
@@ -29,7 +29,7 @@
  */
 
 #include <linux/types.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 #define SERIAL_BASE RC32300_UART0_BASE
 

Index: reset.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/reset.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- reset.c	2002/01/15 23:55:43	1.2
+++ reset.c	2002/01/17 21:07:24	1.3
@@ -35,7 +35,7 @@
 #include <asm/processor.h>
 #include <asm/reboot.h>
 #include <asm/system.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 void rc32300_restart(char *command)
 {

Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/time.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -d -r1.3 -r1.4
--- time.c	2002/01/17 20:14:35	1.3
+++ time.c	2002/01/17 21:07:24	1.4
@@ -35,7 +35,7 @@
 #include <asm/mipsregs.h>
 #include <asm/ptrace.h>
 #include <asm/debug.h>
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 
 static unsigned long r4k_offset; /* Amount to incr compare reg each time */
 static unsigned long r4k_cur;    /* What counter should be at next timer irq */

[Linux-mips-commits]CVS: linux/include/asm-mips/rc32300 79s334.h,1.1,1.2 rc32300.h,1.1,1.2

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/rc32300
In directory usw-pr-cvs1:/tmp/cvs-serv24213/rc32300

Modified Files:
	79s334.h rc32300.h 
Log Message:
Changed include paths to reflect new location of RC32300 headers.


Index: 79s334.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32300/79s334.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- 79s334.h	2002/01/17 20:22:51	1.1
+++ 79s334.h	2002/01/17 21:06:46	1.2
@@ -56,6 +56,6 @@
 
 #define RAM_SIZE	(32*1024*1024)
 
-#include <asm/rc32334.h>
+#include <asm/rc32300/rc32334.h>
 
 #endif /* _79S334_H_ */

Index: rc32300.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32300/rc32300.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- rc32300.h	2002/01/17 20:22:51	1.1
+++ rc32300.h	2002/01/17 21:06:46	1.2
@@ -35,9 +35,9 @@
 #include <asm/io.h>
 
 #ifdef CONFIG_IDT_79S334
-#include <asm/79s334.h>
+#include <asm/rc32300/79s334.h>
 #elif defined(CONFIG_IDT_79EB355)
-#include <asm/79eb355.h>
+#include <asm/rc32300/79eb355.h>
 #endif
 
 /* cpu pipeline flush */

[Linux-mips-commits]CVS: linux/include/asm-mips serial.h,1.9,1.10

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv24213

Modified Files:
	serial.h 
Log Message:
Changed include paths to reflect new location of RC32300 headers.


Index: serial.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/serial.h,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -d -r1.9 -r1.10
--- serial.h	2002/01/16 00:00:42	1.9
+++ serial.h	2002/01/17 21:06:46	1.10
@@ -160,7 +160,7 @@
 #endif
 
 #ifdef CONFIG_CPU_RC32300
-#include <asm/rc32300.h>
+#include <asm/rc32300/rc32300.h>
 #define RC32300_SERIAL_PORT_DEFNS                 \
     { baud_base: RC32300_BASE_BAUD,               \
       iomem_base: KSEG1ADDR(RC32300_UART0_BASE),  \

[Linux-mips-commits]CVS: linux/include/asm-mips/rc32300 79s334.h,NONE,1.1 idtdisplay.h,NONE,1.1 rc32300.h,NONE,1.1 rc32334.h,NONE,1.1

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/rc32300
In directory usw-pr-cvs1:/tmp/cvs-serv11644

Added Files:
	79s334.h idtdisplay.h rc32300.h rc32334.h 
Log Message:
Moved to asm-mips/rc32300/.


--- NEW FILE: 79s334.h ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Definitions for IDT 79S334 evaluation board.
 *
 * Copyright 2000,2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	st...@mv... or so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _79S334_H_
#define _79S334_H_

#define IDT_BUS_FREQ   75 // MHz
#define IDT_CLOCK_MULT 2

/* NVRAM */
#define NVRAM_BASE         0x12000000
#define NVRAM_SIZE         512

/* LCD 4-digit display */
#define LCD_CLEAR          0x14000400
#define LCD_DIGIT0         0x1400000f
#define LCD_DIGIT1         0x14000008
#define LCD_DIGIT2         0x14000007
#define LCD_DIGIT3         0x14000003

extern int idtprintf(const char *fmt, ...);

/* Interrupts routed on 79S334A board (see rc32334.h) */
#define RC32334_SCC8530_IRQ  2
#define RC32334_PCI_INTA_IRQ 3
#define RC32334_PCI_INTB_IRQ 4
#define RC32334_PCI_INTC_IRQ 6
#define RC32334_PCI_INTD_IRQ 7

#define RAM_SIZE	(32*1024*1024)

#include <asm/rc32334.h>

#endif /* _79S334_H_ */

--- NEW FILE: idtdisplay.h ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *	79S334A 4 digits display.
 *
 * Copyright 2002 THOMSON multimedia.
 * Author: Stephane Fillod & Guillaume Lorand
 *         	fi...@th...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _IDTDISPLAY_H
#define _IDTDISPLAY_H

#define IDTDISPLAY_BUF_SIZE 256 /**< size of the internal buffer */

#define IDTDISPLAY_IOC_MAGICNUM 'x'
#define IDTDISPLAY_IOC_BASE 0x00


/**
 * clean the display
 */
#define IDTDISPLAY_IOCTL_CLEAN         _IO   (IDTDISPLAY_IOC_MAGICNUM, (IDTDISPLAY_IOC_BASE +  0))

/**
 * write one char on the display
 * see idtdisplay_wc_struct
 */
#define IDTDISPLAY_IOCTL_WRITE_CHAR    _IOW  (IDTDISPLAY_IOC_MAGICNUM, (IDTDISPLAY_IOC_BASE +  1), struct idtdisp_wc_struct)

/**
 * write four chars on the display
 */
#define IDTDISPLAY_IOCTL_WRITE_4       _IOW  (IDTDISPLAY_IOC_MAGICNUM, (IDTDISPLAY_IOC_BASE +  2), u_long)

/**
 * set up an new delay between scrolling
 */
#define IDTDISPLAY_IOCTL_DELAY         _IOW  (IDTDISPLAY_IOC_MAGICNUM, (IDTDISPLAY_IOC_BASE +  3), u_int)


/**
 * structure passed to ioctl function for IDTDISPLAY_IOCTL_WRITE_CHAR
 */
struct idtdisp_wc_struct {
  char ch ; /**< character to display */
  int nb ;  /**< number of the display */
};

#ifdef __KERNEL__

/** @name __KERNEL__
*/
//@{
#define IDTDISPLAY_MINOR 254 /**< default minor number */
#define IDTDISPLAY_DELAY 500 /**< default inter scrolling delay in ms */


/* 100 = 1 seconde */
/* 100/1000 = 1 milli-second = 0,1 */
#define MS_TO_HZ(ms) ((ms) * HZ / 1000) /** convert delay in millisecond to jiffies */

#endif // __KERNEL__
//@}


#endif // _IDTDISPLAY_H

--- NEW FILE: rc32300.h ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Definitions for IDT RC32300 CPU Core.
 *
 * Copyright 2000,2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	st...@mv... or so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _RC32300_H_
#define _RC32300_H_

#include <linux/delay.h>
#include <asm/io.h>

#ifdef CONFIG_IDT_79S334
#include <asm/79s334.h>
#elif defined(CONFIG_IDT_79EB355)
#include <asm/79eb355.h>
#endif

/* cpu pipeline flush */
static inline void rc32300_sync(void)
{
        __asm__ volatile ("sync");
}

static inline void rc32300_sync_udelay(int us)
{
        __asm__ volatile ("sync");
        udelay(us);
}

static inline void rc32300_sync_delay(int ms)
{
        __asm__ volatile ("sync");
        mdelay(ms);
}

/*
 * C access to CLZ and CLO instructions
 * (count leading zeroes/ones).
 */
static inline int rc32300_clz(unsigned long val)
{
	int ret;
        __asm__ volatile (
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips32\n\t"
		"clz\t%0,%1\n\t"
                ".set\tmips0\n\t"
                ".set\tat\n\t"
                ".set\treorder"
                : "=r" (ret)
		: "r" (val));

	return ret;
}
static inline int rc32300_clo(unsigned long val)
{
	int ret;
        __asm__ volatile (
		".set\tnoreorder\n\t"
		".set\tnoat\n\t"
		".set\tmips32\n\t"
		"clo\t%0,%1\n\t"
                ".set\tmips0\n\t"
                ".set\tat\n\t"
                ".set\treorder"
                : "=r" (ret)
		: "r" (val));

	return ret;
}

#endif  /* _RC32300_H_ */

--- NEW FILE: rc32334.h ---
/*
 *
 * BRIEF MODULE DESCRIPTION
 *	Definitions for IDT RC32334 CPU.
 *
 * Copyright 2000,2001 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *         	st...@mv... or so...@mv...
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */

#ifndef _RC32334_H_
#define _RC32334_H_

#include <linux/delay.h>
#include <asm/io.h>

/* Base address of internal registers */
#define RC32334_REG_BASE   0x18000000

/* CPU and IP Bus Control */
#define CPU_PORT_WIDTH     0xffffe200 // virtual!
#define CPU_BTA            0xffffe204 // virtual!
#define CPU_BUSERR_ADDR    0xffffe208 // virtual!
#define CPU_IP_BTA         (RC32334_REG_BASE + 0x0000)
#define CPU_IP_ADDR_LATCH  (RC32334_REG_BASE + 0x0004)
#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
#define CPU_IP_SYSID       (RC32334_REG_BASE + 0x0018)

/* Memory Controller */
#define MEM_BASE_BANK0     (RC32334_REG_BASE + 0x0080)
#define MEM_MASK_BANK0     (RC32334_REG_BASE + 0x0084)
#define MEM_CNTL_BANK0     (RC32334_REG_BASE + 0x0200)
#define MEM_BASE_BANK1     (RC32334_REG_BASE + 0x0088)
#define MEM_MASK_BANK1     (RC32334_REG_BASE + 0x008c)
#define MEM_CNTL_BANK1     (RC32334_REG_BASE + 0x0204)
#define MEM_CNTL_BANK2     (RC32334_REG_BASE + 0x0208)
#define MEM_CNTL_BANK3     (RC32334_REG_BASE + 0x020c)
#define MEM_CNTL_BANK4     (RC32334_REG_BASE + 0x0210)
#define MEM_CNTL_BANK5     (RC32334_REG_BASE + 0x0214)

/* PCI Controller */
#define PCI_INTR_PEND      (RC32334_REG_BASE + 0x05b0)
#define PCI_INTR_MASK      (RC32334_REG_BASE + 0x05b4)
#define PCI_INTR_CLEAR     (RC32334_REG_BASE + 0x05b8)
#define CPU2PCI_INTR_PEND  (RC32334_REG_BASE + 0x05c0)
#define CPU2PCI_INTR_MASK  (RC32334_REG_BASE + 0x05c4)
#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
#define PCI2CPU_INTR_PEND  (RC32334_REG_BASE + 0x05d0)
#define PCI2CPU_INTR_MASK  (RC32334_REG_BASE + 0x05d4)
#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
#define PCI_MEM1_BASE      (RC32334_REG_BASE + 0x20b0)
#define PCI_MEM2_BASE      (RC32334_REG_BASE + 0x20b8)
#define PCI_MEM3_BASE      (RC32334_REG_BASE + 0x20c0)
#define PCI_IO1_BASE       (RC32334_REG_BASE + 0x20c8)
#define PCI_ARBITRATION    (RC32334_REG_BASE + 0x20e0)
#define PCI_CPU_MEM1_BASE  (RC32334_REG_BASE + 0x20e8)
#define PCI_CPU_IO_BASE    (RC32334_REG_BASE + 0x2100)
#define PCI_CFG_CNTL	   (RC32334_REG_BASE + 0x2cf8)
#define PCI_CFG_DATA	   (RC32334_REG_BASE + 0x2cfc)

/* Timers */
#define TIMER0_CNTL        (RC32334_REG_BASE + 0x0700)
#define TIMER0_COUNT       (RC32334_REG_BASE + 0x0704)
#define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
#define TIMER_REG_OFFSET   0x10

/* Programmable I/O */
#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)

/* 16550 UARTs */
#ifdef __MIPSEB__
#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
#else
#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
#endif
#define RC32300_BASE_BAUD  (IDT_BUS_FREQ * 1000 * 1000 / 16)

/*
 * DMA
 *
 * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
 *
 * DMA0: 18001400
 * DMA1: 18001440
 * DMA2: 18001900
 * DMA3: 18001940
 * NB: dma number must be immediate value or variable.
 *      It MUST NOT be a function since it would get called twice!
 */
#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
 
#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)

#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)

#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))

/* Expansion Interrupt Controller */
#define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)
#define IC_GROUP0_MASK     (RC32334_REG_BASE + 0x0504)
#define IC_GROUP0_CLEAR    (RC32334_REG_BASE + 0x0508)
#define IC_GROUP_OFFSET    0x10

#define NUM_INTR_GROUPS    15
/*
 * The IRQ mapping is as follows:
 *
 *    IRQ         Mapped To
 *    ---     -------------------
 *     0      SW0  (IP0) SW0 intr
 *     1      SW1  (IP1) SW1 intr
 *     2      Int0 (IP2) board-specific
 *     3      Int1 (IP3) board-specific
 *     4      Int2 (IP4) board-specific
 *     -      Int3 (IP5) not used, mapped to IRQ's 8 and up
 *     6      Int4 (IP6) board-specific
 *     7      Int5 (IP7) CP0 Timer
 *
 * IRQ's 8 and up are all mapped to Int3 (IP5), which
 * internally on the RC32334 is routed to the Expansion
 * Interrupt Controller.
 */
#define MIPS_CPU_TIMER_IRQ 7

#define GROUP1_IRQ_BASE  8                       // bus error
#define GROUP2_IRQ_BASE  (GROUP1_IRQ_BASE + 1)   // PIO active low
#define GROUP3_IRQ_BASE  (GROUP2_IRQ_BASE + 12)  // PIO active high
#define GROUP4_IRQ_BASE  (GROUP3_IRQ_BASE + 8)   // Timer Rollovers
#define GROUP5_IRQ_BASE  (GROUP4_IRQ_BASE + 8)   // UART0
#define GROUP6_IRQ_BASE  (GROUP5_IRQ_BASE + 3)   // UART1
#define GROUP7_IRQ_BASE  (GROUP6_IRQ_BASE + 3)   // DMA Ch0
#define GROUP8_IRQ_BASE  (GROUP7_IRQ_BASE + 5)   // DMA Ch1
#define GROUP9_IRQ_BASE  (GROUP8_IRQ_BASE + 5)   // DMA Ch2
#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5)   // DMA Ch3
#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5)  // PCI Ctlr errors
#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4)  // PCI Satellite Mode
#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4)  // SPI

#define RC32334_NR_IRQS  (GROUP14_IRQ_BASE + 1)


#endif /* _RC32334_H_ */

[Linux-mips-commits]CVS: linux/include/asm-mips/rc32300 - New directory

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips/rc32300
In directory usw-pr-cvs1:/tmp/cvs-serv11552/rc32300

Log Message:
Directory /cvsroot/linux-mips/linux/include/asm-mips/rc32300 added to the repository

[Linux-mips-commits]CVS: linux/include/asm-mips 79s334.h,1.2,NONE idtdisplay.h,1.1,NONE rc32300.h,1.1,NONE rc32334.h,1.3,NONE

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv11443

Removed Files:
	79s334.h idtdisplay.h rc32300.h rc32334.h 
Log Message:
Moved to asm-mips/rc32300/.


--- 79s334.h DELETED ---

--- idtdisplay.h DELETED ---

--- rc32300.h DELETED ---

--- rc32334.h DELETED ---

[Linux-mips-commits]CVS: linux/include/asm-mips 79s334.h,1.1,1.2

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv10734

Modified Files:
	79s334.h 
Log Message:
Added some macros.


Index: 79s334.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/79s334.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- 79s334.h	2002/01/16 00:00:42	1.1
+++ 79s334.h	2002/01/17 20:18:20	1.2
@@ -31,10 +31,12 @@
 #ifndef _79S334_H_
 #define _79S334_H_
 
-#define IDT_CPU_FREQ 75 // MHz
+#define IDT_BUS_FREQ   75 // MHz
+#define IDT_CLOCK_MULT 2
 
 /* NVRAM */
 #define NVRAM_BASE         0x12000000
+#define NVRAM_SIZE         512
 
 /* LCD 4-digit display */
 #define LCD_CLEAR          0x14000400
@@ -51,6 +53,8 @@
 #define RC32334_PCI_INTB_IRQ 4
 #define RC32334_PCI_INTC_IRQ 6
 #define RC32334_PCI_INTD_IRQ 7
+
+#define RAM_SIZE	(32*1024*1024)
 
 #include <asm/rc32334.h>
 

[Linux-mips-commits]CVS: linux/include/asm-mips rc32334.h,1.2,1.3

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/include/asm-mips
In directory usw-pr-cvs1:/tmp/cvs-serv10581

Modified Files:
	rc32334.h 
Log Message:
Added somwe macros for on-chip PIO and DMA Controller.


Index: rc32334.h
===================================================================
RCS file: /cvsroot/linux-mips/linux/include/asm-mips/rc32334.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- rc32334.h	2002/01/16 00:00:42	1.2
+++ rc32334.h	2002/01/17 20:17:50	1.3
@@ -86,6 +86,10 @@
 #define TIMER0_COMPARE     (RC32334_REG_BASE + 0x0708)
 #define TIMER_REG_OFFSET   0x10
 
+/* Programmable I/O */
+#define PIO_DATA0          (RC32334_REG_BASE + 0x0600)
+#define PIO_DATA1          (RC32334_REG_BASE + 0x0610)
+
 /* 16550 UARTs */
 #ifdef __MIPSEB__
 #define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
@@ -94,7 +98,33 @@
 #define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
 #define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
 #endif
-#define RC32300_BASE_BAUD  (IDT_CPU_FREQ * 1000 * 1000 / 16)
+#define RC32300_BASE_BAUD  (IDT_BUS_FREQ * 1000 * 1000 / 16)
+
+/*
+ * DMA
+ *
+ * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
+ *
+ * DMA0: 18001400
+ * DMA1: 18001440
+ * DMA2: 18001900
+ * DMA3: 18001940
+ * NB: dma number must be immediate value or variable.
+ *      It MUST NOT be a function since it would get called twice!
+ */
+#define DMA_IO(n)       (((n)>1?0x500:0)+((n)&1?0x40:0))
+ 
+#define RC32300_IO_DMA(n)       (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
+#define RC32300_DMA_CONFREG(n)  RC32300_IO_DMA(n)
+#define RC32300_DMA_BASEREG(n)  (RC32300_IO_DMA(n)+0x4)
+
+#define RC32300_DMA_CURRREG(n)  (RC32300_IO_DMA(n)+0x8)
+#define RC32300_DMA_STATREG(n)  (RC32300_IO_DMA(n)+0x10)
+#define RC32300_DMA_SRCREG(n)   (RC32300_IO_DMA(n)+0x14)
+#define RC32300_DMA_DSTREG(n)   (RC32300_IO_DMA(n)+0x18)
+#define RC32300_DMA_NEXTREG(n)  (RC32300_IO_DMA(n)+0x1c)
+
+#define RC32300_DMA_IRQ(n)  (GROUP7_IRQ_BASE+5*(n))
 
 /* Expansion Interrupt Controller */
 #define IC_GROUP0_PEND     (RC32334_REG_BASE + 0x0500)

[Linux-mips-commits]CVS: linux/arch/mips/rc32300/common time.c,1.2,1.3

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/common
In directory usw-pr-cvs1:/tmp/cvs-serv9228

Modified Files:
	time.c 
Log Message:
Add IDT_CLOCK_MULT to specify CPU clock mutliplier.


Index: time.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/time.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- time.c	2002/01/15 23:55:43	1.2
+++ time.c	2002/01/17 20:14:35	1.3
@@ -45,10 +45,12 @@
 /* 
  * Figure out the r4k offset, the amount to increment the compare
  * register for each time tick. There is no RTC available.
+ *
+ * The RC32300 counts at half the CPU *core* speed.
  */
 static unsigned long __init cal_r4koff(void)
 {
-	mips_counter_frequency = IDT_CPU_FREQ * 1000000;
+	mips_counter_frequency = IDT_CLOCK_MULT * IDT_BUS_FREQ * 1000000 / 2;
 	return (mips_counter_frequency / HZ);
 }
 

[Linux-mips-commits]CVS: linux/arch/mips/rc32300/79S334 setup.c,1.2,1.3

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv9084

Modified Files:
	setup.c 
Log Message:
Use a macro for RAM size.


Index: setup.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/setup.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- setup.c	2002/01/15 23:58:00	1.2
+++ setup.c	2002/01/17 20:13:18	1.3
@@ -79,7 +79,7 @@
 struct resource rc32334_res_ram = {
 	"RAM",
 	0,
-	32*1024*1024,
+	RAM_SIZE,
 	IORESOURCE_MEM
 };
 

[Linux-mips-commits]CVS: linux/arch/mips/rc32300/common int-handler.S,1.1,1.2

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/common
In directory usw-pr-cvs1:/tmp/cvs-serv7559/common

Modified Files:
	int-handler.S 
Log Message:
Use low-level timer handler instead of do_IRQ, saves a jal.


Index: int-handler.S
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/common/int-handler.S,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- int-handler.S	2002/01/15 00:34:07	1.1
+++ int-handler.S	2002/01/17 20:11:46	1.2
@@ -26,9 +26,29 @@
 	.set	at
 	.set	noreorder
 
-	move	a0, sp  
-	jal	rc32300_irqdispatch
+	/* Get the pending interrupts */
+	mfc0    t0, CP0_CAUSE
+	nop
+			 
+	/* Isolate the allowed ones by anding the irq mask */
+	mfc0    t2, CP0_STATUS
+	move	a1, sp		/* need a nop here, hence we anticipate */
+	andi    t0, CAUSEF_IP
+	and     t0, t2
+								  
+	/* check for r4k counter/timer IRQ. */
+	
+	andi    t1, t0, CAUSEF_IP7
+	beqz    t1, 1f
+	nop
+
+	jal     ll_timer_interrupt	/* bypass rc32300_irqdispatch */
+	li	a0, 7
+	j	ret_from_irq
 	nop
+1:
+	jal	rc32300_irqdispatch
+	move	a0, t0
 	j	ret_from_irq
 	nop
 

[Linux-mips-commits]CVS: linux/arch/mips/rc32300/79S334 irq.c,1.4,1.5

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334
In directory usw-pr-cvs1:/tmp/cvs-serv7559/79S334

Modified Files:
	irq.c 
Log Message:
Use low-level timer handler instead of do_IRQ, saves a jal.


Index: irq.c
===================================================================
RCS file: /cvsroot/linux-mips/linux/arch/mips/rc32300/79S334/irq.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -d -r1.4 -r1.5
--- irq.c	2002/01/17 03:10:12	1.4
+++ irq.c	2002/01/17 20:11:46	1.5
@@ -105,12 +105,12 @@
 	{ GROUP14_IRQ_BASE,  1, 0x00000001 }  // SPI intr
 };
 
-#define READ_PEND(g)       inl(IC_GROUP0_PEND + g*IC_GROUP_OFFSET)
-#define WRITE_PEND(g,val)  outl(val, IC_GROUP0_PEND + g*IC_GROUP_OFFSET)
-#define READ_MASK(g)       inl(IC_GROUP0_MASK + g*IC_GROUP_OFFSET)
-#define WRITE_MASK(g,val)  outl(val, IC_GROUP0_MASK + g*IC_GROUP_OFFSET)
-#define READ_CLEAR(g)      inl(IC_GROUP0_CLEAR + g*IC_GROUP_OFFSET)
-#define WRITE_CLEAR(g,val) outl(val, IC_GROUP0_CLEAR + g*IC_GROUP_OFFSET)
+#define READ_PEND(g)       inl(IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define WRITE_PEND(g,val)  outl((val), IC_GROUP0_PEND + (g)*IC_GROUP_OFFSET)
+#define READ_MASK(g)       inl(IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define WRITE_MASK(g,val)  outl((val), IC_GROUP0_MASK + (g)*IC_GROUP_OFFSET)
+#define READ_CLEAR(g)      inl(IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
+#define WRITE_CLEAR(g,val) outl((val), IC_GROUP0_CLEAR + (g)*IC_GROUP_OFFSET)
 
 static inline int irq_to_group(unsigned int irq_nr)
 {
@@ -402,27 +402,19 @@
 }
 
 /* Main Interrupt dispatcher */
-void rc32300_irqdispatch(struct pt_regs *regs)
+void rc32300_irqdispatch(unsigned long cp0_cause, struct pt_regs *regs)
 {
-	unsigned long cp0_cause;
+	unsigned long ip;
 	int ipnum;
 	
-	cp0_cause = read_32bit_cp0_register(CP0_CAUSE);
-	cp0_cause &= read_32bit_cp0_register(CP0_STATUS);
-	cp0_cause &= CAUSEF_IP;
+	ip = (cp0_cause >> 8) & 0xff;
 	
-	/* Fast path to the timer handler */
-	if (cp0_cause & CAUSEF_IP7) {
-		do_IRQ(MIPS_CPU_TIMER_IRQ, regs);
-		return;
-	}
-
-	if (!cp0_cause) {
+	if (!ip) {
 		mips_spurious_interrupt(regs);
 		return;
 	}
 	
-	ipnum = 23 - rc32300_clz(cp0_cause);
+	ipnum = 31 - rc32300_clz(ip);
 	if (ipnum == 5) {
 		int3_dispatch(regs);
 	} else {

[Linux-mips-commits]CVS: linux/Documentation/mips/idt idtdisplay.txt,NONE,1.1

[Steve L. <slo...@us...>]

Update of /cvsroot/linux-mips/linux/Documentation/mips/idt
In directory usw-pr-cvs1:/tmp/cvs-serv27611

Added Files:
	idtdisplay.txt 
Log Message:
Initial version.


--- NEW FILE: idtdisplay.txt ---
Copyright (c) 2001 THOMSON multimedia


Using the idtdisplay character device with Linux
------------------------------------------------

Contents:

	1) Overview
	2) How to use the display ?
	3) Module Command Line Parameters
	4) An example using idtDisplay
	5) Run and Stop the driver
	6) Generate thecnical documentation with doxygen

1) Overview
-----------

Idtdisplay is a driver wich allows one to display 4 characters on a digital display, 
mounted on an IDT 79S334S eval board.

It can be used to :
- write one character on one display cell
- write a "word" of four characters
- write a string of more than four characters and scroll it with a delay.
- clear the display
- change the delay between scrolling

Idtdisplay is a misc driver. Therefore it uses only a minor number (default 254).
The major number (set to 10) is shared with others misc devices.

	$ mknod /dev/idtdisplay c 10 254


2) How to use the display ?
___________________________

* write : you can write on the device such as a file (the character string will scroll).
For example : 

	$ echo "See me scrolling" > /dev/idtdisplay

* read : clean the device. Example:

	$ cat < /dev/idtdisplay

* ioctl perform different fuctions :


 - IDTDISPLAY_IOCTL_CLEAN : clean the display, no arg.
 

 - IDTDISPLAY_IOCTL_WRITE_CHAR : write one char on the display 
 	at the specified location (see idtdisp_wc_struct)

		struct idtdisp_wc_struct {
			char ch ; /* character to display */
			int nb ;  /* cell number where the display start (from 0 to 3) [0|1|2|3] */
		};

 - IDTDISPLAY_IOCTL_WRITE_4 : write four chars on the display
    arg : a string of four characters
 
 - IDTDISPLAY_IOCTL_DELAY : set up a new delay between scrolling
    arg : an unsigned long delay (in ms)

 Ioctl function return -1 if it failled, 0 otherwise.
 For futher details look at the man page for each system call.

2) Module Command Line Parameters
---------------------------------
minor = misc device's minor number
delay = scrolling in ms

3) An example using idtDisplay
---------------------------------

#include <sys/ioctl.h>
#include <errno.h>
#include <fcntl.h>
#include <unistd.h> 
#include <stdio.h>
#include <stdlib.h> 

#include "idtdisplay.h"


int main(int argc, char *argv[])
{
  int desc = 0 ;
  char ref[20]           = "/dev/idtdisplay" ;
  char msg[5]           = "hye!" ;

  if ( (desc = open(ref, O_RDWR)) < 0){
    perror("error open") ;
    exit(1) ;
  }

  if( ioctl(desc, IDTDISPLAY_IOCTL_WRITE_4, (int) msg) < 0 ){
    perror("write four char failed : ") ;
    close(desc) ;
    exit(1) ;
  }    

  close(desc) ;

  return 0 ;
}


4) Run And Stop the driver
--------------------------
make sure /dev/idtdisplay exist. Otherwise it need to be created.
ex : mknod /dev/idtdisplay c 10 254

As root :
insmod idtdisplay.o
rmmod idtdisplay


5) Generate technical documentation with doxygen
------------------------------------------------
This is implementation documentation.
A doxygen options file (Doxyfile.cfg) is provided with the driver. 
You must update it and then run the following command :

doxygen Doxyfile.cfg

You can generate html, man, rtf or latex documentation.