# | Summary▾ |
Milestone▾
|
Status▾
|
Owner▾
|
Created▾ | Updated▾ | |
---|---|---|---|---|---|---|---|
53 | Save and Restore simulation state | devel_(Next_Release) | open | 2024-08-02 | 2024-08-02 | ||
52 | IVL_UVM: UVM support - incremental additions | devel_(Next_Release) | open | 2020-11-26 | 2020-11-26 | ||
51 | VHDL: rotate support for simulation | devel_(Next_Release) | open | 2017-12-04 | 2017-12-08 | ||
50 | Arrays in port declarations | devel_(Next_Release) | open | 2015-11-20 | 2015-11-20 | ||
48 | Named ports in function calls | devel_(Next_Release) | open | 2013-08-28 | 2013-08-28 | ||
46 | Add meaningful names for VCD variables | None | open | 2012-06-13 | 2012-06-13 | ||
45 | no warning on negative delay, related lockup | devel_(Next_Release) | open | 2012-05-13 | 2012-09-04 | ||
44 | support for SystemVerilog "interface" | devel_(Next_Release) | open | Martin Whitaker | 2012-04-15 | 2014-12-19 | |
41 | support for SystemVerilog "parameter type" | devel_(Next_Release) | open | 2012-04-09 | 2012-12-10 | ||
40 | array querying system functions | devel_(Next_Release) | open | Cary R. | 2012-03-31 | 2013-12-19 | |
39 | value list '{} support | devel_(Next_Release) | open | 2012-03-31 | 2012-12-10 | ||
38 | Suppress timescale warnings based on actual usage | None | open | 2011-11-02 | 2012-12-10 | ||
37 | synthesis support | None | open | 2011-02-20 | 2011-03-09 | ||
32 | ifnone compiler error (no support for Cadence syntax) | devel_(Next_Release) | open | 2010-12-13 | 2014-08-21 | ||
19 | vpi search path inconsistent between iverilog and vvp | devel_(Next_Release) | open | 2008-02-27 | 2008-03-01 | ||
17 | add switch to write module hierarchy before elaboration | devel_(Next_Release) | open | 2007-08-19 | 2009-04-14 | ||
1 | timescale command-line option | devel_(Next_Release) | open | Cary R. | 2006-01-11 | 2011-02-01 |