Here is Cary R.'s request for this feature, it matches exactly what I had in mind.
Please add a feature request asking for this enhancement (this is not a bug). Make sure to reference this conversation in the request so we know where to look for additional details.
You can use the flag Larry mentioned previously to remove the check completely if it's causing you trouble.By turning this check off you
get the functionality of most other simulators, but you can turn it on if weird things start happening.
My understanding of what you want is, the time scale check should be improved to only warn about an inherited timescale if the module in question has a nonzero or variable delay.
I personally don't like the idea of using a global time scale file. If I specify a delay I want it to match my expectation not something out of a global file. This avoids the include issue you mentioned previously when working with multiple blocks.
The mail list thread in SourceForge starts with this message in Nov 2011 and is rather long:
[Iverilog-devel] warning: timescale for xxx inherited from another file.
From: R. Diez <rdiezmail-comparevcd@ya...> - 2011-11-01 21:19
The mentioned Icarus warning has sufficient drawbacks that I personally consider it a bug. But thanks anyway for finally taking this up.
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