#48 Named ports in function calls

open
nobody
None
5
2013-08-28
2013-08-28
Russ Dill
No

I noticed a handy feature in the Xilinx verilog parser, I can name ports in calls to functions just like in calls to modules:

assign trn1_output = trn1(
.cid(16'hf00f),
.cstatus(3'b100),
.byte_count(12'b0)
);

This has been really handy for generating the bitfields for PCI express in a manner that makes it much more difficult to make errors. Its a bummer that Icarus Verilog doesn't have support for this.

Related

Feature Requests: #48

Discussion

  • Cary R.

    Cary R. - 2013-08-28

    Interesting, I thought this was already implemented in Icarus. Both functions and tasks should support named port calls but I just verified that they both fail. This is covered in section 13.5 of 1800-2012.

     
  • Stephen Williams

    Then lets reclassify this from feature-request to bug report.

    On 08/28/2013 10:02 AM, Cary R. wrote:

    Interesting, I thought this was already implemented in Icarus. Both
    functions and tasks should support named port calls but I just verified
    that they both fail. This is covered in section 13.5 of 1800-2012.


    [feature-requests:#48]
    http://sourceforge.net/p/iverilog/feature-requests/48/ Named ports in
    function calls

    Status: open
    Created: Wed Aug 28, 2013 09:06 AM UTC by Russ Dill
    Last Updated: Wed Aug 28, 2013 09:06 AM UTC
    Owner: nobody

    I noticed a handy feature in the Xilinx verilog parser, I can name ports
    in calls to functions just like in calls to modules:

    assign trn1_output = trn1(
    .cid(16'hf00f),
    .cstatus(3'b100),
    .byte_count(12'b0)
    );

    This has been really handy for generating the bitfields for PCI express
    in a manner that makes it much more difficult to make errors. Its a
    bummer that Icarus Verilog doesn't have support for this.


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    --
    Steve Williams "The woods are lovely, dark and deep.
    steve at icarus.com But I have promises to keep,
    http://www.icarus.com and lines to code before I sleep,
    http://www.picturel.com And lines to code before I sleep."

     

    Related

    Feature Requests: #48

  • Cary R.

    Cary R. - 2013-08-28

    This is a SystemVerilog addition so I think this can stay as a feature request since we don't profess Icarus to be a SystemVerilog simulator quite yet, though I do consider this a high priority feature request.

     

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